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c5a3c2e5 | 1 | /* |
c5a3c2e5 AB |
2 | * Copyright (C) 2001 Dave Engebretsen, IBM Corporation |
3 | * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM | |
4 | * | |
5 | * RTAS specific routines for PCI. | |
ae65a391 | 6 | * |
c5a3c2e5 AB |
7 | * Based on code from pci.c, chrp_pci.c and pSeries_pci.c |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
ae65a391 | 13 | * |
c5a3c2e5 AB |
14 | * This program is distributed in the hope that it will be useful, |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
ae65a391 | 18 | * |
c5a3c2e5 AB |
19 | * You should have received a copy of the GNU General Public License |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <linux/kernel.h> | |
25 | #include <linux/threads.h> | |
26 | #include <linux/pci.h> | |
27 | #include <linux/string.h> | |
28 | #include <linux/init.h> | |
c5a3c2e5 AB |
29 | |
30 | #include <asm/io.h> | |
31 | #include <asm/pgtable.h> | |
32 | #include <asm/irq.h> | |
33 | #include <asm/prom.h> | |
34 | #include <asm/machdep.h> | |
35 | #include <asm/pci-bridge.h> | |
36 | #include <asm/iommu.h> | |
37 | #include <asm/rtas.h> | |
bbeb3f4c | 38 | #include <asm/mpic.h> |
d387899f | 39 | #include <asm/ppc-pci.h> |
68a64357 | 40 | #include <asm/eeh.h> |
c5a3c2e5 AB |
41 | |
42 | /* RTAS tokens */ | |
43 | static int read_pci_config; | |
44 | static int write_pci_config; | |
45 | static int ibm_read_pci_config; | |
46 | static int ibm_write_pci_config; | |
47 | ||
ae65a391 | 48 | static inline int config_access_valid(struct pci_dn *dn, int where) |
c5a3c2e5 AB |
49 | { |
50 | if (where < 256) | |
51 | return 1; | |
52 | if (where < 4096 && dn->pci_ext_config_space) | |
53 | return 1; | |
54 | ||
55 | return 0; | |
56 | } | |
57 | ||
7684b40c | 58 | int rtas_read_config(struct pci_dn *pdn, int where, int size, u32 *val) |
c5a3c2e5 AB |
59 | { |
60 | int returnval = -1; | |
61 | unsigned long buid, addr; | |
62 | int ret; | |
63 | ||
ae65a391 | 64 | if (!pdn) |
c5a3c2e5 | 65 | return PCIBIOS_DEVICE_NOT_FOUND; |
1635317f | 66 | if (!config_access_valid(pdn, where)) |
c5a3c2e5 | 67 | return PCIBIOS_BAD_REGISTER_NUMBER; |
3409eb4e GS |
68 | #ifdef CONFIG_EEH |
69 | if (pdn->edev && pdn->edev->pe && | |
70 | (pdn->edev->pe->state & EEH_PE_CFG_BLOCKED)) | |
71 | return PCIBIOS_SET_FAILED; | |
72 | #endif | |
c5a3c2e5 | 73 | |
6f3d5d3c | 74 | addr = rtas_config_addr(pdn->busno, pdn->devfn, where); |
1635317f | 75 | buid = pdn->phb->buid; |
c5a3c2e5 AB |
76 | if (buid) { |
77 | ret = rtas_call(ibm_read_pci_config, 4, 2, &returnval, | |
ae65a391 | 78 | addr, BUID_HI(buid), BUID_LO(buid), size); |
c5a3c2e5 AB |
79 | } else { |
80 | ret = rtas_call(read_pci_config, 2, 2, &returnval, addr, size); | |
81 | } | |
82 | *val = returnval; | |
83 | ||
84 | if (ret) | |
85 | return PCIBIOS_DEVICE_NOT_FOUND; | |
86 | ||
c5a3c2e5 AB |
87 | return PCIBIOS_SUCCESSFUL; |
88 | } | |
89 | ||
90 | static int rtas_pci_read_config(struct pci_bus *bus, | |
91 | unsigned int devfn, | |
92 | int where, int size, u32 *val) | |
93 | { | |
94 | struct device_node *busdn, *dn; | |
d0914f50 GS |
95 | struct pci_dn *pdn; |
96 | bool found = false; | |
d0914f50 | 97 | int ret; |
c5a3c2e5 AB |
98 | |
99 | /* Search only direct children of the bus */ | |
d0914f50 GS |
100 | *val = 0xFFFFFFFF; |
101 | busdn = pci_bus_to_OF_node(bus); | |
ae65a391 | 102 | for (dn = busdn->child; dn; dn = dn->sibling) { |
d0914f50 | 103 | pdn = PCI_DN(dn); |
ae65a391 | 104 | if (pdn && pdn->devfn == devfn |
d0914f50 GS |
105 | && of_device_is_available(dn)) { |
106 | found = true; | |
107 | break; | |
108 | } | |
ae65a391 | 109 | } |
1635317f | 110 | |
d0914f50 GS |
111 | if (!found) |
112 | return PCIBIOS_DEVICE_NOT_FOUND; | |
d0914f50 GS |
113 | |
114 | ret = rtas_read_config(pdn, where, size, val); | |
115 | if (*val == EEH_IO_ERROR_VALUE(size) && | |
c6406d8f | 116 | eeh_dev_check_failure(pdn_to_eeh_dev(pdn))) |
d0914f50 GS |
117 | return PCIBIOS_DEVICE_NOT_FOUND; |
118 | ||
119 | return ret; | |
c5a3c2e5 AB |
120 | } |
121 | ||
ae65a391 | 122 | int rtas_write_config(struct pci_dn *pdn, int where, int size, u32 val) |
c5a3c2e5 AB |
123 | { |
124 | unsigned long buid, addr; | |
125 | int ret; | |
126 | ||
ae65a391 | 127 | if (!pdn) |
c5a3c2e5 | 128 | return PCIBIOS_DEVICE_NOT_FOUND; |
1635317f | 129 | if (!config_access_valid(pdn, where)) |
c5a3c2e5 | 130 | return PCIBIOS_BAD_REGISTER_NUMBER; |
3409eb4e GS |
131 | #ifdef CONFIG_EEH |
132 | if (pdn->edev && pdn->edev->pe && | |
133 | (pdn->edev->pe->state & EEH_PE_CFG_BLOCKED)) | |
134 | return PCIBIOS_SET_FAILED; | |
135 | #endif | |
c5a3c2e5 | 136 | |
6f3d5d3c | 137 | addr = rtas_config_addr(pdn->busno, pdn->devfn, where); |
1635317f | 138 | buid = pdn->phb->buid; |
c5a3c2e5 | 139 | if (buid) { |
ae65a391 LV |
140 | ret = rtas_call(ibm_write_pci_config, 5, 1, NULL, addr, |
141 | BUID_HI(buid), BUID_LO(buid), size, (ulong) val); | |
c5a3c2e5 AB |
142 | } else { |
143 | ret = rtas_call(write_pci_config, 3, 1, NULL, addr, size, (ulong)val); | |
144 | } | |
145 | ||
146 | if (ret) | |
147 | return PCIBIOS_DEVICE_NOT_FOUND; | |
148 | ||
149 | return PCIBIOS_SUCCESSFUL; | |
150 | } | |
151 | ||
152 | static int rtas_pci_write_config(struct pci_bus *bus, | |
153 | unsigned int devfn, | |
154 | int where, int size, u32 val) | |
155 | { | |
156 | struct device_node *busdn, *dn; | |
d0914f50 GS |
157 | struct pci_dn *pdn; |
158 | bool found = false; | |
c5a3c2e5 AB |
159 | |
160 | /* Search only direct children of the bus */ | |
d0914f50 | 161 | busdn = pci_bus_to_OF_node(bus); |
ae65a391 | 162 | for (dn = busdn->child; dn; dn = dn->sibling) { |
d0914f50 | 163 | pdn = PCI_DN(dn); |
ae65a391 | 164 | if (pdn && pdn->devfn == devfn |
d0914f50 GS |
165 | && of_device_is_available(dn)) { |
166 | found = true; | |
167 | break; | |
168 | } | |
ae65a391 | 169 | } |
d0914f50 GS |
170 | |
171 | if (!found) | |
172 | return PCIBIOS_DEVICE_NOT_FOUND; | |
d0914f50 | 173 | |
3409eb4e | 174 | return rtas_write_config(pdn, where, size, val); |
c5a3c2e5 AB |
175 | } |
176 | ||
1c21a293 | 177 | static struct pci_ops rtas_pci_ops = { |
8674e0c9 NL |
178 | .read = rtas_pci_read_config, |
179 | .write = rtas_pci_write_config, | |
c5a3c2e5 AB |
180 | }; |
181 | ||
1c21a293 | 182 | static int is_python(struct device_node *dev) |
c5a3c2e5 | 183 | { |
e2eb6392 | 184 | const char *model = of_get_property(dev, "model", NULL); |
c5a3c2e5 AB |
185 | |
186 | if (model && strstr(model, "Python")) | |
187 | return 1; | |
188 | ||
189 | return 0; | |
190 | } | |
191 | ||
cc5d0189 | 192 | static void python_countermeasures(struct device_node *dev) |
c5a3c2e5 | 193 | { |
cc5d0189 | 194 | struct resource registers; |
c5a3c2e5 AB |
195 | void __iomem *chip_regs; |
196 | volatile u32 val; | |
197 | ||
cc5d0189 BH |
198 | if (of_address_to_resource(dev, 0, ®isters)) { |
199 | printk(KERN_ERR "Can't get address for Python workarounds !\n"); | |
c5a3c2e5 | 200 | return; |
cc5d0189 | 201 | } |
c5a3c2e5 AB |
202 | |
203 | /* Python's register file is 1 MB in size. */ | |
cc5d0189 | 204 | chip_regs = ioremap(registers.start & ~(0xfffffUL), 0x100000); |
c5a3c2e5 | 205 | |
ae65a391 | 206 | /* |
c5a3c2e5 AB |
207 | * Firmware doesn't always clear this bit which is critical |
208 | * for good performance - Anton | |
209 | */ | |
210 | ||
211 | #define PRG_CL_RESET_VALID 0x00010000 | |
212 | ||
213 | val = in_be32(chip_regs + 0xf6030); | |
214 | if (val & PRG_CL_RESET_VALID) { | |
215 | printk(KERN_INFO "Python workaround: "); | |
216 | val &= ~PRG_CL_RESET_VALID; | |
217 | out_be32(chip_regs + 0xf6030, val); | |
218 | /* | |
219 | * We must read it back for changes to | |
220 | * take effect | |
221 | */ | |
222 | val = in_be32(chip_regs + 0xf6030); | |
223 | printk("reg0: %x\n", val); | |
224 | } | |
225 | ||
226 | iounmap(chip_regs); | |
227 | } | |
228 | ||
db38f290 | 229 | void __init init_pci_config_tokens(void) |
c5a3c2e5 AB |
230 | { |
231 | read_pci_config = rtas_token("read-pci-config"); | |
232 | write_pci_config = rtas_token("write-pci-config"); | |
233 | ibm_read_pci_config = rtas_token("ibm,read-pci-config"); | |
234 | ibm_write_pci_config = rtas_token("ibm,write-pci-config"); | |
235 | } | |
236 | ||
db38f290 | 237 | unsigned long get_phb_buid(struct device_node *phb) |
c5a3c2e5 | 238 | { |
6506e710 | 239 | struct resource r; |
c5a3c2e5 | 240 | |
6506e710 | 241 | if (ibm_read_pci_config == -1) |
c5a3c2e5 | 242 | return 0; |
6506e710 | 243 | if (of_address_to_resource(phb, 0, &r)) |
c5a3c2e5 | 244 | return 0; |
6506e710 | 245 | return r.start; |
c5a3c2e5 AB |
246 | } |
247 | ||
248 | static int phb_set_bus_ranges(struct device_node *dev, | |
249 | struct pci_controller *phb) | |
250 | { | |
cf059965 | 251 | const __be32 *bus_range; |
c5a3c2e5 AB |
252 | unsigned int len; |
253 | ||
e2eb6392 | 254 | bus_range = of_get_property(dev, "bus-range", &len); |
c5a3c2e5 AB |
255 | if (bus_range == NULL || len < 2 * sizeof(int)) { |
256 | return 1; | |
257 | } | |
ae65a391 | 258 | |
cf059965 CLG |
259 | phb->first_busno = be32_to_cpu(bus_range[0]); |
260 | phb->last_busno = be32_to_cpu(bus_range[1]); | |
c5a3c2e5 AB |
261 | |
262 | return 0; | |
263 | } | |
264 | ||
cad5cef6 | 265 | int rtas_setup_phb(struct pci_controller *phb) |
c5a3c2e5 | 266 | { |
44ef3390 | 267 | struct device_node *dev = phb->dn; |
4c9d2800 | 268 | |
c5a3c2e5 | 269 | if (is_python(dev)) |
cc5d0189 | 270 | python_countermeasures(dev); |
c5a3c2e5 AB |
271 | |
272 | if (phb_set_bus_ranges(dev, phb)) | |
273 | return 1; | |
274 | ||
c5a3c2e5 AB |
275 | phb->ops = &rtas_pci_ops; |
276 | phb->buid = get_phb_buid(dev); | |
277 | ||
278 | return 0; | |
279 | } |