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c5a3c2e5 | 1 | /* |
c5a3c2e5 AB |
2 | * Copyright (C) 2001 Dave Engebretsen, IBM Corporation |
3 | * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM | |
4 | * | |
5 | * RTAS specific routines for PCI. | |
ae65a391 | 6 | * |
c5a3c2e5 AB |
7 | * Based on code from pci.c, chrp_pci.c and pSeries_pci.c |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
ae65a391 | 13 | * |
c5a3c2e5 AB |
14 | * This program is distributed in the hope that it will be useful, |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
ae65a391 | 18 | * |
c5a3c2e5 AB |
19 | * You should have received a copy of the GNU General Public License |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <linux/kernel.h> | |
25 | #include <linux/threads.h> | |
26 | #include <linux/pci.h> | |
27 | #include <linux/string.h> | |
28 | #include <linux/init.h> | |
29 | #include <linux/bootmem.h> | |
30 | ||
31 | #include <asm/io.h> | |
32 | #include <asm/pgtable.h> | |
33 | #include <asm/irq.h> | |
34 | #include <asm/prom.h> | |
35 | #include <asm/machdep.h> | |
36 | #include <asm/pci-bridge.h> | |
37 | #include <asm/iommu.h> | |
38 | #include <asm/rtas.h> | |
bbeb3f4c | 39 | #include <asm/mpic.h> |
d387899f | 40 | #include <asm/ppc-pci.h> |
68a64357 | 41 | #include <asm/eeh.h> |
c5a3c2e5 AB |
42 | |
43 | /* RTAS tokens */ | |
44 | static int read_pci_config; | |
45 | static int write_pci_config; | |
46 | static int ibm_read_pci_config; | |
47 | static int ibm_write_pci_config; | |
48 | ||
ae65a391 | 49 | static inline int config_access_valid(struct pci_dn *dn, int where) |
c5a3c2e5 AB |
50 | { |
51 | if (where < 256) | |
52 | return 1; | |
53 | if (where < 4096 && dn->pci_ext_config_space) | |
54 | return 1; | |
55 | ||
56 | return 0; | |
57 | } | |
58 | ||
7684b40c | 59 | int rtas_read_config(struct pci_dn *pdn, int where, int size, u32 *val) |
c5a3c2e5 AB |
60 | { |
61 | int returnval = -1; | |
62 | unsigned long buid, addr; | |
63 | int ret; | |
64 | ||
ae65a391 | 65 | if (!pdn) |
c5a3c2e5 | 66 | return PCIBIOS_DEVICE_NOT_FOUND; |
1635317f | 67 | if (!config_access_valid(pdn, where)) |
c5a3c2e5 | 68 | return PCIBIOS_BAD_REGISTER_NUMBER; |
3409eb4e GS |
69 | #ifdef CONFIG_EEH |
70 | if (pdn->edev && pdn->edev->pe && | |
71 | (pdn->edev->pe->state & EEH_PE_CFG_BLOCKED)) | |
72 | return PCIBIOS_SET_FAILED; | |
73 | #endif | |
c5a3c2e5 | 74 | |
6f3d5d3c | 75 | addr = rtas_config_addr(pdn->busno, pdn->devfn, where); |
1635317f | 76 | buid = pdn->phb->buid; |
c5a3c2e5 AB |
77 | if (buid) { |
78 | ret = rtas_call(ibm_read_pci_config, 4, 2, &returnval, | |
ae65a391 | 79 | addr, BUID_HI(buid), BUID_LO(buid), size); |
c5a3c2e5 AB |
80 | } else { |
81 | ret = rtas_call(read_pci_config, 2, 2, &returnval, addr, size); | |
82 | } | |
83 | *val = returnval; | |
84 | ||
85 | if (ret) | |
86 | return PCIBIOS_DEVICE_NOT_FOUND; | |
87 | ||
c5a3c2e5 AB |
88 | return PCIBIOS_SUCCESSFUL; |
89 | } | |
90 | ||
91 | static int rtas_pci_read_config(struct pci_bus *bus, | |
92 | unsigned int devfn, | |
93 | int where, int size, u32 *val) | |
94 | { | |
95 | struct device_node *busdn, *dn; | |
d0914f50 GS |
96 | struct pci_dn *pdn; |
97 | bool found = false; | |
d0914f50 | 98 | int ret; |
c5a3c2e5 AB |
99 | |
100 | /* Search only direct children of the bus */ | |
d0914f50 GS |
101 | *val = 0xFFFFFFFF; |
102 | busdn = pci_bus_to_OF_node(bus); | |
ae65a391 | 103 | for (dn = busdn->child; dn; dn = dn->sibling) { |
d0914f50 | 104 | pdn = PCI_DN(dn); |
ae65a391 | 105 | if (pdn && pdn->devfn == devfn |
d0914f50 GS |
106 | && of_device_is_available(dn)) { |
107 | found = true; | |
108 | break; | |
109 | } | |
ae65a391 | 110 | } |
1635317f | 111 | |
d0914f50 GS |
112 | if (!found) |
113 | return PCIBIOS_DEVICE_NOT_FOUND; | |
d0914f50 GS |
114 | |
115 | ret = rtas_read_config(pdn, where, size, val); | |
116 | if (*val == EEH_IO_ERROR_VALUE(size) && | |
117 | eeh_dev_check_failure(of_node_to_eeh_dev(dn))) | |
118 | return PCIBIOS_DEVICE_NOT_FOUND; | |
119 | ||
120 | return ret; | |
c5a3c2e5 AB |
121 | } |
122 | ||
ae65a391 | 123 | int rtas_write_config(struct pci_dn *pdn, int where, int size, u32 val) |
c5a3c2e5 AB |
124 | { |
125 | unsigned long buid, addr; | |
126 | int ret; | |
127 | ||
ae65a391 | 128 | if (!pdn) |
c5a3c2e5 | 129 | return PCIBIOS_DEVICE_NOT_FOUND; |
1635317f | 130 | if (!config_access_valid(pdn, where)) |
c5a3c2e5 | 131 | return PCIBIOS_BAD_REGISTER_NUMBER; |
3409eb4e GS |
132 | #ifdef CONFIG_EEH |
133 | if (pdn->edev && pdn->edev->pe && | |
134 | (pdn->edev->pe->state & EEH_PE_CFG_BLOCKED)) | |
135 | return PCIBIOS_SET_FAILED; | |
136 | #endif | |
c5a3c2e5 | 137 | |
6f3d5d3c | 138 | addr = rtas_config_addr(pdn->busno, pdn->devfn, where); |
1635317f | 139 | buid = pdn->phb->buid; |
c5a3c2e5 | 140 | if (buid) { |
ae65a391 LV |
141 | ret = rtas_call(ibm_write_pci_config, 5, 1, NULL, addr, |
142 | BUID_HI(buid), BUID_LO(buid), size, (ulong) val); | |
c5a3c2e5 AB |
143 | } else { |
144 | ret = rtas_call(write_pci_config, 3, 1, NULL, addr, size, (ulong)val); | |
145 | } | |
146 | ||
147 | if (ret) | |
148 | return PCIBIOS_DEVICE_NOT_FOUND; | |
149 | ||
150 | return PCIBIOS_SUCCESSFUL; | |
151 | } | |
152 | ||
153 | static int rtas_pci_write_config(struct pci_bus *bus, | |
154 | unsigned int devfn, | |
155 | int where, int size, u32 val) | |
156 | { | |
157 | struct device_node *busdn, *dn; | |
d0914f50 GS |
158 | struct pci_dn *pdn; |
159 | bool found = false; | |
c5a3c2e5 AB |
160 | |
161 | /* Search only direct children of the bus */ | |
d0914f50 | 162 | busdn = pci_bus_to_OF_node(bus); |
ae65a391 | 163 | for (dn = busdn->child; dn; dn = dn->sibling) { |
d0914f50 | 164 | pdn = PCI_DN(dn); |
ae65a391 | 165 | if (pdn && pdn->devfn == devfn |
d0914f50 GS |
166 | && of_device_is_available(dn)) { |
167 | found = true; | |
168 | break; | |
169 | } | |
ae65a391 | 170 | } |
d0914f50 GS |
171 | |
172 | if (!found) | |
173 | return PCIBIOS_DEVICE_NOT_FOUND; | |
d0914f50 | 174 | |
3409eb4e | 175 | return rtas_write_config(pdn, where, size, val); |
c5a3c2e5 AB |
176 | } |
177 | ||
1c21a293 | 178 | static struct pci_ops rtas_pci_ops = { |
8674e0c9 NL |
179 | .read = rtas_pci_read_config, |
180 | .write = rtas_pci_write_config, | |
c5a3c2e5 AB |
181 | }; |
182 | ||
1c21a293 | 183 | static int is_python(struct device_node *dev) |
c5a3c2e5 | 184 | { |
e2eb6392 | 185 | const char *model = of_get_property(dev, "model", NULL); |
c5a3c2e5 AB |
186 | |
187 | if (model && strstr(model, "Python")) | |
188 | return 1; | |
189 | ||
190 | return 0; | |
191 | } | |
192 | ||
cc5d0189 | 193 | static void python_countermeasures(struct device_node *dev) |
c5a3c2e5 | 194 | { |
cc5d0189 | 195 | struct resource registers; |
c5a3c2e5 AB |
196 | void __iomem *chip_regs; |
197 | volatile u32 val; | |
198 | ||
cc5d0189 BH |
199 | if (of_address_to_resource(dev, 0, ®isters)) { |
200 | printk(KERN_ERR "Can't get address for Python workarounds !\n"); | |
c5a3c2e5 | 201 | return; |
cc5d0189 | 202 | } |
c5a3c2e5 AB |
203 | |
204 | /* Python's register file is 1 MB in size. */ | |
cc5d0189 | 205 | chip_regs = ioremap(registers.start & ~(0xfffffUL), 0x100000); |
c5a3c2e5 | 206 | |
ae65a391 | 207 | /* |
c5a3c2e5 AB |
208 | * Firmware doesn't always clear this bit which is critical |
209 | * for good performance - Anton | |
210 | */ | |
211 | ||
212 | #define PRG_CL_RESET_VALID 0x00010000 | |
213 | ||
214 | val = in_be32(chip_regs + 0xf6030); | |
215 | if (val & PRG_CL_RESET_VALID) { | |
216 | printk(KERN_INFO "Python workaround: "); | |
217 | val &= ~PRG_CL_RESET_VALID; | |
218 | out_be32(chip_regs + 0xf6030, val); | |
219 | /* | |
220 | * We must read it back for changes to | |
221 | * take effect | |
222 | */ | |
223 | val = in_be32(chip_regs + 0xf6030); | |
224 | printk("reg0: %x\n", val); | |
225 | } | |
226 | ||
227 | iounmap(chip_regs); | |
228 | } | |
229 | ||
db38f290 | 230 | void __init init_pci_config_tokens(void) |
c5a3c2e5 AB |
231 | { |
232 | read_pci_config = rtas_token("read-pci-config"); | |
233 | write_pci_config = rtas_token("write-pci-config"); | |
234 | ibm_read_pci_config = rtas_token("ibm,read-pci-config"); | |
235 | ibm_write_pci_config = rtas_token("ibm,write-pci-config"); | |
236 | } | |
237 | ||
db38f290 | 238 | unsigned long get_phb_buid(struct device_node *phb) |
c5a3c2e5 | 239 | { |
6506e710 | 240 | struct resource r; |
c5a3c2e5 | 241 | |
6506e710 | 242 | if (ibm_read_pci_config == -1) |
c5a3c2e5 | 243 | return 0; |
6506e710 | 244 | if (of_address_to_resource(phb, 0, &r)) |
c5a3c2e5 | 245 | return 0; |
6506e710 | 246 | return r.start; |
c5a3c2e5 AB |
247 | } |
248 | ||
249 | static int phb_set_bus_ranges(struct device_node *dev, | |
250 | struct pci_controller *phb) | |
251 | { | |
cf059965 | 252 | const __be32 *bus_range; |
c5a3c2e5 AB |
253 | unsigned int len; |
254 | ||
e2eb6392 | 255 | bus_range = of_get_property(dev, "bus-range", &len); |
c5a3c2e5 AB |
256 | if (bus_range == NULL || len < 2 * sizeof(int)) { |
257 | return 1; | |
258 | } | |
ae65a391 | 259 | |
cf059965 CLG |
260 | phb->first_busno = be32_to_cpu(bus_range[0]); |
261 | phb->last_busno = be32_to_cpu(bus_range[1]); | |
c5a3c2e5 AB |
262 | |
263 | return 0; | |
264 | } | |
265 | ||
cad5cef6 | 266 | int rtas_setup_phb(struct pci_controller *phb) |
c5a3c2e5 | 267 | { |
44ef3390 | 268 | struct device_node *dev = phb->dn; |
4c9d2800 | 269 | |
c5a3c2e5 | 270 | if (is_python(dev)) |
cc5d0189 | 271 | python_countermeasures(dev); |
c5a3c2e5 AB |
272 | |
273 | if (phb_set_bus_ranges(dev, phb)) | |
274 | return 1; | |
275 | ||
c5a3c2e5 AB |
276 | phb->ops = &rtas_pci_ops; |
277 | phb->buid = get_phb_buid(dev); | |
278 | ||
279 | return 0; | |
280 | } | |
281 | ||
36241ce6 | 282 | void __init find_and_init_phbs(void) |
c5a3c2e5 AB |
283 | { |
284 | struct device_node *node; | |
285 | struct pci_controller *phb; | |
c5a3c2e5 AB |
286 | struct device_node *root = of_find_node_by_path("/"); |
287 | ||
85e99b9f | 288 | for_each_child_of_node(root, node) { |
bb53bb3d JM |
289 | if (node->type == NULL || (strcmp(node->type, "pci") != 0 && |
290 | strcmp(node->type, "pciex") != 0)) | |
c5a3c2e5 AB |
291 | continue; |
292 | ||
b5166cc2 | 293 | phb = pcibios_alloc_controller(node); |
c5a3c2e5 AB |
294 | if (!phb) |
295 | continue; | |
4c9d2800 | 296 | rtas_setup_phb(phb); |
f7abbc19 | 297 | pci_process_bridge_OF_ranges(phb, node, 0); |
3d5134ee | 298 | isa_bridge_find_early(phb); |
c5a3c2e5 AB |
299 | } |
300 | ||
301 | of_node_put(root); | |
302 | pci_devs_phb_init(); | |
303 | ||
304 | /* | |
673c9756 | 305 | * PCI_PROBE_ONLY and PCI_REASSIGN_ALL_BUS can be set via properties |
c5a3c2e5 AB |
306 | * in chosen. |
307 | */ | |
308 | if (of_chosen) { | |
a7f67bdf | 309 | const int *prop; |
c5a3c2e5 | 310 | |
e2eb6392 | 311 | prop = of_get_property(of_chosen, |
a7f67bdf | 312 | "linux,pci-probe-only", NULL); |
673c9756 BH |
313 | if (prop) { |
314 | if (*prop) | |
315 | pci_add_flags(PCI_PROBE_ONLY); | |
316 | else | |
317 | pci_clear_flags(PCI_PROBE_ONLY); | |
318 | } | |
c5a3c2e5 | 319 | |
fc3fb71c | 320 | #ifdef CONFIG_PPC32 /* Will be made generic soon */ |
e2eb6392 | 321 | prop = of_get_property(of_chosen, |
a7f67bdf | 322 | "linux,pci-assign-all-buses", NULL); |
fc3fb71c | 323 | if (prop && *prop) |
0e47ff1c | 324 | pci_add_flags(PCI_REASSIGN_ALL_BUS); |
fc3fb71c | 325 | #endif /* CONFIG_PPC32 */ |
c5a3c2e5 | 326 | } |
c5a3c2e5 | 327 | } |