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Commit | Line | Data |
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9b6b563c PM |
1 | /* |
2 | * Common prep/pmac/chrp boot and setup code. | |
3 | */ | |
4 | ||
9b6b563c PM |
5 | #include <linux/module.h> |
6 | #include <linux/string.h> | |
7 | #include <linux/sched.h> | |
8 | #include <linux/init.h> | |
9 | #include <linux/kernel.h> | |
10 | #include <linux/reboot.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/initrd.h> | |
9b6b563c | 13 | #include <linux/tty.h> |
9b6b563c PM |
14 | #include <linux/seq_file.h> |
15 | #include <linux/root_dev.h> | |
16 | #include <linux/cpu.h> | |
17 | #include <linux/console.h> | |
95f72d1e | 18 | #include <linux/memblock.h> |
9b6b563c | 19 | |
9b6b563c PM |
20 | #include <asm/io.h> |
21 | #include <asm/prom.h> | |
22 | #include <asm/processor.h> | |
23 | #include <asm/pgtable.h> | |
9b6b563c | 24 | #include <asm/setup.h> |
9b6b563c PM |
25 | #include <asm/smp.h> |
26 | #include <asm/elf.h> | |
27 | #include <asm/cputable.h> | |
28 | #include <asm/bootx.h> | |
29 | #include <asm/btext.h> | |
30 | #include <asm/machdep.h> | |
31 | #include <asm/uaccess.h> | |
9b6b563c PM |
32 | #include <asm/pmac_feature.h> |
33 | #include <asm/sections.h> | |
34 | #include <asm/nvram.h> | |
35 | #include <asm/xmon.h> | |
6d7f58b0 | 36 | #include <asm/time.h> |
463ce0e1 | 37 | #include <asm/serial.h> |
51d3082f | 38 | #include <asm/udbg.h> |
1cd03890 | 39 | #include <asm/code-patching.h> |
b92a226e | 40 | #include <asm/cpu_has_feature.h> |
9b6b563c | 41 | |
03501dab PM |
42 | #define DBG(fmt...) |
43 | ||
9b6b563c PM |
44 | extern void bootx_init(unsigned long r4, unsigned long phys); |
45 | ||
80579e1f | 46 | int boot_cpuid_phys; |
9974eec2 | 47 | EXPORT_SYMBOL_GPL(boot_cpuid_phys); |
80579e1f | 48 | |
13a9801e NL |
49 | int smp_hw_index[NR_CPUS]; |
50 | ||
9b6b563c PM |
51 | unsigned long ISA_DMA_THRESHOLD; |
52 | unsigned int DMA_MODE_READ; | |
53 | unsigned int DMA_MODE_WRITE; | |
54 | ||
9b6b563c PM |
55 | /* |
56 | * These are used in binfmt_elf.c to put aux entries on the stack | |
57 | * for each elf executable being started. | |
58 | */ | |
59 | int dcache_bsize; | |
60 | int icache_bsize; | |
61 | int ucache_bsize; | |
62 | ||
9b6b563c | 63 | /* |
bd7c93cc | 64 | * We're called here very early in the boot. |
9b6b563c PM |
65 | * |
66 | * Note that the kernel may be running at an address which is different | |
67 | * from the address that it was linked at, so we must use RELOC/PTRRELOC | |
68 | * to access static data (including strings). -- paulus | |
69 | */ | |
4e491d14 | 70 | notrace unsigned long __init early_init(unsigned long dt_ptr) |
9b6b563c PM |
71 | { |
72 | unsigned long offset = reloc_offset(); | |
73 | ||
dd184343 PM |
74 | /* First zero the BSS -- use memset_io, some platforms don't have |
75 | * caches on yet */ | |
556b09c8 MG |
76 | memset_io((void __iomem *)PTRRELOC(&__bss_start), 0, |
77 | __bss_stop - __bss_start); | |
dd184343 | 78 | |
9b6b563c PM |
79 | /* |
80 | * Identify the CPU type and fix up code sections | |
81 | * that depend on which cpu we have. | |
82 | */ | |
9402c684 | 83 | identify_cpu(offset, mfspr(SPRN_PVR)); |
42c4aaad | 84 | |
9402c684 | 85 | apply_feature_fixups(); |
d715e433 | 86 | |
9b6b563c PM |
87 | return KERNELBASE + offset; |
88 | } | |
89 | ||
9b6b563c | 90 | |
9b6b563c | 91 | /* |
bd7c93cc BH |
92 | * This is run before start_kernel(), the kernel has been relocated |
93 | * and we are running with enough of the MMU enabled to have our | |
94 | * proper kernel virtual addresses | |
95 | * | |
9b6b563c PM |
96 | * Find out what kind of machine we're on and save any data we need |
97 | * from the early boot process (devtree is copied on pmac by prom_init()). | |
98 | * This is called very early on the boot process, after a minimal | |
99 | * MMU environment has been set up but before MMU_init is called. | |
100 | */ | |
400c47d8 LC |
101 | extern unsigned int memset_nocache_branch; /* Insn to be replaced by NOP */ |
102 | ||
6dece0eb | 103 | notrace void __init machine_init(u64 dt_ptr) |
9b6b563c | 104 | { |
719c91cc DG |
105 | /* Enable early debugging if any specified (see udbg.h) */ |
106 | udbg_early_init(); | |
51d3082f | 107 | |
1cd03890 | 108 | patch_instruction((unsigned int *)&memcpy, PPC_INST_NOP); |
400c47d8 | 109 | patch_instruction(&memset_nocache_branch, PPC_INST_NOP); |
1cd03890 | 110 | |
51d3082f | 111 | /* Do some early initialization based on the flat device tree */ |
9b6b563c PM |
112 | early_init_devtree(__va(dt_ptr)); |
113 | ||
91b191c7 DK |
114 | early_init_mmu(); |
115 | ||
f8f50b1b | 116 | setup_kdump_trampoline(); |
9b6b563c PM |
117 | } |
118 | ||
9b6b563c PM |
119 | /* Checks "l2cr=xxxx" command-line option */ |
120 | int __init ppc_setup_l2cr(char *str) | |
121 | { | |
122 | if (cpu_has_feature(CPU_FTR_L2CR)) { | |
123 | unsigned long val = simple_strtoul(str, NULL, 0); | |
124 | printk(KERN_INFO "l2cr set to %lx\n", val); | |
125 | _set_L2CR(0); /* force invalidate by disable cache */ | |
126 | _set_L2CR(val); /* and enable it */ | |
127 | } | |
128 | return 1; | |
129 | } | |
130 | __setup("l2cr=", ppc_setup_l2cr); | |
131 | ||
a78bfbfc RB |
132 | /* Checks "l3cr=xxxx" command-line option */ |
133 | int __init ppc_setup_l3cr(char *str) | |
134 | { | |
135 | if (cpu_has_feature(CPU_FTR_L3CR)) { | |
136 | unsigned long val = simple_strtoul(str, NULL, 0); | |
137 | printk(KERN_INFO "l3cr set to %lx\n", val); | |
138 | _set_L3CR(val); /* and enable it */ | |
139 | } | |
140 | return 1; | |
141 | } | |
142 | __setup("l3cr=", ppc_setup_l3cr); | |
143 | ||
9b6b563c PM |
144 | #ifdef CONFIG_GENERIC_NVRAM |
145 | ||
146 | /* Generic nvram hooks used by drivers/char/gen_nvram.c */ | |
147 | unsigned char nvram_read_byte(int addr) | |
148 | { | |
149 | if (ppc_md.nvram_read_val) | |
150 | return ppc_md.nvram_read_val(addr); | |
151 | return 0xff; | |
152 | } | |
153 | EXPORT_SYMBOL(nvram_read_byte); | |
154 | ||
155 | void nvram_write_byte(unsigned char val, int addr) | |
156 | { | |
157 | if (ppc_md.nvram_write_val) | |
158 | ppc_md.nvram_write_val(addr, val); | |
159 | } | |
160 | EXPORT_SYMBOL(nvram_write_byte); | |
161 | ||
d331d830 MW |
162 | ssize_t nvram_get_size(void) |
163 | { | |
164 | if (ppc_md.nvram_size) | |
165 | return ppc_md.nvram_size(); | |
166 | return -1; | |
167 | } | |
168 | EXPORT_SYMBOL(nvram_get_size); | |
169 | ||
9b6b563c PM |
170 | void nvram_sync(void) |
171 | { | |
172 | if (ppc_md.nvram_sync) | |
173 | ppc_md.nvram_sync(); | |
174 | } | |
175 | EXPORT_SYMBOL(nvram_sync); | |
176 | ||
177 | #endif /* CONFIG_NVRAM */ | |
178 | ||
9b6b563c PM |
179 | int __init ppc_init(void) |
180 | { | |
9b6b563c | 181 | /* clear the progress line */ |
5e41763a GP |
182 | if (ppc_md.progress) |
183 | ppc_md.progress(" ", 0xffff); | |
9b6b563c | 184 | |
9b6b563c PM |
185 | /* call platform init */ |
186 | if (ppc_md.init != NULL) { | |
187 | ppc_md.init(); | |
188 | } | |
189 | return 0; | |
190 | } | |
191 | ||
192 | arch_initcall(ppc_init); | |
193 | ||
b1923caa | 194 | void __init irqstack_early_init(void) |
85218827 KG |
195 | { |
196 | unsigned int i; | |
197 | ||
198 | /* interrupt stacks must be in lowmem, we get that for free on ppc32 | |
e63075a3 | 199 | * as the memblock is limited to lowmem by default */ |
85218827 KG |
200 | for_each_possible_cpu(i) { |
201 | softirq_ctx[i] = (struct thread_info *) | |
95f72d1e | 202 | __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); |
85218827 | 203 | hardirq_ctx[i] = (struct thread_info *) |
95f72d1e | 204 | __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); |
85218827 KG |
205 | } |
206 | } | |
85218827 | 207 | |
bcf0b088 | 208 | #if defined(CONFIG_BOOKE) || defined(CONFIG_40x) |
b1923caa | 209 | void __init exc_lvl_early_init(void) |
bcf0b088 | 210 | { |
3e7f45ad | 211 | unsigned int i, hw_cpu; |
bcf0b088 KG |
212 | |
213 | /* interrupt stacks must be in lowmem, we get that for free on ppc32 | |
95f72d1e | 214 | * as the memblock is limited to lowmem by MEMBLOCK_REAL_LIMIT */ |
bcf0b088 | 215 | for_each_possible_cpu(i) { |
04a34113 | 216 | #ifdef CONFIG_SMP |
3e7f45ad | 217 | hw_cpu = get_hard_smp_processor_id(i); |
04a34113 KH |
218 | #else |
219 | hw_cpu = 0; | |
220 | #endif | |
221 | ||
3e7f45ad | 222 | critirq_ctx[hw_cpu] = (struct thread_info *) |
95f72d1e | 223 | __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); |
bcf0b088 | 224 | #ifdef CONFIG_BOOKE |
3e7f45ad | 225 | dbgirq_ctx[hw_cpu] = (struct thread_info *) |
95f72d1e | 226 | __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); |
3e7f45ad | 227 | mcheckirq_ctx[hw_cpu] = (struct thread_info *) |
95f72d1e | 228 | __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); |
bcf0b088 KG |
229 | #endif |
230 | } | |
231 | } | |
bcf0b088 KG |
232 | #endif |
233 | ||
b1923caa | 234 | void __init setup_power_save(void) |
56571384 BH |
235 | { |
236 | #ifdef CONFIG_6xx | |
237 | if (cpu_has_feature(CPU_FTR_CAN_DOZE) || | |
238 | cpu_has_feature(CPU_FTR_CAN_NAP)) | |
239 | ppc_md.power_save = ppc6xx_idle; | |
240 | #endif | |
241 | ||
242 | #ifdef CONFIG_E500 | |
243 | if (cpu_has_feature(CPU_FTR_CAN_DOZE) || | |
244 | cpu_has_feature(CPU_FTR_CAN_NAP)) | |
245 | ppc_md.power_save = e500_idle; | |
246 | #endif | |
247 | } | |
248 | ||
b1923caa | 249 | __init void initialize_cache_info(void) |
8f212cb2 BH |
250 | { |
251 | /* | |
252 | * Set cache line size based on type of cpu as a default. | |
253 | * Systems with OF can look in the properties on the cpu node(s) | |
254 | * for a possibly more accurate value. | |
255 | */ | |
256 | dcache_bsize = cur_cpu_spec->dcache_bsize; | |
257 | icache_bsize = cur_cpu_spec->icache_bsize; | |
258 | ucache_bsize = 0; | |
259 | if (cpu_has_feature(CPU_FTR_UNIFIED_ID_CACHE)) | |
260 | ucache_bsize = icache_bsize = dcache_bsize; | |
261 | } |