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Commit | Line | Data |
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40ef8cbc PM |
1 | /* |
2 | * | |
3 | * Common boot and setup code. | |
4 | * | |
5 | * Copyright (C) 2001 PPC64 Team, IBM Corp | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version | |
10 | * 2 of the License, or (at your option) any later version. | |
11 | */ | |
12 | ||
7191b615 | 13 | #define DEBUG |
40ef8cbc | 14 | |
4b16f8e2 | 15 | #include <linux/export.h> |
40ef8cbc PM |
16 | #include <linux/string.h> |
17 | #include <linux/sched.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/reboot.h> | |
21 | #include <linux/delay.h> | |
22 | #include <linux/initrd.h> | |
40ef8cbc PM |
23 | #include <linux/seq_file.h> |
24 | #include <linux/ioport.h> | |
25 | #include <linux/console.h> | |
26 | #include <linux/utsname.h> | |
27 | #include <linux/tty.h> | |
28 | #include <linux/root_dev.h> | |
29 | #include <linux/notifier.h> | |
30 | #include <linux/cpu.h> | |
31 | #include <linux/unistd.h> | |
32 | #include <linux/serial.h> | |
33 | #include <linux/serial_8250.h> | |
7a0268fa | 34 | #include <linux/bootmem.h> |
12d04eef | 35 | #include <linux/pci.h> |
945feb17 | 36 | #include <linux/lockdep.h> |
95f72d1e | 37 | #include <linux/memblock.h> |
a6146888 BB |
38 | #include <linux/hugetlb.h> |
39 | ||
40ef8cbc | 40 | #include <asm/io.h> |
0cc4746c | 41 | #include <asm/kdump.h> |
40ef8cbc PM |
42 | #include <asm/prom.h> |
43 | #include <asm/processor.h> | |
44 | #include <asm/pgtable.h> | |
40ef8cbc PM |
45 | #include <asm/smp.h> |
46 | #include <asm/elf.h> | |
47 | #include <asm/machdep.h> | |
48 | #include <asm/paca.h> | |
40ef8cbc PM |
49 | #include <asm/time.h> |
50 | #include <asm/cputable.h> | |
51 | #include <asm/sections.h> | |
52 | #include <asm/btext.h> | |
53 | #include <asm/nvram.h> | |
54 | #include <asm/setup.h> | |
40ef8cbc PM |
55 | #include <asm/rtas.h> |
56 | #include <asm/iommu.h> | |
57 | #include <asm/serial.h> | |
58 | #include <asm/cache.h> | |
59 | #include <asm/page.h> | |
60 | #include <asm/mmu.h> | |
40ef8cbc | 61 | #include <asm/firmware.h> |
f78541dc | 62 | #include <asm/xmon.h> |
dcad47fc | 63 | #include <asm/udbg.h> |
593e537b | 64 | #include <asm/kexec.h> |
25d21ad6 | 65 | #include <asm/mmu_context.h> |
d36b4c4f | 66 | #include <asm/code-patching.h> |
aa04b4cc | 67 | #include <asm/kvm_ppc.h> |
a6146888 | 68 | #include <asm/hugetlb.h> |
4e21b94c | 69 | #include <asm/epapr_hcalls.h> |
40ef8cbc PM |
70 | |
71 | #ifdef DEBUG | |
72 | #define DBG(fmt...) udbg_printf(fmt) | |
73 | #else | |
74 | #define DBG(fmt...) | |
75 | #endif | |
76 | ||
8246aca7 | 77 | int spinning_secondaries; |
40ef8cbc PM |
78 | u64 ppc64_pft_size; |
79 | ||
dabcafd3 OJ |
80 | /* Pick defaults since we might want to patch instructions |
81 | * before we've read this from the device tree. | |
82 | */ | |
83 | struct ppc64_caches ppc64_caches = { | |
5a2fe38d OJ |
84 | .dline_size = 0x40, |
85 | .log_dline_size = 6, | |
86 | .iline_size = 0x40, | |
87 | .log_iline_size = 6 | |
dabcafd3 | 88 | }; |
40ef8cbc PM |
89 | EXPORT_SYMBOL_GPL(ppc64_caches); |
90 | ||
91 | /* | |
92 | * These are used in binfmt_elf.c to put aux entries on the stack | |
93 | * for each elf executable being started. | |
94 | */ | |
95 | int dcache_bsize; | |
96 | int icache_bsize; | |
97 | int ucache_bsize; | |
98 | ||
28efc35f SW |
99 | #if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP) |
100 | static void setup_tlb_core_data(void) | |
101 | { | |
102 | int cpu; | |
103 | ||
82d86de2 SW |
104 | BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0); |
105 | ||
28efc35f SW |
106 | for_each_possible_cpu(cpu) { |
107 | int first = cpu_first_thread_sibling(cpu); | |
108 | ||
109 | paca[cpu].tcd_ptr = &paca[first].tcd; | |
110 | ||
111 | /* | |
112 | * If we have threads, we need either tlbsrx. | |
113 | * or e6500 tablewalk mode, or else TLB handlers | |
114 | * will be racy and could produce duplicate entries. | |
115 | */ | |
116 | if (smt_enabled_at_boot >= 2 && | |
117 | !mmu_has_feature(MMU_FTR_USE_TLBRSRV) && | |
118 | book3e_htw_mode != PPC_HTW_E6500) { | |
119 | /* Should we panic instead? */ | |
120 | WARN_ONCE("%s: unsupported MMU configuration -- expect problems\n", | |
121 | __func__); | |
122 | } | |
123 | } | |
124 | } | |
125 | #else | |
126 | static void setup_tlb_core_data(void) | |
127 | { | |
128 | } | |
129 | #endif | |
130 | ||
40ef8cbc PM |
131 | #ifdef CONFIG_SMP |
132 | ||
954e6da5 | 133 | static char *smt_enabled_cmdline; |
40ef8cbc PM |
134 | |
135 | /* Look for ibm,smt-enabled OF option */ | |
136 | static void check_smt_enabled(void) | |
137 | { | |
138 | struct device_node *dn; | |
a7f67bdf | 139 | const char *smt_option; |
40ef8cbc | 140 | |
954e6da5 NF |
141 | /* Default to enabling all threads */ |
142 | smt_enabled_at_boot = threads_per_core; | |
40ef8cbc | 143 | |
954e6da5 NF |
144 | /* Allow the command line to overrule the OF option */ |
145 | if (smt_enabled_cmdline) { | |
146 | if (!strcmp(smt_enabled_cmdline, "on")) | |
147 | smt_enabled_at_boot = threads_per_core; | |
148 | else if (!strcmp(smt_enabled_cmdline, "off")) | |
149 | smt_enabled_at_boot = 0; | |
150 | else { | |
151 | long smt; | |
152 | int rc; | |
153 | ||
154 | rc = strict_strtol(smt_enabled_cmdline, 10, &smt); | |
155 | if (!rc) | |
156 | smt_enabled_at_boot = | |
157 | min(threads_per_core, (int)smt); | |
158 | } | |
159 | } else { | |
160 | dn = of_find_node_by_path("/options"); | |
161 | if (dn) { | |
162 | smt_option = of_get_property(dn, "ibm,smt-enabled", | |
163 | NULL); | |
164 | ||
165 | if (smt_option) { | |
166 | if (!strcmp(smt_option, "on")) | |
167 | smt_enabled_at_boot = threads_per_core; | |
168 | else if (!strcmp(smt_option, "off")) | |
169 | smt_enabled_at_boot = 0; | |
170 | } | |
171 | ||
172 | of_node_put(dn); | |
173 | } | |
174 | } | |
40ef8cbc PM |
175 | } |
176 | ||
177 | /* Look for smt-enabled= cmdline option */ | |
178 | static int __init early_smt_enabled(char *p) | |
179 | { | |
954e6da5 | 180 | smt_enabled_cmdline = p; |
40ef8cbc PM |
181 | return 0; |
182 | } | |
183 | early_param("smt-enabled", early_smt_enabled); | |
184 | ||
5ad57078 PM |
185 | #else |
186 | #define check_smt_enabled() | |
40ef8cbc PM |
187 | #endif /* CONFIG_SMP */ |
188 | ||
25e13814 ME |
189 | /** Fix up paca fields required for the boot cpu */ |
190 | static void fixup_boot_paca(void) | |
191 | { | |
192 | /* The boot cpu is started */ | |
193 | get_paca()->cpu_start = 1; | |
194 | /* Allow percpu accesses to work until we setup percpu data */ | |
195 | get_paca()->data_offset = 0; | |
196 | } | |
197 | ||
8f619b54 BH |
198 | static void cpu_ready_for_interrupts(void) |
199 | { | |
200 | /* Set IR and DR in PACA MSR */ | |
201 | get_paca()->kernel_msr = MSR_KERNEL; | |
202 | ||
203 | /* Enable AIL if supported */ | |
18aa0da3 PM |
204 | if (cpu_has_feature(CPU_FTR_HVMODE) && |
205 | cpu_has_feature(CPU_FTR_ARCH_207S)) { | |
8f619b54 BH |
206 | unsigned long lpcr = mfspr(SPRN_LPCR); |
207 | mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3); | |
208 | } | |
209 | } | |
210 | ||
40ef8cbc PM |
211 | /* |
212 | * Early initialization entry point. This is called by head.S | |
213 | * with MMU translation disabled. We rely on the "feature" of | |
214 | * the CPU that ignores the top 2 bits of the address in real | |
215 | * mode so we can access kernel globals normally provided we | |
216 | * only toy with things in the RMO region. From here, we do | |
95f72d1e | 217 | * some early parsing of the device-tree to setup out MEMBLOCK |
40ef8cbc PM |
218 | * data structures, and allocate & initialize the hash table |
219 | * and segment tables so we can start running with translation | |
220 | * enabled. | |
221 | * | |
222 | * It is this function which will call the probe() callback of | |
223 | * the various platform types and copy the matching one to the | |
224 | * global ppc_md structure. Your platform can eventually do | |
225 | * some very early initializations from the probe() routine, but | |
226 | * this is not recommended, be very careful as, for example, the | |
227 | * device-tree is not accessible via normal means at this point. | |
228 | */ | |
229 | ||
230 | void __init early_setup(unsigned long dt_ptr) | |
231 | { | |
6a7e4064 GL |
232 | static __initdata struct paca_struct boot_paca; |
233 | ||
24d96495 BH |
234 | /* -------- printk is _NOT_ safe to use here ! ------- */ |
235 | ||
42c4aaad | 236 | /* Identify CPU type */ |
974a76f5 | 237 | identify_cpu(0, mfspr(SPRN_PVR)); |
42c4aaad | 238 | |
33dbcf72 | 239 | /* Assume we're on cpu 0 for now. Don't write to the paca yet! */ |
1426d5a3 ME |
240 | initialise_paca(&boot_paca, 0); |
241 | setup_paca(&boot_paca); | |
25e13814 | 242 | fixup_boot_paca(); |
33dbcf72 | 243 | |
945feb17 BH |
244 | /* Initialize lockdep early or else spinlocks will blow */ |
245 | lockdep_init(); | |
246 | ||
24d96495 BH |
247 | /* -------- printk is now safe to use ------- */ |
248 | ||
f2fd2513 BH |
249 | /* Enable early debugging if any specified (see udbg.h) */ |
250 | udbg_early_init(); | |
251 | ||
e8222502 | 252 | DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr); |
40ef8cbc | 253 | |
40ef8cbc | 254 | /* |
3c607ce2 LV |
255 | * Do early initialization using the flattened device |
256 | * tree, such as retrieving the physical memory map or | |
257 | * calculating/retrieving the hash table size. | |
40ef8cbc PM |
258 | */ |
259 | early_init_devtree(__va(dt_ptr)); | |
260 | ||
4e21b94c LT |
261 | epapr_paravirt_early_init(); |
262 | ||
4df20460 | 263 | /* Now we know the logical id of our boot cpu, setup the paca. */ |
1426d5a3 | 264 | setup_paca(&paca[boot_cpuid]); |
25e13814 | 265 | fixup_boot_paca(); |
4df20460 | 266 | |
e8222502 BH |
267 | /* Probe the machine type */ |
268 | probe_machine(); | |
40ef8cbc | 269 | |
47310413 | 270 | setup_kdump_trampoline(); |
0cc4746c | 271 | |
40ef8cbc PM |
272 | DBG("Found, Initializing memory management...\n"); |
273 | ||
757c74d2 BH |
274 | /* Initialize the hash table or TLB handling */ |
275 | early_init_mmu(); | |
40ef8cbc | 276 | |
a944a9c4 BH |
277 | /* |
278 | * At this point, we can let interrupts switch to virtual mode | |
279 | * (the MMU has been setup), so adjust the MSR in the PACA to | |
8f619b54 | 280 | * have IR and DR set and enable AIL if it exists |
a944a9c4 | 281 | */ |
8f619b54 | 282 | cpu_ready_for_interrupts(); |
a944a9c4 BH |
283 | |
284 | /* Reserve large chunks of memory for use by CMA for KVM */ | |
fa61a4e3 AK |
285 | kvm_cma_reserve(); |
286 | ||
a6146888 BB |
287 | /* |
288 | * Reserve any gigantic pages requested on the command line. | |
289 | * memblock needs to have been initialized by the time this is | |
290 | * called since this will reserve memory. | |
291 | */ | |
292 | reserve_hugetlb_gpages(); | |
293 | ||
40ef8cbc | 294 | DBG(" <- early_setup()\n"); |
7191b615 BH |
295 | |
296 | #ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX | |
297 | /* | |
298 | * This needs to be done *last* (after the above DBG() even) | |
299 | * | |
300 | * Right after we return from this function, we turn on the MMU | |
301 | * which means the real-mode access trick that btext does will | |
302 | * no longer work, it needs to switch to using a real MMU | |
303 | * mapping. This call will ensure that it does | |
304 | */ | |
305 | btext_map(); | |
306 | #endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */ | |
40ef8cbc PM |
307 | } |
308 | ||
799d6046 PM |
309 | #ifdef CONFIG_SMP |
310 | void early_setup_secondary(void) | |
311 | { | |
d04c56f7 | 312 | /* Mark interrupts enabled in PACA */ |
757c74d2 | 313 | get_paca()->soft_enabled = 0; |
799d6046 | 314 | |
757c74d2 BH |
315 | /* Initialize the hash table or TLB handling */ |
316 | early_init_mmu_secondary(); | |
a944a9c4 BH |
317 | |
318 | /* | |
319 | * At this point, we can let interrupts switch to virtual mode | |
320 | * (the MMU has been setup), so adjust the MSR in the PACA to | |
321 | * have IR and DR set. | |
322 | */ | |
8f619b54 | 323 | cpu_ready_for_interrupts(); |
799d6046 PM |
324 | } |
325 | ||
326 | #endif /* CONFIG_SMP */ | |
40ef8cbc | 327 | |
b8f51021 ME |
328 | #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC) |
329 | void smp_release_cpus(void) | |
330 | { | |
758438a7 | 331 | unsigned long *ptr; |
9d07bc84 | 332 | int i; |
b8f51021 ME |
333 | |
334 | DBG(" -> smp_release_cpus()\n"); | |
335 | ||
336 | /* All secondary cpus are spinning on a common spinloop, release them | |
337 | * all now so they can start to spin on their individual paca | |
338 | * spinloops. For non SMP kernels, the secondary cpus never get out | |
339 | * of the common spinloop. | |
1f6a93e4 | 340 | */ |
b8f51021 | 341 | |
758438a7 ME |
342 | ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop |
343 | - PHYSICAL_START); | |
1f6a93e4 | 344 | *ptr = __pa(generic_secondary_smp_init); |
9d07bc84 BH |
345 | |
346 | /* And wait a bit for them to catch up */ | |
347 | for (i = 0; i < 100000; i++) { | |
348 | mb(); | |
349 | HMT_low(); | |
7ac87abb | 350 | if (spinning_secondaries == 0) |
9d07bc84 BH |
351 | break; |
352 | udelay(1); | |
353 | } | |
7ac87abb | 354 | DBG("spinning_secondaries = %d\n", spinning_secondaries); |
b8f51021 ME |
355 | |
356 | DBG(" <- smp_release_cpus()\n"); | |
357 | } | |
358 | #endif /* CONFIG_SMP || CONFIG_KEXEC */ | |
359 | ||
40ef8cbc | 360 | /* |
799d6046 PM |
361 | * Initialize some remaining members of the ppc64_caches and systemcfg |
362 | * structures | |
40ef8cbc PM |
363 | * (at least until we get rid of them completely). This is mostly some |
364 | * cache informations about the CPU that will be used by cache flush | |
365 | * routines and/or provided to userland | |
366 | */ | |
367 | static void __init initialize_cache_info(void) | |
368 | { | |
369 | struct device_node *np; | |
370 | unsigned long num_cpus = 0; | |
371 | ||
372 | DBG(" -> initialize_cache_info()\n"); | |
373 | ||
94db7c5e | 374 | for_each_node_by_type(np, "cpu") { |
40ef8cbc PM |
375 | num_cpus += 1; |
376 | ||
dfbe93a2 AB |
377 | /* |
378 | * We're assuming *all* of the CPUs have the same | |
40ef8cbc PM |
379 | * d-cache and i-cache sizes... -Peter |
380 | */ | |
dfbe93a2 | 381 | if (num_cpus == 1) { |
7946d5a5 | 382 | const __be32 *sizep, *lsizep; |
40ef8cbc | 383 | u32 size, lsize; |
40ef8cbc PM |
384 | |
385 | size = 0; | |
386 | lsize = cur_cpu_spec->dcache_bsize; | |
e2eb6392 | 387 | sizep = of_get_property(np, "d-cache-size", NULL); |
40ef8cbc | 388 | if (sizep != NULL) |
7946d5a5 | 389 | size = be32_to_cpu(*sizep); |
dfbe93a2 AB |
390 | lsizep = of_get_property(np, "d-cache-block-size", |
391 | NULL); | |
20474abd BH |
392 | /* fallback if block size missing */ |
393 | if (lsizep == NULL) | |
dfbe93a2 AB |
394 | lsizep = of_get_property(np, |
395 | "d-cache-line-size", | |
396 | NULL); | |
40ef8cbc | 397 | if (lsizep != NULL) |
7946d5a5 | 398 | lsize = be32_to_cpu(*lsizep); |
b0d436c7 | 399 | if (sizep == NULL || lsizep == NULL) |
40ef8cbc PM |
400 | DBG("Argh, can't find dcache properties ! " |
401 | "sizep: %p, lsizep: %p\n", sizep, lsizep); | |
402 | ||
a7f290da BH |
403 | ppc64_caches.dsize = size; |
404 | ppc64_caches.dline_size = lsize; | |
40ef8cbc PM |
405 | ppc64_caches.log_dline_size = __ilog2(lsize); |
406 | ppc64_caches.dlines_per_page = PAGE_SIZE / lsize; | |
407 | ||
408 | size = 0; | |
409 | lsize = cur_cpu_spec->icache_bsize; | |
e2eb6392 | 410 | sizep = of_get_property(np, "i-cache-size", NULL); |
40ef8cbc | 411 | if (sizep != NULL) |
7946d5a5 | 412 | size = be32_to_cpu(*sizep); |
dfbe93a2 AB |
413 | lsizep = of_get_property(np, "i-cache-block-size", |
414 | NULL); | |
20474abd | 415 | if (lsizep == NULL) |
dfbe93a2 AB |
416 | lsizep = of_get_property(np, |
417 | "i-cache-line-size", | |
418 | NULL); | |
40ef8cbc | 419 | if (lsizep != NULL) |
7946d5a5 | 420 | lsize = be32_to_cpu(*lsizep); |
b0d436c7 | 421 | if (sizep == NULL || lsizep == NULL) |
40ef8cbc PM |
422 | DBG("Argh, can't find icache properties ! " |
423 | "sizep: %p, lsizep: %p\n", sizep, lsizep); | |
424 | ||
a7f290da BH |
425 | ppc64_caches.isize = size; |
426 | ppc64_caches.iline_size = lsize; | |
40ef8cbc PM |
427 | ppc64_caches.log_iline_size = __ilog2(lsize); |
428 | ppc64_caches.ilines_per_page = PAGE_SIZE / lsize; | |
429 | } | |
430 | } | |
431 | ||
40ef8cbc PM |
432 | DBG(" <- initialize_cache_info()\n"); |
433 | } | |
434 | ||
40ef8cbc PM |
435 | |
436 | /* | |
437 | * Do some initial setup of the system. The parameters are those which | |
438 | * were passed in from the bootloader. | |
439 | */ | |
440 | void __init setup_system(void) | |
441 | { | |
442 | DBG(" -> setup_system()\n"); | |
443 | ||
826ea8f2 TB |
444 | /* Apply the CPUs-specific and firmware specific fixups to kernel |
445 | * text (nop out sections not relevant to this CPU or this firmware) | |
42c4aaad | 446 | */ |
0909c8c2 | 447 | do_feature_fixups(cur_cpu_spec->cpu_features, |
42c4aaad | 448 | &__start___ftr_fixup, &__stop___ftr_fixup); |
7c03d653 BH |
449 | do_feature_fixups(cur_cpu_spec->mmu_features, |
450 | &__start___mmu_ftr_fixup, &__stop___mmu_ftr_fixup); | |
826ea8f2 TB |
451 | do_feature_fixups(powerpc_firmware_features, |
452 | &__start___fw_ftr_fixup, &__stop___fw_ftr_fixup); | |
2d1b2027 KG |
453 | do_lwsync_fixups(cur_cpu_spec->cpu_features, |
454 | &__start___lwsync_fixup, &__stop___lwsync_fixup); | |
d715e433 | 455 | do_final_fixups(); |
42c4aaad | 456 | |
40ef8cbc PM |
457 | /* |
458 | * Unflatten the device-tree passed by prom_init or kexec | |
459 | */ | |
460 | unflatten_device_tree(); | |
461 | ||
462 | /* | |
463 | * Fill the ppc64_caches & systemcfg structures with informations | |
0ebfff14 | 464 | * retrieved from the device-tree. |
40ef8cbc PM |
465 | */ |
466 | initialize_cache_info(); | |
467 | ||
468 | #ifdef CONFIG_PPC_RTAS | |
469 | /* | |
470 | * Initialize RTAS if available | |
471 | */ | |
472 | rtas_initialize(); | |
473 | #endif /* CONFIG_PPC_RTAS */ | |
40ef8cbc PM |
474 | |
475 | /* | |
476 | * Check if we have an initrd provided via the device-tree | |
477 | */ | |
478 | check_for_initrd(); | |
40ef8cbc PM |
479 | |
480 | /* | |
481 | * Do some platform specific early initializations, that includes | |
482 | * setting up the hash table pointers. It also sets up some interrupt-mapping | |
483 | * related options that will be used by finish_device_tree() | |
484 | */ | |
57744ea9 GL |
485 | if (ppc_md.init_early) |
486 | ppc_md.init_early(); | |
40ef8cbc | 487 | |
463ce0e1 BH |
488 | /* |
489 | * We can discover serial ports now since the above did setup the | |
490 | * hash table management for us, thus ioremap works. We do that early | |
491 | * so that further code can be debugged | |
492 | */ | |
463ce0e1 | 493 | find_legacy_serial_ports(); |
463ce0e1 | 494 | |
40ef8cbc PM |
495 | /* |
496 | * Register early console | |
497 | */ | |
498 | register_early_udbg_console(); | |
40ef8cbc | 499 | |
47679283 ME |
500 | /* |
501 | * Initialize xmon | |
502 | */ | |
503 | xmon_setup(); | |
480f6f35 | 504 | |
5ad57078 | 505 | smp_setup_cpu_maps(); |
954e6da5 | 506 | check_smt_enabled(); |
28efc35f | 507 | setup_tlb_core_data(); |
40ef8cbc | 508 | |
f018b36f | 509 | #ifdef CONFIG_SMP |
40ef8cbc PM |
510 | /* Release secondary cpus out of their spinloops at 0x60 now that |
511 | * we can map physical -> logical CPU ids | |
512 | */ | |
513 | smp_release_cpus(); | |
f018b36f | 514 | #endif |
40ef8cbc | 515 | |
96b644bd | 516 | printk("Starting Linux PPC64 %s\n", init_utsname()->version); |
40ef8cbc PM |
517 | |
518 | printk("-----------------------------------------------------\n"); | |
fe333321 | 519 | printk("ppc64_pft_size = 0x%llx\n", ppc64_pft_size); |
95f72d1e | 520 | printk("physicalMemorySize = 0x%llx\n", memblock_phys_mem_size()); |
9697add0 AB |
521 | if (ppc64_caches.dline_size != 0x80) |
522 | printk("ppc64_caches.dcache_line_size = 0x%x\n", | |
523 | ppc64_caches.dline_size); | |
524 | if (ppc64_caches.iline_size != 0x80) | |
525 | printk("ppc64_caches.icache_line_size = 0x%x\n", | |
526 | ppc64_caches.iline_size); | |
94491685 | 527 | #ifdef CONFIG_PPC_STD_MMU_64 |
9697add0 AB |
528 | if (htab_address) |
529 | printk("htab_address = 0x%p\n", htab_address); | |
40ef8cbc | 530 | printk("htab_hash_mask = 0x%lx\n", htab_hash_mask); |
94491685 | 531 | #endif /* CONFIG_PPC_STD_MMU_64 */ |
b160544c | 532 | if (PHYSICAL_START > 0) |
e468455e ME |
533 | printk("physical_start = 0x%llx\n", |
534 | (unsigned long long)PHYSICAL_START); | |
40ef8cbc | 535 | printk("-----------------------------------------------------\n"); |
40ef8cbc | 536 | |
40ef8cbc PM |
537 | DBG(" <- setup_system()\n"); |
538 | } | |
539 | ||
40bd587a BH |
540 | /* This returns the limit below which memory accesses to the linear |
541 | * mapping are guarnateed not to cause a TLB or SLB miss. This is | |
542 | * used to allocate interrupt or emergency stacks for which our | |
543 | * exception entry path doesn't deal with being interrupted. | |
544 | */ | |
545 | static u64 safe_stack_limit(void) | |
095c7965 | 546 | { |
40bd587a BH |
547 | #ifdef CONFIG_PPC_BOOK3E |
548 | /* Freescale BookE bolts the entire linear mapping */ | |
549 | if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) | |
550 | return linear_map_top; | |
551 | /* Other BookE, we assume the first GB is bolted */ | |
552 | return 1ul << 30; | |
553 | #else | |
554 | /* BookS, the first segment is bolted */ | |
555 | if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) | |
095c7965 | 556 | return 1UL << SID_SHIFT_1T; |
095c7965 | 557 | return 1UL << SID_SHIFT; |
40bd587a | 558 | #endif |
095c7965 AB |
559 | } |
560 | ||
40ef8cbc PM |
561 | static void __init irqstack_early_init(void) |
562 | { | |
40bd587a | 563 | u64 limit = safe_stack_limit(); |
40ef8cbc PM |
564 | unsigned int i; |
565 | ||
566 | /* | |
8f4da26e AB |
567 | * Interrupt stacks must be in the first segment since we |
568 | * cannot afford to take SLB misses on them. | |
40ef8cbc | 569 | */ |
0e551954 | 570 | for_each_possible_cpu(i) { |
3c726f8d | 571 | softirq_ctx[i] = (struct thread_info *) |
95f72d1e | 572 | __va(memblock_alloc_base(THREAD_SIZE, |
095c7965 | 573 | THREAD_SIZE, limit)); |
3c726f8d | 574 | hardirq_ctx[i] = (struct thread_info *) |
95f72d1e | 575 | __va(memblock_alloc_base(THREAD_SIZE, |
095c7965 | 576 | THREAD_SIZE, limit)); |
40ef8cbc PM |
577 | } |
578 | } | |
40ef8cbc | 579 | |
2d27cfd3 BH |
580 | #ifdef CONFIG_PPC_BOOK3E |
581 | static void __init exc_lvl_early_init(void) | |
582 | { | |
583 | unsigned int i; | |
160c7324 | 584 | unsigned long sp; |
2d27cfd3 BH |
585 | |
586 | for_each_possible_cpu(i) { | |
160c7324 TC |
587 | sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); |
588 | critirq_ctx[i] = (struct thread_info *)__va(sp); | |
589 | paca[i].crit_kstack = __va(sp + THREAD_SIZE); | |
590 | ||
591 | sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); | |
592 | dbgirq_ctx[i] = (struct thread_info *)__va(sp); | |
593 | paca[i].dbg_kstack = __va(sp + THREAD_SIZE); | |
594 | ||
595 | sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); | |
596 | mcheckirq_ctx[i] = (struct thread_info *)__va(sp); | |
597 | paca[i].mc_kstack = __va(sp + THREAD_SIZE); | |
2d27cfd3 | 598 | } |
d36b4c4f KG |
599 | |
600 | if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC)) | |
565c2f24 | 601 | patch_exception(0x040, exc_debug_debug_book3e); |
2d27cfd3 BH |
602 | } |
603 | #else | |
604 | #define exc_lvl_early_init() | |
605 | #endif | |
606 | ||
40ef8cbc PM |
607 | /* |
608 | * Stack space used when we detect a bad kernel stack pointer, and | |
729b0f71 MS |
609 | * early in SMP boots before relocation is enabled. Exclusive emergency |
610 | * stack for machine checks. | |
40ef8cbc PM |
611 | */ |
612 | static void __init emergency_stack_init(void) | |
613 | { | |
095c7965 | 614 | u64 limit; |
40ef8cbc PM |
615 | unsigned int i; |
616 | ||
617 | /* | |
618 | * Emergency stacks must be under 256MB, we cannot afford to take | |
619 | * SLB misses on them. The ABI also requires them to be 128-byte | |
620 | * aligned. | |
621 | * | |
622 | * Since we use these as temporary stacks during secondary CPU | |
623 | * bringup, we need to get at them in real mode. This means they | |
624 | * must also be within the RMO region. | |
625 | */ | |
40bd587a | 626 | limit = min(safe_stack_limit(), ppc64_rma_size); |
40ef8cbc | 627 | |
3243d874 ME |
628 | for_each_possible_cpu(i) { |
629 | unsigned long sp; | |
95f72d1e | 630 | sp = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit); |
3243d874 ME |
631 | sp += THREAD_SIZE; |
632 | paca[i].emergency_sp = __va(sp); | |
729b0f71 MS |
633 | |
634 | #ifdef CONFIG_PPC_BOOK3S_64 | |
635 | /* emergency stack for machine check exception handling. */ | |
636 | sp = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit); | |
637 | sp += THREAD_SIZE; | |
638 | paca[i].mc_emergency_sp = __va(sp); | |
639 | #endif | |
3243d874 | 640 | } |
40ef8cbc PM |
641 | } |
642 | ||
40ef8cbc | 643 | /* |
0f6b77ca AIB |
644 | * Called into from start_kernel this initializes bootmem, which is used |
645 | * to manage page allocation until mem_init is called. | |
40ef8cbc PM |
646 | */ |
647 | void __init setup_arch(char **cmdline_p) | |
648 | { | |
40ef8cbc PM |
649 | ppc64_boot_msg(0x12, "Setup Arch"); |
650 | ||
651 | *cmdline_p = cmd_line; | |
652 | ||
653 | /* | |
654 | * Set cache line size based on type of cpu as a default. | |
655 | * Systems with OF can look in the properties on the cpu node(s) | |
656 | * for a possibly more accurate value. | |
657 | */ | |
658 | dcache_bsize = ppc64_caches.dline_size; | |
659 | icache_bsize = ppc64_caches.iline_size; | |
660 | ||
40ef8cbc | 661 | if (ppc_md.panic) |
7e990266 | 662 | setup_panic(); |
40ef8cbc | 663 | |
4846c5de | 664 | init_mm.start_code = (unsigned long)_stext; |
40ef8cbc PM |
665 | init_mm.end_code = (unsigned long) _etext; |
666 | init_mm.end_data = (unsigned long) _edata; | |
667 | init_mm.brk = klimit; | |
5c1f6ee9 AK |
668 | #ifdef CONFIG_PPC_64K_PAGES |
669 | init_mm.context.pte_frag = NULL; | |
670 | #endif | |
40ef8cbc | 671 | irqstack_early_init(); |
2d27cfd3 | 672 | exc_lvl_early_init(); |
40ef8cbc PM |
673 | emergency_stack_init(); |
674 | ||
94491685 | 675 | #ifdef CONFIG_PPC_STD_MMU_64 |
40ef8cbc | 676 | stabs_alloc(); |
94491685 | 677 | #endif |
40ef8cbc PM |
678 | /* set up the bootmem stuff with available memory */ |
679 | do_init_bootmem(); | |
680 | sparse_init(); | |
681 | ||
0458060c PM |
682 | #ifdef CONFIG_DUMMY_CONSOLE |
683 | conswitchp = &dummy_con; | |
684 | #endif | |
685 | ||
38db7e74 GL |
686 | if (ppc_md.setup_arch) |
687 | ppc_md.setup_arch(); | |
40ef8cbc | 688 | |
40ef8cbc | 689 | paging_init(); |
6f0ef0f5 BH |
690 | |
691 | /* Initialize the MMU context management stuff */ | |
692 | mmu_context_init(); | |
693 | ||
61e2390e MN |
694 | /* Interrupt code needs to be 64K-aligned */ |
695 | if ((unsigned long)_stext & 0xffff) | |
696 | panic("Kernelbase not 64K-aligned (0x%lx)!\n", | |
697 | (unsigned long)_stext); | |
698 | ||
40ef8cbc PM |
699 | ppc64_boot_msg(0x15, "Setup Done"); |
700 | } | |
701 | ||
702 | ||
703 | /* ToDo: do something useful if ppc_md is not yet setup. */ | |
704 | #define PPC64_LINUX_FUNCTION 0x0f000000 | |
705 | #define PPC64_IPL_MESSAGE 0xc0000000 | |
706 | #define PPC64_TERM_MESSAGE 0xb0000000 | |
707 | ||
708 | static void ppc64_do_msg(unsigned int src, const char *msg) | |
709 | { | |
710 | if (ppc_md.progress) { | |
711 | char buf[128]; | |
712 | ||
713 | sprintf(buf, "%08X\n", src); | |
714 | ppc_md.progress(buf, 0); | |
715 | snprintf(buf, 128, "%s", msg); | |
716 | ppc_md.progress(buf, 0); | |
717 | } | |
718 | } | |
719 | ||
720 | /* Print a boot progress message. */ | |
721 | void ppc64_boot_msg(unsigned int src, const char *msg) | |
722 | { | |
723 | ppc64_do_msg(PPC64_LINUX_FUNCTION|PPC64_IPL_MESSAGE|src, msg); | |
724 | printk("[boot]%04x %s\n", src, msg); | |
725 | } | |
726 | ||
7a0268fa | 727 | #ifdef CONFIG_SMP |
c2a7e818 TH |
728 | #define PCPU_DYN_SIZE () |
729 | ||
730 | static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align) | |
7a0268fa | 731 | { |
c2a7e818 TH |
732 | return __alloc_bootmem_node(NODE_DATA(cpu_to_node(cpu)), size, align, |
733 | __pa(MAX_DMA_ADDRESS)); | |
734 | } | |
7a0268fa | 735 | |
c2a7e818 TH |
736 | static void __init pcpu_fc_free(void *ptr, size_t size) |
737 | { | |
738 | free_bootmem(__pa(ptr), size); | |
739 | } | |
7a0268fa | 740 | |
c2a7e818 TH |
741 | static int pcpu_cpu_distance(unsigned int from, unsigned int to) |
742 | { | |
743 | if (cpu_to_node(from) == cpu_to_node(to)) | |
744 | return LOCAL_DISTANCE; | |
745 | else | |
746 | return REMOTE_DISTANCE; | |
747 | } | |
748 | ||
ae01f84b AB |
749 | unsigned long __per_cpu_offset[NR_CPUS] __read_mostly; |
750 | EXPORT_SYMBOL(__per_cpu_offset); | |
751 | ||
c2a7e818 TH |
752 | void __init setup_per_cpu_areas(void) |
753 | { | |
754 | const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE; | |
755 | size_t atom_size; | |
756 | unsigned long delta; | |
757 | unsigned int cpu; | |
758 | int rc; | |
759 | ||
760 | /* | |
761 | * Linear mapping is one of 4K, 1M and 16M. For 4K, no need | |
762 | * to group units. For larger mappings, use 1M atom which | |
763 | * should be large enough to contain a number of units. | |
764 | */ | |
765 | if (mmu_linear_psize == MMU_PAGE_4K) | |
766 | atom_size = PAGE_SIZE; | |
767 | else | |
768 | atom_size = 1 << 20; | |
769 | ||
770 | rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance, | |
771 | pcpu_fc_alloc, pcpu_fc_free); | |
772 | if (rc < 0) | |
773 | panic("cannot initialize percpu area (err=%d)", rc); | |
774 | ||
775 | delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start; | |
ae01f84b AB |
776 | for_each_possible_cpu(cpu) { |
777 | __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu]; | |
778 | paca[cpu].data_offset = __per_cpu_offset[cpu]; | |
779 | } | |
7a0268fa AB |
780 | } |
781 | #endif | |
4cb3cee0 BH |
782 | |
783 | ||
ecd73cc5 | 784 | #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO) |
4cb3cee0 BH |
785 | struct ppc_pci_io ppc_pci_io; |
786 | EXPORT_SYMBOL(ppc_pci_io); | |
ecd73cc5 | 787 | #endif |