[mirror_ubuntu-zesty-kernel.git] / arch / powerpc / kernel / tm.S

/*
 * Transactional memory support routines to reclaim and recheckpoint
 * transactional process state.
 *
 * Copyright 2012 Matt Evans & Michael Neuling, IBM Corporation.
 */

#include <asm/asm-offsets.h>
#include <asm/ppc_asm.h>
#include <asm/ppc-opcode.h>
#include <asm/ptrace.h>
#include <asm/reg.h>
#include <asm/bug.h>

#ifdef CONFIG_VSX
/* See fpu.S, this is borrowed from there */
#define __SAVE_32FPRS_VSRS(n,c,base)		\
BEGIN_FTR_SECTION				\
	b	2f;				\
END_FTR_SECTION_IFSET(CPU_FTR_VSX);		\
	SAVE_32FPRS(n,base);			\
	b	3f;				\
2:	SAVE_32VSRS(n,c,base);			\
3:
#define __REST_32FPRS_VSRS(n,c,base)		\
BEGIN_FTR_SECTION				\
	b	2f;				\
END_FTR_SECTION_IFSET(CPU_FTR_VSX);		\
	REST_32FPRS(n,base);			\
	b	3f;				\
2:	REST_32VSRS(n,c,base);			\
3:
#else
#define __SAVE_32FPRS_VSRS(n,c,base)	SAVE_32FPRS(n, base)
#define __REST_32FPRS_VSRS(n,c,base)	REST_32FPRS(n, base)
#endif
#define SAVE_32FPRS_VSRS(n,c,base) \
	__SAVE_32FPRS_VSRS(n,__REG_##c,__REG_##base)
#define REST_32FPRS_VSRS(n,c,base) \
	__REST_32FPRS_VSRS(n,__REG_##c,__REG_##base)

/* Stack frame offsets for local variables. */
#define TM_FRAME_L0	TM_FRAME_SIZE-16
#define TM_FRAME_L1	TM_FRAME_SIZE-8


/* In order to access the TM SPRs, TM must be enabled.  So, do so: */
_GLOBAL(tm_enable)
	mfmsr	r4
	li	r3, MSR_TM >> 32
	sldi	r3, r3, 32
	and.	r0, r4, r3
	bne	1f
	or	r4, r4, r3
	mtmsrd	r4
1:	blr

_GLOBAL(tm_save_sprs)
	mfspr	r0, SPRN_TFHAR
	std	r0, THREAD_TM_TFHAR(r3)
	mfspr	r0, SPRN_TEXASR
	std	r0, THREAD_TM_TEXASR(r3)
	mfspr	r0, SPRN_TFIAR
	std	r0, THREAD_TM_TFIAR(r3)
	blr

_GLOBAL(tm_restore_sprs)
	ld	r0, THREAD_TM_TFHAR(r3)
	mtspr	SPRN_TFHAR, r0
	ld	r0, THREAD_TM_TEXASR(r3)
	mtspr	SPRN_TEXASR, r0
	ld	r0, THREAD_TM_TFIAR(r3)
	mtspr	SPRN_TFIAR, r0
	blr

	/* Passed an 8-bit failure cause as first argument. */
_GLOBAL(tm_abort)
	TABORT(R3)
	blr

/* void tm_reclaim(struct thread_struct *thread,
 *                 unsigned long orig_msr,
 *		   uint8_t cause)
 *
 *	- Performs a full reclaim.  This destroys outstanding
 *	  transactions and updates thread->regs.tm_ckpt_* with the
 *	  original checkpointed state.  Note that thread->regs is
 *	  unchanged.
 *	- FP regs are written back to thread->transact_fpr before
 *	  reclaiming.  These are the transactional (current) versions.
 *
 * Purpose is to both abort transactions of, and preserve the state of,
 * a transactions at a context switch. We preserve/restore both sets of process
 * state to restore them when the thread's scheduled again.  We continue in
 * userland as though nothing happened, but when the transaction is resumed
 * they will abort back to the checkpointed state we save out here.
 *
 * Call with IRQs off, stacks get all out of sync for some periods in here!
 */
_GLOBAL(tm_reclaim)
	mfcr	r6
	mflr	r0
	stw	r6, 8(r1)
	std	r0, 16(r1)
	std	r2, STK_GOT(r1)
	stdu	r1, -TM_FRAME_SIZE(r1)

	/* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD]. */

	std	r3, STK_PARAM(R3)(r1)
	std	r4, STK_PARAM(R4)(r1)
	SAVE_NVGPRS(r1)

	/* We need to setup MSR for VSX register save instructions. */
	mfmsr	r14
	mr	r15, r14
	ori	r15, r15, MSR_FP
	li	r16, 0
	ori	r16, r16, MSR_EE /* IRQs hard off */
	andc	r15, r15, r16
	oris	r15, r15, MSR_VEC@h
#ifdef CONFIG_VSX
	BEGIN_FTR_SECTION
	oris	r15,r15, MSR_VSX@h
	END_FTR_SECTION_IFSET(CPU_FTR_VSX)
#endif
	mtmsrd	r15
	std	r14, TM_FRAME_L0(r1)

	/* Do sanity check on MSR to make sure we are suspended */
	li	r7, (MSR_TS_S)@higher
	srdi	r6, r14, 32
	and	r6, r6, r7
1:	tdeqi   r6, 0
	EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0

	/* Stash the stack pointer away for use after reclaim */
	std	r1, PACAR1(r13)

	/* Clear MSR RI since we are about to change r1, EE is already off. */
	li	r4, 0
	mtmsrd	r4, 1

	/*
	 * BE CAREFUL HERE:
	 * At this point we can't take an SLB miss since we have MSR_RI
	 * off. Load only to/from the stack/paca which are in SLB bolted regions
	 * until we turn MSR RI back on.
	 *
	 * The moment we treclaim, ALL of our GPRs will switch
	 * to user register state.  (FPRs, CCR etc. also!)
	 * Use an sprg and a tm_scratch in the PACA to shuffle.
	 */
	TRECLAIM(R5)				/* Cause in r5 */

	/* ******************** GPRs ******************** */
	/* Stash the checkpointed r13 away in the scratch SPR and get the real
	 *  paca
	 */
	SET_SCRATCH0(r13)
	GET_PACA(r13)

	/* Stash the checkpointed r1 away in paca tm_scratch and get the real
	 * stack pointer back
	 */
	std	r1, PACATMSCRATCH(r13)
	ld	r1, PACAR1(r13)

	/* Store the PPR in r11 and reset to decent value */
	std	r11, GPR11(r1)			/* Temporary stash */

	/* Reset MSR RI so we can take SLB faults again */
	li	r11, MSR_RI
	mtmsrd	r11, 1

	mfspr	r11, SPRN_PPR
	HMT_MEDIUM

	/* Now get some more GPRS free */
	std	r7, GPR7(r1)			/* Temporary stash */
	std	r12, GPR12(r1)			/* ''   ''    ''   */
	ld	r12, STK_PARAM(R3)(r1)		/* Param 0, thread_struct * */

	std	r11, THREAD_TM_PPR(r12)		/* Store PPR and free r11 */

	addi	r7, r12, PT_CKPT_REGS		/* Thread's ckpt_regs */

	/* Make r7 look like an exception frame so that we
	 * can use the neat GPRx(n) macros.  r7 is NOT a pt_regs ptr!
	 */
	subi	r7, r7, STACK_FRAME_OVERHEAD

	/* Sync the userland GPRs 2-12, 14-31 to thread->regs: */
	SAVE_GPR(0, r7)				/* user r0 */
	SAVE_GPR(2, r7)			/* user r2 */
	SAVE_4GPRS(3, r7)			/* user r3-r6 */
	SAVE_GPR(8, r7)				/* user r8 */
	SAVE_GPR(9, r7)				/* user r9 */
	SAVE_GPR(10, r7)			/* user r10 */
	ld	r3, PACATMSCRATCH(r13)		/* user r1 */
	ld	r4, GPR7(r1)			/* user r7 */
	ld	r5, GPR11(r1)			/* user r11 */
	ld	r6, GPR12(r1)			/* user r12 */
	GET_SCRATCH0(8)				/* user r13 */
	std	r3, GPR1(r7)
	std	r4, GPR7(r7)
	std	r5, GPR11(r7)
	std	r6, GPR12(r7)
	std	r8, GPR13(r7)

	SAVE_NVGPRS(r7)				/* user r14-r31 */

	/* ******************** NIP ******************** */
	mfspr	r3, SPRN_TFHAR
	std	r3, _NIP(r7)			/* Returns to failhandler */
	/* The checkpointed NIP is ignored when rescheduling/rechkpting,
	 * but is used in signal return to 'wind back' to the abort handler.
	 */

	/* ******************** CR,LR,CCR,MSR ********** */
	mfctr	r3
	mflr	r4
	mfcr	r5
	mfxer	r6

	std	r3, _CTR(r7)
	std	r4, _LINK(r7)
	std	r5, _CCR(r7)
	std	r6, _XER(r7)


	/* ******************** TAR, DSCR ********** */
	mfspr	r3, SPRN_TAR
	mfspr	r4, SPRN_DSCR

	std	r3, THREAD_TM_TAR(r12)
	std	r4, THREAD_TM_DSCR(r12)

	/* MSR and flags:  We don't change CRs, and we don't need to alter
	 * MSR.
	 */


	/* ******************** FPR/VR/VSRs ************
	 * After reclaiming, capture the checkpointed FPRs/VRs /if used/.
	 *
	 * (If VSX used, FP and VMX are implied.  Or, we don't need to look
	 * at MSR.VSX as copying FP regs if .FP, vector regs if .VMX covers it.)
	 *
	 * We're passed the thread's MSR as the second parameter
	 *
	 * We enabled VEC/FP/VSX in the msr above, so we can execute these
	 * instructions!
	 */
	ld	r4, STK_PARAM(R4)(r1)		/* Second parameter, MSR * */
	mr	r3, r12
	andis.		r0, r4, MSR_VEC@h
	beq	dont_backup_vec

	addi	r7, r3, THREAD_CKVRSTATE
	SAVE_32VRS(0, r6, r7)	/* r6 scratch, r7 transact vr state */
	mfvscr	v0
	li	r6, VRSTATE_VSCR
	stvx	v0, r7, r6
dont_backup_vec:
	mfspr	r0, SPRN_VRSAVE
	std	r0, THREAD_CKVRSAVE(r3)

	andi.	r0, r4, MSR_FP
	beq	dont_backup_fp

	addi	r7, r3, THREAD_CKFPSTATE
	SAVE_32FPRS_VSRS(0, R6, R7)	/* r6 scratch, r7 transact fp state */

	mffs    fr0
	stfd    fr0,FPSTATE_FPSCR(r7)

dont_backup_fp:

	/* TM regs, incl TEXASR -- these live in thread_struct.  Note they've
	 * been updated by the treclaim, to explain to userland the failure
	 * cause (aborted).
	 */
	mfspr	r0, SPRN_TEXASR
	mfspr	r3, SPRN_TFHAR
	mfspr	r4, SPRN_TFIAR
	std	r0, THREAD_TM_TEXASR(r12)
	std	r3, THREAD_TM_TFHAR(r12)
	std	r4, THREAD_TM_TFIAR(r12)

	/* AMR is checkpointed too, but is unsupported by Linux. */

	/* Restore original MSR/IRQ state & clear TM mode */
	ld	r14, TM_FRAME_L0(r1)		/* Orig MSR */

	li	r15, 0
	rldimi  r14, r15, MSR_TS_LG, (63-MSR_TS_LG)-1
	mtmsrd  r14

	REST_NVGPRS(r1)

	addi    r1, r1, TM_FRAME_SIZE
	lwz	r4, 8(r1)
	ld	r0, 16(r1)
	mtcr	r4
	mtlr	r0
	ld	r2, STK_GOT(r1)

	/* Load CPU's default DSCR */
	ld	r0, PACA_DSCR_DEFAULT(r13)
	mtspr	SPRN_DSCR, r0

	blr


	/* void tm_recheckpoint(struct thread_struct *thread,
	 *			unsigned long orig_msr)
	 *	- Restore the checkpointed register state saved by tm_reclaim
	 *	  when we switch_to a process.
	 *
	 *	Call with IRQs off, stacks get all out of sync for
	 *	some periods in here!
	 */
_GLOBAL(__tm_recheckpoint)
	mfcr	r5
	mflr	r0
	stw	r5, 8(r1)
	std	r0, 16(r1)
	std	r2, STK_GOT(r1)
	stdu	r1, -TM_FRAME_SIZE(r1)

	/* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD].
	 * This is used for backing up the NVGPRs:
	 */
	SAVE_NVGPRS(r1)

	/* Load complete register state from ts_ckpt* registers */

	addi	r7, r3, PT_CKPT_REGS		/* Thread's ckpt_regs */

	/* Make r7 look like an exception frame so that we
	 * can use the neat GPRx(n) macros.  r7 is now NOT a pt_regs ptr!
	 */
	subi	r7, r7, STACK_FRAME_OVERHEAD

	mfmsr	r6
	/* R4 = original MSR to indicate whether thread used FP/Vector etc. */

	/* Enable FP/vec in MSR if necessary! */
	lis	r5, MSR_VEC@h
	ori	r5, r5, MSR_FP
	and.	r5, r4, r5
	beq	restore_gprs			/* if neither, skip both */

#ifdef CONFIG_VSX
	BEGIN_FTR_SECTION
	oris	r5, r5, MSR_VSX@h
	END_FTR_SECTION_IFSET(CPU_FTR_VSX)
#endif
	or	r5, r6, r5			/* Set MSR.FP+.VSX/.VEC */
	mtmsr	r5

#ifdef CONFIG_ALTIVEC
	/*
	 * FP and VEC registers: These are recheckpointed from
	 * thread.ckfp_state and thread.ckvr_state respectively. The
	 * thread.fp_state[] version holds the 'live' (transactional)
	 * and will be loaded subsequently by any FPUnavailable trap.
	 */
	andis.	r0, r4, MSR_VEC@h
	beq	dont_restore_vec

	addi	r8, r3, THREAD_CKVRSTATE
	li	r5, VRSTATE_VSCR
	lvx	v0, r8, r5
	mtvscr	v0
	REST_32VRS(0, r5, r8)			/* r5 scratch, r8 ptr */
dont_restore_vec:
	ld	r5, THREAD_CKVRSAVE(r3)
	mtspr	SPRN_VRSAVE, r5
#endif

	andi.	r0, r4, MSR_FP
	beq	dont_restore_fp

	addi	r8, r3, THREAD_CKFPSTATE
	lfd	fr0, FPSTATE_FPSCR(r8)
	MTFSF_L(fr0)
	REST_32FPRS_VSRS(0, R4, R8)

dont_restore_fp:
	mtmsr	r6				/* FP/Vec off again! */

restore_gprs:

	/* ******************** CR,LR,CCR,MSR ********** */
	ld	r4, _CTR(r7)
	ld	r5, _LINK(r7)
	ld	r8, _XER(r7)

	mtctr	r4
	mtlr	r5
	mtxer	r8

	/* ******************** TAR ******************** */
	ld	r4, THREAD_TM_TAR(r3)
	mtspr	SPRN_TAR,	r4

	/* Load up the PPR and DSCR in GPRs only at this stage */
	ld	r5, THREAD_TM_DSCR(r3)
	ld	r6, THREAD_TM_PPR(r3)

	REST_GPR(0, r7)				/* GPR0 */
	REST_2GPRS(2, r7)			/* GPR2-3 */
	REST_GPR(4, r7)				/* GPR4 */
	REST_4GPRS(8, r7)			/* GPR8-11 */
	REST_2GPRS(12, r7)			/* GPR12-13 */

	REST_NVGPRS(r7)				/* GPR14-31 */

	/* Load up PPR and DSCR here so we don't run with user values for long
	 */
	mtspr	SPRN_DSCR, r5
	mtspr	SPRN_PPR, r6

	/* Do final sanity check on TEXASR to make sure FS is set.  Do this
	 * here before we load up the userspace r1 so any bugs we hit will get
	 * a call chain */
	mfspr	r5, SPRN_TEXASR
	srdi	r5, r5, 16
	li	r6, (TEXASR_FS)@h
	and	r6, r6, r5
1:	tdeqi	r6, 0
	EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0

	/* Do final sanity check on MSR to make sure we are not transactional
	 * or suspended
	 */
	mfmsr   r6
	li	r5, (MSR_TS_MASK)@higher
	srdi	r6, r6, 32
	and	r6, r6, r5
1:	tdnei   r6, 0
	EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0

	/* Restore CR */
	ld	r6, _CCR(r7)
	mtcr    r6

	REST_GPR(6, r7)

	/*
	 * Store r1 and r5 on the stack so that we can access them
	 * after we clear MSR RI.
	 */

	REST_GPR(5, r7)
	std	r5, -8(r1)
	ld	r5, GPR1(r7)
	std	r5, -16(r1)

	REST_GPR(7, r7)

	/* Clear MSR RI since we are about to change r1. EE is already off */
	li	r5, 0
	mtmsrd	r5, 1

	/*
	 * BE CAREFUL HERE:
	 * At this point we can't take an SLB miss since we have MSR_RI
	 * off. Load only to/from the stack/paca which are in SLB bolted regions
	 * until we turn MSR RI back on.
	 */

	SET_SCRATCH0(r1)
	ld	r5, -8(r1)
	ld	r1, -16(r1)

	/* Commit register state as checkpointed state: */
	TRECHKPT

	HMT_MEDIUM

	/* Our transactional state has now changed.
	 *
	 * Now just get out of here.  Transactional (current) state will be
	 * updated once restore is called on the return path in the _switch-ed
	 * -to process.
	 */

	GET_PACA(r13)
	GET_SCRATCH0(r1)

	/* R1 is restored, so we are recoverable again.  EE is still off */
	li	r4, MSR_RI
	mtmsrd	r4, 1

	REST_NVGPRS(r1)

	addi    r1, r1, TM_FRAME_SIZE
	lwz	r4, 8(r1)
	ld	r0, 16(r1)
	mtcr	r4
	mtlr	r0
	ld	r2, STK_GOT(r1)

	/* Load CPU's default DSCR */
	ld	r0, PACA_DSCR_DEFAULT(r13)
	mtspr	SPRN_DSCR, r0

	blr

	/* ****************************************************************** */
Commit	Line	Data
98ae22e1 MN	1	/*
	2	* Transactional memory support routines to reclaim and recheckpoint
	3	* transactional process state.
	4	*
	5	* Copyright 2012 Matt Evans & Michael Neuling, IBM Corporation.
	6	*/
	7
	8	#include <asm/asm-offsets.h>
	9	#include <asm/ppc_asm.h>
	10	#include <asm/ppc-opcode.h>
	11	#include <asm/ptrace.h>
	12	#include <asm/reg.h>
7f06f21d	13	#include <asm/bug.h>
98ae22e1 MN	14
98ae22e1 MN	15	#ifdef CONFIG_VSX
de79f7b9 PM	16	/* See fpu.S, this is borrowed from there */
de79f7b9 PM	17	#define __SAVE_32FPRS_VSRS(n,c,base) \
98ae22e1 MN	18	BEGIN_FTR_SECTION \
	19	b 2f; \
	20	END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
de79f7b9	21	SAVE_32FPRS(n,base); \
98ae22e1	22	b 3f; \
de79f7b9	23	2: SAVE_32VSRS(n,c,base); \
98ae22e1	24	3:
98ae22e1 MN	25	#define __REST_32FPRS_VSRS(n,c,base) \
	26	BEGIN_FTR_SECTION \
	27	b 2f; \
	28	END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
	29	REST_32FPRS(n,base); \
	30	b 3f; \
	31	2: REST_32VSRS(n,c,base); \
	32	3:
	33	#else
de79f7b9 PM	34	#define __SAVE_32FPRS_VSRS(n,c,base) SAVE_32FPRS(n, base)
de79f7b9 PM	35	#define __REST_32FPRS_VSRS(n,c,base) REST_32FPRS(n, base)
98ae22e1	36	#endif
de79f7b9 PM	37	#define SAVE_32FPRS_VSRS(n,c,base) \
de79f7b9 PM	38	__SAVE_32FPRS_VSRS(n,__REG_##c,__REG_##base)
98ae22e1 MN	39	#define REST_32FPRS_VSRS(n,c,base) \
	40	__REST_32FPRS_VSRS(n,__REG_##c,__REG_##base)
	41
	42	/* Stack frame offsets for local variables. */
	43	#define TM_FRAME_L0 TM_FRAME_SIZE-16
	44	#define TM_FRAME_L1 TM_FRAME_SIZE-8
98ae22e1 MN	45
	46
	47	/* In order to access the TM SPRs, TM must be enabled. So, do so: */
	48	_GLOBAL(tm_enable)
	49	mfmsr r4
	50	li r3, MSR_TM >> 32
	51	sldi r3, r3, 32
	52	and. r0, r4, r3
	53	bne 1f
	54	or r4, r4, r3
	55	mtmsrd r4
	56	1: blr
	57
	58	_GLOBAL(tm_save_sprs)
	59	mfspr r0, SPRN_TFHAR
	60	std r0, THREAD_TM_TFHAR(r3)
	61	mfspr r0, SPRN_TEXASR
	62	std r0, THREAD_TM_TEXASR(r3)
	63	mfspr r0, SPRN_TFIAR
	64	std r0, THREAD_TM_TFIAR(r3)
	65	blr
	66
	67	_GLOBAL(tm_restore_sprs)
	68	ld r0, THREAD_TM_TFHAR(r3)
	69	mtspr SPRN_TFHAR, r0
	70	ld r0, THREAD_TM_TEXASR(r3)
	71	mtspr SPRN_TEXASR, r0
	72	ld r0, THREAD_TM_TFIAR(r3)
	73	mtspr SPRN_TFIAR, r0
	74	blr
	75
	76	/* Passed an 8-bit failure cause as first argument. */
	77	_GLOBAL(tm_abort)
	78	TABORT(R3)
	79	blr
	80
98ae22e1 MN	81	/* void tm_reclaim(struct thread_struct *thread,
	82	* unsigned long orig_msr,
	83	* uint8_t cause)
	84	*
	85	* - Performs a full reclaim. This destroys outstanding
	86	* transactions and updates thread->regs.tm_ckpt_* with the
	87	* original checkpointed state. Note that thread->regs is
	88	* unchanged.
	89	* - FP regs are written back to thread->transact_fpr before
	90	* reclaiming. These are the transactional (current) versions.
	91	*
	92	* Purpose is to both abort transactions of, and preserve the state of,
	93	* a transactions at a context switch. We preserve/restore both sets of process
	94	* state to restore them when the thread's scheduled again. We continue in
	95	* userland as though nothing happened, but when the transaction is resumed
	96	* they will abort back to the checkpointed state we save out here.
	97	*
	98	* Call with IRQs off, stacks get all out of sync for some periods in here!
	99	*/
	100	_GLOBAL(tm_reclaim)
	101	mfcr r6
	102	mflr r0
bbe30b3b	103	stw r6, 8(r1)
98ae22e1	104	std r0, 16(r1)
6403105b	105	std r2, STK_GOT(r1)
98ae22e1 MN	106	stdu r1, -TM_FRAME_SIZE(r1)
	107
	108	/* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD]. */
	109
c2e31bdc	110	std r3, STK_PARAM(R3)(r1)
dc310669	111	std r4, STK_PARAM(R4)(r1)
98ae22e1 MN	112	SAVE_NVGPRS(r1)
98ae22e1 MN	113
190ce869	114	/* We need to setup MSR for VSX register save instructions. */
98ae22e1 MN	115	mfmsr r14
	116	mr r15, r14
	117	ori r15, r15, MSR_FP
190ce869	118	li r16, 0
c69e63b0	119	ori r16, r16, MSR_EE /* IRQs hard off */
090b9284	120	andc r15, r15, r16
98ae22e1 MN	121	oris r15, r15, MSR_VEC@h
	122	#ifdef CONFIG_VSX
	123	BEGIN_FTR_SECTION
	124	oris r15,r15, MSR_VSX@h
	125	END_FTR_SECTION_IFSET(CPU_FTR_VSX)
	126	#endif
	127	mtmsrd r15
	128	std r14, TM_FRAME_L0(r1)
	129
7f06f21d MN	130	/* Do sanity check on MSR to make sure we are suspended */
	131	li r7, (MSR_TS_S)@higher
	132	srdi r6, r14, 32
	133	and r6, r6, r7
	134	1: tdeqi r6, 0
	135	EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
	136
dc310669 CB	137	/* Stash the stack pointer away for use after reclaim */
	138	std r1, PACAR1(r13)
	139
190ce869 MN	140	/* Clear MSR RI since we are about to change r1, EE is already off. */
	141	li r4, 0
	142	mtmsrd r4, 1
	143
	144	/*
	145	* BE CAREFUL HERE:
	146	* At this point we can't take an SLB miss since we have MSR_RI
	147	* off. Load only to/from the stack/paca which are in SLB bolted regions
	148	* until we turn MSR RI back on.
	149	*
	150	* The moment we treclaim, ALL of our GPRs will switch
98ae22e1 MN	151	* to user register state. (FPRs, CCR etc. also!)
	152	* Use an sprg and a tm_scratch in the PACA to shuffle.
	153	*/
	154	TRECLAIM(R5) /* Cause in r5 */
	155
	156	/* ****************** GPRs ****************** */
	157	/* Stash the checkpointed r13 away in the scratch SPR and get the real
	158	* paca
	159	*/
	160	SET_SCRATCH0(r13)
	161	GET_PACA(r13)
	162
	163	/* Stash the checkpointed r1 away in paca tm_scratch and get the real
	164	* stack pointer back
	165	*/
	166	std r1, PACATMSCRATCH(r13)
	167	ld r1, PACAR1(r13)
	168
e9bdc3d6 MN	169	/* Store the PPR in r11 and reset to decent value */
e9bdc3d6 MN	170	std r11, GPR11(r1) /* Temporary stash */
190ce869 MN	171
	172	/* Reset MSR RI so we can take SLB faults again */
	173	li r11, MSR_RI
	174	mtmsrd r11, 1
	175
e9bdc3d6 MN	176	mfspr r11, SPRN_PPR
	177	HMT_MEDIUM
	178
98ae22e1 MN	179	/* Now get some more GPRS free */
	180	std r7, GPR7(r1) /* Temporary stash */
	181	std r12, GPR12(r1) /* '' '' '' */
c2e31bdc	182	ld r12, STK_PARAM(R3)(r1) /* Param 0, thread_struct * */
98ae22e1	183
e9bdc3d6 MN	184	std r11, THREAD_TM_PPR(r12) /* Store PPR and free r11 */
e9bdc3d6 MN	185
98ae22e1 MN	186	addi r7, r12, PT_CKPT_REGS /* Thread's ckpt_regs */
	187
	188	/* Make r7 look like an exception frame so that we
	189	* can use the neat GPRx(n) macros. r7 is NOT a pt_regs ptr!
	190	*/
	191	subi r7, r7, STACK_FRAME_OVERHEAD
	192
	193	/* Sync the userland GPRs 2-12, 14-31 to thread->regs: */
	194	SAVE_GPR(0, r7) /* user r0 */
	195	SAVE_GPR(2, r7) /* user r2 */
	196	SAVE_4GPRS(3, r7) /* user r3-r6 */
e9bdc3d6 MN	197	SAVE_GPR(8, r7) /* user r8 */
	198	SAVE_GPR(9, r7) /* user r9 */
	199	SAVE_GPR(10, r7) /* user r10 */
98ae22e1 MN	200	ld r3, PACATMSCRATCH(r13) /* user r1 */
98ae22e1 MN	201	ld r4, GPR7(r1) /* user r7 */
e9bdc3d6 MN	202	ld r5, GPR11(r1) /* user r11 */
	203	ld r6, GPR12(r1) /* user r12 */
	204	GET_SCRATCH0(8) /* user r13 */
98ae22e1 MN	205	std r3, GPR1(r7)
98ae22e1 MN	206	std r4, GPR7(r7)
e9bdc3d6 MN	207	std r5, GPR11(r7)
	208	std r6, GPR12(r7)
	209	std r8, GPR13(r7)
98ae22e1 MN	210
	211	SAVE_NVGPRS(r7) /* user r14-r31 */
	212
	213	/* ****************** NIP ****************** */
	214	mfspr r3, SPRN_TFHAR
	215	std r3, _NIP(r7) /* Returns to failhandler */
	216	/* The checkpointed NIP is ignored when rescheduling/rechkpting,
	217	* but is used in signal return to 'wind back' to the abort handler.
	218	*/
	219
	220	/* ****************** CR,LR,CCR,MSR ******** */
	221	mfctr r3
	222	mflr r4
	223	mfcr r5
	224	mfxer r6
	225
	226	std r3, _CTR(r7)
	227	std r4, _LINK(r7)
	228	std r5, _CCR(r7)
	229	std r6, _XER(r7)
	230
28e61cc4	231
e9bdc3d6	232	/* ****************** TAR, DSCR ******** */
28e61cc4	233	mfspr r3, SPRN_TAR
e9bdc3d6	234	mfspr r4, SPRN_DSCR
28e61cc4 MN	235
28e61cc4 MN	236	std r3, THREAD_TM_TAR(r12)
e9bdc3d6	237	std r4, THREAD_TM_DSCR(r12)
28e61cc4	238
98ae22e1 MN	239	/* MSR and flags: We don't change CRs, and we don't need to alter
	240	* MSR.
	241	*/
	242
dc310669 CB	243
	244	/* ****************** FPR/VR/VSRs **********
	245	* After reclaiming, capture the checkpointed FPRs/VRs /if used/.
	246	*
	247	* (If VSX used, FP and VMX are implied. Or, we don't need to look
	248	* at MSR.VSX as copying FP regs if .FP, vector regs if .VMX covers it.)
	249	*
	250	* We're passed the thread's MSR as the second parameter
	251	*
	252	* We enabled VEC/FP/VSX in the msr above, so we can execute these
	253	* instructions!
	254	*/
	255	ld r4, STK_PARAM(R4)(r1) /* Second parameter, MSR * */
	256	mr r3, r12
	257	andis. r0, r4, MSR_VEC@h
	258	beq dont_backup_vec
	259
000ec280	260	addi r7, r3, THREAD_CKVRSTATE
dc310669 CB	261	SAVE_32VRS(0, r6, r7) /* r6 scratch, r7 transact vr state */
	262	mfvscr v0
	263	li r6, VRSTATE_VSCR
	264	stvx v0, r7, r6
	265	dont_backup_vec:
	266	mfspr r0, SPRN_VRSAVE
000ec280	267	std r0, THREAD_CKVRSAVE(r3)
dc310669 CB	268
	269	andi. r0, r4, MSR_FP
	270	beq dont_backup_fp
	271
000ec280	272	addi r7, r3, THREAD_CKFPSTATE
dc310669 CB	273	SAVE_32FPRS_VSRS(0, R6, R7) /* r6 scratch, r7 transact fp state */
	274
	275	mffs fr0
	276	stfd fr0,FPSTATE_FPSCR(r7)
	277
	278	dont_backup_fp:
	279
98ae22e1 MN	280	/* TM regs, incl TEXASR -- these live in thread_struct. Note they've
	281	* been updated by the treclaim, to explain to userland the failure
	282	* cause (aborted).
	283	*/
	284	mfspr r0, SPRN_TEXASR
	285	mfspr r3, SPRN_TFHAR
	286	mfspr r4, SPRN_TFIAR
	287	std r0, THREAD_TM_TEXASR(r12)
	288	std r3, THREAD_TM_TFHAR(r12)
	289	std r4, THREAD_TM_TFIAR(r12)
	290
e9bdc3d6	291	/* AMR is checkpointed too, but is unsupported by Linux. */
98ae22e1 MN	292
	293	/* Restore original MSR/IRQ state & clear TM mode */
	294	ld r14, TM_FRAME_L0(r1) /* Orig MSR */
dc310669	295
98ae22e1 MN	296	li r15, 0
	297	rldimi r14, r15, MSR_TS_LG, (63-MSR_TS_LG)-1
	298	mtmsrd r14
	299
	300	REST_NVGPRS(r1)
	301
	302	addi r1, r1, TM_FRAME_SIZE
bbe30b3b	303	lwz r4, 8(r1)
98ae22e1 MN	304	ld r0, 16(r1)
	305	mtcr r4
	306	mtlr r0
6403105b	307	ld r2, STK_GOT(r1)
e9bdc3d6	308
1739ea9e	309	/* Load CPU's default DSCR */
1db36525	310	ld r0, PACA_DSCR_DEFAULT(r13)
e9bdc3d6 MN	311	mtspr SPRN_DSCR, r0
e9bdc3d6 MN	312
98ae22e1 MN	313	blr
	314
	315
	316	/* void tm_recheckpoint(struct thread_struct *thread,
	317	* unsigned long orig_msr)
	318	* - Restore the checkpointed register state saved by tm_reclaim
	319	* when we switch_to a process.
	320	*
	321	* Call with IRQs off, stacks get all out of sync for
	322	* some periods in here!
	323	*/
e6b8fd02	324	_GLOBAL(__tm_recheckpoint)
98ae22e1 MN	325	mfcr r5
98ae22e1 MN	326	mflr r0
bbe30b3b	327	stw r5, 8(r1)
98ae22e1	328	std r0, 16(r1)
6403105b	329	std r2, STK_GOT(r1)
98ae22e1 MN	330	stdu r1, -TM_FRAME_SIZE(r1)
	331
	332	/* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD].
	333	* This is used for backing up the NVGPRs:
	334	*/
	335	SAVE_NVGPRS(r1)
	336
98ae22e1 MN	337	/* Load complete register state from ts_ckpt* registers */
	338
	339	addi r7, r3, PT_CKPT_REGS /* Thread's ckpt_regs */
	340
	341	/* Make r7 look like an exception frame so that we
	342	* can use the neat GPRx(n) macros. r7 is now NOT a pt_regs ptr!
	343	*/
	344	subi r7, r7, STACK_FRAME_OVERHEAD
	345
98ae22e1 MN	346	mfmsr r6
	347	/* R4 = original MSR to indicate whether thread used FP/Vector etc. */
	348
	349	/* Enable FP/vec in MSR if necessary! */
	350	lis r5, MSR_VEC@h
	351	ori r5, r5, MSR_FP
	352	and. r5, r4, r5
	353	beq restore_gprs /* if neither, skip both */
	354
	355	#ifdef CONFIG_VSX
	356	BEGIN_FTR_SECTION
	357	oris r5, r5, MSR_VSX@h
	358	END_FTR_SECTION_IFSET(CPU_FTR_VSX)
	359	#endif
	360	or r5, r6, r5 /* Set MSR.FP+.VSX/.VEC */
	361	mtmsr r5
	362
f110c0c1	363	#ifdef CONFIG_ALTIVEC
dc310669 CB	364	/*
	365	* FP and VEC registers: These are recheckpointed from
	366	* thread.ckfp_state and thread.ckvr_state respectively. The
	367	* thread.fp_state[] version holds the 'live' (transactional)
	368	* and will be loaded subsequently by any FPUnavailable trap.
98ae22e1 MN	369	*/
	370	andis. r0, r4, MSR_VEC@h
	371	beq dont_restore_vec
	372
000ec280	373	addi r8, r3, THREAD_CKVRSTATE
de79f7b9	374	li r5, VRSTATE_VSCR
c2ce6f9f AB	375	lvx v0, r8, r5
c2ce6f9f AB	376	mtvscr v0
de79f7b9	377	REST_32VRS(0, r5, r8) /* r5 scratch, r8 ptr */
408a7e08	378	dont_restore_vec:
000ec280	379	ld r5, THREAD_CKVRSAVE(r3)
98ae22e1	380	mtspr SPRN_VRSAVE, r5
f110c0c1	381	#endif
98ae22e1	382
98ae22e1 MN	383	andi. r0, r4, MSR_FP
	384	beq dont_restore_fp
	385
000ec280	386	addi r8, r3, THREAD_CKFPSTATE
de79f7b9	387	lfd fr0, FPSTATE_FPSCR(r8)
98ae22e1	388	MTFSF_L(fr0)
de79f7b9	389	REST_32FPRS_VSRS(0, R4, R8)
98ae22e1 MN	390
	391	dont_restore_fp:
	392	mtmsr r6 /* FP/Vec off again! */
	393
	394	restore_gprs:
28e61cc4	395
e9bdc3d6 MN	396	/* ****************** CR,LR,CCR,MSR ******** */
	397	ld r4, _CTR(r7)
	398	ld r5, _LINK(r7)
e9bdc3d6	399	ld r8, _XER(r7)
28e61cc4	400
e9bdc3d6 MN	401	mtctr r4
e9bdc3d6 MN	402	mtlr r5
e9bdc3d6	403	mtxer r8
28e61cc4	404
e9bdc3d6 MN	405	/* ****************** TAR ****************** */
	406	ld r4, THREAD_TM_TAR(r3)
	407	mtspr SPRN_TAR, r4
98ae22e1	408
e9bdc3d6 MN	409	/* Load up the PPR and DSCR in GPRs only at this stage */
	410	ld r5, THREAD_TM_DSCR(r3)
	411	ld r6, THREAD_TM_PPR(r3)
98ae22e1	412
7f06f21d MN	413	REST_GPR(0, r7) /* GPR0 */
7f06f21d MN	414	REST_2GPRS(2, r7) /* GPR2-3 */
e9bdc3d6	415	REST_GPR(4, r7) /* GPR4 */
98ae22e1 MN	416	REST_4GPRS(8, r7) /* GPR8-11 */
	417	REST_2GPRS(12, r7) /* GPR12-13 */
	418
	419	REST_NVGPRS(r7) /* GPR14-31 */
	420
e9bdc3d6 MN	421	/* Load up PPR and DSCR here so we don't run with user values for long
	422	*/
	423	mtspr SPRN_DSCR, r5
	424	mtspr SPRN_PPR, r6
	425
7f06f21d MN	426	/* Do final sanity check on TEXASR to make sure FS is set. Do this
	427	* here before we load up the userspace r1 so any bugs we hit will get
	428	* a call chain */
	429	mfspr r5, SPRN_TEXASR
	430	srdi r5, r5, 16
	431	li r6, (TEXASR_FS)@h
	432	and r6, r6, r5
	433	1: tdeqi r6, 0
	434	EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
	435
	436	/* Do final sanity check on MSR to make sure we are not transactional
	437	* or suspended
	438	*/
	439	mfmsr r6
	440	li r5, (MSR_TS_MASK)@higher
	441	srdi r6, r6, 32
	442	and r6, r6, r5
	443	1: tdnei r6, 0
	444	EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
	445
	446	/* Restore CR */
	447	ld r6, _CCR(r7)
	448	mtcr r6
	449
e9bdc3d6	450	REST_GPR(6, r7)
190ce869 MN	451
	452	/*
	453	* Store r1 and r5 on the stack so that we can access them
	454	* after we clear MSR RI.
	455	*/
	456
	457	REST_GPR(5, r7)
	458	std r5, -8(r1)
	459	ld r5, GPR1(r7)
	460	std r5, -16(r1)
	461
	462	REST_GPR(7, r7)
	463
	464	/* Clear MSR RI since we are about to change r1. EE is already off */
	465	li r5, 0
	466	mtmsrd r5, 1
	467
	468	/*
	469	* BE CAREFUL HERE:
	470	* At this point we can't take an SLB miss since we have MSR_RI
	471	* off. Load only to/from the stack/paca which are in SLB bolted regions
	472	* until we turn MSR RI back on.
	473	*/
	474
6bcb8014	475	SET_SCRATCH0(r1)
190ce869 MN	476	ld r5, -8(r1)
190ce869 MN	477	ld r1, -16(r1)
98ae22e1 MN	478
	479	/* Commit register state as checkpointed state: */
	480	TRECHKPT
	481
e9bdc3d6 MN	482	HMT_MEDIUM
e9bdc3d6 MN	483
98ae22e1 MN	484	/* Our transactional state has now changed.
	485	*
	486	* Now just get out of here. Transactional (current) state will be
	487	* updated once restore is called on the return path in the _switch-ed
	488	* -to process.
	489	*/
	490
	491	GET_PACA(r13)
	492	GET_SCRATCH0(r1)
	493
090b9284 MN	494	/* R1 is restored, so we are recoverable again. EE is still off */
	495	li r4, MSR_RI
	496	mtmsrd r4, 1
	497
98ae22e1 MN	498	REST_NVGPRS(r1)
	499
	500	addi r1, r1, TM_FRAME_SIZE
bbe30b3b	501	lwz r4, 8(r1)
98ae22e1 MN	502	ld r0, 16(r1)
	503	mtcr r4
	504	mtlr r0
6403105b	505	ld r2, STK_GOT(r1)
e9bdc3d6	506
1739ea9e	507	/* Load CPU's default DSCR */
1db36525	508	ld r0, PACA_DSCR_DEFAULT(r13)
e9bdc3d6 MN	509	mtspr SPRN_DSCR, r0
e9bdc3d6 MN	510
98ae22e1 MN	511	blr
	512
	513	/* ****************************************************************** */