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Commit | Line | Data |
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98ae22e1 MN |
1 | /* |
2 | * Transactional memory support routines to reclaim and recheckpoint | |
3 | * transactional process state. | |
4 | * | |
5 | * Copyright 2012 Matt Evans & Michael Neuling, IBM Corporation. | |
6 | */ | |
7 | ||
8 | #include <asm/asm-offsets.h> | |
9 | #include <asm/ppc_asm.h> | |
10 | #include <asm/ppc-opcode.h> | |
11 | #include <asm/ptrace.h> | |
12 | #include <asm/reg.h> | |
13 | ||
14 | #ifdef CONFIG_VSX | |
15 | /* See fpu.S, this is very similar but to save/restore checkpointed FPRs/VSRs */ | |
16 | #define __SAVE_32FPRS_VSRS_TRANSACT(n,c,base) \ | |
17 | BEGIN_FTR_SECTION \ | |
18 | b 2f; \ | |
19 | END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ | |
20 | SAVE_32FPRS_TRANSACT(n,base); \ | |
21 | b 3f; \ | |
22 | 2: SAVE_32VSRS_TRANSACT(n,c,base); \ | |
23 | 3: | |
24 | /* ...and this is just plain borrowed from there. */ | |
25 | #define __REST_32FPRS_VSRS(n,c,base) \ | |
26 | BEGIN_FTR_SECTION \ | |
27 | b 2f; \ | |
28 | END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ | |
29 | REST_32FPRS(n,base); \ | |
30 | b 3f; \ | |
31 | 2: REST_32VSRS(n,c,base); \ | |
32 | 3: | |
33 | #else | |
34 | #define __SAVE_32FPRS_VSRS_TRANSACT(n,c,base) SAVE_32FPRS_TRANSACT(n, base) | |
35 | #define __REST_32FPRS_VSRS(n,c,base) REST_32FPRS(n, base) | |
36 | #endif | |
37 | #define SAVE_32FPRS_VSRS_TRANSACT(n,c,base) \ | |
38 | __SAVE_32FPRS_VSRS_TRANSACT(n,__REG_##c,__REG_##base) | |
39 | #define REST_32FPRS_VSRS(n,c,base) \ | |
40 | __REST_32FPRS_VSRS(n,__REG_##c,__REG_##base) | |
41 | ||
42 | /* Stack frame offsets for local variables. */ | |
43 | #define TM_FRAME_L0 TM_FRAME_SIZE-16 | |
44 | #define TM_FRAME_L1 TM_FRAME_SIZE-8 | |
45 | #define STACK_PARAM(x) (48+((x)*8)) | |
46 | ||
47 | ||
48 | /* In order to access the TM SPRs, TM must be enabled. So, do so: */ | |
49 | _GLOBAL(tm_enable) | |
50 | mfmsr r4 | |
51 | li r3, MSR_TM >> 32 | |
52 | sldi r3, r3, 32 | |
53 | and. r0, r4, r3 | |
54 | bne 1f | |
55 | or r4, r4, r3 | |
56 | mtmsrd r4 | |
57 | 1: blr | |
58 | ||
59 | _GLOBAL(tm_save_sprs) | |
60 | mfspr r0, SPRN_TFHAR | |
61 | std r0, THREAD_TM_TFHAR(r3) | |
62 | mfspr r0, SPRN_TEXASR | |
63 | std r0, THREAD_TM_TEXASR(r3) | |
64 | mfspr r0, SPRN_TFIAR | |
65 | std r0, THREAD_TM_TFIAR(r3) | |
66 | blr | |
67 | ||
68 | _GLOBAL(tm_restore_sprs) | |
69 | ld r0, THREAD_TM_TFHAR(r3) | |
70 | mtspr SPRN_TFHAR, r0 | |
71 | ld r0, THREAD_TM_TEXASR(r3) | |
72 | mtspr SPRN_TEXASR, r0 | |
73 | ld r0, THREAD_TM_TFIAR(r3) | |
74 | mtspr SPRN_TFIAR, r0 | |
75 | blr | |
76 | ||
77 | /* Passed an 8-bit failure cause as first argument. */ | |
78 | _GLOBAL(tm_abort) | |
79 | TABORT(R3) | |
80 | blr | |
81 | ||
e9bdc3d6 MN |
82 | .section ".toc","aw" |
83 | DSCR_DEFAULT: | |
84 | .tc dscr_default[TC],dscr_default | |
85 | ||
86 | .section ".text" | |
98ae22e1 MN |
87 | |
88 | /* void tm_reclaim(struct thread_struct *thread, | |
89 | * unsigned long orig_msr, | |
90 | * uint8_t cause) | |
91 | * | |
92 | * - Performs a full reclaim. This destroys outstanding | |
93 | * transactions and updates thread->regs.tm_ckpt_* with the | |
94 | * original checkpointed state. Note that thread->regs is | |
95 | * unchanged. | |
96 | * - FP regs are written back to thread->transact_fpr before | |
97 | * reclaiming. These are the transactional (current) versions. | |
98 | * | |
99 | * Purpose is to both abort transactions of, and preserve the state of, | |
100 | * a transactions at a context switch. We preserve/restore both sets of process | |
101 | * state to restore them when the thread's scheduled again. We continue in | |
102 | * userland as though nothing happened, but when the transaction is resumed | |
103 | * they will abort back to the checkpointed state we save out here. | |
104 | * | |
105 | * Call with IRQs off, stacks get all out of sync for some periods in here! | |
106 | */ | |
107 | _GLOBAL(tm_reclaim) | |
108 | mfcr r6 | |
109 | mflr r0 | |
110 | std r6, 8(r1) | |
111 | std r0, 16(r1) | |
112 | std r2, 40(r1) | |
113 | stdu r1, -TM_FRAME_SIZE(r1) | |
114 | ||
115 | /* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD]. */ | |
116 | ||
117 | std r3, STACK_PARAM(0)(r1) | |
118 | SAVE_NVGPRS(r1) | |
119 | ||
090b9284 MN |
120 | /* We need to setup MSR for VSX register save instructions. Here we |
121 | * also clear the MSR RI since when we do the treclaim, we won't have a | |
122 | * valid kernel pointer for a while. We clear RI here as it avoids | |
123 | * adding another mtmsr closer to the treclaim. This makes the region | |
124 | * maked as non-recoverable wider than it needs to be but it saves on | |
125 | * inserting another mtmsrd later. | |
126 | */ | |
98ae22e1 MN |
127 | mfmsr r14 |
128 | mr r15, r14 | |
129 | ori r15, r15, MSR_FP | |
090b9284 | 130 | li r16, MSR_RI |
c69e63b0 | 131 | ori r16, r16, MSR_EE /* IRQs hard off */ |
090b9284 | 132 | andc r15, r15, r16 |
98ae22e1 MN |
133 | oris r15, r15, MSR_VEC@h |
134 | #ifdef CONFIG_VSX | |
135 | BEGIN_FTR_SECTION | |
136 | oris r15,r15, MSR_VSX@h | |
137 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
138 | #endif | |
139 | mtmsrd r15 | |
140 | std r14, TM_FRAME_L0(r1) | |
141 | ||
142 | /* Stash the stack pointer away for use after reclaim */ | |
143 | std r1, PACAR1(r13) | |
144 | ||
145 | /* ******************** FPR/VR/VSRs ************ | |
146 | * Before reclaiming, capture the current/transactional FPR/VR | |
147 | * versions /if used/. | |
148 | * | |
149 | * (If VSX used, FP and VMX are implied. Or, we don't need to look | |
150 | * at MSR.VSX as copying FP regs if .FP, vector regs if .VMX covers it.) | |
151 | * | |
152 | * We're passed the thread's MSR as parameter 2. | |
153 | * | |
154 | * We enabled VEC/FP/VSX in the msr above, so we can execute these | |
155 | * instructions! | |
156 | */ | |
157 | andis. r0, r4, MSR_VEC@h | |
158 | beq dont_backup_vec | |
159 | ||
160 | SAVE_32VRS_TRANSACT(0, r6, r3) /* r6 scratch, r3 thread */ | |
161 | mfvscr vr0 | |
162 | li r6, THREAD_TRANSACT_VSCR | |
163 | stvx vr0, r3, r6 | |
408a7e08 | 164 | dont_backup_vec: |
98ae22e1 MN |
165 | mfspr r0, SPRN_VRSAVE |
166 | std r0, THREAD_TRANSACT_VRSAVE(r3) | |
167 | ||
98ae22e1 MN |
168 | andi. r0, r4, MSR_FP |
169 | beq dont_backup_fp | |
170 | ||
171 | SAVE_32FPRS_VSRS_TRANSACT(0, R6, R3) /* r6 scratch, r3 thread */ | |
172 | ||
173 | mffs fr0 | |
174 | stfd fr0,THREAD_TRANSACT_FPSCR(r3) | |
175 | ||
176 | dont_backup_fp: | |
177 | /* The moment we treclaim, ALL of our GPRs will switch | |
178 | * to user register state. (FPRs, CCR etc. also!) | |
179 | * Use an sprg and a tm_scratch in the PACA to shuffle. | |
180 | */ | |
181 | TRECLAIM(R5) /* Cause in r5 */ | |
182 | ||
183 | /* ******************** GPRs ******************** */ | |
184 | /* Stash the checkpointed r13 away in the scratch SPR and get the real | |
185 | * paca | |
186 | */ | |
187 | SET_SCRATCH0(r13) | |
188 | GET_PACA(r13) | |
189 | ||
190 | /* Stash the checkpointed r1 away in paca tm_scratch and get the real | |
191 | * stack pointer back | |
192 | */ | |
193 | std r1, PACATMSCRATCH(r13) | |
194 | ld r1, PACAR1(r13) | |
195 | ||
e9bdc3d6 MN |
196 | /* Store the PPR in r11 and reset to decent value */ |
197 | std r11, GPR11(r1) /* Temporary stash */ | |
198 | mfspr r11, SPRN_PPR | |
199 | HMT_MEDIUM | |
200 | ||
98ae22e1 MN |
201 | /* Now get some more GPRS free */ |
202 | std r7, GPR7(r1) /* Temporary stash */ | |
203 | std r12, GPR12(r1) /* '' '' '' */ | |
204 | ld r12, STACK_PARAM(0)(r1) /* Param 0, thread_struct * */ | |
205 | ||
e9bdc3d6 MN |
206 | std r11, THREAD_TM_PPR(r12) /* Store PPR and free r11 */ |
207 | ||
98ae22e1 MN |
208 | addi r7, r12, PT_CKPT_REGS /* Thread's ckpt_regs */ |
209 | ||
210 | /* Make r7 look like an exception frame so that we | |
211 | * can use the neat GPRx(n) macros. r7 is NOT a pt_regs ptr! | |
212 | */ | |
213 | subi r7, r7, STACK_FRAME_OVERHEAD | |
214 | ||
215 | /* Sync the userland GPRs 2-12, 14-31 to thread->regs: */ | |
216 | SAVE_GPR(0, r7) /* user r0 */ | |
217 | SAVE_GPR(2, r7) /* user r2 */ | |
218 | SAVE_4GPRS(3, r7) /* user r3-r6 */ | |
e9bdc3d6 MN |
219 | SAVE_GPR(8, r7) /* user r8 */ |
220 | SAVE_GPR(9, r7) /* user r9 */ | |
221 | SAVE_GPR(10, r7) /* user r10 */ | |
98ae22e1 MN |
222 | ld r3, PACATMSCRATCH(r13) /* user r1 */ |
223 | ld r4, GPR7(r1) /* user r7 */ | |
e9bdc3d6 MN |
224 | ld r5, GPR11(r1) /* user r11 */ |
225 | ld r6, GPR12(r1) /* user r12 */ | |
226 | GET_SCRATCH0(8) /* user r13 */ | |
98ae22e1 MN |
227 | std r3, GPR1(r7) |
228 | std r4, GPR7(r7) | |
e9bdc3d6 MN |
229 | std r5, GPR11(r7) |
230 | std r6, GPR12(r7) | |
231 | std r8, GPR13(r7) | |
98ae22e1 MN |
232 | |
233 | SAVE_NVGPRS(r7) /* user r14-r31 */ | |
234 | ||
235 | /* ******************** NIP ******************** */ | |
236 | mfspr r3, SPRN_TFHAR | |
237 | std r3, _NIP(r7) /* Returns to failhandler */ | |
238 | /* The checkpointed NIP is ignored when rescheduling/rechkpting, | |
239 | * but is used in signal return to 'wind back' to the abort handler. | |
240 | */ | |
241 | ||
242 | /* ******************** CR,LR,CCR,MSR ********** */ | |
243 | mfctr r3 | |
244 | mflr r4 | |
245 | mfcr r5 | |
246 | mfxer r6 | |
247 | ||
248 | std r3, _CTR(r7) | |
249 | std r4, _LINK(r7) | |
250 | std r5, _CCR(r7) | |
251 | std r6, _XER(r7) | |
252 | ||
28e61cc4 | 253 | |
e9bdc3d6 | 254 | /* ******************** TAR, DSCR ********** */ |
28e61cc4 | 255 | mfspr r3, SPRN_TAR |
e9bdc3d6 | 256 | mfspr r4, SPRN_DSCR |
28e61cc4 MN |
257 | |
258 | std r3, THREAD_TM_TAR(r12) | |
e9bdc3d6 | 259 | std r4, THREAD_TM_DSCR(r12) |
28e61cc4 | 260 | |
98ae22e1 MN |
261 | /* MSR and flags: We don't change CRs, and we don't need to alter |
262 | * MSR. | |
263 | */ | |
264 | ||
265 | /* TM regs, incl TEXASR -- these live in thread_struct. Note they've | |
266 | * been updated by the treclaim, to explain to userland the failure | |
267 | * cause (aborted). | |
268 | */ | |
269 | mfspr r0, SPRN_TEXASR | |
270 | mfspr r3, SPRN_TFHAR | |
271 | mfspr r4, SPRN_TFIAR | |
272 | std r0, THREAD_TM_TEXASR(r12) | |
273 | std r3, THREAD_TM_TFHAR(r12) | |
274 | std r4, THREAD_TM_TFIAR(r12) | |
275 | ||
e9bdc3d6 | 276 | /* AMR is checkpointed too, but is unsupported by Linux. */ |
98ae22e1 MN |
277 | |
278 | /* Restore original MSR/IRQ state & clear TM mode */ | |
279 | ld r14, TM_FRAME_L0(r1) /* Orig MSR */ | |
280 | li r15, 0 | |
281 | rldimi r14, r15, MSR_TS_LG, (63-MSR_TS_LG)-1 | |
282 | mtmsrd r14 | |
283 | ||
284 | REST_NVGPRS(r1) | |
285 | ||
286 | addi r1, r1, TM_FRAME_SIZE | |
287 | ld r4, 8(r1) | |
288 | ld r0, 16(r1) | |
289 | mtcr r4 | |
290 | mtlr r0 | |
291 | ld r2, 40(r1) | |
e9bdc3d6 MN |
292 | |
293 | /* Load system default DSCR */ | |
294 | ld r4, DSCR_DEFAULT@toc(r2) | |
295 | ld r0, 0(r4) | |
296 | mtspr SPRN_DSCR, r0 | |
297 | ||
98ae22e1 MN |
298 | blr |
299 | ||
300 | ||
301 | /* void tm_recheckpoint(struct thread_struct *thread, | |
302 | * unsigned long orig_msr) | |
303 | * - Restore the checkpointed register state saved by tm_reclaim | |
304 | * when we switch_to a process. | |
305 | * | |
306 | * Call with IRQs off, stacks get all out of sync for | |
307 | * some periods in here! | |
308 | */ | |
309 | _GLOBAL(tm_recheckpoint) | |
310 | mfcr r5 | |
311 | mflr r0 | |
312 | std r5, 8(r1) | |
313 | std r0, 16(r1) | |
314 | std r2, 40(r1) | |
315 | stdu r1, -TM_FRAME_SIZE(r1) | |
316 | ||
317 | /* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD]. | |
318 | * This is used for backing up the NVGPRs: | |
319 | */ | |
320 | SAVE_NVGPRS(r1) | |
321 | ||
322 | std r1, PACAR1(r13) | |
323 | ||
324 | /* Load complete register state from ts_ckpt* registers */ | |
325 | ||
326 | addi r7, r3, PT_CKPT_REGS /* Thread's ckpt_regs */ | |
327 | ||
328 | /* Make r7 look like an exception frame so that we | |
329 | * can use the neat GPRx(n) macros. r7 is now NOT a pt_regs ptr! | |
330 | */ | |
331 | subi r7, r7, STACK_FRAME_OVERHEAD | |
332 | ||
333 | SET_SCRATCH0(r1) | |
334 | ||
335 | mfmsr r6 | |
336 | /* R4 = original MSR to indicate whether thread used FP/Vector etc. */ | |
337 | ||
338 | /* Enable FP/vec in MSR if necessary! */ | |
339 | lis r5, MSR_VEC@h | |
340 | ori r5, r5, MSR_FP | |
341 | and. r5, r4, r5 | |
342 | beq restore_gprs /* if neither, skip both */ | |
343 | ||
344 | #ifdef CONFIG_VSX | |
345 | BEGIN_FTR_SECTION | |
346 | oris r5, r5, MSR_VSX@h | |
347 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
348 | #endif | |
349 | or r5, r6, r5 /* Set MSR.FP+.VSX/.VEC */ | |
350 | mtmsr r5 | |
351 | ||
f110c0c1 | 352 | #ifdef CONFIG_ALTIVEC |
98ae22e1 MN |
353 | /* FP and VEC registers: These are recheckpointed from thread.fpr[] |
354 | * and thread.vr[] respectively. The thread.transact_fpr[] version | |
355 | * is more modern, and will be loaded subsequently by any FPUnavailable | |
356 | * trap. | |
357 | */ | |
358 | andis. r0, r4, MSR_VEC@h | |
359 | beq dont_restore_vec | |
360 | ||
361 | li r5, THREAD_VSCR | |
362 | lvx vr0, r3, r5 | |
363 | mtvscr vr0 | |
364 | REST_32VRS(0, r5, r3) /* r5 scratch, r3 THREAD ptr */ | |
408a7e08 | 365 | dont_restore_vec: |
98ae22e1 MN |
366 | ld r5, THREAD_VRSAVE(r3) |
367 | mtspr SPRN_VRSAVE, r5 | |
f110c0c1 | 368 | #endif |
98ae22e1 | 369 | |
98ae22e1 MN |
370 | andi. r0, r4, MSR_FP |
371 | beq dont_restore_fp | |
372 | ||
373 | lfd fr0, THREAD_FPSCR(r3) | |
374 | MTFSF_L(fr0) | |
375 | REST_32FPRS_VSRS(0, R4, R3) | |
376 | ||
377 | dont_restore_fp: | |
378 | mtmsr r6 /* FP/Vec off again! */ | |
379 | ||
380 | restore_gprs: | |
28e61cc4 | 381 | |
e9bdc3d6 MN |
382 | /* ******************** CR,LR,CCR,MSR ********** */ |
383 | ld r4, _CTR(r7) | |
384 | ld r5, _LINK(r7) | |
385 | ld r6, _CCR(r7) | |
386 | ld r8, _XER(r7) | |
28e61cc4 | 387 | |
e9bdc3d6 MN |
388 | mtctr r4 |
389 | mtlr r5 | |
390 | mtcr r6 | |
391 | mtxer r8 | |
28e61cc4 | 392 | |
e9bdc3d6 MN |
393 | /* ******************** TAR ******************** */ |
394 | ld r4, THREAD_TM_TAR(r3) | |
395 | mtspr SPRN_TAR, r4 | |
98ae22e1 | 396 | |
e9bdc3d6 MN |
397 | /* Load up the PPR and DSCR in GPRs only at this stage */ |
398 | ld r5, THREAD_TM_DSCR(r3) | |
399 | ld r6, THREAD_TM_PPR(r3) | |
98ae22e1 | 400 | |
090b9284 | 401 | /* Clear the MSR RI since we are about to change R1. EE is already off |
98ae22e1 | 402 | */ |
090b9284 MN |
403 | li r4, 0 |
404 | mtmsrd r4, 1 | |
98ae22e1 MN |
405 | |
406 | REST_4GPRS(0, r7) /* GPR0-3 */ | |
e9bdc3d6 | 407 | REST_GPR(4, r7) /* GPR4 */ |
98ae22e1 MN |
408 | REST_4GPRS(8, r7) /* GPR8-11 */ |
409 | REST_2GPRS(12, r7) /* GPR12-13 */ | |
410 | ||
411 | REST_NVGPRS(r7) /* GPR14-31 */ | |
412 | ||
e9bdc3d6 MN |
413 | /* Load up PPR and DSCR here so we don't run with user values for long |
414 | */ | |
415 | mtspr SPRN_DSCR, r5 | |
416 | mtspr SPRN_PPR, r6 | |
417 | ||
418 | REST_GPR(5, r7) /* GPR5-7 */ | |
419 | REST_GPR(6, r7) | |
420 | ld r7, GPR7(r7) | |
98ae22e1 MN |
421 | |
422 | /* Commit register state as checkpointed state: */ | |
423 | TRECHKPT | |
424 | ||
e9bdc3d6 MN |
425 | HMT_MEDIUM |
426 | ||
98ae22e1 MN |
427 | /* Our transactional state has now changed. |
428 | * | |
429 | * Now just get out of here. Transactional (current) state will be | |
430 | * updated once restore is called on the return path in the _switch-ed | |
431 | * -to process. | |
432 | */ | |
433 | ||
434 | GET_PACA(r13) | |
435 | GET_SCRATCH0(r1) | |
436 | ||
090b9284 MN |
437 | /* R1 is restored, so we are recoverable again. EE is still off */ |
438 | li r4, MSR_RI | |
439 | mtmsrd r4, 1 | |
440 | ||
98ae22e1 MN |
441 | REST_NVGPRS(r1) |
442 | ||
443 | addi r1, r1, TM_FRAME_SIZE | |
444 | ld r4, 8(r1) | |
445 | ld r0, 16(r1) | |
446 | mtcr r4 | |
447 | mtlr r0 | |
448 | ld r2, 40(r1) | |
e9bdc3d6 MN |
449 | |
450 | /* Load system default DSCR */ | |
451 | ld r4, DSCR_DEFAULT@toc(r2) | |
452 | ld r0, 0(r4) | |
453 | mtspr SPRN_DSCR, r0 | |
454 | ||
98ae22e1 MN |
455 | blr |
456 | ||
457 | /* ****************************************************************** */ |