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Commit | Line | Data |
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98ae22e1 MN |
1 | /* |
2 | * Transactional memory support routines to reclaim and recheckpoint | |
3 | * transactional process state. | |
4 | * | |
5 | * Copyright 2012 Matt Evans & Michael Neuling, IBM Corporation. | |
6 | */ | |
7 | ||
8 | #include <asm/asm-offsets.h> | |
9 | #include <asm/ppc_asm.h> | |
10 | #include <asm/ppc-opcode.h> | |
11 | #include <asm/ptrace.h> | |
12 | #include <asm/reg.h> | |
13 | ||
14 | #ifdef CONFIG_VSX | |
15 | /* See fpu.S, this is very similar but to save/restore checkpointed FPRs/VSRs */ | |
16 | #define __SAVE_32FPRS_VSRS_TRANSACT(n,c,base) \ | |
17 | BEGIN_FTR_SECTION \ | |
18 | b 2f; \ | |
19 | END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ | |
20 | SAVE_32FPRS_TRANSACT(n,base); \ | |
21 | b 3f; \ | |
22 | 2: SAVE_32VSRS_TRANSACT(n,c,base); \ | |
23 | 3: | |
24 | /* ...and this is just plain borrowed from there. */ | |
25 | #define __REST_32FPRS_VSRS(n,c,base) \ | |
26 | BEGIN_FTR_SECTION \ | |
27 | b 2f; \ | |
28 | END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ | |
29 | REST_32FPRS(n,base); \ | |
30 | b 3f; \ | |
31 | 2: REST_32VSRS(n,c,base); \ | |
32 | 3: | |
33 | #else | |
34 | #define __SAVE_32FPRS_VSRS_TRANSACT(n,c,base) SAVE_32FPRS_TRANSACT(n, base) | |
35 | #define __REST_32FPRS_VSRS(n,c,base) REST_32FPRS(n, base) | |
36 | #endif | |
37 | #define SAVE_32FPRS_VSRS_TRANSACT(n,c,base) \ | |
38 | __SAVE_32FPRS_VSRS_TRANSACT(n,__REG_##c,__REG_##base) | |
39 | #define REST_32FPRS_VSRS(n,c,base) \ | |
40 | __REST_32FPRS_VSRS(n,__REG_##c,__REG_##base) | |
41 | ||
42 | /* Stack frame offsets for local variables. */ | |
43 | #define TM_FRAME_L0 TM_FRAME_SIZE-16 | |
44 | #define TM_FRAME_L1 TM_FRAME_SIZE-8 | |
45 | #define STACK_PARAM(x) (48+((x)*8)) | |
46 | ||
47 | ||
48 | /* In order to access the TM SPRs, TM must be enabled. So, do so: */ | |
49 | _GLOBAL(tm_enable) | |
50 | mfmsr r4 | |
51 | li r3, MSR_TM >> 32 | |
52 | sldi r3, r3, 32 | |
53 | and. r0, r4, r3 | |
54 | bne 1f | |
55 | or r4, r4, r3 | |
56 | mtmsrd r4 | |
57 | 1: blr | |
58 | ||
59 | _GLOBAL(tm_save_sprs) | |
60 | mfspr r0, SPRN_TFHAR | |
61 | std r0, THREAD_TM_TFHAR(r3) | |
62 | mfspr r0, SPRN_TEXASR | |
63 | std r0, THREAD_TM_TEXASR(r3) | |
64 | mfspr r0, SPRN_TFIAR | |
65 | std r0, THREAD_TM_TFIAR(r3) | |
66 | blr | |
67 | ||
68 | _GLOBAL(tm_restore_sprs) | |
69 | ld r0, THREAD_TM_TFHAR(r3) | |
70 | mtspr SPRN_TFHAR, r0 | |
71 | ld r0, THREAD_TM_TEXASR(r3) | |
72 | mtspr SPRN_TEXASR, r0 | |
73 | ld r0, THREAD_TM_TFIAR(r3) | |
74 | mtspr SPRN_TFIAR, r0 | |
75 | blr | |
76 | ||
77 | /* Passed an 8-bit failure cause as first argument. */ | |
78 | _GLOBAL(tm_abort) | |
79 | TABORT(R3) | |
80 | blr | |
81 | ||
82 | ||
83 | /* void tm_reclaim(struct thread_struct *thread, | |
84 | * unsigned long orig_msr, | |
85 | * uint8_t cause) | |
86 | * | |
87 | * - Performs a full reclaim. This destroys outstanding | |
88 | * transactions and updates thread->regs.tm_ckpt_* with the | |
89 | * original checkpointed state. Note that thread->regs is | |
90 | * unchanged. | |
91 | * - FP regs are written back to thread->transact_fpr before | |
92 | * reclaiming. These are the transactional (current) versions. | |
93 | * | |
94 | * Purpose is to both abort transactions of, and preserve the state of, | |
95 | * a transactions at a context switch. We preserve/restore both sets of process | |
96 | * state to restore them when the thread's scheduled again. We continue in | |
97 | * userland as though nothing happened, but when the transaction is resumed | |
98 | * they will abort back to the checkpointed state we save out here. | |
99 | * | |
100 | * Call with IRQs off, stacks get all out of sync for some periods in here! | |
101 | */ | |
102 | _GLOBAL(tm_reclaim) | |
103 | mfcr r6 | |
104 | mflr r0 | |
105 | std r6, 8(r1) | |
106 | std r0, 16(r1) | |
107 | std r2, 40(r1) | |
108 | stdu r1, -TM_FRAME_SIZE(r1) | |
109 | ||
110 | /* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD]. */ | |
111 | ||
112 | std r3, STACK_PARAM(0)(r1) | |
113 | SAVE_NVGPRS(r1) | |
114 | ||
090b9284 MN |
115 | /* We need to setup MSR for VSX register save instructions. Here we |
116 | * also clear the MSR RI since when we do the treclaim, we won't have a | |
117 | * valid kernel pointer for a while. We clear RI here as it avoids | |
118 | * adding another mtmsr closer to the treclaim. This makes the region | |
119 | * maked as non-recoverable wider than it needs to be but it saves on | |
120 | * inserting another mtmsrd later. | |
121 | */ | |
98ae22e1 MN |
122 | mfmsr r14 |
123 | mr r15, r14 | |
124 | ori r15, r15, MSR_FP | |
090b9284 MN |
125 | li r16, MSR_RI |
126 | andc r15, r15, r16 | |
98ae22e1 MN |
127 | oris r15, r15, MSR_VEC@h |
128 | #ifdef CONFIG_VSX | |
129 | BEGIN_FTR_SECTION | |
130 | oris r15,r15, MSR_VSX@h | |
131 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
132 | #endif | |
133 | mtmsrd r15 | |
134 | std r14, TM_FRAME_L0(r1) | |
135 | ||
136 | /* Stash the stack pointer away for use after reclaim */ | |
137 | std r1, PACAR1(r13) | |
138 | ||
139 | /* ******************** FPR/VR/VSRs ************ | |
140 | * Before reclaiming, capture the current/transactional FPR/VR | |
141 | * versions /if used/. | |
142 | * | |
143 | * (If VSX used, FP and VMX are implied. Or, we don't need to look | |
144 | * at MSR.VSX as copying FP regs if .FP, vector regs if .VMX covers it.) | |
145 | * | |
146 | * We're passed the thread's MSR as parameter 2. | |
147 | * | |
148 | * We enabled VEC/FP/VSX in the msr above, so we can execute these | |
149 | * instructions! | |
150 | */ | |
151 | andis. r0, r4, MSR_VEC@h | |
152 | beq dont_backup_vec | |
153 | ||
154 | SAVE_32VRS_TRANSACT(0, r6, r3) /* r6 scratch, r3 thread */ | |
155 | mfvscr vr0 | |
156 | li r6, THREAD_TRANSACT_VSCR | |
157 | stvx vr0, r3, r6 | |
158 | mfspr r0, SPRN_VRSAVE | |
159 | std r0, THREAD_TRANSACT_VRSAVE(r3) | |
160 | ||
161 | dont_backup_vec: | |
162 | andi. r0, r4, MSR_FP | |
163 | beq dont_backup_fp | |
164 | ||
165 | SAVE_32FPRS_VSRS_TRANSACT(0, R6, R3) /* r6 scratch, r3 thread */ | |
166 | ||
167 | mffs fr0 | |
168 | stfd fr0,THREAD_TRANSACT_FPSCR(r3) | |
169 | ||
170 | dont_backup_fp: | |
171 | /* The moment we treclaim, ALL of our GPRs will switch | |
172 | * to user register state. (FPRs, CCR etc. also!) | |
173 | * Use an sprg and a tm_scratch in the PACA to shuffle. | |
174 | */ | |
175 | TRECLAIM(R5) /* Cause in r5 */ | |
176 | ||
177 | /* ******************** GPRs ******************** */ | |
178 | /* Stash the checkpointed r13 away in the scratch SPR and get the real | |
179 | * paca | |
180 | */ | |
181 | SET_SCRATCH0(r13) | |
182 | GET_PACA(r13) | |
183 | ||
184 | /* Stash the checkpointed r1 away in paca tm_scratch and get the real | |
185 | * stack pointer back | |
186 | */ | |
187 | std r1, PACATMSCRATCH(r13) | |
188 | ld r1, PACAR1(r13) | |
189 | ||
190 | /* Now get some more GPRS free */ | |
191 | std r7, GPR7(r1) /* Temporary stash */ | |
192 | std r12, GPR12(r1) /* '' '' '' */ | |
193 | ld r12, STACK_PARAM(0)(r1) /* Param 0, thread_struct * */ | |
194 | ||
195 | addi r7, r12, PT_CKPT_REGS /* Thread's ckpt_regs */ | |
196 | ||
197 | /* Make r7 look like an exception frame so that we | |
198 | * can use the neat GPRx(n) macros. r7 is NOT a pt_regs ptr! | |
199 | */ | |
200 | subi r7, r7, STACK_FRAME_OVERHEAD | |
201 | ||
202 | /* Sync the userland GPRs 2-12, 14-31 to thread->regs: */ | |
203 | SAVE_GPR(0, r7) /* user r0 */ | |
204 | SAVE_GPR(2, r7) /* user r2 */ | |
205 | SAVE_4GPRS(3, r7) /* user r3-r6 */ | |
206 | SAVE_4GPRS(8, r7) /* user r8-r11 */ | |
207 | ld r3, PACATMSCRATCH(r13) /* user r1 */ | |
208 | ld r4, GPR7(r1) /* user r7 */ | |
209 | ld r5, GPR12(r1) /* user r12 */ | |
210 | GET_SCRATCH0(6) /* user r13 */ | |
211 | std r3, GPR1(r7) | |
212 | std r4, GPR7(r7) | |
213 | std r5, GPR12(r7) | |
214 | std r6, GPR13(r7) | |
215 | ||
216 | SAVE_NVGPRS(r7) /* user r14-r31 */ | |
217 | ||
218 | /* ******************** NIP ******************** */ | |
219 | mfspr r3, SPRN_TFHAR | |
220 | std r3, _NIP(r7) /* Returns to failhandler */ | |
221 | /* The checkpointed NIP is ignored when rescheduling/rechkpting, | |
222 | * but is used in signal return to 'wind back' to the abort handler. | |
223 | */ | |
224 | ||
225 | /* ******************** CR,LR,CCR,MSR ********** */ | |
226 | mfctr r3 | |
227 | mflr r4 | |
228 | mfcr r5 | |
229 | mfxer r6 | |
230 | ||
231 | std r3, _CTR(r7) | |
232 | std r4, _LINK(r7) | |
233 | std r5, _CCR(r7) | |
234 | std r6, _XER(r7) | |
235 | ||
236 | /* MSR and flags: We don't change CRs, and we don't need to alter | |
237 | * MSR. | |
238 | */ | |
239 | ||
240 | /* TM regs, incl TEXASR -- these live in thread_struct. Note they've | |
241 | * been updated by the treclaim, to explain to userland the failure | |
242 | * cause (aborted). | |
243 | */ | |
244 | mfspr r0, SPRN_TEXASR | |
245 | mfspr r3, SPRN_TFHAR | |
246 | mfspr r4, SPRN_TFIAR | |
247 | std r0, THREAD_TM_TEXASR(r12) | |
248 | std r3, THREAD_TM_TFHAR(r12) | |
249 | std r4, THREAD_TM_TFIAR(r12) | |
250 | ||
251 | /* AMR and PPR are checkpointed too, but are unsupported by Linux. */ | |
252 | ||
253 | /* Restore original MSR/IRQ state & clear TM mode */ | |
254 | ld r14, TM_FRAME_L0(r1) /* Orig MSR */ | |
255 | li r15, 0 | |
256 | rldimi r14, r15, MSR_TS_LG, (63-MSR_TS_LG)-1 | |
257 | mtmsrd r14 | |
258 | ||
259 | REST_NVGPRS(r1) | |
260 | ||
261 | addi r1, r1, TM_FRAME_SIZE | |
262 | ld r4, 8(r1) | |
263 | ld r0, 16(r1) | |
264 | mtcr r4 | |
265 | mtlr r0 | |
266 | ld r2, 40(r1) | |
267 | blr | |
268 | ||
269 | ||
270 | /* void tm_recheckpoint(struct thread_struct *thread, | |
271 | * unsigned long orig_msr) | |
272 | * - Restore the checkpointed register state saved by tm_reclaim | |
273 | * when we switch_to a process. | |
274 | * | |
275 | * Call with IRQs off, stacks get all out of sync for | |
276 | * some periods in here! | |
277 | */ | |
278 | _GLOBAL(tm_recheckpoint) | |
279 | mfcr r5 | |
280 | mflr r0 | |
281 | std r5, 8(r1) | |
282 | std r0, 16(r1) | |
283 | std r2, 40(r1) | |
284 | stdu r1, -TM_FRAME_SIZE(r1) | |
285 | ||
286 | /* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD]. | |
287 | * This is used for backing up the NVGPRs: | |
288 | */ | |
289 | SAVE_NVGPRS(r1) | |
290 | ||
291 | std r1, PACAR1(r13) | |
292 | ||
293 | /* Load complete register state from ts_ckpt* registers */ | |
294 | ||
295 | addi r7, r3, PT_CKPT_REGS /* Thread's ckpt_regs */ | |
296 | ||
297 | /* Make r7 look like an exception frame so that we | |
298 | * can use the neat GPRx(n) macros. r7 is now NOT a pt_regs ptr! | |
299 | */ | |
300 | subi r7, r7, STACK_FRAME_OVERHEAD | |
301 | ||
302 | SET_SCRATCH0(r1) | |
303 | ||
304 | mfmsr r6 | |
305 | /* R4 = original MSR to indicate whether thread used FP/Vector etc. */ | |
306 | ||
307 | /* Enable FP/vec in MSR if necessary! */ | |
308 | lis r5, MSR_VEC@h | |
309 | ori r5, r5, MSR_FP | |
310 | and. r5, r4, r5 | |
311 | beq restore_gprs /* if neither, skip both */ | |
312 | ||
313 | #ifdef CONFIG_VSX | |
314 | BEGIN_FTR_SECTION | |
315 | oris r5, r5, MSR_VSX@h | |
316 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
317 | #endif | |
318 | or r5, r6, r5 /* Set MSR.FP+.VSX/.VEC */ | |
319 | mtmsr r5 | |
320 | ||
f110c0c1 | 321 | #ifdef CONFIG_ALTIVEC |
98ae22e1 MN |
322 | /* FP and VEC registers: These are recheckpointed from thread.fpr[] |
323 | * and thread.vr[] respectively. The thread.transact_fpr[] version | |
324 | * is more modern, and will be loaded subsequently by any FPUnavailable | |
325 | * trap. | |
326 | */ | |
327 | andis. r0, r4, MSR_VEC@h | |
328 | beq dont_restore_vec | |
329 | ||
330 | li r5, THREAD_VSCR | |
331 | lvx vr0, r3, r5 | |
332 | mtvscr vr0 | |
333 | REST_32VRS(0, r5, r3) /* r5 scratch, r3 THREAD ptr */ | |
334 | ld r5, THREAD_VRSAVE(r3) | |
335 | mtspr SPRN_VRSAVE, r5 | |
f110c0c1 | 336 | #endif |
98ae22e1 MN |
337 | |
338 | dont_restore_vec: | |
339 | andi. r0, r4, MSR_FP | |
340 | beq dont_restore_fp | |
341 | ||
342 | lfd fr0, THREAD_FPSCR(r3) | |
343 | MTFSF_L(fr0) | |
344 | REST_32FPRS_VSRS(0, R4, R3) | |
345 | ||
346 | dont_restore_fp: | |
347 | mtmsr r6 /* FP/Vec off again! */ | |
348 | ||
349 | restore_gprs: | |
350 | /* ******************** CR,LR,CCR,MSR ********** */ | |
351 | ld r3, _CTR(r7) | |
352 | ld r4, _LINK(r7) | |
353 | ld r5, _CCR(r7) | |
354 | ld r6, _XER(r7) | |
355 | ||
356 | mtctr r3 | |
357 | mtlr r4 | |
358 | mtcr r5 | |
359 | mtxer r6 | |
360 | ||
090b9284 | 361 | /* Clear the MSR RI since we are about to change R1. EE is already off |
98ae22e1 | 362 | */ |
090b9284 MN |
363 | li r4, 0 |
364 | mtmsrd r4, 1 | |
98ae22e1 MN |
365 | |
366 | REST_4GPRS(0, r7) /* GPR0-3 */ | |
367 | REST_GPR(4, r7) /* GPR4-6 */ | |
368 | REST_GPR(5, r7) | |
369 | REST_GPR(6, r7) | |
370 | REST_4GPRS(8, r7) /* GPR8-11 */ | |
371 | REST_2GPRS(12, r7) /* GPR12-13 */ | |
372 | ||
373 | REST_NVGPRS(r7) /* GPR14-31 */ | |
374 | ||
375 | ld r7, GPR7(r7) /* GPR7 */ | |
376 | ||
377 | /* Commit register state as checkpointed state: */ | |
378 | TRECHKPT | |
379 | ||
380 | /* Our transactional state has now changed. | |
381 | * | |
382 | * Now just get out of here. Transactional (current) state will be | |
383 | * updated once restore is called on the return path in the _switch-ed | |
384 | * -to process. | |
385 | */ | |
386 | ||
387 | GET_PACA(r13) | |
388 | GET_SCRATCH0(r1) | |
389 | ||
090b9284 MN |
390 | /* R1 is restored, so we are recoverable again. EE is still off */ |
391 | li r4, MSR_RI | |
392 | mtmsrd r4, 1 | |
393 | ||
98ae22e1 MN |
394 | REST_NVGPRS(r1) |
395 | ||
396 | addi r1, r1, TM_FRAME_SIZE | |
397 | ld r4, 8(r1) | |
398 | ld r0, 16(r1) | |
399 | mtcr r4 | |
400 | mtlr r0 | |
401 | ld r2, 40(r1) | |
402 | blr | |
403 | ||
404 | /* ****************************************************************** */ |