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14cf11af | 1 | /* |
14cf11af | 2 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) |
fe04b112 | 3 | * Copyright 2007-2010 Freescale Semiconductor, Inc. |
14cf11af PM |
4 | * |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version | |
8 | * 2 of the License, or (at your option) any later version. | |
9 | * | |
10 | * Modified by Cort Dougan (cort@cs.nmt.edu) | |
11 | * and Paul Mackerras (paulus@samba.org) | |
12 | */ | |
13 | ||
14 | /* | |
15 | * This file handles the architecture-dependent parts of hardware exceptions | |
16 | */ | |
17 | ||
14cf11af PM |
18 | #include <linux/errno.h> |
19 | #include <linux/sched.h> | |
b17b0153 | 20 | #include <linux/sched/debug.h> |
14cf11af PM |
21 | #include <linux/kernel.h> |
22 | #include <linux/mm.h> | |
23 | #include <linux/stddef.h> | |
24 | #include <linux/unistd.h> | |
8dad3f92 | 25 | #include <linux/ptrace.h> |
14cf11af | 26 | #include <linux/user.h> |
14cf11af | 27 | #include <linux/interrupt.h> |
14cf11af | 28 | #include <linux/init.h> |
8a39b05f PG |
29 | #include <linux/extable.h> |
30 | #include <linux/module.h> /* print_modules */ | |
8dad3f92 | 31 | #include <linux/prctl.h> |
14cf11af PM |
32 | #include <linux/delay.h> |
33 | #include <linux/kprobes.h> | |
cc532915 | 34 | #include <linux/kexec.h> |
5474c120 | 35 | #include <linux/backlight.h> |
73c9ceab | 36 | #include <linux/bug.h> |
1eeb66a1 | 37 | #include <linux/kdebug.h> |
76462232 | 38 | #include <linux/ratelimit.h> |
ba12eede | 39 | #include <linux/context_tracking.h> |
5080332c | 40 | #include <linux/smp.h> |
14cf11af | 41 | |
80947e7c | 42 | #include <asm/emulated_ops.h> |
14cf11af | 43 | #include <asm/pgtable.h> |
7c0f6ba6 | 44 | #include <linux/uaccess.h> |
7644d581 | 45 | #include <asm/debugfs.h> |
14cf11af | 46 | #include <asm/io.h> |
86417780 PM |
47 | #include <asm/machdep.h> |
48 | #include <asm/rtas.h> | |
f7f6f4fe | 49 | #include <asm/pmc.h> |
14cf11af | 50 | #include <asm/reg.h> |
14cf11af PM |
51 | #ifdef CONFIG_PMAC_BACKLIGHT |
52 | #include <asm/backlight.h> | |
53 | #endif | |
dc1c1ca3 | 54 | #ifdef CONFIG_PPC64 |
86417780 | 55 | #include <asm/firmware.h> |
dc1c1ca3 | 56 | #include <asm/processor.h> |
6ce6c629 | 57 | #include <asm/tm.h> |
dc1c1ca3 | 58 | #endif |
c0ce7d08 | 59 | #include <asm/kexec.h> |
16c57b36 | 60 | #include <asm/ppc-opcode.h> |
cce1f106 | 61 | #include <asm/rio.h> |
ebaeb5ae | 62 | #include <asm/fadump.h> |
ae3a197e | 63 | #include <asm/switch_to.h> |
f54db641 | 64 | #include <asm/tm.h> |
ae3a197e | 65 | #include <asm/debug.h> |
42f5b4ca | 66 | #include <asm/asm-prototypes.h> |
fd7bacbc | 67 | #include <asm/hmi.h> |
4e0e3435 | 68 | #include <sysdev/fsl_pci.h> |
6cc89bad | 69 | #include <asm/kprobes.h> |
dc1c1ca3 | 70 | |
da665885 | 71 | #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC_CORE) |
5be3492f AB |
72 | int (*__debugger)(struct pt_regs *regs) __read_mostly; |
73 | int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly; | |
74 | int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly; | |
75 | int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly; | |
76 | int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly; | |
9422de3e | 77 | int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly; |
5be3492f | 78 | int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly; |
14cf11af PM |
79 | |
80 | EXPORT_SYMBOL(__debugger); | |
81 | EXPORT_SYMBOL(__debugger_ipi); | |
82 | EXPORT_SYMBOL(__debugger_bpt); | |
83 | EXPORT_SYMBOL(__debugger_sstep); | |
84 | EXPORT_SYMBOL(__debugger_iabr_match); | |
9422de3e | 85 | EXPORT_SYMBOL(__debugger_break_match); |
14cf11af PM |
86 | EXPORT_SYMBOL(__debugger_fault_handler); |
87 | #endif | |
88 | ||
8b3c34cf MN |
89 | /* Transactional Memory trap debug */ |
90 | #ifdef TM_DEBUG_SW | |
91 | #define TM_DEBUG(x...) printk(KERN_INFO x) | |
92 | #else | |
93 | #define TM_DEBUG(x...) do { } while(0) | |
94 | #endif | |
95 | ||
14cf11af PM |
96 | /* |
97 | * Trap & Exception support | |
98 | */ | |
99 | ||
6031d9d9 | 100 | #ifdef CONFIG_PMAC_BACKLIGHT |
101 | static void pmac_backlight_unblank(void) | |
102 | { | |
103 | mutex_lock(&pmac_backlight_mutex); | |
104 | if (pmac_backlight) { | |
105 | struct backlight_properties *props; | |
106 | ||
107 | props = &pmac_backlight->props; | |
108 | props->brightness = props->max_brightness; | |
109 | props->power = FB_BLANK_UNBLANK; | |
110 | backlight_update_status(pmac_backlight); | |
111 | } | |
112 | mutex_unlock(&pmac_backlight_mutex); | |
113 | } | |
114 | #else | |
115 | static inline void pmac_backlight_unblank(void) { } | |
116 | #endif | |
117 | ||
6fcd6baa NP |
118 | /* |
119 | * If oops/die is expected to crash the machine, return true here. | |
120 | * | |
121 | * This should not be expected to be 100% accurate, there may be | |
122 | * notifiers registered or other unexpected conditions that may bring | |
123 | * down the kernel. Or if the current process in the kernel is holding | |
124 | * locks or has other critical state, the kernel may become effectively | |
125 | * unusable anyway. | |
126 | */ | |
127 | bool die_will_crash(void) | |
128 | { | |
129 | if (should_fadump_crash()) | |
130 | return true; | |
131 | if (kexec_should_crash(current)) | |
132 | return true; | |
133 | if (in_interrupt() || panic_on_oops || | |
134 | !current->pid || is_global_init(current)) | |
135 | return true; | |
136 | ||
137 | return false; | |
138 | } | |
139 | ||
760ca4dc AB |
140 | static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED; |
141 | static int die_owner = -1; | |
142 | static unsigned int die_nest_count; | |
143 | static int die_counter; | |
144 | ||
03465f89 | 145 | static unsigned long oops_begin(struct pt_regs *regs) |
14cf11af | 146 | { |
760ca4dc | 147 | int cpu; |
34c2a14f | 148 | unsigned long flags; |
14cf11af | 149 | |
293e4688 | 150 | oops_enter(); |
151 | ||
760ca4dc AB |
152 | /* racy, but better than risking deadlock. */ |
153 | raw_local_irq_save(flags); | |
154 | cpu = smp_processor_id(); | |
155 | if (!arch_spin_trylock(&die_lock)) { | |
156 | if (cpu == die_owner) | |
157 | /* nested oops. should stop eventually */; | |
158 | else | |
159 | arch_spin_lock(&die_lock); | |
34c2a14f | 160 | } |
760ca4dc AB |
161 | die_nest_count++; |
162 | die_owner = cpu; | |
163 | console_verbose(); | |
164 | bust_spinlocks(1); | |
165 | if (machine_is(powermac)) | |
166 | pmac_backlight_unblank(); | |
167 | return flags; | |
168 | } | |
03465f89 | 169 | NOKPROBE_SYMBOL(oops_begin); |
e8222502 | 170 | |
03465f89 | 171 | static void oops_end(unsigned long flags, struct pt_regs *regs, |
760ca4dc AB |
172 | int signr) |
173 | { | |
14cf11af | 174 | bust_spinlocks(0); |
373d4d09 | 175 | add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); |
760ca4dc | 176 | die_nest_count--; |
58154c8c AB |
177 | oops_exit(); |
178 | printk("\n"); | |
7458e8b2 | 179 | if (!die_nest_count) { |
760ca4dc | 180 | /* Nest count reaches zero, release the lock. */ |
7458e8b2 | 181 | die_owner = -1; |
760ca4dc | 182 | arch_spin_unlock(&die_lock); |
7458e8b2 | 183 | } |
760ca4dc | 184 | raw_local_irq_restore(flags); |
cc532915 | 185 | |
ebaeb5ae MS |
186 | crash_fadump(regs, "die oops"); |
187 | ||
4388c9b3 | 188 | if (kexec_should_crash(current)) |
cc532915 | 189 | crash_kexec(regs); |
9b00ac06 | 190 | |
760ca4dc AB |
191 | if (!signr) |
192 | return; | |
193 | ||
58154c8c AB |
194 | /* |
195 | * While our oops output is serialised by a spinlock, output | |
196 | * from panic() called below can race and corrupt it. If we | |
197 | * know we are going to panic, delay for 1 second so we have a | |
198 | * chance to get clean backtraces from all CPUs that are oopsing. | |
199 | */ | |
200 | if (in_interrupt() || panic_on_oops || !current->pid || | |
201 | is_global_init(current)) { | |
202 | mdelay(MSEC_PER_SEC); | |
203 | } | |
204 | ||
14cf11af PM |
205 | if (in_interrupt()) |
206 | panic("Fatal exception in interrupt"); | |
cea6a4ba | 207 | if (panic_on_oops) |
012c437d | 208 | panic("Fatal exception"); |
760ca4dc AB |
209 | do_exit(signr); |
210 | } | |
03465f89 | 211 | NOKPROBE_SYMBOL(oops_end); |
cea6a4ba | 212 | |
03465f89 | 213 | static int __die(const char *str, struct pt_regs *regs, long err) |
760ca4dc AB |
214 | { |
215 | printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); | |
2e82ca3c ME |
216 | |
217 | if (IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN)) | |
218 | printk("LE "); | |
219 | else | |
220 | printk("BE "); | |
221 | ||
1c56cd8e ME |
222 | if (IS_ENABLED(CONFIG_PREEMPT)) |
223 | pr_cont("PREEMPT "); | |
224 | ||
225 | if (IS_ENABLED(CONFIG_SMP)) | |
226 | pr_cont("SMP NR_CPUS=%d ", NR_CPUS); | |
227 | ||
e7df0d88 | 228 | if (debug_pagealloc_enabled()) |
72c0d9ee | 229 | pr_cont("DEBUG_PAGEALLOC "); |
1c56cd8e ME |
230 | |
231 | if (IS_ENABLED(CONFIG_NUMA)) | |
232 | pr_cont("NUMA "); | |
233 | ||
72c0d9ee | 234 | pr_cont("%s\n", ppc_md.name ? ppc_md.name : ""); |
760ca4dc AB |
235 | |
236 | if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP) | |
237 | return 1; | |
238 | ||
239 | print_modules(); | |
240 | show_regs(regs); | |
14cf11af PM |
241 | |
242 | return 0; | |
243 | } | |
03465f89 | 244 | NOKPROBE_SYMBOL(__die); |
14cf11af | 245 | |
760ca4dc AB |
246 | void die(const char *str, struct pt_regs *regs, long err) |
247 | { | |
6f44b20e NP |
248 | unsigned long flags; |
249 | ||
250 | if (debugger(regs)) | |
251 | return; | |
760ca4dc | 252 | |
6f44b20e | 253 | flags = oops_begin(regs); |
760ca4dc AB |
254 | if (__die(str, regs, err)) |
255 | err = 0; | |
256 | oops_end(flags, regs, err); | |
257 | } | |
15770a13 | 258 | NOKPROBE_SYMBOL(die); |
760ca4dc | 259 | |
25baa35b ON |
260 | void user_single_step_siginfo(struct task_struct *tsk, |
261 | struct pt_regs *regs, siginfo_t *info) | |
262 | { | |
263 | memset(info, 0, sizeof(*info)); | |
264 | info->si_signo = SIGTRAP; | |
265 | info->si_code = TRAP_TRACE; | |
266 | info->si_addr = (void __user *)regs->nip; | |
267 | } | |
268 | ||
14cf11af PM |
269 | void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) |
270 | { | |
271 | siginfo_t info; | |
d0c3d534 OJ |
272 | const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \ |
273 | "at %08lx nip %08lx lr %08lx code %x\n"; | |
274 | const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \ | |
275 | "at %016lx nip %016lx lr %016lx code %x\n"; | |
14cf11af PM |
276 | |
277 | if (!user_mode(regs)) { | |
760ca4dc AB |
278 | die("Exception in kernel mode", regs, signr); |
279 | return; | |
280 | } | |
281 | ||
282 | if (show_unhandled_signals && unhandled_signal(current, signr)) { | |
76462232 CD |
283 | printk_ratelimited(regs->msr & MSR_64BIT ? fmt64 : fmt32, |
284 | current->comm, current->pid, signr, | |
285 | addr, regs->nip, regs->link, code); | |
286 | } | |
14cf11af | 287 | |
a3512b2d | 288 | if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs)) |
9f2f79e3 BH |
289 | local_irq_enable(); |
290 | ||
41ab5266 | 291 | current->thread.trap_nr = code; |
14cf11af PM |
292 | memset(&info, 0, sizeof(info)); |
293 | info.si_signo = signr; | |
294 | info.si_code = code; | |
295 | info.si_addr = (void __user *) addr; | |
296 | force_sig_info(signr, &info, current); | |
14cf11af PM |
297 | } |
298 | ||
14cf11af PM |
299 | void system_reset_exception(struct pt_regs *regs) |
300 | { | |
2b4f3ac5 NP |
301 | /* |
302 | * Avoid crashes in case of nested NMI exceptions. Recoverability | |
303 | * is determined by RI and in_nmi | |
304 | */ | |
305 | bool nested = in_nmi(); | |
306 | if (!nested) | |
307 | nmi_enter(); | |
308 | ||
ca41ad43 NP |
309 | __this_cpu_inc(irq_stat.sreset_irqs); |
310 | ||
14cf11af | 311 | /* See if any machine dependent calls */ |
c902be71 AB |
312 | if (ppc_md.system_reset_exception) { |
313 | if (ppc_md.system_reset_exception(regs)) | |
c4f3b52c | 314 | goto out; |
c902be71 | 315 | } |
14cf11af | 316 | |
4388c9b3 NP |
317 | if (debugger(regs)) |
318 | goto out; | |
319 | ||
320 | /* | |
321 | * A system reset is a request to dump, so we always send | |
322 | * it through the crashdump code (if fadump or kdump are | |
323 | * registered). | |
324 | */ | |
325 | crash_fadump(regs, "System Reset"); | |
326 | ||
327 | crash_kexec(regs); | |
328 | ||
329 | /* | |
330 | * We aren't the primary crash CPU. We need to send it | |
331 | * to a holding pattern to avoid it ending up in the panic | |
332 | * code. | |
333 | */ | |
334 | crash_kexec_secondary(regs); | |
335 | ||
336 | /* | |
337 | * No debugger or crash dump registered, print logs then | |
338 | * panic. | |
339 | */ | |
340 | __die("System Reset", regs, SIGABRT); | |
341 | ||
342 | mdelay(2*MSEC_PER_SEC); /* Wait a little while for others to print */ | |
343 | add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); | |
344 | nmi_panic(regs, "System Reset"); | |
14cf11af | 345 | |
c4f3b52c NP |
346 | out: |
347 | #ifdef CONFIG_PPC_BOOK3S_64 | |
348 | BUG_ON(get_paca()->in_nmi == 0); | |
349 | if (get_paca()->in_nmi > 1) | |
4388c9b3 | 350 | nmi_panic(regs, "Unrecoverable nested System Reset"); |
c4f3b52c | 351 | #endif |
14cf11af PM |
352 | /* Must die if the interrupt is not recoverable */ |
353 | if (!(regs->msr & MSR_RI)) | |
4388c9b3 | 354 | nmi_panic(regs, "Unrecoverable System Reset"); |
14cf11af | 355 | |
2b4f3ac5 NP |
356 | if (!nested) |
357 | nmi_exit(); | |
358 | ||
14cf11af PM |
359 | /* What should we do here? We could issue a shutdown or hard reset. */ |
360 | } | |
1e9b4507 | 361 | |
14cf11af PM |
362 | /* |
363 | * I/O accesses can cause machine checks on powermacs. | |
364 | * Check if the NIP corresponds to the address of a sync | |
365 | * instruction for which there is an entry in the exception | |
366 | * table. | |
367 | * Note that the 601 only takes a machine check on TEA | |
368 | * (transfer error ack) signal assertion, and does not | |
369 | * set any of the top 16 bits of SRR1. | |
370 | * -- paulus. | |
371 | */ | |
372 | static inline int check_io_access(struct pt_regs *regs) | |
373 | { | |
68a64357 | 374 | #ifdef CONFIG_PPC32 |
14cf11af PM |
375 | unsigned long msr = regs->msr; |
376 | const struct exception_table_entry *entry; | |
377 | unsigned int *nip = (unsigned int *)regs->nip; | |
378 | ||
379 | if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) | |
380 | && (entry = search_exception_tables(regs->nip)) != NULL) { | |
381 | /* | |
382 | * Check that it's a sync instruction, or somewhere | |
383 | * in the twi; isync; nop sequence that inb/inw/inl uses. | |
384 | * As the address is in the exception table | |
385 | * we should be able to read the instr there. | |
386 | * For the debug message, we look at the preceding | |
387 | * load or store. | |
388 | */ | |
ddc6cd0d | 389 | if (*nip == PPC_INST_NOP) |
14cf11af | 390 | nip -= 2; |
ddc6cd0d | 391 | else if (*nip == PPC_INST_ISYNC) |
14cf11af | 392 | --nip; |
ddc6cd0d | 393 | if (*nip == PPC_INST_SYNC || (*nip >> 26) == OP_TRAP) { |
14cf11af PM |
394 | unsigned int rb; |
395 | ||
396 | --nip; | |
397 | rb = (*nip >> 11) & 0x1f; | |
398 | printk(KERN_DEBUG "%s bad port %lx at %p\n", | |
399 | (*nip & 0x100)? "OUT to": "IN from", | |
400 | regs->gpr[rb] - _IO_BASE, nip); | |
401 | regs->msr |= MSR_RI; | |
61a92f70 | 402 | regs->nip = extable_fixup(entry); |
14cf11af PM |
403 | return 1; |
404 | } | |
405 | } | |
68a64357 | 406 | #endif /* CONFIG_PPC32 */ |
14cf11af PM |
407 | return 0; |
408 | } | |
409 | ||
172ae2e7 | 410 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
14cf11af PM |
411 | /* On 4xx, the reason for the machine check or program exception |
412 | is in the ESR. */ | |
413 | #define get_reason(regs) ((regs)->dsisr) | |
14cf11af PM |
414 | #define REASON_FP ESR_FP |
415 | #define REASON_ILLEGAL (ESR_PIL | ESR_PUO) | |
416 | #define REASON_PRIVILEGED ESR_PPR | |
417 | #define REASON_TRAP ESR_PTR | |
418 | ||
419 | /* single-step stuff */ | |
51ae8d4a BB |
420 | #define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC) |
421 | #define clear_single_step(regs) (current->thread.debug.dbcr0 &= ~DBCR0_IC) | |
14cf11af PM |
422 | |
423 | #else | |
424 | /* On non-4xx, the reason for the machine check or program | |
425 | exception is in the MSR. */ | |
426 | #define get_reason(regs) ((regs)->msr) | |
d30a5a52 ME |
427 | #define REASON_TM SRR1_PROGTM |
428 | #define REASON_FP SRR1_PROGFPE | |
429 | #define REASON_ILLEGAL SRR1_PROGILL | |
430 | #define REASON_PRIVILEGED SRR1_PROGPRIV | |
431 | #define REASON_TRAP SRR1_PROGTRAP | |
14cf11af PM |
432 | |
433 | #define single_stepping(regs) ((regs)->msr & MSR_SE) | |
434 | #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE) | |
435 | #endif | |
436 | ||
0d0935b3 | 437 | #if defined(CONFIG_E500) |
fe04b112 SW |
438 | int machine_check_e500mc(struct pt_regs *regs) |
439 | { | |
440 | unsigned long mcsr = mfspr(SPRN_MCSR); | |
a4e89ffb | 441 | unsigned long pvr = mfspr(SPRN_PVR); |
fe04b112 SW |
442 | unsigned long reason = mcsr; |
443 | int recoverable = 1; | |
444 | ||
82a9a480 | 445 | if (reason & MCSR_LD) { |
cce1f106 SX |
446 | recoverable = fsl_rio_mcheck_exception(regs); |
447 | if (recoverable == 1) | |
448 | goto silent_out; | |
449 | } | |
450 | ||
fe04b112 SW |
451 | printk("Machine check in kernel mode.\n"); |
452 | printk("Caused by (from MCSR=%lx): ", reason); | |
453 | ||
454 | if (reason & MCSR_MCP) | |
455 | printk("Machine Check Signal\n"); | |
456 | ||
457 | if (reason & MCSR_ICPERR) { | |
458 | printk("Instruction Cache Parity Error\n"); | |
459 | ||
460 | /* | |
461 | * This is recoverable by invalidating the i-cache. | |
462 | */ | |
463 | mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI); | |
464 | while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI) | |
465 | ; | |
466 | ||
467 | /* | |
468 | * This will generally be accompanied by an instruction | |
469 | * fetch error report -- only treat MCSR_IF as fatal | |
470 | * if it wasn't due to an L1 parity error. | |
471 | */ | |
472 | reason &= ~MCSR_IF; | |
473 | } | |
474 | ||
475 | if (reason & MCSR_DCPERR_MC) { | |
476 | printk("Data Cache Parity Error\n"); | |
37caf9f2 KG |
477 | |
478 | /* | |
479 | * In write shadow mode we auto-recover from the error, but it | |
480 | * may still get logged and cause a machine check. We should | |
481 | * only treat the non-write shadow case as non-recoverable. | |
482 | */ | |
a4e89ffb MW |
483 | /* On e6500 core, L1 DCWS (Data cache write shadow mode) bit |
484 | * is not implemented but L1 data cache always runs in write | |
485 | * shadow mode. Hence on data cache parity errors HW will | |
486 | * automatically invalidate the L1 Data Cache. | |
487 | */ | |
488 | if (PVR_VER(pvr) != PVR_VER_E6500) { | |
489 | if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS)) | |
490 | recoverable = 0; | |
491 | } | |
fe04b112 SW |
492 | } |
493 | ||
494 | if (reason & MCSR_L2MMU_MHIT) { | |
495 | printk("Hit on multiple TLB entries\n"); | |
496 | recoverable = 0; | |
497 | } | |
498 | ||
499 | if (reason & MCSR_NMI) | |
500 | printk("Non-maskable interrupt\n"); | |
501 | ||
502 | if (reason & MCSR_IF) { | |
503 | printk("Instruction Fetch Error Report\n"); | |
504 | recoverable = 0; | |
505 | } | |
506 | ||
507 | if (reason & MCSR_LD) { | |
508 | printk("Load Error Report\n"); | |
509 | recoverable = 0; | |
510 | } | |
511 | ||
512 | if (reason & MCSR_ST) { | |
513 | printk("Store Error Report\n"); | |
514 | recoverable = 0; | |
515 | } | |
516 | ||
517 | if (reason & MCSR_LDG) { | |
518 | printk("Guarded Load Error Report\n"); | |
519 | recoverable = 0; | |
520 | } | |
521 | ||
522 | if (reason & MCSR_TLBSYNC) | |
523 | printk("Simultaneous tlbsync operations\n"); | |
524 | ||
525 | if (reason & MCSR_BSL2_ERR) { | |
526 | printk("Level 2 Cache Error\n"); | |
527 | recoverable = 0; | |
528 | } | |
529 | ||
530 | if (reason & MCSR_MAV) { | |
531 | u64 addr; | |
532 | ||
533 | addr = mfspr(SPRN_MCAR); | |
534 | addr |= (u64)mfspr(SPRN_MCARU) << 32; | |
535 | ||
536 | printk("Machine Check %s Address: %#llx\n", | |
537 | reason & MCSR_MEA ? "Effective" : "Physical", addr); | |
538 | } | |
539 | ||
cce1f106 | 540 | silent_out: |
fe04b112 SW |
541 | mtspr(SPRN_MCSR, mcsr); |
542 | return mfspr(SPRN_MCSR) == 0 && recoverable; | |
543 | } | |
544 | ||
47c0bd1a BH |
545 | int machine_check_e500(struct pt_regs *regs) |
546 | { | |
42bff234 | 547 | unsigned long reason = mfspr(SPRN_MCSR); |
47c0bd1a | 548 | |
cce1f106 SX |
549 | if (reason & MCSR_BUS_RBERR) { |
550 | if (fsl_rio_mcheck_exception(regs)) | |
551 | return 1; | |
4e0e3435 HJ |
552 | if (fsl_pci_mcheck_exception(regs)) |
553 | return 1; | |
cce1f106 SX |
554 | } |
555 | ||
14cf11af PM |
556 | printk("Machine check in kernel mode.\n"); |
557 | printk("Caused by (from MCSR=%lx): ", reason); | |
558 | ||
559 | if (reason & MCSR_MCP) | |
560 | printk("Machine Check Signal\n"); | |
561 | if (reason & MCSR_ICPERR) | |
562 | printk("Instruction Cache Parity Error\n"); | |
563 | if (reason & MCSR_DCP_PERR) | |
564 | printk("Data Cache Push Parity Error\n"); | |
565 | if (reason & MCSR_DCPERR) | |
566 | printk("Data Cache Parity Error\n"); | |
14cf11af PM |
567 | if (reason & MCSR_BUS_IAERR) |
568 | printk("Bus - Instruction Address Error\n"); | |
569 | if (reason & MCSR_BUS_RAERR) | |
570 | printk("Bus - Read Address Error\n"); | |
571 | if (reason & MCSR_BUS_WAERR) | |
572 | printk("Bus - Write Address Error\n"); | |
573 | if (reason & MCSR_BUS_IBERR) | |
574 | printk("Bus - Instruction Data Error\n"); | |
575 | if (reason & MCSR_BUS_RBERR) | |
576 | printk("Bus - Read Data Bus Error\n"); | |
577 | if (reason & MCSR_BUS_WBERR) | |
c1528339 | 578 | printk("Bus - Write Data Bus Error\n"); |
14cf11af PM |
579 | if (reason & MCSR_BUS_IPERR) |
580 | printk("Bus - Instruction Parity Error\n"); | |
581 | if (reason & MCSR_BUS_RPERR) | |
582 | printk("Bus - Read Parity Error\n"); | |
47c0bd1a BH |
583 | |
584 | return 0; | |
585 | } | |
4490c06b KG |
586 | |
587 | int machine_check_generic(struct pt_regs *regs) | |
588 | { | |
589 | return 0; | |
590 | } | |
47c0bd1a BH |
591 | #elif defined(CONFIG_E200) |
592 | int machine_check_e200(struct pt_regs *regs) | |
593 | { | |
42bff234 | 594 | unsigned long reason = mfspr(SPRN_MCSR); |
47c0bd1a | 595 | |
14cf11af PM |
596 | printk("Machine check in kernel mode.\n"); |
597 | printk("Caused by (from MCSR=%lx): ", reason); | |
598 | ||
599 | if (reason & MCSR_MCP) | |
600 | printk("Machine Check Signal\n"); | |
601 | if (reason & MCSR_CP_PERR) | |
602 | printk("Cache Push Parity Error\n"); | |
603 | if (reason & MCSR_CPERR) | |
604 | printk("Cache Parity Error\n"); | |
605 | if (reason & MCSR_EXCP_ERR) | |
606 | printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n"); | |
607 | if (reason & MCSR_BUS_IRERR) | |
608 | printk("Bus - Read Bus Error on instruction fetch\n"); | |
609 | if (reason & MCSR_BUS_DRERR) | |
610 | printk("Bus - Read Bus Error on data load\n"); | |
611 | if (reason & MCSR_BUS_WRERR) | |
612 | printk("Bus - Write Bus Error on buffered store or cache line push\n"); | |
47c0bd1a BH |
613 | |
614 | return 0; | |
615 | } | |
7f3f819e | 616 | #elif defined(CONFIG_PPC32) |
47c0bd1a BH |
617 | int machine_check_generic(struct pt_regs *regs) |
618 | { | |
42bff234 | 619 | unsigned long reason = regs->msr; |
47c0bd1a | 620 | |
14cf11af PM |
621 | printk("Machine check in kernel mode.\n"); |
622 | printk("Caused by (from SRR1=%lx): ", reason); | |
623 | switch (reason & 0x601F0000) { | |
624 | case 0x80000: | |
625 | printk("Machine check signal\n"); | |
626 | break; | |
627 | case 0: /* for 601 */ | |
628 | case 0x40000: | |
629 | case 0x140000: /* 7450 MSS error and TEA */ | |
630 | printk("Transfer error ack signal\n"); | |
631 | break; | |
632 | case 0x20000: | |
633 | printk("Data parity error signal\n"); | |
634 | break; | |
635 | case 0x10000: | |
636 | printk("Address parity error signal\n"); | |
637 | break; | |
638 | case 0x20000000: | |
639 | printk("L1 Data Cache error\n"); | |
640 | break; | |
641 | case 0x40000000: | |
642 | printk("L1 Instruction Cache error\n"); | |
643 | break; | |
644 | case 0x00100000: | |
645 | printk("L2 data cache parity error\n"); | |
646 | break; | |
647 | default: | |
648 | printk("Unknown values in msr\n"); | |
649 | } | |
75918a4b OJ |
650 | return 0; |
651 | } | |
47c0bd1a | 652 | #endif /* everything else */ |
75918a4b OJ |
653 | |
654 | void machine_check_exception(struct pt_regs *regs) | |
655 | { | |
656 | int recover = 0; | |
b96672dd NP |
657 | bool nested = in_nmi(); |
658 | if (!nested) | |
659 | nmi_enter(); | |
75918a4b | 660 | |
f886f0f6 NP |
661 | /* 64s accounts the mce in machine_check_early when in HVMODE */ |
662 | if (!IS_ENABLED(CONFIG_PPC_BOOK3S_64) || !cpu_has_feature(CPU_FTR_HVMODE)) | |
663 | __this_cpu_inc(irq_stat.mce_exceptions); | |
89713ed1 | 664 | |
d93b0ac0 MS |
665 | add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE); |
666 | ||
47c0bd1a BH |
667 | /* See if any machine dependent calls. In theory, we would want |
668 | * to call the CPU first, and call the ppc_md. one if the CPU | |
669 | * one returns a positive number. However there is existing code | |
670 | * that assumes the board gets a first chance, so let's keep it | |
671 | * that way for now and fix things later. --BenH. | |
672 | */ | |
75918a4b OJ |
673 | if (ppc_md.machine_check_exception) |
674 | recover = ppc_md.machine_check_exception(regs); | |
47c0bd1a BH |
675 | else if (cur_cpu_spec->machine_check) |
676 | recover = cur_cpu_spec->machine_check(regs); | |
75918a4b | 677 | |
47c0bd1a | 678 | if (recover > 0) |
ba12eede | 679 | goto bail; |
75918a4b | 680 | |
a443506b | 681 | if (debugger_fault_handler(regs)) |
ba12eede | 682 | goto bail; |
75918a4b OJ |
683 | |
684 | if (check_io_access(regs)) | |
ba12eede | 685 | goto bail; |
75918a4b | 686 | |
8dad3f92 | 687 | die("Machine check", regs, SIGBUS); |
14cf11af PM |
688 | |
689 | /* Must die if the interrupt is not recoverable */ | |
690 | if (!(regs->msr & MSR_RI)) | |
b96672dd | 691 | nmi_panic(regs, "Unrecoverable Machine check"); |
ba12eede LZ |
692 | |
693 | bail: | |
b96672dd NP |
694 | if (!nested) |
695 | nmi_exit(); | |
14cf11af PM |
696 | } |
697 | ||
698 | void SMIException(struct pt_regs *regs) | |
699 | { | |
700 | die("System Management Interrupt", regs, SIGABRT); | |
701 | } | |
702 | ||
5080332c MN |
703 | #ifdef CONFIG_VSX |
704 | static void p9_hmi_special_emu(struct pt_regs *regs) | |
705 | { | |
706 | unsigned int ra, rb, t, i, sel, instr, rc; | |
707 | const void __user *addr; | |
708 | u8 vbuf[16], *vdst; | |
709 | unsigned long ea, msr, msr_mask; | |
710 | bool swap; | |
711 | ||
712 | if (__get_user_inatomic(instr, (unsigned int __user *)regs->nip)) | |
713 | return; | |
714 | ||
715 | /* | |
716 | * lxvb16x opcode: 0x7c0006d8 | |
717 | * lxvd2x opcode: 0x7c000698 | |
718 | * lxvh8x opcode: 0x7c000658 | |
719 | * lxvw4x opcode: 0x7c000618 | |
720 | */ | |
721 | if ((instr & 0xfc00073e) != 0x7c000618) { | |
722 | pr_devel("HMI vec emu: not vector CI %i:%s[%d] nip=%016lx" | |
723 | " instr=%08x\n", | |
724 | smp_processor_id(), current->comm, current->pid, | |
725 | regs->nip, instr); | |
726 | return; | |
727 | } | |
728 | ||
729 | /* Grab vector registers into the task struct */ | |
730 | msr = regs->msr; /* Grab msr before we flush the bits */ | |
731 | flush_vsx_to_thread(current); | |
732 | enable_kernel_altivec(); | |
733 | ||
734 | /* | |
735 | * Is userspace running with a different endian (this is rare but | |
736 | * not impossible) | |
737 | */ | |
738 | swap = (msr & MSR_LE) != (MSR_KERNEL & MSR_LE); | |
739 | ||
740 | /* Decode the instruction */ | |
741 | ra = (instr >> 16) & 0x1f; | |
742 | rb = (instr >> 11) & 0x1f; | |
743 | t = (instr >> 21) & 0x1f; | |
744 | if (instr & 1) | |
745 | vdst = (u8 *)¤t->thread.vr_state.vr[t]; | |
746 | else | |
747 | vdst = (u8 *)¤t->thread.fp_state.fpr[t][0]; | |
748 | ||
749 | /* Grab the vector address */ | |
750 | ea = regs->gpr[rb] + (ra ? regs->gpr[ra] : 0); | |
751 | if (is_32bit_task()) | |
752 | ea &= 0xfffffffful; | |
753 | addr = (__force const void __user *)ea; | |
754 | ||
755 | /* Check it */ | |
756 | if (!access_ok(VERIFY_READ, addr, 16)) { | |
757 | pr_devel("HMI vec emu: bad access %i:%s[%d] nip=%016lx" | |
758 | " instr=%08x addr=%016lx\n", | |
759 | smp_processor_id(), current->comm, current->pid, | |
760 | regs->nip, instr, (unsigned long)addr); | |
761 | return; | |
762 | } | |
763 | ||
764 | /* Read the vector */ | |
765 | rc = 0; | |
766 | if ((unsigned long)addr & 0xfUL) | |
767 | /* unaligned case */ | |
768 | rc = __copy_from_user_inatomic(vbuf, addr, 16); | |
769 | else | |
770 | __get_user_atomic_128_aligned(vbuf, addr, rc); | |
771 | if (rc) { | |
772 | pr_devel("HMI vec emu: page fault %i:%s[%d] nip=%016lx" | |
773 | " instr=%08x addr=%016lx\n", | |
774 | smp_processor_id(), current->comm, current->pid, | |
775 | regs->nip, instr, (unsigned long)addr); | |
776 | return; | |
777 | } | |
778 | ||
779 | pr_devel("HMI vec emu: emulated vector CI %i:%s[%d] nip=%016lx" | |
780 | " instr=%08x addr=%016lx\n", | |
781 | smp_processor_id(), current->comm, current->pid, regs->nip, | |
782 | instr, (unsigned long) addr); | |
783 | ||
784 | /* Grab instruction "selector" */ | |
785 | sel = (instr >> 6) & 3; | |
786 | ||
787 | /* | |
788 | * Check to make sure the facility is actually enabled. This | |
789 | * could happen if we get a false positive hit. | |
790 | * | |
791 | * lxvd2x/lxvw4x always check MSR VSX sel = 0,2 | |
792 | * lxvh8x/lxvb16x check MSR VSX or VEC depending on VSR used sel = 1,3 | |
793 | */ | |
794 | msr_mask = MSR_VSX; | |
795 | if ((sel & 1) && (instr & 1)) /* lxvh8x & lxvb16x + VSR >= 32 */ | |
796 | msr_mask = MSR_VEC; | |
797 | if (!(msr & msr_mask)) { | |
798 | pr_devel("HMI vec emu: MSR fac clear %i:%s[%d] nip=%016lx" | |
799 | " instr=%08x msr:%016lx\n", | |
800 | smp_processor_id(), current->comm, current->pid, | |
801 | regs->nip, instr, msr); | |
802 | return; | |
803 | } | |
804 | ||
805 | /* Do logging here before we modify sel based on endian */ | |
806 | switch (sel) { | |
807 | case 0: /* lxvw4x */ | |
808 | PPC_WARN_EMULATED(lxvw4x, regs); | |
809 | break; | |
810 | case 1: /* lxvh8x */ | |
811 | PPC_WARN_EMULATED(lxvh8x, regs); | |
812 | break; | |
813 | case 2: /* lxvd2x */ | |
814 | PPC_WARN_EMULATED(lxvd2x, regs); | |
815 | break; | |
816 | case 3: /* lxvb16x */ | |
817 | PPC_WARN_EMULATED(lxvb16x, regs); | |
818 | break; | |
819 | } | |
820 | ||
821 | #ifdef __LITTLE_ENDIAN__ | |
822 | /* | |
823 | * An LE kernel stores the vector in the task struct as an LE | |
824 | * byte array (effectively swapping both the components and | |
825 | * the content of the components). Those instructions expect | |
826 | * the components to remain in ascending address order, so we | |
827 | * swap them back. | |
828 | * | |
829 | * If we are running a BE user space, the expectation is that | |
830 | * of a simple memcpy, so forcing the emulation to look like | |
831 | * a lxvb16x should do the trick. | |
832 | */ | |
833 | if (swap) | |
834 | sel = 3; | |
835 | ||
836 | switch (sel) { | |
837 | case 0: /* lxvw4x */ | |
838 | for (i = 0; i < 4; i++) | |
839 | ((u32 *)vdst)[i] = ((u32 *)vbuf)[3-i]; | |
840 | break; | |
841 | case 1: /* lxvh8x */ | |
842 | for (i = 0; i < 8; i++) | |
843 | ((u16 *)vdst)[i] = ((u16 *)vbuf)[7-i]; | |
844 | break; | |
845 | case 2: /* lxvd2x */ | |
846 | for (i = 0; i < 2; i++) | |
847 | ((u64 *)vdst)[i] = ((u64 *)vbuf)[1-i]; | |
848 | break; | |
849 | case 3: /* lxvb16x */ | |
850 | for (i = 0; i < 16; i++) | |
851 | vdst[i] = vbuf[15-i]; | |
852 | break; | |
853 | } | |
854 | #else /* __LITTLE_ENDIAN__ */ | |
855 | /* On a big endian kernel, a BE userspace only needs a memcpy */ | |
856 | if (!swap) | |
857 | sel = 3; | |
858 | ||
859 | /* Otherwise, we need to swap the content of the components */ | |
860 | switch (sel) { | |
861 | case 0: /* lxvw4x */ | |
862 | for (i = 0; i < 4; i++) | |
863 | ((u32 *)vdst)[i] = cpu_to_le32(((u32 *)vbuf)[i]); | |
864 | break; | |
865 | case 1: /* lxvh8x */ | |
866 | for (i = 0; i < 8; i++) | |
867 | ((u16 *)vdst)[i] = cpu_to_le16(((u16 *)vbuf)[i]); | |
868 | break; | |
869 | case 2: /* lxvd2x */ | |
870 | for (i = 0; i < 2; i++) | |
871 | ((u64 *)vdst)[i] = cpu_to_le64(((u64 *)vbuf)[i]); | |
872 | break; | |
873 | case 3: /* lxvb16x */ | |
874 | memcpy(vdst, vbuf, 16); | |
875 | break; | |
876 | } | |
877 | #endif /* !__LITTLE_ENDIAN__ */ | |
878 | ||
879 | /* Go to next instruction */ | |
880 | regs->nip += 4; | |
881 | } | |
882 | #endif /* CONFIG_VSX */ | |
883 | ||
0869b6fd MS |
884 | void handle_hmi_exception(struct pt_regs *regs) |
885 | { | |
886 | struct pt_regs *old_regs; | |
887 | ||
888 | old_regs = set_irq_regs(regs); | |
889 | irq_enter(); | |
890 | ||
5080332c MN |
891 | #ifdef CONFIG_VSX |
892 | /* Real mode flagged P9 special emu is needed */ | |
893 | if (local_paca->hmi_p9_special_emu) { | |
894 | local_paca->hmi_p9_special_emu = 0; | |
895 | ||
896 | /* | |
897 | * We don't want to take page faults while doing the | |
898 | * emulation, we just replay the instruction if necessary. | |
899 | */ | |
900 | pagefault_disable(); | |
901 | p9_hmi_special_emu(regs); | |
902 | pagefault_enable(); | |
903 | } | |
904 | #endif /* CONFIG_VSX */ | |
905 | ||
0869b6fd MS |
906 | if (ppc_md.handle_hmi_exception) |
907 | ppc_md.handle_hmi_exception(regs); | |
908 | ||
909 | irq_exit(); | |
910 | set_irq_regs(old_regs); | |
911 | } | |
912 | ||
dc1c1ca3 | 913 | void unknown_exception(struct pt_regs *regs) |
14cf11af | 914 | { |
ba12eede LZ |
915 | enum ctx_state prev_state = exception_enter(); |
916 | ||
14cf11af PM |
917 | printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", |
918 | regs->nip, regs->msr, regs->trap); | |
919 | ||
cf4674c4 | 920 | _exception(SIGTRAP, regs, TRAP_FIXME, 0); |
ba12eede LZ |
921 | |
922 | exception_exit(prev_state); | |
14cf11af PM |
923 | } |
924 | ||
dc1c1ca3 | 925 | void instruction_breakpoint_exception(struct pt_regs *regs) |
14cf11af | 926 | { |
ba12eede LZ |
927 | enum ctx_state prev_state = exception_enter(); |
928 | ||
14cf11af PM |
929 | if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5, |
930 | 5, SIGTRAP) == NOTIFY_STOP) | |
ba12eede | 931 | goto bail; |
14cf11af | 932 | if (debugger_iabr_match(regs)) |
ba12eede | 933 | goto bail; |
14cf11af | 934 | _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); |
ba12eede LZ |
935 | |
936 | bail: | |
937 | exception_exit(prev_state); | |
14cf11af PM |
938 | } |
939 | ||
940 | void RunModeException(struct pt_regs *regs) | |
941 | { | |
cf4674c4 | 942 | _exception(SIGTRAP, regs, TRAP_FIXME, 0); |
14cf11af PM |
943 | } |
944 | ||
03465f89 | 945 | void single_step_exception(struct pt_regs *regs) |
14cf11af | 946 | { |
ba12eede LZ |
947 | enum ctx_state prev_state = exception_enter(); |
948 | ||
2538c2d0 | 949 | clear_single_step(regs); |
14cf11af | 950 | |
6cc89bad NR |
951 | if (kprobe_post_handler(regs)) |
952 | return; | |
953 | ||
14cf11af PM |
954 | if (notify_die(DIE_SSTEP, "single_step", regs, 5, |
955 | 5, SIGTRAP) == NOTIFY_STOP) | |
ba12eede | 956 | goto bail; |
14cf11af | 957 | if (debugger_sstep(regs)) |
ba12eede | 958 | goto bail; |
14cf11af PM |
959 | |
960 | _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); | |
ba12eede LZ |
961 | |
962 | bail: | |
963 | exception_exit(prev_state); | |
14cf11af | 964 | } |
03465f89 | 965 | NOKPROBE_SYMBOL(single_step_exception); |
14cf11af PM |
966 | |
967 | /* | |
968 | * After we have successfully emulated an instruction, we have to | |
969 | * check if the instruction was being single-stepped, and if so, | |
970 | * pretend we got a single-step exception. This was pointed out | |
971 | * by Kumar Gala. -- paulus | |
972 | */ | |
8dad3f92 | 973 | static void emulate_single_step(struct pt_regs *regs) |
14cf11af | 974 | { |
2538c2d0 P |
975 | if (single_stepping(regs)) |
976 | single_step_exception(regs); | |
14cf11af PM |
977 | } |
978 | ||
5fad293b | 979 | static inline int __parse_fpscr(unsigned long fpscr) |
dc1c1ca3 | 980 | { |
cf4674c4 | 981 | int ret = FPE_FIXME; |
dc1c1ca3 SR |
982 | |
983 | /* Invalid operation */ | |
984 | if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX)) | |
5fad293b | 985 | ret = FPE_FLTINV; |
dc1c1ca3 SR |
986 | |
987 | /* Overflow */ | |
988 | else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX)) | |
5fad293b | 989 | ret = FPE_FLTOVF; |
dc1c1ca3 SR |
990 | |
991 | /* Underflow */ | |
992 | else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX)) | |
5fad293b | 993 | ret = FPE_FLTUND; |
dc1c1ca3 SR |
994 | |
995 | /* Divide by zero */ | |
996 | else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX)) | |
5fad293b | 997 | ret = FPE_FLTDIV; |
dc1c1ca3 SR |
998 | |
999 | /* Inexact result */ | |
1000 | else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX)) | |
5fad293b KG |
1001 | ret = FPE_FLTRES; |
1002 | ||
1003 | return ret; | |
1004 | } | |
1005 | ||
1006 | static void parse_fpe(struct pt_regs *regs) | |
1007 | { | |
1008 | int code = 0; | |
1009 | ||
1010 | flush_fp_to_thread(current); | |
1011 | ||
de79f7b9 | 1012 | code = __parse_fpscr(current->thread.fp_state.fpscr); |
dc1c1ca3 SR |
1013 | |
1014 | _exception(SIGFPE, regs, code, regs->nip); | |
1015 | } | |
1016 | ||
1017 | /* | |
1018 | * Illegal instruction emulation support. Originally written to | |
14cf11af PM |
1019 | * provide the PVR to user applications using the mfspr rd, PVR. |
1020 | * Return non-zero if we can't emulate, or -EFAULT if the associated | |
1021 | * memory access caused an access fault. Return zero on success. | |
1022 | * | |
1023 | * There are a couple of ways to do this, either "decode" the instruction | |
1024 | * or directly match lots of bits. In this case, matching lots of | |
1025 | * bits is faster and easier. | |
86417780 | 1026 | * |
14cf11af | 1027 | */ |
14cf11af PM |
1028 | static int emulate_string_inst(struct pt_regs *regs, u32 instword) |
1029 | { | |
1030 | u8 rT = (instword >> 21) & 0x1f; | |
1031 | u8 rA = (instword >> 16) & 0x1f; | |
1032 | u8 NB_RB = (instword >> 11) & 0x1f; | |
1033 | u32 num_bytes; | |
1034 | unsigned long EA; | |
1035 | int pos = 0; | |
1036 | ||
1037 | /* Early out if we are an invalid form of lswx */ | |
16c57b36 | 1038 | if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX) |
14cf11af PM |
1039 | if ((rT == rA) || (rT == NB_RB)) |
1040 | return -EINVAL; | |
1041 | ||
1042 | EA = (rA == 0) ? 0 : regs->gpr[rA]; | |
1043 | ||
16c57b36 KG |
1044 | switch (instword & PPC_INST_STRING_MASK) { |
1045 | case PPC_INST_LSWX: | |
1046 | case PPC_INST_STSWX: | |
14cf11af PM |
1047 | EA += NB_RB; |
1048 | num_bytes = regs->xer & 0x7f; | |
1049 | break; | |
16c57b36 KG |
1050 | case PPC_INST_LSWI: |
1051 | case PPC_INST_STSWI: | |
14cf11af PM |
1052 | num_bytes = (NB_RB == 0) ? 32 : NB_RB; |
1053 | break; | |
1054 | default: | |
1055 | return -EINVAL; | |
1056 | } | |
1057 | ||
1058 | while (num_bytes != 0) | |
1059 | { | |
1060 | u8 val; | |
1061 | u32 shift = 8 * (3 - (pos & 0x3)); | |
1062 | ||
80aa0fb4 JY |
1063 | /* if process is 32-bit, clear upper 32 bits of EA */ |
1064 | if ((regs->msr & MSR_64BIT) == 0) | |
1065 | EA &= 0xFFFFFFFF; | |
1066 | ||
16c57b36 KG |
1067 | switch ((instword & PPC_INST_STRING_MASK)) { |
1068 | case PPC_INST_LSWX: | |
1069 | case PPC_INST_LSWI: | |
14cf11af PM |
1070 | if (get_user(val, (u8 __user *)EA)) |
1071 | return -EFAULT; | |
1072 | /* first time updating this reg, | |
1073 | * zero it out */ | |
1074 | if (pos == 0) | |
1075 | regs->gpr[rT] = 0; | |
1076 | regs->gpr[rT] |= val << shift; | |
1077 | break; | |
16c57b36 KG |
1078 | case PPC_INST_STSWI: |
1079 | case PPC_INST_STSWX: | |
14cf11af PM |
1080 | val = regs->gpr[rT] >> shift; |
1081 | if (put_user(val, (u8 __user *)EA)) | |
1082 | return -EFAULT; | |
1083 | break; | |
1084 | } | |
1085 | /* move EA to next address */ | |
1086 | EA += 1; | |
1087 | num_bytes--; | |
1088 | ||
1089 | /* manage our position within the register */ | |
1090 | if (++pos == 4) { | |
1091 | pos = 0; | |
1092 | if (++rT == 32) | |
1093 | rT = 0; | |
1094 | } | |
1095 | } | |
1096 | ||
1097 | return 0; | |
1098 | } | |
1099 | ||
c3412dcb WS |
1100 | static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword) |
1101 | { | |
1102 | u32 ra,rs; | |
1103 | unsigned long tmp; | |
1104 | ||
1105 | ra = (instword >> 16) & 0x1f; | |
1106 | rs = (instword >> 21) & 0x1f; | |
1107 | ||
1108 | tmp = regs->gpr[rs]; | |
1109 | tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL); | |
1110 | tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL); | |
1111 | tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL; | |
1112 | regs->gpr[ra] = tmp; | |
1113 | ||
1114 | return 0; | |
1115 | } | |
1116 | ||
c1469f13 KG |
1117 | static int emulate_isel(struct pt_regs *regs, u32 instword) |
1118 | { | |
1119 | u8 rT = (instword >> 21) & 0x1f; | |
1120 | u8 rA = (instword >> 16) & 0x1f; | |
1121 | u8 rB = (instword >> 11) & 0x1f; | |
1122 | u8 BC = (instword >> 6) & 0x1f; | |
1123 | u8 bit; | |
1124 | unsigned long tmp; | |
1125 | ||
1126 | tmp = (rA == 0) ? 0 : regs->gpr[rA]; | |
1127 | bit = (regs->ccr >> (31 - BC)) & 0x1; | |
1128 | ||
1129 | regs->gpr[rT] = bit ? tmp : regs->gpr[rB]; | |
1130 | ||
1131 | return 0; | |
1132 | } | |
1133 | ||
6ce6c629 MN |
1134 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1135 | static inline bool tm_abort_check(struct pt_regs *regs, int cause) | |
1136 | { | |
1137 | /* If we're emulating a load/store in an active transaction, we cannot | |
1138 | * emulate it as the kernel operates in transaction suspended context. | |
1139 | * We need to abort the transaction. This creates a persistent TM | |
1140 | * abort so tell the user what caused it with a new code. | |
1141 | */ | |
1142 | if (MSR_TM_TRANSACTIONAL(regs->msr)) { | |
1143 | tm_enable(); | |
1144 | tm_abort(cause); | |
1145 | return true; | |
1146 | } | |
1147 | return false; | |
1148 | } | |
1149 | #else | |
1150 | static inline bool tm_abort_check(struct pt_regs *regs, int reason) | |
1151 | { | |
1152 | return false; | |
1153 | } | |
1154 | #endif | |
1155 | ||
14cf11af PM |
1156 | static int emulate_instruction(struct pt_regs *regs) |
1157 | { | |
1158 | u32 instword; | |
1159 | u32 rd; | |
1160 | ||
4288e343 | 1161 | if (!user_mode(regs)) |
14cf11af PM |
1162 | return -EINVAL; |
1163 | CHECK_FULL_REGS(regs); | |
1164 | ||
1165 | if (get_user(instword, (u32 __user *)(regs->nip))) | |
1166 | return -EFAULT; | |
1167 | ||
1168 | /* Emulate the mfspr rD, PVR. */ | |
16c57b36 | 1169 | if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) { |
eecff81d | 1170 | PPC_WARN_EMULATED(mfpvr, regs); |
14cf11af PM |
1171 | rd = (instword >> 21) & 0x1f; |
1172 | regs->gpr[rd] = mfspr(SPRN_PVR); | |
1173 | return 0; | |
1174 | } | |
1175 | ||
1176 | /* Emulating the dcba insn is just a no-op. */ | |
80947e7c | 1177 | if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) { |
eecff81d | 1178 | PPC_WARN_EMULATED(dcba, regs); |
14cf11af | 1179 | return 0; |
80947e7c | 1180 | } |
14cf11af PM |
1181 | |
1182 | /* Emulate the mcrxr insn. */ | |
16c57b36 | 1183 | if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) { |
86417780 | 1184 | int shift = (instword >> 21) & 0x1c; |
14cf11af PM |
1185 | unsigned long msk = 0xf0000000UL >> shift; |
1186 | ||
eecff81d | 1187 | PPC_WARN_EMULATED(mcrxr, regs); |
14cf11af PM |
1188 | regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); |
1189 | regs->xer &= ~0xf0000000UL; | |
1190 | return 0; | |
1191 | } | |
1192 | ||
1193 | /* Emulate load/store string insn. */ | |
80947e7c | 1194 | if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) { |
6ce6c629 MN |
1195 | if (tm_abort_check(regs, |
1196 | TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT)) | |
1197 | return -EINVAL; | |
eecff81d | 1198 | PPC_WARN_EMULATED(string, regs); |
14cf11af | 1199 | return emulate_string_inst(regs, instword); |
80947e7c | 1200 | } |
14cf11af | 1201 | |
c3412dcb | 1202 | /* Emulate the popcntb (Population Count Bytes) instruction. */ |
16c57b36 | 1203 | if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) { |
eecff81d | 1204 | PPC_WARN_EMULATED(popcntb, regs); |
c3412dcb WS |
1205 | return emulate_popcntb_inst(regs, instword); |
1206 | } | |
1207 | ||
c1469f13 | 1208 | /* Emulate isel (Integer Select) instruction */ |
16c57b36 | 1209 | if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) { |
eecff81d | 1210 | PPC_WARN_EMULATED(isel, regs); |
c1469f13 KG |
1211 | return emulate_isel(regs, instword); |
1212 | } | |
1213 | ||
9863c28a JY |
1214 | /* Emulate sync instruction variants */ |
1215 | if ((instword & PPC_INST_SYNC_MASK) == PPC_INST_SYNC) { | |
1216 | PPC_WARN_EMULATED(sync, regs); | |
1217 | asm volatile("sync"); | |
1218 | return 0; | |
1219 | } | |
1220 | ||
efcac658 AK |
1221 | #ifdef CONFIG_PPC64 |
1222 | /* Emulate the mfspr rD, DSCR. */ | |
73d2fb75 AB |
1223 | if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) == |
1224 | PPC_INST_MFSPR_DSCR_USER) || | |
1225 | ((instword & PPC_INST_MFSPR_DSCR_MASK) == | |
1226 | PPC_INST_MFSPR_DSCR)) && | |
efcac658 AK |
1227 | cpu_has_feature(CPU_FTR_DSCR)) { |
1228 | PPC_WARN_EMULATED(mfdscr, regs); | |
1229 | rd = (instword >> 21) & 0x1f; | |
1230 | regs->gpr[rd] = mfspr(SPRN_DSCR); | |
1231 | return 0; | |
1232 | } | |
1233 | /* Emulate the mtspr DSCR, rD. */ | |
73d2fb75 AB |
1234 | if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) == |
1235 | PPC_INST_MTSPR_DSCR_USER) || | |
1236 | ((instword & PPC_INST_MTSPR_DSCR_MASK) == | |
1237 | PPC_INST_MTSPR_DSCR)) && | |
efcac658 AK |
1238 | cpu_has_feature(CPU_FTR_DSCR)) { |
1239 | PPC_WARN_EMULATED(mtdscr, regs); | |
1240 | rd = (instword >> 21) & 0x1f; | |
00ca0de0 | 1241 | current->thread.dscr = regs->gpr[rd]; |
efcac658 | 1242 | current->thread.dscr_inherit = 1; |
00ca0de0 | 1243 | mtspr(SPRN_DSCR, current->thread.dscr); |
efcac658 AK |
1244 | return 0; |
1245 | } | |
1246 | #endif | |
1247 | ||
14cf11af PM |
1248 | return -EINVAL; |
1249 | } | |
1250 | ||
73c9ceab | 1251 | int is_valid_bugaddr(unsigned long addr) |
14cf11af | 1252 | { |
73c9ceab | 1253 | return is_kernel_addr(addr); |
14cf11af PM |
1254 | } |
1255 | ||
3a3b5aa6 KH |
1256 | #ifdef CONFIG_MATH_EMULATION |
1257 | static int emulate_math(struct pt_regs *regs) | |
1258 | { | |
1259 | int ret; | |
1260 | extern int do_mathemu(struct pt_regs *regs); | |
1261 | ||
1262 | ret = do_mathemu(regs); | |
1263 | if (ret >= 0) | |
1264 | PPC_WARN_EMULATED(math, regs); | |
1265 | ||
1266 | switch (ret) { | |
1267 | case 0: | |
1268 | emulate_single_step(regs); | |
1269 | return 0; | |
1270 | case 1: { | |
1271 | int code = 0; | |
de79f7b9 | 1272 | code = __parse_fpscr(current->thread.fp_state.fpscr); |
3a3b5aa6 KH |
1273 | _exception(SIGFPE, regs, code, regs->nip); |
1274 | return 0; | |
1275 | } | |
1276 | case -EFAULT: | |
1277 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
1278 | return 0; | |
1279 | } | |
1280 | ||
1281 | return -1; | |
1282 | } | |
1283 | #else | |
1284 | static inline int emulate_math(struct pt_regs *regs) { return -1; } | |
1285 | #endif | |
1286 | ||
03465f89 | 1287 | void program_check_exception(struct pt_regs *regs) |
14cf11af | 1288 | { |
ba12eede | 1289 | enum ctx_state prev_state = exception_enter(); |
14cf11af | 1290 | unsigned int reason = get_reason(regs); |
14cf11af | 1291 | |
aa42c69c | 1292 | /* We can now get here via a FP Unavailable exception if the core |
04903a30 | 1293 | * has no FPU, in that case the reason flags will be 0 */ |
14cf11af | 1294 | |
dc1c1ca3 SR |
1295 | if (reason & REASON_FP) { |
1296 | /* IEEE FP exception */ | |
1297 | parse_fpe(regs); | |
ba12eede | 1298 | goto bail; |
8dad3f92 PM |
1299 | } |
1300 | if (reason & REASON_TRAP) { | |
a4c3f909 | 1301 | unsigned long bugaddr; |
ba797b28 JW |
1302 | /* Debugger is first in line to stop recursive faults in |
1303 | * rcu_lock, notify_die, or atomic_notifier_call_chain */ | |
1304 | if (debugger_bpt(regs)) | |
ba12eede | 1305 | goto bail; |
ba797b28 | 1306 | |
6cc89bad NR |
1307 | if (kprobe_handler(regs)) |
1308 | goto bail; | |
1309 | ||
14cf11af | 1310 | /* trap exception */ |
dc1c1ca3 SR |
1311 | if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP) |
1312 | == NOTIFY_STOP) | |
ba12eede | 1313 | goto bail; |
73c9ceab | 1314 | |
a4c3f909 BS |
1315 | bugaddr = regs->nip; |
1316 | /* | |
1317 | * Fixup bugaddr for BUG_ON() in real mode | |
1318 | */ | |
1319 | if (!is_kernel_addr(bugaddr) && !(regs->msr & MSR_IR)) | |
1320 | bugaddr += PAGE_OFFSET; | |
1321 | ||
73c9ceab | 1322 | if (!(regs->msr & MSR_PR) && /* not user-mode */ |
a4c3f909 | 1323 | report_bug(bugaddr, regs) == BUG_TRAP_TYPE_WARN) { |
14cf11af | 1324 | regs->nip += 4; |
ba12eede | 1325 | goto bail; |
14cf11af | 1326 | } |
8dad3f92 | 1327 | _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); |
ba12eede | 1328 | goto bail; |
8dad3f92 | 1329 | } |
bc2a9408 MN |
1330 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1331 | if (reason & REASON_TM) { | |
1332 | /* This is a TM "Bad Thing Exception" program check. | |
1333 | * This occurs when: | |
1334 | * - An rfid/hrfid/mtmsrd attempts to cause an illegal | |
1335 | * transition in TM states. | |
1336 | * - A trechkpt is attempted when transactional. | |
1337 | * - A treclaim is attempted when non transactional. | |
1338 | * - A tend is illegally attempted. | |
1339 | * - writing a TM SPR when transactional. | |
632f0574 ME |
1340 | * |
1341 | * If usermode caused this, it's done something illegal and | |
bc2a9408 MN |
1342 | * gets a SIGILL slap on the wrist. We call it an illegal |
1343 | * operand to distinguish from the instruction just being bad | |
1344 | * (e.g. executing a 'tend' on a CPU without TM!); it's an | |
1345 | * illegal /placement/ of a valid instruction. | |
1346 | */ | |
1347 | if (user_mode(regs)) { | |
1348 | _exception(SIGILL, regs, ILL_ILLOPN, regs->nip); | |
ba12eede | 1349 | goto bail; |
bc2a9408 MN |
1350 | } else { |
1351 | printk(KERN_EMERG "Unexpected TM Bad Thing exception " | |
1352 | "at %lx (msr 0x%x)\n", regs->nip, reason); | |
1353 | die("Unrecoverable exception", regs, SIGABRT); | |
1354 | } | |
1355 | } | |
1356 | #endif | |
8dad3f92 | 1357 | |
b3f6a459 ME |
1358 | /* |
1359 | * If we took the program check in the kernel skip down to sending a | |
1360 | * SIGILL. The subsequent cases all relate to emulating instructions | |
1361 | * which we should only do for userspace. We also do not want to enable | |
1362 | * interrupts for kernel faults because that might lead to further | |
1363 | * faults, and loose the context of the original exception. | |
1364 | */ | |
1365 | if (!user_mode(regs)) | |
1366 | goto sigill; | |
1367 | ||
a3512b2d BH |
1368 | /* We restore the interrupt state now */ |
1369 | if (!arch_irq_disabled_regs(regs)) | |
1370 | local_irq_enable(); | |
cd8a5673 | 1371 | |
04903a30 KG |
1372 | /* (reason & REASON_ILLEGAL) would be the obvious thing here, |
1373 | * but there seems to be a hardware bug on the 405GP (RevD) | |
1374 | * that means ESR is sometimes set incorrectly - either to | |
1375 | * ESR_DST (!?) or 0. In the process of chasing this with the | |
1376 | * hardware people - not sure if it can happen on any illegal | |
1377 | * instruction or only on FP instructions, whether there is a | |
4e63f8ed BH |
1378 | * pattern to occurrences etc. -dgibson 31/Mar/2003 |
1379 | */ | |
3a3b5aa6 | 1380 | if (!emulate_math(regs)) |
ba12eede | 1381 | goto bail; |
04903a30 | 1382 | |
8dad3f92 PM |
1383 | /* Try to emulate it if we should. */ |
1384 | if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { | |
14cf11af PM |
1385 | switch (emulate_instruction(regs)) { |
1386 | case 0: | |
1387 | regs->nip += 4; | |
1388 | emulate_single_step(regs); | |
ba12eede | 1389 | goto bail; |
14cf11af PM |
1390 | case -EFAULT: |
1391 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
ba12eede | 1392 | goto bail; |
14cf11af PM |
1393 | } |
1394 | } | |
8dad3f92 | 1395 | |
b3f6a459 | 1396 | sigill: |
8dad3f92 PM |
1397 | if (reason & REASON_PRIVILEGED) |
1398 | _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); | |
1399 | else | |
1400 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
ba12eede LZ |
1401 | |
1402 | bail: | |
1403 | exception_exit(prev_state); | |
14cf11af | 1404 | } |
03465f89 | 1405 | NOKPROBE_SYMBOL(program_check_exception); |
14cf11af | 1406 | |
bf593907 PM |
1407 | /* |
1408 | * This occurs when running in hypervisor mode on POWER6 or later | |
1409 | * and an illegal instruction is encountered. | |
1410 | */ | |
03465f89 | 1411 | void emulation_assist_interrupt(struct pt_regs *regs) |
bf593907 PM |
1412 | { |
1413 | regs->msr |= REASON_ILLEGAL; | |
1414 | program_check_exception(regs); | |
1415 | } | |
03465f89 | 1416 | NOKPROBE_SYMBOL(emulation_assist_interrupt); |
bf593907 | 1417 | |
dc1c1ca3 | 1418 | void alignment_exception(struct pt_regs *regs) |
14cf11af | 1419 | { |
ba12eede | 1420 | enum ctx_state prev_state = exception_enter(); |
4393c4f6 | 1421 | int sig, code, fixed = 0; |
14cf11af | 1422 | |
a3512b2d BH |
1423 | /* We restore the interrupt state now */ |
1424 | if (!arch_irq_disabled_regs(regs)) | |
1425 | local_irq_enable(); | |
1426 | ||
6ce6c629 MN |
1427 | if (tm_abort_check(regs, TM_CAUSE_ALIGNMENT | TM_CAUSE_PERSISTENT)) |
1428 | goto bail; | |
1429 | ||
e9370ae1 PM |
1430 | /* we don't implement logging of alignment exceptions */ |
1431 | if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS)) | |
1432 | fixed = fix_alignment(regs); | |
14cf11af PM |
1433 | |
1434 | if (fixed == 1) { | |
1435 | regs->nip += 4; /* skip over emulated instruction */ | |
1436 | emulate_single_step(regs); | |
ba12eede | 1437 | goto bail; |
14cf11af PM |
1438 | } |
1439 | ||
dc1c1ca3 | 1440 | /* Operand address was bad */ |
14cf11af | 1441 | if (fixed == -EFAULT) { |
4393c4f6 BH |
1442 | sig = SIGSEGV; |
1443 | code = SEGV_ACCERR; | |
1444 | } else { | |
1445 | sig = SIGBUS; | |
1446 | code = BUS_ADRALN; | |
14cf11af | 1447 | } |
4393c4f6 BH |
1448 | if (user_mode(regs)) |
1449 | _exception(sig, regs, code, regs->dar); | |
1450 | else | |
1451 | bad_page_fault(regs, regs->dar, sig); | |
ba12eede LZ |
1452 | |
1453 | bail: | |
1454 | exception_exit(prev_state); | |
14cf11af PM |
1455 | } |
1456 | ||
f0f558b1 PM |
1457 | void slb_miss_bad_addr(struct pt_regs *regs) |
1458 | { | |
1459 | enum ctx_state prev_state = exception_enter(); | |
1460 | ||
1461 | if (user_mode(regs)) | |
1462 | _exception(SIGSEGV, regs, SEGV_BNDERR, regs->dar); | |
1463 | else | |
1464 | bad_page_fault(regs, regs->dar, SIGSEGV); | |
1465 | ||
1466 | exception_exit(prev_state); | |
1467 | } | |
1468 | ||
14cf11af PM |
1469 | void StackOverflow(struct pt_regs *regs) |
1470 | { | |
1471 | printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n", | |
1472 | current, regs->gpr[1]); | |
1473 | debugger(regs); | |
1474 | show_regs(regs); | |
1475 | panic("kernel stack overflow"); | |
1476 | } | |
1477 | ||
1478 | void nonrecoverable_exception(struct pt_regs *regs) | |
1479 | { | |
1480 | printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n", | |
1481 | regs->nip, regs->msr); | |
1482 | debugger(regs); | |
1483 | die("nonrecoverable exception", regs, SIGKILL); | |
1484 | } | |
1485 | ||
dc1c1ca3 SR |
1486 | void kernel_fp_unavailable_exception(struct pt_regs *regs) |
1487 | { | |
ba12eede LZ |
1488 | enum ctx_state prev_state = exception_enter(); |
1489 | ||
dc1c1ca3 SR |
1490 | printk(KERN_EMERG "Unrecoverable FP Unavailable Exception " |
1491 | "%lx at %lx\n", regs->trap, regs->nip); | |
1492 | die("Unrecoverable FP Unavailable Exception", regs, SIGABRT); | |
ba12eede LZ |
1493 | |
1494 | exception_exit(prev_state); | |
dc1c1ca3 | 1495 | } |
dc1c1ca3 SR |
1496 | |
1497 | void altivec_unavailable_exception(struct pt_regs *regs) | |
1498 | { | |
ba12eede LZ |
1499 | enum ctx_state prev_state = exception_enter(); |
1500 | ||
dc1c1ca3 SR |
1501 | if (user_mode(regs)) { |
1502 | /* A user program has executed an altivec instruction, | |
1503 | but this kernel doesn't support altivec. */ | |
1504 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
ba12eede | 1505 | goto bail; |
dc1c1ca3 | 1506 | } |
6c4841c2 | 1507 | |
dc1c1ca3 SR |
1508 | printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception " |
1509 | "%lx at %lx\n", regs->trap, regs->nip); | |
1510 | die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT); | |
ba12eede LZ |
1511 | |
1512 | bail: | |
1513 | exception_exit(prev_state); | |
dc1c1ca3 SR |
1514 | } |
1515 | ||
ce48b210 MN |
1516 | void vsx_unavailable_exception(struct pt_regs *regs) |
1517 | { | |
1518 | if (user_mode(regs)) { | |
1519 | /* A user program has executed an vsx instruction, | |
1520 | but this kernel doesn't support vsx. */ | |
1521 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
1522 | return; | |
1523 | } | |
1524 | ||
1525 | printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception " | |
1526 | "%lx at %lx\n", regs->trap, regs->nip); | |
1527 | die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT); | |
1528 | } | |
1529 | ||
2517617e | 1530 | #ifdef CONFIG_PPC64 |
172f7aaa CB |
1531 | static void tm_unavailable(struct pt_regs *regs) |
1532 | { | |
5d176f75 CB |
1533 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1534 | if (user_mode(regs)) { | |
1535 | current->thread.load_tm++; | |
1536 | regs->msr |= MSR_TM; | |
1537 | tm_enable(); | |
1538 | tm_restore_sprs(¤t->thread); | |
1539 | return; | |
1540 | } | |
1541 | #endif | |
172f7aaa CB |
1542 | pr_emerg("Unrecoverable TM Unavailable Exception " |
1543 | "%lx at %lx\n", regs->trap, regs->nip); | |
1544 | die("Unrecoverable TM Unavailable Exception", regs, SIGABRT); | |
1545 | } | |
1546 | ||
021424a1 | 1547 | void facility_unavailable_exception(struct pt_regs *regs) |
d0c0c9a1 | 1548 | { |
021424a1 | 1549 | static char *facility_strings[] = { |
2517617e MN |
1550 | [FSCR_FP_LG] = "FPU", |
1551 | [FSCR_VECVSX_LG] = "VMX/VSX", | |
1552 | [FSCR_DSCR_LG] = "DSCR", | |
1553 | [FSCR_PM_LG] = "PMU SPRs", | |
1554 | [FSCR_BHRB_LG] = "BHRB", | |
1555 | [FSCR_TM_LG] = "TM", | |
1556 | [FSCR_EBB_LG] = "EBB", | |
1557 | [FSCR_TAR_LG] = "TAR", | |
794464f4 | 1558 | [FSCR_MSGP_LG] = "MSGP", |
9b7ff0c6 | 1559 | [FSCR_SCV_LG] = "SCV", |
021424a1 | 1560 | }; |
2517617e | 1561 | char *facility = "unknown"; |
021424a1 | 1562 | u64 value; |
c952c1c4 | 1563 | u32 instword, rd; |
2517617e MN |
1564 | u8 status; |
1565 | bool hv; | |
021424a1 | 1566 | |
2517617e MN |
1567 | hv = (regs->trap == 0xf80); |
1568 | if (hv) | |
b14b6260 | 1569 | value = mfspr(SPRN_HFSCR); |
2517617e MN |
1570 | else |
1571 | value = mfspr(SPRN_FSCR); | |
1572 | ||
1573 | status = value >> 56; | |
1574 | if (status == FSCR_DSCR_LG) { | |
c952c1c4 AK |
1575 | /* |
1576 | * User is accessing the DSCR register using the problem | |
1577 | * state only SPR number (0x03) either through a mfspr or | |
1578 | * a mtspr instruction. If it is a write attempt through | |
1579 | * a mtspr, then we set the inherit bit. This also allows | |
1580 | * the user to write or read the register directly in the | |
1581 | * future by setting via the FSCR DSCR bit. But in case it | |
1582 | * is a read DSCR attempt through a mfspr instruction, we | |
1583 | * just emulate the instruction instead. This code path will | |
1584 | * always emulate all the mfspr instructions till the user | |
446957ba | 1585 | * has attempted at least one mtspr instruction. This way it |
c952c1c4 AK |
1586 | * preserves the same behaviour when the user is accessing |
1587 | * the DSCR through privilege level only SPR number (0x11) | |
1588 | * which is emulated through illegal instruction exception. | |
1589 | * We always leave HFSCR DSCR set. | |
2517617e | 1590 | */ |
c952c1c4 AK |
1591 | if (get_user(instword, (u32 __user *)(regs->nip))) { |
1592 | pr_err("Failed to fetch the user instruction\n"); | |
1593 | return; | |
1594 | } | |
1595 | ||
1596 | /* Write into DSCR (mtspr 0x03, RS) */ | |
1597 | if ((instword & PPC_INST_MTSPR_DSCR_USER_MASK) | |
1598 | == PPC_INST_MTSPR_DSCR_USER) { | |
1599 | rd = (instword >> 21) & 0x1f; | |
1600 | current->thread.dscr = regs->gpr[rd]; | |
1601 | current->thread.dscr_inherit = 1; | |
b57bd2de MN |
1602 | current->thread.fscr |= FSCR_DSCR; |
1603 | mtspr(SPRN_FSCR, current->thread.fscr); | |
c952c1c4 AK |
1604 | } |
1605 | ||
1606 | /* Read from DSCR (mfspr RT, 0x03) */ | |
1607 | if ((instword & PPC_INST_MFSPR_DSCR_USER_MASK) | |
1608 | == PPC_INST_MFSPR_DSCR_USER) { | |
1609 | if (emulate_instruction(regs)) { | |
1610 | pr_err("DSCR based mfspr emulation failed\n"); | |
1611 | return; | |
1612 | } | |
1613 | regs->nip += 4; | |
1614 | emulate_single_step(regs); | |
1615 | } | |
2517617e | 1616 | return; |
b14b6260 ME |
1617 | } |
1618 | ||
172f7aaa CB |
1619 | if (status == FSCR_TM_LG) { |
1620 | /* | |
1621 | * If we're here then the hardware is TM aware because it | |
1622 | * generated an exception with FSRM_TM set. | |
1623 | * | |
1624 | * If cpu_has_feature(CPU_FTR_TM) is false, then either firmware | |
1625 | * told us not to do TM, or the kernel is not built with TM | |
1626 | * support. | |
1627 | * | |
1628 | * If both of those things are true, then userspace can spam the | |
1629 | * console by triggering the printk() below just by continually | |
1630 | * doing tbegin (or any TM instruction). So in that case just | |
1631 | * send the process a SIGILL immediately. | |
1632 | */ | |
1633 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1634 | goto out; | |
1635 | ||
1636 | tm_unavailable(regs); | |
1637 | return; | |
1638 | } | |
1639 | ||
93c2ec0f BS |
1640 | if ((hv || status >= 2) && |
1641 | (status < ARRAY_SIZE(facility_strings)) && | |
2517617e MN |
1642 | facility_strings[status]) |
1643 | facility = facility_strings[status]; | |
021424a1 | 1644 | |
d0c0c9a1 MN |
1645 | /* We restore the interrupt state now */ |
1646 | if (!arch_irq_disabled_regs(regs)) | |
1647 | local_irq_enable(); | |
1648 | ||
93c2ec0f BS |
1649 | pr_err_ratelimited("%sFacility '%s' unavailable (%d), exception at 0x%lx, MSR=%lx\n", |
1650 | hv ? "Hypervisor " : "", facility, status, regs->nip, regs->msr); | |
d0c0c9a1 | 1651 | |
172f7aaa | 1652 | out: |
d0c0c9a1 MN |
1653 | if (user_mode(regs)) { |
1654 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
1655 | return; | |
1656 | } | |
1657 | ||
021424a1 | 1658 | die("Unexpected facility unavailable exception", regs, SIGABRT); |
d0c0c9a1 | 1659 | } |
2517617e | 1660 | #endif |
d0c0c9a1 | 1661 | |
f54db641 MN |
1662 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1663 | ||
f54db641 MN |
1664 | void fp_unavailable_tm(struct pt_regs *regs) |
1665 | { | |
1666 | /* Note: This does not handle any kind of FP laziness. */ | |
1667 | ||
1668 | TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n", | |
1669 | regs->nip, regs->msr); | |
f54db641 MN |
1670 | |
1671 | /* We can only have got here if the task started using FP after | |
1672 | * beginning the transaction. So, the transactional regs are just a | |
1673 | * copy of the checkpointed ones. But, we still need to recheckpoint | |
1674 | * as we're enabling FP for the process; it will return, abort the | |
1675 | * transaction, and probably retry but now with FP enabled. So the | |
1676 | * checkpointed FP registers need to be loaded. | |
1677 | */ | |
d31626f7 | 1678 | tm_reclaim_current(TM_CAUSE_FAC_UNAV); |
f54db641 MN |
1679 | /* Reclaim didn't save out any FPRs to transact_fprs. */ |
1680 | ||
1681 | /* Enable FP for the task: */ | |
a7771176 | 1682 | current->thread.load_fp = 1; |
f54db641 MN |
1683 | |
1684 | /* This loads and recheckpoints the FP registers from | |
1685 | * thread.fpr[]. They will remain in registers after the | |
1686 | * checkpoint so we don't need to reload them after. | |
3ac8ff1c PM |
1687 | * If VMX is in use, the VRs now hold checkpointed values, |
1688 | * so we don't want to load the VRs from the thread_struct. | |
f54db641 | 1689 | */ |
eb5c3f1c | 1690 | tm_recheckpoint(¤t->thread); |
f54db641 MN |
1691 | } |
1692 | ||
f54db641 MN |
1693 | void altivec_unavailable_tm(struct pt_regs *regs) |
1694 | { | |
1695 | /* See the comments in fp_unavailable_tm(). This function operates | |
1696 | * the same way. | |
1697 | */ | |
1698 | ||
1699 | TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx," | |
1700 | "MSR=%lx\n", | |
1701 | regs->nip, regs->msr); | |
d31626f7 | 1702 | tm_reclaim_current(TM_CAUSE_FAC_UNAV); |
a7771176 | 1703 | current->thread.load_vec = 1; |
eb5c3f1c | 1704 | tm_recheckpoint(¤t->thread); |
f54db641 MN |
1705 | current->thread.used_vr = 1; |
1706 | } | |
f54db641 | 1707 | |
f54db641 MN |
1708 | void vsx_unavailable_tm(struct pt_regs *regs) |
1709 | { | |
1710 | /* See the comments in fp_unavailable_tm(). This works similarly, | |
1711 | * though we're loading both FP and VEC registers in here. | |
1712 | * | |
1713 | * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC | |
1714 | * regs. Either way, set MSR_VSX. | |
1715 | */ | |
1716 | ||
1717 | TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx," | |
1718 | "MSR=%lx\n", | |
1719 | regs->nip, regs->msr); | |
1720 | ||
3ac8ff1c PM |
1721 | current->thread.used_vsr = 1; |
1722 | ||
f54db641 | 1723 | /* This reclaims FP and/or VR regs if they're already enabled */ |
d31626f7 | 1724 | tm_reclaim_current(TM_CAUSE_FAC_UNAV); |
f54db641 | 1725 | |
a7771176 CB |
1726 | current->thread.load_vec = 1; |
1727 | current->thread.load_fp = 1; | |
3ac8ff1c | 1728 | |
eb5c3f1c | 1729 | tm_recheckpoint(¤t->thread); |
f54db641 | 1730 | } |
f54db641 MN |
1731 | #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ |
1732 | ||
dc1c1ca3 SR |
1733 | void performance_monitor_exception(struct pt_regs *regs) |
1734 | { | |
69111bac | 1735 | __this_cpu_inc(irq_stat.pmu_irqs); |
89713ed1 | 1736 | |
dc1c1ca3 SR |
1737 | perf_irq(regs); |
1738 | } | |
dc1c1ca3 | 1739 | |
172ae2e7 | 1740 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
3bffb652 DK |
1741 | static void handle_debug(struct pt_regs *regs, unsigned long debug_status) |
1742 | { | |
1743 | int changed = 0; | |
1744 | /* | |
1745 | * Determine the cause of the debug event, clear the | |
1746 | * event flags and send a trap to the handler. Torez | |
1747 | */ | |
1748 | if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) { | |
1749 | dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W); | |
1750 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
51ae8d4a | 1751 | current->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE; |
3bffb652 | 1752 | #endif |
47355040 | 1753 | do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, |
3bffb652 DK |
1754 | 5); |
1755 | changed |= 0x01; | |
1756 | } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) { | |
1757 | dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W); | |
47355040 | 1758 | do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, |
3bffb652 DK |
1759 | 6); |
1760 | changed |= 0x01; | |
1761 | } else if (debug_status & DBSR_IAC1) { | |
51ae8d4a | 1762 | current->thread.debug.dbcr0 &= ~DBCR0_IAC1; |
3bffb652 | 1763 | dbcr_iac_range(current) &= ~DBCR_IAC12MODE; |
47355040 | 1764 | do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, |
3bffb652 DK |
1765 | 1); |
1766 | changed |= 0x01; | |
1767 | } else if (debug_status & DBSR_IAC2) { | |
51ae8d4a | 1768 | current->thread.debug.dbcr0 &= ~DBCR0_IAC2; |
47355040 | 1769 | do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, |
3bffb652 DK |
1770 | 2); |
1771 | changed |= 0x01; | |
1772 | } else if (debug_status & DBSR_IAC3) { | |
51ae8d4a | 1773 | current->thread.debug.dbcr0 &= ~DBCR0_IAC3; |
3bffb652 | 1774 | dbcr_iac_range(current) &= ~DBCR_IAC34MODE; |
47355040 | 1775 | do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, |
3bffb652 DK |
1776 | 3); |
1777 | changed |= 0x01; | |
1778 | } else if (debug_status & DBSR_IAC4) { | |
51ae8d4a | 1779 | current->thread.debug.dbcr0 &= ~DBCR0_IAC4; |
47355040 | 1780 | do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, |
3bffb652 DK |
1781 | 4); |
1782 | changed |= 0x01; | |
1783 | } | |
1784 | /* | |
1785 | * At the point this routine was called, the MSR(DE) was turned off. | |
1786 | * Check all other debug flags and see if that bit needs to be turned | |
1787 | * back on or not. | |
1788 | */ | |
51ae8d4a | 1789 | if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0, |
95791988 | 1790 | current->thread.debug.dbcr1)) |
3bffb652 DK |
1791 | regs->msr |= MSR_DE; |
1792 | else | |
1793 | /* Make sure the IDM flag is off */ | |
51ae8d4a | 1794 | current->thread.debug.dbcr0 &= ~DBCR0_IDM; |
3bffb652 DK |
1795 | |
1796 | if (changed & 0x01) | |
51ae8d4a | 1797 | mtspr(SPRN_DBCR0, current->thread.debug.dbcr0); |
3bffb652 | 1798 | } |
14cf11af | 1799 | |
03465f89 | 1800 | void DebugException(struct pt_regs *regs, unsigned long debug_status) |
14cf11af | 1801 | { |
51ae8d4a | 1802 | current->thread.debug.dbsr = debug_status; |
3bffb652 | 1803 | |
ec097c84 RM |
1804 | /* Hack alert: On BookE, Branch Taken stops on the branch itself, while |
1805 | * on server, it stops on the target of the branch. In order to simulate | |
1806 | * the server behaviour, we thus restart right away with a single step | |
1807 | * instead of stopping here when hitting a BT | |
1808 | */ | |
1809 | if (debug_status & DBSR_BT) { | |
1810 | regs->msr &= ~MSR_DE; | |
1811 | ||
1812 | /* Disable BT */ | |
1813 | mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT); | |
1814 | /* Clear the BT event */ | |
1815 | mtspr(SPRN_DBSR, DBSR_BT); | |
1816 | ||
1817 | /* Do the single step trick only when coming from userspace */ | |
1818 | if (user_mode(regs)) { | |
51ae8d4a BB |
1819 | current->thread.debug.dbcr0 &= ~DBCR0_BT; |
1820 | current->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC; | |
ec097c84 RM |
1821 | regs->msr |= MSR_DE; |
1822 | return; | |
1823 | } | |
1824 | ||
6cc89bad NR |
1825 | if (kprobe_post_handler(regs)) |
1826 | return; | |
1827 | ||
ec097c84 RM |
1828 | if (notify_die(DIE_SSTEP, "block_step", regs, 5, |
1829 | 5, SIGTRAP) == NOTIFY_STOP) { | |
1830 | return; | |
1831 | } | |
1832 | if (debugger_sstep(regs)) | |
1833 | return; | |
1834 | } else if (debug_status & DBSR_IC) { /* Instruction complete */ | |
14cf11af | 1835 | regs->msr &= ~MSR_DE; |
f8279621 KG |
1836 | |
1837 | /* Disable instruction completion */ | |
1838 | mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC); | |
1839 | /* Clear the instruction completion event */ | |
1840 | mtspr(SPRN_DBSR, DBSR_IC); | |
1841 | ||
6cc89bad NR |
1842 | if (kprobe_post_handler(regs)) |
1843 | return; | |
1844 | ||
f8279621 KG |
1845 | if (notify_die(DIE_SSTEP, "single_step", regs, 5, |
1846 | 5, SIGTRAP) == NOTIFY_STOP) { | |
1847 | return; | |
1848 | } | |
1849 | ||
1850 | if (debugger_sstep(regs)) | |
1851 | return; | |
1852 | ||
d6a61bfc | 1853 | if (user_mode(regs)) { |
51ae8d4a BB |
1854 | current->thread.debug.dbcr0 &= ~DBCR0_IC; |
1855 | if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0, | |
1856 | current->thread.debug.dbcr1)) | |
3bffb652 DK |
1857 | regs->msr |= MSR_DE; |
1858 | else | |
1859 | /* Make sure the IDM bit is off */ | |
51ae8d4a | 1860 | current->thread.debug.dbcr0 &= ~DBCR0_IDM; |
d6a61bfc | 1861 | } |
3bffb652 DK |
1862 | |
1863 | _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); | |
1864 | } else | |
1865 | handle_debug(regs, debug_status); | |
14cf11af | 1866 | } |
03465f89 | 1867 | NOKPROBE_SYMBOL(DebugException); |
172ae2e7 | 1868 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ |
14cf11af PM |
1869 | |
1870 | #if !defined(CONFIG_TAU_INT) | |
1871 | void TAUException(struct pt_regs *regs) | |
1872 | { | |
1873 | printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n", | |
1874 | regs->nip, regs->msr, regs->trap, print_tainted()); | |
1875 | } | |
1876 | #endif /* CONFIG_INT_TAU */ | |
14cf11af PM |
1877 | |
1878 | #ifdef CONFIG_ALTIVEC | |
dc1c1ca3 | 1879 | void altivec_assist_exception(struct pt_regs *regs) |
14cf11af PM |
1880 | { |
1881 | int err; | |
1882 | ||
14cf11af PM |
1883 | if (!user_mode(regs)) { |
1884 | printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode" | |
1885 | " at %lx\n", regs->nip); | |
8dad3f92 | 1886 | die("Kernel VMX/Altivec assist exception", regs, SIGILL); |
14cf11af PM |
1887 | } |
1888 | ||
dc1c1ca3 | 1889 | flush_altivec_to_thread(current); |
dc1c1ca3 | 1890 | |
eecff81d | 1891 | PPC_WARN_EMULATED(altivec, regs); |
14cf11af PM |
1892 | err = emulate_altivec(regs); |
1893 | if (err == 0) { | |
1894 | regs->nip += 4; /* skip emulated instruction */ | |
1895 | emulate_single_step(regs); | |
1896 | return; | |
1897 | } | |
1898 | ||
1899 | if (err == -EFAULT) { | |
1900 | /* got an error reading the instruction */ | |
1901 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); | |
1902 | } else { | |
1903 | /* didn't recognize the instruction */ | |
1904 | /* XXX quick hack for now: set the non-Java bit in the VSCR */ | |
76462232 CD |
1905 | printk_ratelimited(KERN_ERR "Unrecognized altivec instruction " |
1906 | "in %s at %lx\n", current->comm, regs->nip); | |
de79f7b9 | 1907 | current->thread.vr_state.vscr.u[3] |= 0x10000; |
14cf11af PM |
1908 | } |
1909 | } | |
1910 | #endif /* CONFIG_ALTIVEC */ | |
1911 | ||
14cf11af PM |
1912 | #ifdef CONFIG_FSL_BOOKE |
1913 | void CacheLockingException(struct pt_regs *regs, unsigned long address, | |
1914 | unsigned long error_code) | |
1915 | { | |
1916 | /* We treat cache locking instructions from the user | |
1917 | * as priv ops, in the future we could try to do | |
1918 | * something smarter | |
1919 | */ | |
1920 | if (error_code & (ESR_DLK|ESR_ILK)) | |
1921 | _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); | |
1922 | return; | |
1923 | } | |
1924 | #endif /* CONFIG_FSL_BOOKE */ | |
1925 | ||
1926 | #ifdef CONFIG_SPE | |
1927 | void SPEFloatingPointException(struct pt_regs *regs) | |
1928 | { | |
6a800f36 | 1929 | extern int do_spe_mathemu(struct pt_regs *regs); |
14cf11af PM |
1930 | unsigned long spefscr; |
1931 | int fpexc_mode; | |
cf4674c4 | 1932 | int code = FPE_FIXME; |
6a800f36 LY |
1933 | int err; |
1934 | ||
685659ee | 1935 | flush_spe_to_thread(current); |
14cf11af PM |
1936 | |
1937 | spefscr = current->thread.spefscr; | |
1938 | fpexc_mode = current->thread.fpexc_mode; | |
1939 | ||
14cf11af PM |
1940 | if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) { |
1941 | code = FPE_FLTOVF; | |
14cf11af PM |
1942 | } |
1943 | else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) { | |
1944 | code = FPE_FLTUND; | |
14cf11af PM |
1945 | } |
1946 | else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV)) | |
1947 | code = FPE_FLTDIV; | |
1948 | else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) { | |
1949 | code = FPE_FLTINV; | |
14cf11af PM |
1950 | } |
1951 | else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES)) | |
1952 | code = FPE_FLTRES; | |
1953 | ||
6a800f36 LY |
1954 | err = do_spe_mathemu(regs); |
1955 | if (err == 0) { | |
1956 | regs->nip += 4; /* skip emulated instruction */ | |
1957 | emulate_single_step(regs); | |
1958 | return; | |
1959 | } | |
1960 | ||
1961 | if (err == -EFAULT) { | |
1962 | /* got an error reading the instruction */ | |
1963 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); | |
1964 | } else if (err == -EINVAL) { | |
1965 | /* didn't recognize the instruction */ | |
1966 | printk(KERN_ERR "unrecognized spe instruction " | |
1967 | "in %s at %lx\n", current->comm, regs->nip); | |
1968 | } else { | |
1969 | _exception(SIGFPE, regs, code, regs->nip); | |
1970 | } | |
14cf11af | 1971 | |
14cf11af PM |
1972 | return; |
1973 | } | |
6a800f36 LY |
1974 | |
1975 | void SPEFloatingPointRoundException(struct pt_regs *regs) | |
1976 | { | |
1977 | extern int speround_handler(struct pt_regs *regs); | |
1978 | int err; | |
1979 | ||
1980 | preempt_disable(); | |
1981 | if (regs->msr & MSR_SPE) | |
1982 | giveup_spe(current); | |
1983 | preempt_enable(); | |
1984 | ||
1985 | regs->nip -= 4; | |
1986 | err = speround_handler(regs); | |
1987 | if (err == 0) { | |
1988 | regs->nip += 4; /* skip emulated instruction */ | |
1989 | emulate_single_step(regs); | |
1990 | return; | |
1991 | } | |
1992 | ||
1993 | if (err == -EFAULT) { | |
1994 | /* got an error reading the instruction */ | |
1995 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); | |
1996 | } else if (err == -EINVAL) { | |
1997 | /* didn't recognize the instruction */ | |
1998 | printk(KERN_ERR "unrecognized spe instruction " | |
1999 | "in %s at %lx\n", current->comm, regs->nip); | |
2000 | } else { | |
cf4674c4 | 2001 | _exception(SIGFPE, regs, FPE_FIXME, regs->nip); |
6a800f36 LY |
2002 | return; |
2003 | } | |
2004 | } | |
14cf11af PM |
2005 | #endif |
2006 | ||
dc1c1ca3 SR |
2007 | /* |
2008 | * We enter here if we get an unrecoverable exception, that is, one | |
2009 | * that happened at a point where the RI (recoverable interrupt) bit | |
2010 | * in the MSR is 0. This indicates that SRR0/1 are live, and that | |
2011 | * we therefore lost state by taking this exception. | |
2012 | */ | |
2013 | void unrecoverable_exception(struct pt_regs *regs) | |
2014 | { | |
2015 | printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n", | |
2016 | regs->trap, regs->nip); | |
2017 | die("Unrecoverable exception", regs, SIGABRT); | |
2018 | } | |
15770a13 | 2019 | NOKPROBE_SYMBOL(unrecoverable_exception); |
dc1c1ca3 | 2020 | |
1e18c17a | 2021 | #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x) |
14cf11af PM |
2022 | /* |
2023 | * Default handler for a Watchdog exception, | |
2024 | * spins until a reboot occurs | |
2025 | */ | |
2026 | void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs) | |
2027 | { | |
2028 | /* Generic WatchdogHandler, implement your own */ | |
2029 | mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE)); | |
2030 | return; | |
2031 | } | |
2032 | ||
2033 | void WatchdogException(struct pt_regs *regs) | |
2034 | { | |
2035 | printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n"); | |
2036 | WatchdogHandler(regs); | |
2037 | } | |
2038 | #endif | |
dc1c1ca3 | 2039 | |
dc1c1ca3 SR |
2040 | /* |
2041 | * We enter here if we discover during exception entry that we are | |
2042 | * running in supervisor mode with a userspace value in the stack pointer. | |
2043 | */ | |
2044 | void kernel_bad_stack(struct pt_regs *regs) | |
2045 | { | |
2046 | printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n", | |
2047 | regs->gpr[1], regs->nip); | |
2048 | die("Bad kernel stack pointer", regs, SIGABRT); | |
2049 | } | |
15770a13 | 2050 | NOKPROBE_SYMBOL(kernel_bad_stack); |
14cf11af PM |
2051 | |
2052 | void __init trap_init(void) | |
2053 | { | |
2054 | } | |
80947e7c GU |
2055 | |
2056 | ||
2057 | #ifdef CONFIG_PPC_EMULATED_STATS | |
2058 | ||
2059 | #define WARN_EMULATED_SETUP(type) .type = { .name = #type } | |
2060 | ||
2061 | struct ppc_emulated ppc_emulated = { | |
2062 | #ifdef CONFIG_ALTIVEC | |
2063 | WARN_EMULATED_SETUP(altivec), | |
2064 | #endif | |
2065 | WARN_EMULATED_SETUP(dcba), | |
2066 | WARN_EMULATED_SETUP(dcbz), | |
2067 | WARN_EMULATED_SETUP(fp_pair), | |
2068 | WARN_EMULATED_SETUP(isel), | |
2069 | WARN_EMULATED_SETUP(mcrxr), | |
2070 | WARN_EMULATED_SETUP(mfpvr), | |
2071 | WARN_EMULATED_SETUP(multiple), | |
2072 | WARN_EMULATED_SETUP(popcntb), | |
2073 | WARN_EMULATED_SETUP(spe), | |
2074 | WARN_EMULATED_SETUP(string), | |
a3821b2a | 2075 | WARN_EMULATED_SETUP(sync), |
80947e7c GU |
2076 | WARN_EMULATED_SETUP(unaligned), |
2077 | #ifdef CONFIG_MATH_EMULATION | |
2078 | WARN_EMULATED_SETUP(math), | |
80947e7c GU |
2079 | #endif |
2080 | #ifdef CONFIG_VSX | |
2081 | WARN_EMULATED_SETUP(vsx), | |
2082 | #endif | |
efcac658 AK |
2083 | #ifdef CONFIG_PPC64 |
2084 | WARN_EMULATED_SETUP(mfdscr), | |
2085 | WARN_EMULATED_SETUP(mtdscr), | |
f83319d7 | 2086 | WARN_EMULATED_SETUP(lq_stq), |
5080332c MN |
2087 | WARN_EMULATED_SETUP(lxvw4x), |
2088 | WARN_EMULATED_SETUP(lxvh8x), | |
2089 | WARN_EMULATED_SETUP(lxvd2x), | |
2090 | WARN_EMULATED_SETUP(lxvb16x), | |
efcac658 | 2091 | #endif |
80947e7c GU |
2092 | }; |
2093 | ||
2094 | u32 ppc_warn_emulated; | |
2095 | ||
2096 | void ppc_warn_emulated_print(const char *type) | |
2097 | { | |
76462232 CD |
2098 | pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm, |
2099 | type); | |
80947e7c GU |
2100 | } |
2101 | ||
2102 | static int __init ppc_warn_emulated_init(void) | |
2103 | { | |
2104 | struct dentry *dir, *d; | |
2105 | unsigned int i; | |
2106 | struct ppc_emulated_entry *entries = (void *)&ppc_emulated; | |
2107 | ||
2108 | if (!powerpc_debugfs_root) | |
2109 | return -ENODEV; | |
2110 | ||
2111 | dir = debugfs_create_dir("emulated_instructions", | |
2112 | powerpc_debugfs_root); | |
2113 | if (!dir) | |
2114 | return -ENOMEM; | |
2115 | ||
2116 | d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir, | |
2117 | &ppc_warn_emulated); | |
2118 | if (!d) | |
2119 | goto fail; | |
2120 | ||
2121 | for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) { | |
2122 | d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir, | |
2123 | (u32 *)&entries[i].val.counter); | |
2124 | if (!d) | |
2125 | goto fail; | |
2126 | } | |
2127 | ||
2128 | return 0; | |
2129 | ||
2130 | fail: | |
2131 | debugfs_remove_recursive(dir); | |
2132 | return -ENOMEM; | |
2133 | } | |
2134 | ||
2135 | device_initcall(ppc_warn_emulated_init); | |
2136 | ||
2137 | #endif /* CONFIG_PPC_EMULATED_STATS */ |