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14cf11af | 1 | /* |
14cf11af | 2 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) |
fe04b112 | 3 | * Copyright 2007-2010 Freescale Semiconductor, Inc. |
14cf11af PM |
4 | * |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version | |
8 | * 2 of the License, or (at your option) any later version. | |
9 | * | |
10 | * Modified by Cort Dougan (cort@cs.nmt.edu) | |
11 | * and Paul Mackerras (paulus@samba.org) | |
12 | */ | |
13 | ||
14 | /* | |
15 | * This file handles the architecture-dependent parts of hardware exceptions | |
16 | */ | |
17 | ||
14cf11af PM |
18 | #include <linux/errno.h> |
19 | #include <linux/sched.h> | |
b17b0153 | 20 | #include <linux/sched/debug.h> |
14cf11af PM |
21 | #include <linux/kernel.h> |
22 | #include <linux/mm.h> | |
23 | #include <linux/stddef.h> | |
24 | #include <linux/unistd.h> | |
8dad3f92 | 25 | #include <linux/ptrace.h> |
14cf11af | 26 | #include <linux/user.h> |
14cf11af | 27 | #include <linux/interrupt.h> |
14cf11af | 28 | #include <linux/init.h> |
8a39b05f PG |
29 | #include <linux/extable.h> |
30 | #include <linux/module.h> /* print_modules */ | |
8dad3f92 | 31 | #include <linux/prctl.h> |
14cf11af PM |
32 | #include <linux/delay.h> |
33 | #include <linux/kprobes.h> | |
cc532915 | 34 | #include <linux/kexec.h> |
5474c120 | 35 | #include <linux/backlight.h> |
73c9ceab | 36 | #include <linux/bug.h> |
1eeb66a1 | 37 | #include <linux/kdebug.h> |
76462232 | 38 | #include <linux/ratelimit.h> |
ba12eede | 39 | #include <linux/context_tracking.h> |
14cf11af | 40 | |
80947e7c | 41 | #include <asm/emulated_ops.h> |
14cf11af | 42 | #include <asm/pgtable.h> |
7c0f6ba6 | 43 | #include <linux/uaccess.h> |
7644d581 | 44 | #include <asm/debugfs.h> |
14cf11af | 45 | #include <asm/io.h> |
86417780 PM |
46 | #include <asm/machdep.h> |
47 | #include <asm/rtas.h> | |
f7f6f4fe | 48 | #include <asm/pmc.h> |
14cf11af | 49 | #include <asm/reg.h> |
14cf11af PM |
50 | #ifdef CONFIG_PMAC_BACKLIGHT |
51 | #include <asm/backlight.h> | |
52 | #endif | |
dc1c1ca3 | 53 | #ifdef CONFIG_PPC64 |
86417780 | 54 | #include <asm/firmware.h> |
dc1c1ca3 | 55 | #include <asm/processor.h> |
6ce6c629 | 56 | #include <asm/tm.h> |
dc1c1ca3 | 57 | #endif |
c0ce7d08 | 58 | #include <asm/kexec.h> |
16c57b36 | 59 | #include <asm/ppc-opcode.h> |
cce1f106 | 60 | #include <asm/rio.h> |
ebaeb5ae | 61 | #include <asm/fadump.h> |
ae3a197e | 62 | #include <asm/switch_to.h> |
f54db641 | 63 | #include <asm/tm.h> |
ae3a197e | 64 | #include <asm/debug.h> |
42f5b4ca | 65 | #include <asm/asm-prototypes.h> |
fd7bacbc | 66 | #include <asm/hmi.h> |
4e0e3435 | 67 | #include <sysdev/fsl_pci.h> |
6cc89bad | 68 | #include <asm/kprobes.h> |
dc1c1ca3 | 69 | |
da665885 | 70 | #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC_CORE) |
5be3492f AB |
71 | int (*__debugger)(struct pt_regs *regs) __read_mostly; |
72 | int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly; | |
73 | int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly; | |
74 | int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly; | |
75 | int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly; | |
9422de3e | 76 | int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly; |
5be3492f | 77 | int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly; |
14cf11af PM |
78 | |
79 | EXPORT_SYMBOL(__debugger); | |
80 | EXPORT_SYMBOL(__debugger_ipi); | |
81 | EXPORT_SYMBOL(__debugger_bpt); | |
82 | EXPORT_SYMBOL(__debugger_sstep); | |
83 | EXPORT_SYMBOL(__debugger_iabr_match); | |
9422de3e | 84 | EXPORT_SYMBOL(__debugger_break_match); |
14cf11af PM |
85 | EXPORT_SYMBOL(__debugger_fault_handler); |
86 | #endif | |
87 | ||
8b3c34cf MN |
88 | /* Transactional Memory trap debug */ |
89 | #ifdef TM_DEBUG_SW | |
90 | #define TM_DEBUG(x...) printk(KERN_INFO x) | |
91 | #else | |
92 | #define TM_DEBUG(x...) do { } while(0) | |
93 | #endif | |
94 | ||
14cf11af PM |
95 | /* |
96 | * Trap & Exception support | |
97 | */ | |
98 | ||
6031d9d9 | 99 | #ifdef CONFIG_PMAC_BACKLIGHT |
100 | static void pmac_backlight_unblank(void) | |
101 | { | |
102 | mutex_lock(&pmac_backlight_mutex); | |
103 | if (pmac_backlight) { | |
104 | struct backlight_properties *props; | |
105 | ||
106 | props = &pmac_backlight->props; | |
107 | props->brightness = props->max_brightness; | |
108 | props->power = FB_BLANK_UNBLANK; | |
109 | backlight_update_status(pmac_backlight); | |
110 | } | |
111 | mutex_unlock(&pmac_backlight_mutex); | |
112 | } | |
113 | #else | |
114 | static inline void pmac_backlight_unblank(void) { } | |
115 | #endif | |
116 | ||
760ca4dc AB |
117 | static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED; |
118 | static int die_owner = -1; | |
119 | static unsigned int die_nest_count; | |
120 | static int die_counter; | |
121 | ||
03465f89 | 122 | static unsigned long oops_begin(struct pt_regs *regs) |
14cf11af | 123 | { |
760ca4dc | 124 | int cpu; |
34c2a14f | 125 | unsigned long flags; |
14cf11af | 126 | |
293e4688 | 127 | oops_enter(); |
128 | ||
760ca4dc AB |
129 | /* racy, but better than risking deadlock. */ |
130 | raw_local_irq_save(flags); | |
131 | cpu = smp_processor_id(); | |
132 | if (!arch_spin_trylock(&die_lock)) { | |
133 | if (cpu == die_owner) | |
134 | /* nested oops. should stop eventually */; | |
135 | else | |
136 | arch_spin_lock(&die_lock); | |
34c2a14f | 137 | } |
760ca4dc AB |
138 | die_nest_count++; |
139 | die_owner = cpu; | |
140 | console_verbose(); | |
141 | bust_spinlocks(1); | |
142 | if (machine_is(powermac)) | |
143 | pmac_backlight_unblank(); | |
144 | return flags; | |
145 | } | |
03465f89 | 146 | NOKPROBE_SYMBOL(oops_begin); |
e8222502 | 147 | |
03465f89 | 148 | static void oops_end(unsigned long flags, struct pt_regs *regs, |
760ca4dc AB |
149 | int signr) |
150 | { | |
14cf11af | 151 | bust_spinlocks(0); |
373d4d09 | 152 | add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); |
760ca4dc | 153 | die_nest_count--; |
58154c8c AB |
154 | oops_exit(); |
155 | printk("\n"); | |
7458e8b2 | 156 | if (!die_nest_count) { |
760ca4dc | 157 | /* Nest count reaches zero, release the lock. */ |
7458e8b2 | 158 | die_owner = -1; |
760ca4dc | 159 | arch_spin_unlock(&die_lock); |
7458e8b2 | 160 | } |
760ca4dc | 161 | raw_local_irq_restore(flags); |
cc532915 | 162 | |
ebaeb5ae MS |
163 | crash_fadump(regs, "die oops"); |
164 | ||
9b00ac06 AB |
165 | /* |
166 | * A system reset (0x100) is a request to dump, so we always send | |
167 | * it through the crashdump code. | |
168 | */ | |
169 | if (kexec_should_crash(current) || (TRAP(regs) == 0x100)) { | |
cc532915 | 170 | crash_kexec(regs); |
9b00ac06 AB |
171 | |
172 | /* | |
173 | * We aren't the primary crash CPU. We need to send it | |
174 | * to a holding pattern to avoid it ending up in the panic | |
175 | * code. | |
176 | */ | |
177 | crash_kexec_secondary(regs); | |
178 | } | |
14cf11af | 179 | |
760ca4dc AB |
180 | if (!signr) |
181 | return; | |
182 | ||
58154c8c AB |
183 | /* |
184 | * While our oops output is serialised by a spinlock, output | |
185 | * from panic() called below can race and corrupt it. If we | |
186 | * know we are going to panic, delay for 1 second so we have a | |
187 | * chance to get clean backtraces from all CPUs that are oopsing. | |
188 | */ | |
189 | if (in_interrupt() || panic_on_oops || !current->pid || | |
190 | is_global_init(current)) { | |
191 | mdelay(MSEC_PER_SEC); | |
192 | } | |
193 | ||
14cf11af PM |
194 | if (in_interrupt()) |
195 | panic("Fatal exception in interrupt"); | |
cea6a4ba | 196 | if (panic_on_oops) |
012c437d | 197 | panic("Fatal exception"); |
760ca4dc AB |
198 | do_exit(signr); |
199 | } | |
03465f89 | 200 | NOKPROBE_SYMBOL(oops_end); |
cea6a4ba | 201 | |
03465f89 | 202 | static int __die(const char *str, struct pt_regs *regs, long err) |
760ca4dc AB |
203 | { |
204 | printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); | |
205 | #ifdef CONFIG_PREEMPT | |
206 | printk("PREEMPT "); | |
207 | #endif | |
208 | #ifdef CONFIG_SMP | |
209 | printk("SMP NR_CPUS=%d ", NR_CPUS); | |
210 | #endif | |
e7df0d88 JK |
211 | if (debug_pagealloc_enabled()) |
212 | printk("DEBUG_PAGEALLOC "); | |
760ca4dc AB |
213 | #ifdef CONFIG_NUMA |
214 | printk("NUMA "); | |
215 | #endif | |
216 | printk("%s\n", ppc_md.name ? ppc_md.name : ""); | |
217 | ||
218 | if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP) | |
219 | return 1; | |
220 | ||
221 | print_modules(); | |
222 | show_regs(regs); | |
14cf11af PM |
223 | |
224 | return 0; | |
225 | } | |
03465f89 | 226 | NOKPROBE_SYMBOL(__die); |
14cf11af | 227 | |
760ca4dc AB |
228 | void die(const char *str, struct pt_regs *regs, long err) |
229 | { | |
6f44b20e NP |
230 | unsigned long flags; |
231 | ||
232 | if (debugger(regs)) | |
233 | return; | |
760ca4dc | 234 | |
6f44b20e | 235 | flags = oops_begin(regs); |
760ca4dc AB |
236 | if (__die(str, regs, err)) |
237 | err = 0; | |
238 | oops_end(flags, regs, err); | |
239 | } | |
240 | ||
25baa35b ON |
241 | void user_single_step_siginfo(struct task_struct *tsk, |
242 | struct pt_regs *regs, siginfo_t *info) | |
243 | { | |
244 | memset(info, 0, sizeof(*info)); | |
245 | info->si_signo = SIGTRAP; | |
246 | info->si_code = TRAP_TRACE; | |
247 | info->si_addr = (void __user *)regs->nip; | |
248 | } | |
249 | ||
14cf11af PM |
250 | void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) |
251 | { | |
252 | siginfo_t info; | |
d0c3d534 OJ |
253 | const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \ |
254 | "at %08lx nip %08lx lr %08lx code %x\n"; | |
255 | const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \ | |
256 | "at %016lx nip %016lx lr %016lx code %x\n"; | |
14cf11af PM |
257 | |
258 | if (!user_mode(regs)) { | |
760ca4dc AB |
259 | die("Exception in kernel mode", regs, signr); |
260 | return; | |
261 | } | |
262 | ||
263 | if (show_unhandled_signals && unhandled_signal(current, signr)) { | |
76462232 CD |
264 | printk_ratelimited(regs->msr & MSR_64BIT ? fmt64 : fmt32, |
265 | current->comm, current->pid, signr, | |
266 | addr, regs->nip, regs->link, code); | |
267 | } | |
14cf11af | 268 | |
a3512b2d | 269 | if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs)) |
9f2f79e3 BH |
270 | local_irq_enable(); |
271 | ||
41ab5266 | 272 | current->thread.trap_nr = code; |
14cf11af PM |
273 | memset(&info, 0, sizeof(info)); |
274 | info.si_signo = signr; | |
275 | info.si_code = code; | |
276 | info.si_addr = (void __user *) addr; | |
277 | force_sig_info(signr, &info, current); | |
14cf11af PM |
278 | } |
279 | ||
14cf11af PM |
280 | void system_reset_exception(struct pt_regs *regs) |
281 | { | |
2b4f3ac5 NP |
282 | /* |
283 | * Avoid crashes in case of nested NMI exceptions. Recoverability | |
284 | * is determined by RI and in_nmi | |
285 | */ | |
286 | bool nested = in_nmi(); | |
287 | if (!nested) | |
288 | nmi_enter(); | |
289 | ||
14cf11af | 290 | /* See if any machine dependent calls */ |
c902be71 AB |
291 | if (ppc_md.system_reset_exception) { |
292 | if (ppc_md.system_reset_exception(regs)) | |
c4f3b52c | 293 | goto out; |
c902be71 | 294 | } |
14cf11af | 295 | |
8dad3f92 | 296 | die("System Reset", regs, SIGABRT); |
14cf11af | 297 | |
c4f3b52c NP |
298 | out: |
299 | #ifdef CONFIG_PPC_BOOK3S_64 | |
300 | BUG_ON(get_paca()->in_nmi == 0); | |
301 | if (get_paca()->in_nmi > 1) | |
302 | panic("Unrecoverable nested System Reset"); | |
303 | #endif | |
14cf11af PM |
304 | /* Must die if the interrupt is not recoverable */ |
305 | if (!(regs->msr & MSR_RI)) | |
306 | panic("Unrecoverable System Reset"); | |
307 | ||
2b4f3ac5 NP |
308 | if (!nested) |
309 | nmi_exit(); | |
310 | ||
14cf11af PM |
311 | /* What should we do here? We could issue a shutdown or hard reset. */ |
312 | } | |
1e9b4507 | 313 | |
f307939f | 314 | #ifdef CONFIG_PPC64 |
1e9b4507 MS |
315 | /* |
316 | * This function is called in real mode. Strictly no printk's please. | |
317 | * | |
318 | * regs->nip and regs->msr contains srr0 and ssr1. | |
319 | */ | |
320 | long machine_check_early(struct pt_regs *regs) | |
321 | { | |
4c703416 MS |
322 | long handled = 0; |
323 | ||
69111bac | 324 | __this_cpu_inc(irq_stat.mce_exceptions); |
e6654d5b | 325 | |
27ea2c42 DA |
326 | add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE); |
327 | ||
4c703416 MS |
328 | if (cur_cpu_spec && cur_cpu_spec->machine_check_early) |
329 | handled = cur_cpu_spec->machine_check_early(regs); | |
330 | return handled; | |
1e9b4507 MS |
331 | } |
332 | ||
0869b6fd MS |
333 | long hmi_exception_realmode(struct pt_regs *regs) |
334 | { | |
69111bac | 335 | __this_cpu_inc(irq_stat.hmi_exceptions); |
0869b6fd | 336 | |
fd7bacbc MS |
337 | wait_for_subcore_guest_exit(); |
338 | ||
0869b6fd MS |
339 | if (ppc_md.hmi_exception_early) |
340 | ppc_md.hmi_exception_early(regs); | |
341 | ||
fd7bacbc MS |
342 | wait_for_tb_resync(); |
343 | ||
0869b6fd MS |
344 | return 0; |
345 | } | |
346 | ||
14cf11af PM |
347 | #endif |
348 | ||
349 | /* | |
350 | * I/O accesses can cause machine checks on powermacs. | |
351 | * Check if the NIP corresponds to the address of a sync | |
352 | * instruction for which there is an entry in the exception | |
353 | * table. | |
354 | * Note that the 601 only takes a machine check on TEA | |
355 | * (transfer error ack) signal assertion, and does not | |
356 | * set any of the top 16 bits of SRR1. | |
357 | * -- paulus. | |
358 | */ | |
359 | static inline int check_io_access(struct pt_regs *regs) | |
360 | { | |
68a64357 | 361 | #ifdef CONFIG_PPC32 |
14cf11af PM |
362 | unsigned long msr = regs->msr; |
363 | const struct exception_table_entry *entry; | |
364 | unsigned int *nip = (unsigned int *)regs->nip; | |
365 | ||
366 | if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) | |
367 | && (entry = search_exception_tables(regs->nip)) != NULL) { | |
368 | /* | |
369 | * Check that it's a sync instruction, or somewhere | |
370 | * in the twi; isync; nop sequence that inb/inw/inl uses. | |
371 | * As the address is in the exception table | |
372 | * we should be able to read the instr there. | |
373 | * For the debug message, we look at the preceding | |
374 | * load or store. | |
375 | */ | |
ddc6cd0d | 376 | if (*nip == PPC_INST_NOP) |
14cf11af | 377 | nip -= 2; |
ddc6cd0d | 378 | else if (*nip == PPC_INST_ISYNC) |
14cf11af | 379 | --nip; |
ddc6cd0d | 380 | if (*nip == PPC_INST_SYNC || (*nip >> 26) == OP_TRAP) { |
14cf11af PM |
381 | unsigned int rb; |
382 | ||
383 | --nip; | |
384 | rb = (*nip >> 11) & 0x1f; | |
385 | printk(KERN_DEBUG "%s bad port %lx at %p\n", | |
386 | (*nip & 0x100)? "OUT to": "IN from", | |
387 | regs->gpr[rb] - _IO_BASE, nip); | |
388 | regs->msr |= MSR_RI; | |
61a92f70 | 389 | regs->nip = extable_fixup(entry); |
14cf11af PM |
390 | return 1; |
391 | } | |
392 | } | |
68a64357 | 393 | #endif /* CONFIG_PPC32 */ |
14cf11af PM |
394 | return 0; |
395 | } | |
396 | ||
172ae2e7 | 397 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
14cf11af PM |
398 | /* On 4xx, the reason for the machine check or program exception |
399 | is in the ESR. */ | |
400 | #define get_reason(regs) ((regs)->dsisr) | |
401 | #ifndef CONFIG_FSL_BOOKE | |
402 | #define get_mc_reason(regs) ((regs)->dsisr) | |
403 | #else | |
fe04b112 | 404 | #define get_mc_reason(regs) (mfspr(SPRN_MCSR)) |
14cf11af PM |
405 | #endif |
406 | #define REASON_FP ESR_FP | |
407 | #define REASON_ILLEGAL (ESR_PIL | ESR_PUO) | |
408 | #define REASON_PRIVILEGED ESR_PPR | |
409 | #define REASON_TRAP ESR_PTR | |
410 | ||
411 | /* single-step stuff */ | |
51ae8d4a BB |
412 | #define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC) |
413 | #define clear_single_step(regs) (current->thread.debug.dbcr0 &= ~DBCR0_IC) | |
14cf11af PM |
414 | |
415 | #else | |
416 | /* On non-4xx, the reason for the machine check or program | |
417 | exception is in the MSR. */ | |
418 | #define get_reason(regs) ((regs)->msr) | |
419 | #define get_mc_reason(regs) ((regs)->msr) | |
8b3c34cf | 420 | #define REASON_TM 0x200000 |
14cf11af PM |
421 | #define REASON_FP 0x100000 |
422 | #define REASON_ILLEGAL 0x80000 | |
423 | #define REASON_PRIVILEGED 0x40000 | |
424 | #define REASON_TRAP 0x20000 | |
425 | ||
426 | #define single_stepping(regs) ((regs)->msr & MSR_SE) | |
427 | #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE) | |
428 | #endif | |
429 | ||
47c0bd1a BH |
430 | #if defined(CONFIG_4xx) |
431 | int machine_check_4xx(struct pt_regs *regs) | |
14cf11af | 432 | { |
1a6a4ffe | 433 | unsigned long reason = get_mc_reason(regs); |
14cf11af | 434 | |
14cf11af PM |
435 | if (reason & ESR_IMCP) { |
436 | printk("Instruction"); | |
437 | mtspr(SPRN_ESR, reason & ~ESR_IMCP); | |
438 | } else | |
439 | printk("Data"); | |
440 | printk(" machine check in kernel mode.\n"); | |
47c0bd1a BH |
441 | |
442 | return 0; | |
443 | } | |
444 | ||
445 | int machine_check_440A(struct pt_regs *regs) | |
446 | { | |
447 | unsigned long reason = get_mc_reason(regs); | |
448 | ||
14cf11af PM |
449 | printk("Machine check in kernel mode.\n"); |
450 | if (reason & ESR_IMCP){ | |
451 | printk("Instruction Synchronous Machine Check exception\n"); | |
452 | mtspr(SPRN_ESR, reason & ~ESR_IMCP); | |
453 | } | |
454 | else { | |
455 | u32 mcsr = mfspr(SPRN_MCSR); | |
456 | if (mcsr & MCSR_IB) | |
457 | printk("Instruction Read PLB Error\n"); | |
458 | if (mcsr & MCSR_DRB) | |
459 | printk("Data Read PLB Error\n"); | |
460 | if (mcsr & MCSR_DWB) | |
461 | printk("Data Write PLB Error\n"); | |
462 | if (mcsr & MCSR_TLBP) | |
463 | printk("TLB Parity Error\n"); | |
464 | if (mcsr & MCSR_ICP){ | |
465 | flush_instruction_cache(); | |
466 | printk("I-Cache Parity Error\n"); | |
467 | } | |
468 | if (mcsr & MCSR_DCSP) | |
469 | printk("D-Cache Search Parity Error\n"); | |
470 | if (mcsr & MCSR_DCFP) | |
471 | printk("D-Cache Flush Parity Error\n"); | |
472 | if (mcsr & MCSR_IMPE) | |
473 | printk("Machine Check exception is imprecise\n"); | |
474 | ||
475 | /* Clear MCSR */ | |
476 | mtspr(SPRN_MCSR, mcsr); | |
477 | } | |
47c0bd1a BH |
478 | return 0; |
479 | } | |
fc5e7097 DK |
480 | |
481 | int machine_check_47x(struct pt_regs *regs) | |
482 | { | |
483 | unsigned long reason = get_mc_reason(regs); | |
484 | u32 mcsr; | |
485 | ||
486 | printk(KERN_ERR "Machine check in kernel mode.\n"); | |
487 | if (reason & ESR_IMCP) { | |
488 | printk(KERN_ERR | |
489 | "Instruction Synchronous Machine Check exception\n"); | |
490 | mtspr(SPRN_ESR, reason & ~ESR_IMCP); | |
491 | return 0; | |
492 | } | |
493 | mcsr = mfspr(SPRN_MCSR); | |
494 | if (mcsr & MCSR_IB) | |
495 | printk(KERN_ERR "Instruction Read PLB Error\n"); | |
496 | if (mcsr & MCSR_DRB) | |
497 | printk(KERN_ERR "Data Read PLB Error\n"); | |
498 | if (mcsr & MCSR_DWB) | |
499 | printk(KERN_ERR "Data Write PLB Error\n"); | |
500 | if (mcsr & MCSR_TLBP) | |
501 | printk(KERN_ERR "TLB Parity Error\n"); | |
502 | if (mcsr & MCSR_ICP) { | |
503 | flush_instruction_cache(); | |
504 | printk(KERN_ERR "I-Cache Parity Error\n"); | |
505 | } | |
506 | if (mcsr & MCSR_DCSP) | |
507 | printk(KERN_ERR "D-Cache Search Parity Error\n"); | |
508 | if (mcsr & PPC47x_MCSR_GPR) | |
509 | printk(KERN_ERR "GPR Parity Error\n"); | |
510 | if (mcsr & PPC47x_MCSR_FPR) | |
511 | printk(KERN_ERR "FPR Parity Error\n"); | |
512 | if (mcsr & PPC47x_MCSR_IPR) | |
513 | printk(KERN_ERR "Machine Check exception is imprecise\n"); | |
514 | ||
515 | /* Clear MCSR */ | |
516 | mtspr(SPRN_MCSR, mcsr); | |
517 | ||
518 | return 0; | |
519 | } | |
47c0bd1a | 520 | #elif defined(CONFIG_E500) |
fe04b112 SW |
521 | int machine_check_e500mc(struct pt_regs *regs) |
522 | { | |
523 | unsigned long mcsr = mfspr(SPRN_MCSR); | |
524 | unsigned long reason = mcsr; | |
525 | int recoverable = 1; | |
526 | ||
82a9a480 | 527 | if (reason & MCSR_LD) { |
cce1f106 SX |
528 | recoverable = fsl_rio_mcheck_exception(regs); |
529 | if (recoverable == 1) | |
530 | goto silent_out; | |
531 | } | |
532 | ||
fe04b112 SW |
533 | printk("Machine check in kernel mode.\n"); |
534 | printk("Caused by (from MCSR=%lx): ", reason); | |
535 | ||
536 | if (reason & MCSR_MCP) | |
537 | printk("Machine Check Signal\n"); | |
538 | ||
539 | if (reason & MCSR_ICPERR) { | |
540 | printk("Instruction Cache Parity Error\n"); | |
541 | ||
542 | /* | |
543 | * This is recoverable by invalidating the i-cache. | |
544 | */ | |
545 | mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI); | |
546 | while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI) | |
547 | ; | |
548 | ||
549 | /* | |
550 | * This will generally be accompanied by an instruction | |
551 | * fetch error report -- only treat MCSR_IF as fatal | |
552 | * if it wasn't due to an L1 parity error. | |
553 | */ | |
554 | reason &= ~MCSR_IF; | |
555 | } | |
556 | ||
557 | if (reason & MCSR_DCPERR_MC) { | |
558 | printk("Data Cache Parity Error\n"); | |
37caf9f2 KG |
559 | |
560 | /* | |
561 | * In write shadow mode we auto-recover from the error, but it | |
562 | * may still get logged and cause a machine check. We should | |
563 | * only treat the non-write shadow case as non-recoverable. | |
564 | */ | |
565 | if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS)) | |
566 | recoverable = 0; | |
fe04b112 SW |
567 | } |
568 | ||
569 | if (reason & MCSR_L2MMU_MHIT) { | |
570 | printk("Hit on multiple TLB entries\n"); | |
571 | recoverable = 0; | |
572 | } | |
573 | ||
574 | if (reason & MCSR_NMI) | |
575 | printk("Non-maskable interrupt\n"); | |
576 | ||
577 | if (reason & MCSR_IF) { | |
578 | printk("Instruction Fetch Error Report\n"); | |
579 | recoverable = 0; | |
580 | } | |
581 | ||
582 | if (reason & MCSR_LD) { | |
583 | printk("Load Error Report\n"); | |
584 | recoverable = 0; | |
585 | } | |
586 | ||
587 | if (reason & MCSR_ST) { | |
588 | printk("Store Error Report\n"); | |
589 | recoverable = 0; | |
590 | } | |
591 | ||
592 | if (reason & MCSR_LDG) { | |
593 | printk("Guarded Load Error Report\n"); | |
594 | recoverable = 0; | |
595 | } | |
596 | ||
597 | if (reason & MCSR_TLBSYNC) | |
598 | printk("Simultaneous tlbsync operations\n"); | |
599 | ||
600 | if (reason & MCSR_BSL2_ERR) { | |
601 | printk("Level 2 Cache Error\n"); | |
602 | recoverable = 0; | |
603 | } | |
604 | ||
605 | if (reason & MCSR_MAV) { | |
606 | u64 addr; | |
607 | ||
608 | addr = mfspr(SPRN_MCAR); | |
609 | addr |= (u64)mfspr(SPRN_MCARU) << 32; | |
610 | ||
611 | printk("Machine Check %s Address: %#llx\n", | |
612 | reason & MCSR_MEA ? "Effective" : "Physical", addr); | |
613 | } | |
614 | ||
cce1f106 | 615 | silent_out: |
fe04b112 SW |
616 | mtspr(SPRN_MCSR, mcsr); |
617 | return mfspr(SPRN_MCSR) == 0 && recoverable; | |
618 | } | |
619 | ||
47c0bd1a BH |
620 | int machine_check_e500(struct pt_regs *regs) |
621 | { | |
622 | unsigned long reason = get_mc_reason(regs); | |
623 | ||
cce1f106 SX |
624 | if (reason & MCSR_BUS_RBERR) { |
625 | if (fsl_rio_mcheck_exception(regs)) | |
626 | return 1; | |
4e0e3435 HJ |
627 | if (fsl_pci_mcheck_exception(regs)) |
628 | return 1; | |
cce1f106 SX |
629 | } |
630 | ||
14cf11af PM |
631 | printk("Machine check in kernel mode.\n"); |
632 | printk("Caused by (from MCSR=%lx): ", reason); | |
633 | ||
634 | if (reason & MCSR_MCP) | |
635 | printk("Machine Check Signal\n"); | |
636 | if (reason & MCSR_ICPERR) | |
637 | printk("Instruction Cache Parity Error\n"); | |
638 | if (reason & MCSR_DCP_PERR) | |
639 | printk("Data Cache Push Parity Error\n"); | |
640 | if (reason & MCSR_DCPERR) | |
641 | printk("Data Cache Parity Error\n"); | |
14cf11af PM |
642 | if (reason & MCSR_BUS_IAERR) |
643 | printk("Bus - Instruction Address Error\n"); | |
644 | if (reason & MCSR_BUS_RAERR) | |
645 | printk("Bus - Read Address Error\n"); | |
646 | if (reason & MCSR_BUS_WAERR) | |
647 | printk("Bus - Write Address Error\n"); | |
648 | if (reason & MCSR_BUS_IBERR) | |
649 | printk("Bus - Instruction Data Error\n"); | |
650 | if (reason & MCSR_BUS_RBERR) | |
651 | printk("Bus - Read Data Bus Error\n"); | |
652 | if (reason & MCSR_BUS_WBERR) | |
c1528339 | 653 | printk("Bus - Write Data Bus Error\n"); |
14cf11af PM |
654 | if (reason & MCSR_BUS_IPERR) |
655 | printk("Bus - Instruction Parity Error\n"); | |
656 | if (reason & MCSR_BUS_RPERR) | |
657 | printk("Bus - Read Parity Error\n"); | |
47c0bd1a BH |
658 | |
659 | return 0; | |
660 | } | |
4490c06b KG |
661 | |
662 | int machine_check_generic(struct pt_regs *regs) | |
663 | { | |
664 | return 0; | |
665 | } | |
47c0bd1a BH |
666 | #elif defined(CONFIG_E200) |
667 | int machine_check_e200(struct pt_regs *regs) | |
668 | { | |
669 | unsigned long reason = get_mc_reason(regs); | |
670 | ||
14cf11af PM |
671 | printk("Machine check in kernel mode.\n"); |
672 | printk("Caused by (from MCSR=%lx): ", reason); | |
673 | ||
674 | if (reason & MCSR_MCP) | |
675 | printk("Machine Check Signal\n"); | |
676 | if (reason & MCSR_CP_PERR) | |
677 | printk("Cache Push Parity Error\n"); | |
678 | if (reason & MCSR_CPERR) | |
679 | printk("Cache Parity Error\n"); | |
680 | if (reason & MCSR_EXCP_ERR) | |
681 | printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n"); | |
682 | if (reason & MCSR_BUS_IRERR) | |
683 | printk("Bus - Read Bus Error on instruction fetch\n"); | |
684 | if (reason & MCSR_BUS_DRERR) | |
685 | printk("Bus - Read Bus Error on data load\n"); | |
686 | if (reason & MCSR_BUS_WRERR) | |
687 | printk("Bus - Write Bus Error on buffered store or cache line push\n"); | |
47c0bd1a BH |
688 | |
689 | return 0; | |
690 | } | |
e627f8dc CL |
691 | #elif defined(CONFIG_PPC_8xx) |
692 | int machine_check_8xx(struct pt_regs *regs) | |
693 | { | |
694 | unsigned long reason = get_mc_reason(regs); | |
695 | ||
696 | pr_err("Machine check in kernel mode.\n"); | |
697 | pr_err("Caused by (from SRR1=%lx): ", reason); | |
698 | if (reason & 0x40000000) | |
699 | pr_err("Fetch error at address %lx\n", regs->nip); | |
700 | else | |
701 | pr_err("Data access error at address %lx\n", regs->dar); | |
702 | ||
703 | #ifdef CONFIG_PCI | |
704 | /* the qspan pci read routines can cause machine checks -- Cort | |
705 | * | |
706 | * yuck !!! that totally needs to go away ! There are better ways | |
707 | * to deal with that than having a wart in the mcheck handler. | |
708 | * -- BenH | |
709 | */ | |
710 | bad_page_fault(regs, regs->dar, SIGBUS); | |
711 | return 1; | |
712 | #else | |
713 | return 0; | |
714 | #endif | |
715 | } | |
47c0bd1a BH |
716 | #else |
717 | int machine_check_generic(struct pt_regs *regs) | |
718 | { | |
719 | unsigned long reason = get_mc_reason(regs); | |
720 | ||
14cf11af PM |
721 | printk("Machine check in kernel mode.\n"); |
722 | printk("Caused by (from SRR1=%lx): ", reason); | |
723 | switch (reason & 0x601F0000) { | |
724 | case 0x80000: | |
725 | printk("Machine check signal\n"); | |
726 | break; | |
727 | case 0: /* for 601 */ | |
728 | case 0x40000: | |
729 | case 0x140000: /* 7450 MSS error and TEA */ | |
730 | printk("Transfer error ack signal\n"); | |
731 | break; | |
732 | case 0x20000: | |
733 | printk("Data parity error signal\n"); | |
734 | break; | |
735 | case 0x10000: | |
736 | printk("Address parity error signal\n"); | |
737 | break; | |
738 | case 0x20000000: | |
739 | printk("L1 Data Cache error\n"); | |
740 | break; | |
741 | case 0x40000000: | |
742 | printk("L1 Instruction Cache error\n"); | |
743 | break; | |
744 | case 0x00100000: | |
745 | printk("L2 data cache parity error\n"); | |
746 | break; | |
747 | default: | |
748 | printk("Unknown values in msr\n"); | |
749 | } | |
75918a4b OJ |
750 | return 0; |
751 | } | |
47c0bd1a | 752 | #endif /* everything else */ |
75918a4b OJ |
753 | |
754 | void machine_check_exception(struct pt_regs *regs) | |
755 | { | |
ba12eede | 756 | enum ctx_state prev_state = exception_enter(); |
75918a4b OJ |
757 | int recover = 0; |
758 | ||
69111bac | 759 | __this_cpu_inc(irq_stat.mce_exceptions); |
89713ed1 | 760 | |
47c0bd1a BH |
761 | /* See if any machine dependent calls. In theory, we would want |
762 | * to call the CPU first, and call the ppc_md. one if the CPU | |
763 | * one returns a positive number. However there is existing code | |
764 | * that assumes the board gets a first chance, so let's keep it | |
765 | * that way for now and fix things later. --BenH. | |
766 | */ | |
75918a4b OJ |
767 | if (ppc_md.machine_check_exception) |
768 | recover = ppc_md.machine_check_exception(regs); | |
47c0bd1a BH |
769 | else if (cur_cpu_spec->machine_check) |
770 | recover = cur_cpu_spec->machine_check(regs); | |
75918a4b | 771 | |
47c0bd1a | 772 | if (recover > 0) |
ba12eede | 773 | goto bail; |
75918a4b | 774 | |
a443506b | 775 | if (debugger_fault_handler(regs)) |
ba12eede | 776 | goto bail; |
75918a4b OJ |
777 | |
778 | if (check_io_access(regs)) | |
ba12eede | 779 | goto bail; |
75918a4b | 780 | |
8dad3f92 | 781 | die("Machine check", regs, SIGBUS); |
14cf11af PM |
782 | |
783 | /* Must die if the interrupt is not recoverable */ | |
784 | if (!(regs->msr & MSR_RI)) | |
785 | panic("Unrecoverable Machine check"); | |
ba12eede LZ |
786 | |
787 | bail: | |
788 | exception_exit(prev_state); | |
14cf11af PM |
789 | } |
790 | ||
791 | void SMIException(struct pt_regs *regs) | |
792 | { | |
793 | die("System Management Interrupt", regs, SIGABRT); | |
794 | } | |
795 | ||
0869b6fd MS |
796 | void handle_hmi_exception(struct pt_regs *regs) |
797 | { | |
798 | struct pt_regs *old_regs; | |
799 | ||
800 | old_regs = set_irq_regs(regs); | |
801 | irq_enter(); | |
802 | ||
803 | if (ppc_md.handle_hmi_exception) | |
804 | ppc_md.handle_hmi_exception(regs); | |
805 | ||
806 | irq_exit(); | |
807 | set_irq_regs(old_regs); | |
808 | } | |
809 | ||
dc1c1ca3 | 810 | void unknown_exception(struct pt_regs *regs) |
14cf11af | 811 | { |
ba12eede LZ |
812 | enum ctx_state prev_state = exception_enter(); |
813 | ||
14cf11af PM |
814 | printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", |
815 | regs->nip, regs->msr, regs->trap); | |
816 | ||
817 | _exception(SIGTRAP, regs, 0, 0); | |
ba12eede LZ |
818 | |
819 | exception_exit(prev_state); | |
14cf11af PM |
820 | } |
821 | ||
dc1c1ca3 | 822 | void instruction_breakpoint_exception(struct pt_regs *regs) |
14cf11af | 823 | { |
ba12eede LZ |
824 | enum ctx_state prev_state = exception_enter(); |
825 | ||
14cf11af PM |
826 | if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5, |
827 | 5, SIGTRAP) == NOTIFY_STOP) | |
ba12eede | 828 | goto bail; |
14cf11af | 829 | if (debugger_iabr_match(regs)) |
ba12eede | 830 | goto bail; |
14cf11af | 831 | _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); |
ba12eede LZ |
832 | |
833 | bail: | |
834 | exception_exit(prev_state); | |
14cf11af PM |
835 | } |
836 | ||
837 | void RunModeException(struct pt_regs *regs) | |
838 | { | |
839 | _exception(SIGTRAP, regs, 0, 0); | |
840 | } | |
841 | ||
03465f89 | 842 | void single_step_exception(struct pt_regs *regs) |
14cf11af | 843 | { |
ba12eede LZ |
844 | enum ctx_state prev_state = exception_enter(); |
845 | ||
2538c2d0 | 846 | clear_single_step(regs); |
14cf11af | 847 | |
6cc89bad NR |
848 | if (kprobe_post_handler(regs)) |
849 | return; | |
850 | ||
14cf11af PM |
851 | if (notify_die(DIE_SSTEP, "single_step", regs, 5, |
852 | 5, SIGTRAP) == NOTIFY_STOP) | |
ba12eede | 853 | goto bail; |
14cf11af | 854 | if (debugger_sstep(regs)) |
ba12eede | 855 | goto bail; |
14cf11af PM |
856 | |
857 | _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); | |
ba12eede LZ |
858 | |
859 | bail: | |
860 | exception_exit(prev_state); | |
14cf11af | 861 | } |
03465f89 | 862 | NOKPROBE_SYMBOL(single_step_exception); |
14cf11af PM |
863 | |
864 | /* | |
865 | * After we have successfully emulated an instruction, we have to | |
866 | * check if the instruction was being single-stepped, and if so, | |
867 | * pretend we got a single-step exception. This was pointed out | |
868 | * by Kumar Gala. -- paulus | |
869 | */ | |
8dad3f92 | 870 | static void emulate_single_step(struct pt_regs *regs) |
14cf11af | 871 | { |
2538c2d0 P |
872 | if (single_stepping(regs)) |
873 | single_step_exception(regs); | |
14cf11af PM |
874 | } |
875 | ||
5fad293b | 876 | static inline int __parse_fpscr(unsigned long fpscr) |
dc1c1ca3 | 877 | { |
5fad293b | 878 | int ret = 0; |
dc1c1ca3 SR |
879 | |
880 | /* Invalid operation */ | |
881 | if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX)) | |
5fad293b | 882 | ret = FPE_FLTINV; |
dc1c1ca3 SR |
883 | |
884 | /* Overflow */ | |
885 | else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX)) | |
5fad293b | 886 | ret = FPE_FLTOVF; |
dc1c1ca3 SR |
887 | |
888 | /* Underflow */ | |
889 | else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX)) | |
5fad293b | 890 | ret = FPE_FLTUND; |
dc1c1ca3 SR |
891 | |
892 | /* Divide by zero */ | |
893 | else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX)) | |
5fad293b | 894 | ret = FPE_FLTDIV; |
dc1c1ca3 SR |
895 | |
896 | /* Inexact result */ | |
897 | else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX)) | |
5fad293b KG |
898 | ret = FPE_FLTRES; |
899 | ||
900 | return ret; | |
901 | } | |
902 | ||
903 | static void parse_fpe(struct pt_regs *regs) | |
904 | { | |
905 | int code = 0; | |
906 | ||
907 | flush_fp_to_thread(current); | |
908 | ||
de79f7b9 | 909 | code = __parse_fpscr(current->thread.fp_state.fpscr); |
dc1c1ca3 SR |
910 | |
911 | _exception(SIGFPE, regs, code, regs->nip); | |
912 | } | |
913 | ||
914 | /* | |
915 | * Illegal instruction emulation support. Originally written to | |
14cf11af PM |
916 | * provide the PVR to user applications using the mfspr rd, PVR. |
917 | * Return non-zero if we can't emulate, or -EFAULT if the associated | |
918 | * memory access caused an access fault. Return zero on success. | |
919 | * | |
920 | * There are a couple of ways to do this, either "decode" the instruction | |
921 | * or directly match lots of bits. In this case, matching lots of | |
922 | * bits is faster and easier. | |
86417780 | 923 | * |
14cf11af | 924 | */ |
14cf11af PM |
925 | static int emulate_string_inst(struct pt_regs *regs, u32 instword) |
926 | { | |
927 | u8 rT = (instword >> 21) & 0x1f; | |
928 | u8 rA = (instword >> 16) & 0x1f; | |
929 | u8 NB_RB = (instword >> 11) & 0x1f; | |
930 | u32 num_bytes; | |
931 | unsigned long EA; | |
932 | int pos = 0; | |
933 | ||
934 | /* Early out if we are an invalid form of lswx */ | |
16c57b36 | 935 | if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX) |
14cf11af PM |
936 | if ((rT == rA) || (rT == NB_RB)) |
937 | return -EINVAL; | |
938 | ||
939 | EA = (rA == 0) ? 0 : regs->gpr[rA]; | |
940 | ||
16c57b36 KG |
941 | switch (instword & PPC_INST_STRING_MASK) { |
942 | case PPC_INST_LSWX: | |
943 | case PPC_INST_STSWX: | |
14cf11af PM |
944 | EA += NB_RB; |
945 | num_bytes = regs->xer & 0x7f; | |
946 | break; | |
16c57b36 KG |
947 | case PPC_INST_LSWI: |
948 | case PPC_INST_STSWI: | |
14cf11af PM |
949 | num_bytes = (NB_RB == 0) ? 32 : NB_RB; |
950 | break; | |
951 | default: | |
952 | return -EINVAL; | |
953 | } | |
954 | ||
955 | while (num_bytes != 0) | |
956 | { | |
957 | u8 val; | |
958 | u32 shift = 8 * (3 - (pos & 0x3)); | |
959 | ||
80aa0fb4 JY |
960 | /* if process is 32-bit, clear upper 32 bits of EA */ |
961 | if ((regs->msr & MSR_64BIT) == 0) | |
962 | EA &= 0xFFFFFFFF; | |
963 | ||
16c57b36 KG |
964 | switch ((instword & PPC_INST_STRING_MASK)) { |
965 | case PPC_INST_LSWX: | |
966 | case PPC_INST_LSWI: | |
14cf11af PM |
967 | if (get_user(val, (u8 __user *)EA)) |
968 | return -EFAULT; | |
969 | /* first time updating this reg, | |
970 | * zero it out */ | |
971 | if (pos == 0) | |
972 | regs->gpr[rT] = 0; | |
973 | regs->gpr[rT] |= val << shift; | |
974 | break; | |
16c57b36 KG |
975 | case PPC_INST_STSWI: |
976 | case PPC_INST_STSWX: | |
14cf11af PM |
977 | val = regs->gpr[rT] >> shift; |
978 | if (put_user(val, (u8 __user *)EA)) | |
979 | return -EFAULT; | |
980 | break; | |
981 | } | |
982 | /* move EA to next address */ | |
983 | EA += 1; | |
984 | num_bytes--; | |
985 | ||
986 | /* manage our position within the register */ | |
987 | if (++pos == 4) { | |
988 | pos = 0; | |
989 | if (++rT == 32) | |
990 | rT = 0; | |
991 | } | |
992 | } | |
993 | ||
994 | return 0; | |
995 | } | |
996 | ||
c3412dcb WS |
997 | static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword) |
998 | { | |
999 | u32 ra,rs; | |
1000 | unsigned long tmp; | |
1001 | ||
1002 | ra = (instword >> 16) & 0x1f; | |
1003 | rs = (instword >> 21) & 0x1f; | |
1004 | ||
1005 | tmp = regs->gpr[rs]; | |
1006 | tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL); | |
1007 | tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL); | |
1008 | tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL; | |
1009 | regs->gpr[ra] = tmp; | |
1010 | ||
1011 | return 0; | |
1012 | } | |
1013 | ||
c1469f13 KG |
1014 | static int emulate_isel(struct pt_regs *regs, u32 instword) |
1015 | { | |
1016 | u8 rT = (instword >> 21) & 0x1f; | |
1017 | u8 rA = (instword >> 16) & 0x1f; | |
1018 | u8 rB = (instword >> 11) & 0x1f; | |
1019 | u8 BC = (instword >> 6) & 0x1f; | |
1020 | u8 bit; | |
1021 | unsigned long tmp; | |
1022 | ||
1023 | tmp = (rA == 0) ? 0 : regs->gpr[rA]; | |
1024 | bit = (regs->ccr >> (31 - BC)) & 0x1; | |
1025 | ||
1026 | regs->gpr[rT] = bit ? tmp : regs->gpr[rB]; | |
1027 | ||
1028 | return 0; | |
1029 | } | |
1030 | ||
6ce6c629 MN |
1031 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1032 | static inline bool tm_abort_check(struct pt_regs *regs, int cause) | |
1033 | { | |
1034 | /* If we're emulating a load/store in an active transaction, we cannot | |
1035 | * emulate it as the kernel operates in transaction suspended context. | |
1036 | * We need to abort the transaction. This creates a persistent TM | |
1037 | * abort so tell the user what caused it with a new code. | |
1038 | */ | |
1039 | if (MSR_TM_TRANSACTIONAL(regs->msr)) { | |
1040 | tm_enable(); | |
1041 | tm_abort(cause); | |
1042 | return true; | |
1043 | } | |
1044 | return false; | |
1045 | } | |
1046 | #else | |
1047 | static inline bool tm_abort_check(struct pt_regs *regs, int reason) | |
1048 | { | |
1049 | return false; | |
1050 | } | |
1051 | #endif | |
1052 | ||
14cf11af PM |
1053 | static int emulate_instruction(struct pt_regs *regs) |
1054 | { | |
1055 | u32 instword; | |
1056 | u32 rd; | |
1057 | ||
4288e343 | 1058 | if (!user_mode(regs)) |
14cf11af PM |
1059 | return -EINVAL; |
1060 | CHECK_FULL_REGS(regs); | |
1061 | ||
1062 | if (get_user(instword, (u32 __user *)(regs->nip))) | |
1063 | return -EFAULT; | |
1064 | ||
1065 | /* Emulate the mfspr rD, PVR. */ | |
16c57b36 | 1066 | if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) { |
eecff81d | 1067 | PPC_WARN_EMULATED(mfpvr, regs); |
14cf11af PM |
1068 | rd = (instword >> 21) & 0x1f; |
1069 | regs->gpr[rd] = mfspr(SPRN_PVR); | |
1070 | return 0; | |
1071 | } | |
1072 | ||
1073 | /* Emulating the dcba insn is just a no-op. */ | |
80947e7c | 1074 | if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) { |
eecff81d | 1075 | PPC_WARN_EMULATED(dcba, regs); |
14cf11af | 1076 | return 0; |
80947e7c | 1077 | } |
14cf11af PM |
1078 | |
1079 | /* Emulate the mcrxr insn. */ | |
16c57b36 | 1080 | if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) { |
86417780 | 1081 | int shift = (instword >> 21) & 0x1c; |
14cf11af PM |
1082 | unsigned long msk = 0xf0000000UL >> shift; |
1083 | ||
eecff81d | 1084 | PPC_WARN_EMULATED(mcrxr, regs); |
14cf11af PM |
1085 | regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); |
1086 | regs->xer &= ~0xf0000000UL; | |
1087 | return 0; | |
1088 | } | |
1089 | ||
1090 | /* Emulate load/store string insn. */ | |
80947e7c | 1091 | if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) { |
6ce6c629 MN |
1092 | if (tm_abort_check(regs, |
1093 | TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT)) | |
1094 | return -EINVAL; | |
eecff81d | 1095 | PPC_WARN_EMULATED(string, regs); |
14cf11af | 1096 | return emulate_string_inst(regs, instword); |
80947e7c | 1097 | } |
14cf11af | 1098 | |
c3412dcb | 1099 | /* Emulate the popcntb (Population Count Bytes) instruction. */ |
16c57b36 | 1100 | if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) { |
eecff81d | 1101 | PPC_WARN_EMULATED(popcntb, regs); |
c3412dcb WS |
1102 | return emulate_popcntb_inst(regs, instword); |
1103 | } | |
1104 | ||
c1469f13 | 1105 | /* Emulate isel (Integer Select) instruction */ |
16c57b36 | 1106 | if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) { |
eecff81d | 1107 | PPC_WARN_EMULATED(isel, regs); |
c1469f13 KG |
1108 | return emulate_isel(regs, instword); |
1109 | } | |
1110 | ||
9863c28a JY |
1111 | /* Emulate sync instruction variants */ |
1112 | if ((instword & PPC_INST_SYNC_MASK) == PPC_INST_SYNC) { | |
1113 | PPC_WARN_EMULATED(sync, regs); | |
1114 | asm volatile("sync"); | |
1115 | return 0; | |
1116 | } | |
1117 | ||
efcac658 AK |
1118 | #ifdef CONFIG_PPC64 |
1119 | /* Emulate the mfspr rD, DSCR. */ | |
73d2fb75 AB |
1120 | if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) == |
1121 | PPC_INST_MFSPR_DSCR_USER) || | |
1122 | ((instword & PPC_INST_MFSPR_DSCR_MASK) == | |
1123 | PPC_INST_MFSPR_DSCR)) && | |
efcac658 AK |
1124 | cpu_has_feature(CPU_FTR_DSCR)) { |
1125 | PPC_WARN_EMULATED(mfdscr, regs); | |
1126 | rd = (instword >> 21) & 0x1f; | |
1127 | regs->gpr[rd] = mfspr(SPRN_DSCR); | |
1128 | return 0; | |
1129 | } | |
1130 | /* Emulate the mtspr DSCR, rD. */ | |
73d2fb75 AB |
1131 | if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) == |
1132 | PPC_INST_MTSPR_DSCR_USER) || | |
1133 | ((instword & PPC_INST_MTSPR_DSCR_MASK) == | |
1134 | PPC_INST_MTSPR_DSCR)) && | |
efcac658 AK |
1135 | cpu_has_feature(CPU_FTR_DSCR)) { |
1136 | PPC_WARN_EMULATED(mtdscr, regs); | |
1137 | rd = (instword >> 21) & 0x1f; | |
00ca0de0 | 1138 | current->thread.dscr = regs->gpr[rd]; |
efcac658 | 1139 | current->thread.dscr_inherit = 1; |
00ca0de0 | 1140 | mtspr(SPRN_DSCR, current->thread.dscr); |
efcac658 AK |
1141 | return 0; |
1142 | } | |
1143 | #endif | |
1144 | ||
14cf11af PM |
1145 | return -EINVAL; |
1146 | } | |
1147 | ||
73c9ceab | 1148 | int is_valid_bugaddr(unsigned long addr) |
14cf11af | 1149 | { |
73c9ceab | 1150 | return is_kernel_addr(addr); |
14cf11af PM |
1151 | } |
1152 | ||
3a3b5aa6 KH |
1153 | #ifdef CONFIG_MATH_EMULATION |
1154 | static int emulate_math(struct pt_regs *regs) | |
1155 | { | |
1156 | int ret; | |
1157 | extern int do_mathemu(struct pt_regs *regs); | |
1158 | ||
1159 | ret = do_mathemu(regs); | |
1160 | if (ret >= 0) | |
1161 | PPC_WARN_EMULATED(math, regs); | |
1162 | ||
1163 | switch (ret) { | |
1164 | case 0: | |
1165 | emulate_single_step(regs); | |
1166 | return 0; | |
1167 | case 1: { | |
1168 | int code = 0; | |
de79f7b9 | 1169 | code = __parse_fpscr(current->thread.fp_state.fpscr); |
3a3b5aa6 KH |
1170 | _exception(SIGFPE, regs, code, regs->nip); |
1171 | return 0; | |
1172 | } | |
1173 | case -EFAULT: | |
1174 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
1175 | return 0; | |
1176 | } | |
1177 | ||
1178 | return -1; | |
1179 | } | |
1180 | #else | |
1181 | static inline int emulate_math(struct pt_regs *regs) { return -1; } | |
1182 | #endif | |
1183 | ||
03465f89 | 1184 | void program_check_exception(struct pt_regs *regs) |
14cf11af | 1185 | { |
ba12eede | 1186 | enum ctx_state prev_state = exception_enter(); |
14cf11af | 1187 | unsigned int reason = get_reason(regs); |
14cf11af | 1188 | |
aa42c69c | 1189 | /* We can now get here via a FP Unavailable exception if the core |
04903a30 | 1190 | * has no FPU, in that case the reason flags will be 0 */ |
14cf11af | 1191 | |
dc1c1ca3 SR |
1192 | if (reason & REASON_FP) { |
1193 | /* IEEE FP exception */ | |
1194 | parse_fpe(regs); | |
ba12eede | 1195 | goto bail; |
8dad3f92 PM |
1196 | } |
1197 | if (reason & REASON_TRAP) { | |
a4c3f909 | 1198 | unsigned long bugaddr; |
ba797b28 JW |
1199 | /* Debugger is first in line to stop recursive faults in |
1200 | * rcu_lock, notify_die, or atomic_notifier_call_chain */ | |
1201 | if (debugger_bpt(regs)) | |
ba12eede | 1202 | goto bail; |
ba797b28 | 1203 | |
6cc89bad NR |
1204 | if (kprobe_handler(regs)) |
1205 | goto bail; | |
1206 | ||
14cf11af | 1207 | /* trap exception */ |
dc1c1ca3 SR |
1208 | if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP) |
1209 | == NOTIFY_STOP) | |
ba12eede | 1210 | goto bail; |
73c9ceab | 1211 | |
a4c3f909 BS |
1212 | bugaddr = regs->nip; |
1213 | /* | |
1214 | * Fixup bugaddr for BUG_ON() in real mode | |
1215 | */ | |
1216 | if (!is_kernel_addr(bugaddr) && !(regs->msr & MSR_IR)) | |
1217 | bugaddr += PAGE_OFFSET; | |
1218 | ||
73c9ceab | 1219 | if (!(regs->msr & MSR_PR) && /* not user-mode */ |
a4c3f909 | 1220 | report_bug(bugaddr, regs) == BUG_TRAP_TYPE_WARN) { |
14cf11af | 1221 | regs->nip += 4; |
ba12eede | 1222 | goto bail; |
14cf11af | 1223 | } |
8dad3f92 | 1224 | _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); |
ba12eede | 1225 | goto bail; |
8dad3f92 | 1226 | } |
bc2a9408 MN |
1227 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1228 | if (reason & REASON_TM) { | |
1229 | /* This is a TM "Bad Thing Exception" program check. | |
1230 | * This occurs when: | |
1231 | * - An rfid/hrfid/mtmsrd attempts to cause an illegal | |
1232 | * transition in TM states. | |
1233 | * - A trechkpt is attempted when transactional. | |
1234 | * - A treclaim is attempted when non transactional. | |
1235 | * - A tend is illegally attempted. | |
1236 | * - writing a TM SPR when transactional. | |
1237 | */ | |
1238 | if (!user_mode(regs) && | |
1239 | report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) { | |
1240 | regs->nip += 4; | |
ba12eede | 1241 | goto bail; |
bc2a9408 MN |
1242 | } |
1243 | /* If usermode caused this, it's done something illegal and | |
1244 | * gets a SIGILL slap on the wrist. We call it an illegal | |
1245 | * operand to distinguish from the instruction just being bad | |
1246 | * (e.g. executing a 'tend' on a CPU without TM!); it's an | |
1247 | * illegal /placement/ of a valid instruction. | |
1248 | */ | |
1249 | if (user_mode(regs)) { | |
1250 | _exception(SIGILL, regs, ILL_ILLOPN, regs->nip); | |
ba12eede | 1251 | goto bail; |
bc2a9408 MN |
1252 | } else { |
1253 | printk(KERN_EMERG "Unexpected TM Bad Thing exception " | |
1254 | "at %lx (msr 0x%x)\n", regs->nip, reason); | |
1255 | die("Unrecoverable exception", regs, SIGABRT); | |
1256 | } | |
1257 | } | |
1258 | #endif | |
8dad3f92 | 1259 | |
b3f6a459 ME |
1260 | /* |
1261 | * If we took the program check in the kernel skip down to sending a | |
1262 | * SIGILL. The subsequent cases all relate to emulating instructions | |
1263 | * which we should only do for userspace. We also do not want to enable | |
1264 | * interrupts for kernel faults because that might lead to further | |
1265 | * faults, and loose the context of the original exception. | |
1266 | */ | |
1267 | if (!user_mode(regs)) | |
1268 | goto sigill; | |
1269 | ||
a3512b2d BH |
1270 | /* We restore the interrupt state now */ |
1271 | if (!arch_irq_disabled_regs(regs)) | |
1272 | local_irq_enable(); | |
cd8a5673 | 1273 | |
04903a30 KG |
1274 | /* (reason & REASON_ILLEGAL) would be the obvious thing here, |
1275 | * but there seems to be a hardware bug on the 405GP (RevD) | |
1276 | * that means ESR is sometimes set incorrectly - either to | |
1277 | * ESR_DST (!?) or 0. In the process of chasing this with the | |
1278 | * hardware people - not sure if it can happen on any illegal | |
1279 | * instruction or only on FP instructions, whether there is a | |
4e63f8ed BH |
1280 | * pattern to occurrences etc. -dgibson 31/Mar/2003 |
1281 | */ | |
3a3b5aa6 | 1282 | if (!emulate_math(regs)) |
ba12eede | 1283 | goto bail; |
04903a30 | 1284 | |
8dad3f92 PM |
1285 | /* Try to emulate it if we should. */ |
1286 | if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { | |
14cf11af PM |
1287 | switch (emulate_instruction(regs)) { |
1288 | case 0: | |
1289 | regs->nip += 4; | |
1290 | emulate_single_step(regs); | |
ba12eede | 1291 | goto bail; |
14cf11af PM |
1292 | case -EFAULT: |
1293 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
ba12eede | 1294 | goto bail; |
14cf11af PM |
1295 | } |
1296 | } | |
8dad3f92 | 1297 | |
b3f6a459 | 1298 | sigill: |
8dad3f92 PM |
1299 | if (reason & REASON_PRIVILEGED) |
1300 | _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); | |
1301 | else | |
1302 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
ba12eede LZ |
1303 | |
1304 | bail: | |
1305 | exception_exit(prev_state); | |
14cf11af | 1306 | } |
03465f89 | 1307 | NOKPROBE_SYMBOL(program_check_exception); |
14cf11af | 1308 | |
bf593907 PM |
1309 | /* |
1310 | * This occurs when running in hypervisor mode on POWER6 or later | |
1311 | * and an illegal instruction is encountered. | |
1312 | */ | |
03465f89 | 1313 | void emulation_assist_interrupt(struct pt_regs *regs) |
bf593907 PM |
1314 | { |
1315 | regs->msr |= REASON_ILLEGAL; | |
1316 | program_check_exception(regs); | |
1317 | } | |
03465f89 | 1318 | NOKPROBE_SYMBOL(emulation_assist_interrupt); |
bf593907 | 1319 | |
dc1c1ca3 | 1320 | void alignment_exception(struct pt_regs *regs) |
14cf11af | 1321 | { |
ba12eede | 1322 | enum ctx_state prev_state = exception_enter(); |
4393c4f6 | 1323 | int sig, code, fixed = 0; |
14cf11af | 1324 | |
a3512b2d BH |
1325 | /* We restore the interrupt state now */ |
1326 | if (!arch_irq_disabled_regs(regs)) | |
1327 | local_irq_enable(); | |
1328 | ||
6ce6c629 MN |
1329 | if (tm_abort_check(regs, TM_CAUSE_ALIGNMENT | TM_CAUSE_PERSISTENT)) |
1330 | goto bail; | |
1331 | ||
e9370ae1 PM |
1332 | /* we don't implement logging of alignment exceptions */ |
1333 | if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS)) | |
1334 | fixed = fix_alignment(regs); | |
14cf11af PM |
1335 | |
1336 | if (fixed == 1) { | |
1337 | regs->nip += 4; /* skip over emulated instruction */ | |
1338 | emulate_single_step(regs); | |
ba12eede | 1339 | goto bail; |
14cf11af PM |
1340 | } |
1341 | ||
dc1c1ca3 | 1342 | /* Operand address was bad */ |
14cf11af | 1343 | if (fixed == -EFAULT) { |
4393c4f6 BH |
1344 | sig = SIGSEGV; |
1345 | code = SEGV_ACCERR; | |
1346 | } else { | |
1347 | sig = SIGBUS; | |
1348 | code = BUS_ADRALN; | |
14cf11af | 1349 | } |
4393c4f6 BH |
1350 | if (user_mode(regs)) |
1351 | _exception(sig, regs, code, regs->dar); | |
1352 | else | |
1353 | bad_page_fault(regs, regs->dar, sig); | |
ba12eede LZ |
1354 | |
1355 | bail: | |
1356 | exception_exit(prev_state); | |
14cf11af PM |
1357 | } |
1358 | ||
f0f558b1 PM |
1359 | void slb_miss_bad_addr(struct pt_regs *regs) |
1360 | { | |
1361 | enum ctx_state prev_state = exception_enter(); | |
1362 | ||
1363 | if (user_mode(regs)) | |
1364 | _exception(SIGSEGV, regs, SEGV_BNDERR, regs->dar); | |
1365 | else | |
1366 | bad_page_fault(regs, regs->dar, SIGSEGV); | |
1367 | ||
1368 | exception_exit(prev_state); | |
1369 | } | |
1370 | ||
14cf11af PM |
1371 | void StackOverflow(struct pt_regs *regs) |
1372 | { | |
1373 | printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n", | |
1374 | current, regs->gpr[1]); | |
1375 | debugger(regs); | |
1376 | show_regs(regs); | |
1377 | panic("kernel stack overflow"); | |
1378 | } | |
1379 | ||
1380 | void nonrecoverable_exception(struct pt_regs *regs) | |
1381 | { | |
1382 | printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n", | |
1383 | regs->nip, regs->msr); | |
1384 | debugger(regs); | |
1385 | die("nonrecoverable exception", regs, SIGKILL); | |
1386 | } | |
1387 | ||
dc1c1ca3 SR |
1388 | void kernel_fp_unavailable_exception(struct pt_regs *regs) |
1389 | { | |
ba12eede LZ |
1390 | enum ctx_state prev_state = exception_enter(); |
1391 | ||
dc1c1ca3 SR |
1392 | printk(KERN_EMERG "Unrecoverable FP Unavailable Exception " |
1393 | "%lx at %lx\n", regs->trap, regs->nip); | |
1394 | die("Unrecoverable FP Unavailable Exception", regs, SIGABRT); | |
ba12eede LZ |
1395 | |
1396 | exception_exit(prev_state); | |
dc1c1ca3 | 1397 | } |
dc1c1ca3 SR |
1398 | |
1399 | void altivec_unavailable_exception(struct pt_regs *regs) | |
1400 | { | |
ba12eede LZ |
1401 | enum ctx_state prev_state = exception_enter(); |
1402 | ||
dc1c1ca3 SR |
1403 | if (user_mode(regs)) { |
1404 | /* A user program has executed an altivec instruction, | |
1405 | but this kernel doesn't support altivec. */ | |
1406 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
ba12eede | 1407 | goto bail; |
dc1c1ca3 | 1408 | } |
6c4841c2 | 1409 | |
dc1c1ca3 SR |
1410 | printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception " |
1411 | "%lx at %lx\n", regs->trap, regs->nip); | |
1412 | die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT); | |
ba12eede LZ |
1413 | |
1414 | bail: | |
1415 | exception_exit(prev_state); | |
dc1c1ca3 SR |
1416 | } |
1417 | ||
ce48b210 MN |
1418 | void vsx_unavailable_exception(struct pt_regs *regs) |
1419 | { | |
1420 | if (user_mode(regs)) { | |
1421 | /* A user program has executed an vsx instruction, | |
1422 | but this kernel doesn't support vsx. */ | |
1423 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
1424 | return; | |
1425 | } | |
1426 | ||
1427 | printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception " | |
1428 | "%lx at %lx\n", regs->trap, regs->nip); | |
1429 | die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT); | |
1430 | } | |
1431 | ||
2517617e | 1432 | #ifdef CONFIG_PPC64 |
172f7aaa CB |
1433 | static void tm_unavailable(struct pt_regs *regs) |
1434 | { | |
5d176f75 CB |
1435 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1436 | if (user_mode(regs)) { | |
1437 | current->thread.load_tm++; | |
1438 | regs->msr |= MSR_TM; | |
1439 | tm_enable(); | |
1440 | tm_restore_sprs(¤t->thread); | |
1441 | return; | |
1442 | } | |
1443 | #endif | |
172f7aaa CB |
1444 | pr_emerg("Unrecoverable TM Unavailable Exception " |
1445 | "%lx at %lx\n", regs->trap, regs->nip); | |
1446 | die("Unrecoverable TM Unavailable Exception", regs, SIGABRT); | |
1447 | } | |
1448 | ||
021424a1 | 1449 | void facility_unavailable_exception(struct pt_regs *regs) |
d0c0c9a1 | 1450 | { |
021424a1 | 1451 | static char *facility_strings[] = { |
2517617e MN |
1452 | [FSCR_FP_LG] = "FPU", |
1453 | [FSCR_VECVSX_LG] = "VMX/VSX", | |
1454 | [FSCR_DSCR_LG] = "DSCR", | |
1455 | [FSCR_PM_LG] = "PMU SPRs", | |
1456 | [FSCR_BHRB_LG] = "BHRB", | |
1457 | [FSCR_TM_LG] = "TM", | |
1458 | [FSCR_EBB_LG] = "EBB", | |
1459 | [FSCR_TAR_LG] = "TAR", | |
794464f4 | 1460 | [FSCR_MSGP_LG] = "MSGP", |
9b7ff0c6 | 1461 | [FSCR_SCV_LG] = "SCV", |
021424a1 | 1462 | }; |
2517617e | 1463 | char *facility = "unknown"; |
021424a1 | 1464 | u64 value; |
c952c1c4 | 1465 | u32 instword, rd; |
2517617e MN |
1466 | u8 status; |
1467 | bool hv; | |
021424a1 | 1468 | |
2517617e MN |
1469 | hv = (regs->trap == 0xf80); |
1470 | if (hv) | |
b14b6260 | 1471 | value = mfspr(SPRN_HFSCR); |
2517617e MN |
1472 | else |
1473 | value = mfspr(SPRN_FSCR); | |
1474 | ||
1475 | status = value >> 56; | |
1476 | if (status == FSCR_DSCR_LG) { | |
c952c1c4 AK |
1477 | /* |
1478 | * User is accessing the DSCR register using the problem | |
1479 | * state only SPR number (0x03) either through a mfspr or | |
1480 | * a mtspr instruction. If it is a write attempt through | |
1481 | * a mtspr, then we set the inherit bit. This also allows | |
1482 | * the user to write or read the register directly in the | |
1483 | * future by setting via the FSCR DSCR bit. But in case it | |
1484 | * is a read DSCR attempt through a mfspr instruction, we | |
1485 | * just emulate the instruction instead. This code path will | |
1486 | * always emulate all the mfspr instructions till the user | |
446957ba | 1487 | * has attempted at least one mtspr instruction. This way it |
c952c1c4 AK |
1488 | * preserves the same behaviour when the user is accessing |
1489 | * the DSCR through privilege level only SPR number (0x11) | |
1490 | * which is emulated through illegal instruction exception. | |
1491 | * We always leave HFSCR DSCR set. | |
2517617e | 1492 | */ |
c952c1c4 AK |
1493 | if (get_user(instword, (u32 __user *)(regs->nip))) { |
1494 | pr_err("Failed to fetch the user instruction\n"); | |
1495 | return; | |
1496 | } | |
1497 | ||
1498 | /* Write into DSCR (mtspr 0x03, RS) */ | |
1499 | if ((instword & PPC_INST_MTSPR_DSCR_USER_MASK) | |
1500 | == PPC_INST_MTSPR_DSCR_USER) { | |
1501 | rd = (instword >> 21) & 0x1f; | |
1502 | current->thread.dscr = regs->gpr[rd]; | |
1503 | current->thread.dscr_inherit = 1; | |
b57bd2de MN |
1504 | current->thread.fscr |= FSCR_DSCR; |
1505 | mtspr(SPRN_FSCR, current->thread.fscr); | |
c952c1c4 AK |
1506 | } |
1507 | ||
1508 | /* Read from DSCR (mfspr RT, 0x03) */ | |
1509 | if ((instword & PPC_INST_MFSPR_DSCR_USER_MASK) | |
1510 | == PPC_INST_MFSPR_DSCR_USER) { | |
1511 | if (emulate_instruction(regs)) { | |
1512 | pr_err("DSCR based mfspr emulation failed\n"); | |
1513 | return; | |
1514 | } | |
1515 | regs->nip += 4; | |
1516 | emulate_single_step(regs); | |
1517 | } | |
2517617e | 1518 | return; |
b14b6260 ME |
1519 | } |
1520 | ||
172f7aaa CB |
1521 | if (status == FSCR_TM_LG) { |
1522 | /* | |
1523 | * If we're here then the hardware is TM aware because it | |
1524 | * generated an exception with FSRM_TM set. | |
1525 | * | |
1526 | * If cpu_has_feature(CPU_FTR_TM) is false, then either firmware | |
1527 | * told us not to do TM, or the kernel is not built with TM | |
1528 | * support. | |
1529 | * | |
1530 | * If both of those things are true, then userspace can spam the | |
1531 | * console by triggering the printk() below just by continually | |
1532 | * doing tbegin (or any TM instruction). So in that case just | |
1533 | * send the process a SIGILL immediately. | |
1534 | */ | |
1535 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1536 | goto out; | |
1537 | ||
1538 | tm_unavailable(regs); | |
1539 | return; | |
1540 | } | |
1541 | ||
93c2ec0f BS |
1542 | if ((hv || status >= 2) && |
1543 | (status < ARRAY_SIZE(facility_strings)) && | |
2517617e MN |
1544 | facility_strings[status]) |
1545 | facility = facility_strings[status]; | |
021424a1 | 1546 | |
d0c0c9a1 MN |
1547 | /* We restore the interrupt state now */ |
1548 | if (!arch_irq_disabled_regs(regs)) | |
1549 | local_irq_enable(); | |
1550 | ||
93c2ec0f BS |
1551 | pr_err_ratelimited("%sFacility '%s' unavailable (%d), exception at 0x%lx, MSR=%lx\n", |
1552 | hv ? "Hypervisor " : "", facility, status, regs->nip, regs->msr); | |
d0c0c9a1 | 1553 | |
172f7aaa | 1554 | out: |
d0c0c9a1 MN |
1555 | if (user_mode(regs)) { |
1556 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
1557 | return; | |
1558 | } | |
1559 | ||
021424a1 | 1560 | die("Unexpected facility unavailable exception", regs, SIGABRT); |
d0c0c9a1 | 1561 | } |
2517617e | 1562 | #endif |
d0c0c9a1 | 1563 | |
f54db641 MN |
1564 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1565 | ||
f54db641 MN |
1566 | void fp_unavailable_tm(struct pt_regs *regs) |
1567 | { | |
1568 | /* Note: This does not handle any kind of FP laziness. */ | |
1569 | ||
1570 | TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n", | |
1571 | regs->nip, regs->msr); | |
f54db641 MN |
1572 | |
1573 | /* We can only have got here if the task started using FP after | |
1574 | * beginning the transaction. So, the transactional regs are just a | |
1575 | * copy of the checkpointed ones. But, we still need to recheckpoint | |
1576 | * as we're enabling FP for the process; it will return, abort the | |
1577 | * transaction, and probably retry but now with FP enabled. So the | |
1578 | * checkpointed FP registers need to be loaded. | |
1579 | */ | |
d31626f7 | 1580 | tm_reclaim_current(TM_CAUSE_FAC_UNAV); |
f54db641 MN |
1581 | /* Reclaim didn't save out any FPRs to transact_fprs. */ |
1582 | ||
1583 | /* Enable FP for the task: */ | |
1584 | regs->msr |= (MSR_FP | current->thread.fpexc_mode); | |
1585 | ||
1586 | /* This loads and recheckpoints the FP registers from | |
1587 | * thread.fpr[]. They will remain in registers after the | |
1588 | * checkpoint so we don't need to reload them after. | |
3ac8ff1c PM |
1589 | * If VMX is in use, the VRs now hold checkpointed values, |
1590 | * so we don't want to load the VRs from the thread_struct. | |
f54db641 | 1591 | */ |
3ac8ff1c PM |
1592 | tm_recheckpoint(¤t->thread, MSR_FP); |
1593 | ||
1594 | /* If VMX is in use, get the transactional values back */ | |
1595 | if (regs->msr & MSR_VEC) { | |
dc310669 CB |
1596 | msr_check_and_set(MSR_VEC); |
1597 | load_vr_state(¤t->thread.vr_state); | |
3ac8ff1c PM |
1598 | /* At this point all the VSX state is loaded, so enable it */ |
1599 | regs->msr |= MSR_VSX; | |
1600 | } | |
f54db641 MN |
1601 | } |
1602 | ||
f54db641 MN |
1603 | void altivec_unavailable_tm(struct pt_regs *regs) |
1604 | { | |
1605 | /* See the comments in fp_unavailable_tm(). This function operates | |
1606 | * the same way. | |
1607 | */ | |
1608 | ||
1609 | TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx," | |
1610 | "MSR=%lx\n", | |
1611 | regs->nip, regs->msr); | |
d31626f7 | 1612 | tm_reclaim_current(TM_CAUSE_FAC_UNAV); |
f54db641 | 1613 | regs->msr |= MSR_VEC; |
3ac8ff1c | 1614 | tm_recheckpoint(¤t->thread, MSR_VEC); |
f54db641 | 1615 | current->thread.used_vr = 1; |
3ac8ff1c PM |
1616 | |
1617 | if (regs->msr & MSR_FP) { | |
dc310669 CB |
1618 | msr_check_and_set(MSR_FP); |
1619 | load_fp_state(¤t->thread.fp_state); | |
3ac8ff1c PM |
1620 | regs->msr |= MSR_VSX; |
1621 | } | |
f54db641 | 1622 | } |
f54db641 | 1623 | |
f54db641 MN |
1624 | void vsx_unavailable_tm(struct pt_regs *regs) |
1625 | { | |
3ac8ff1c PM |
1626 | unsigned long orig_msr = regs->msr; |
1627 | ||
f54db641 MN |
1628 | /* See the comments in fp_unavailable_tm(). This works similarly, |
1629 | * though we're loading both FP and VEC registers in here. | |
1630 | * | |
1631 | * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC | |
1632 | * regs. Either way, set MSR_VSX. | |
1633 | */ | |
1634 | ||
1635 | TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx," | |
1636 | "MSR=%lx\n", | |
1637 | regs->nip, regs->msr); | |
1638 | ||
3ac8ff1c PM |
1639 | current->thread.used_vsr = 1; |
1640 | ||
1641 | /* If FP and VMX are already loaded, we have all the state we need */ | |
1642 | if ((orig_msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC)) { | |
1643 | regs->msr |= MSR_VSX; | |
1644 | return; | |
1645 | } | |
1646 | ||
f54db641 | 1647 | /* This reclaims FP and/or VR regs if they're already enabled */ |
d31626f7 | 1648 | tm_reclaim_current(TM_CAUSE_FAC_UNAV); |
f54db641 MN |
1649 | |
1650 | regs->msr |= MSR_VEC | MSR_FP | current->thread.fpexc_mode | | |
1651 | MSR_VSX; | |
3ac8ff1c PM |
1652 | |
1653 | /* This loads & recheckpoints FP and VRs; but we have | |
1654 | * to be sure not to overwrite previously-valid state. | |
1655 | */ | |
1656 | tm_recheckpoint(¤t->thread, regs->msr & ~orig_msr); | |
1657 | ||
dc310669 CB |
1658 | msr_check_and_set(orig_msr & (MSR_FP | MSR_VEC)); |
1659 | ||
3ac8ff1c | 1660 | if (orig_msr & MSR_FP) |
dc310669 | 1661 | load_fp_state(¤t->thread.fp_state); |
3ac8ff1c | 1662 | if (orig_msr & MSR_VEC) |
dc310669 | 1663 | load_vr_state(¤t->thread.vr_state); |
f54db641 | 1664 | } |
f54db641 MN |
1665 | #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ |
1666 | ||
dc1c1ca3 SR |
1667 | void performance_monitor_exception(struct pt_regs *regs) |
1668 | { | |
69111bac | 1669 | __this_cpu_inc(irq_stat.pmu_irqs); |
89713ed1 | 1670 | |
dc1c1ca3 SR |
1671 | perf_irq(regs); |
1672 | } | |
dc1c1ca3 | 1673 | |
8dad3f92 | 1674 | #ifdef CONFIG_8xx |
14cf11af PM |
1675 | void SoftwareEmulation(struct pt_regs *regs) |
1676 | { | |
14cf11af PM |
1677 | CHECK_FULL_REGS(regs); |
1678 | ||
1679 | if (!user_mode(regs)) { | |
1680 | debugger(regs); | |
1eb2819d LC |
1681 | die("Kernel Mode Unimplemented Instruction or SW FPU Emulation", |
1682 | regs, SIGFPE); | |
14cf11af PM |
1683 | } |
1684 | ||
3a3b5aa6 | 1685 | if (!emulate_math(regs)) |
5fad293b | 1686 | return; |
3a3b5aa6 | 1687 | |
5dd57a13 | 1688 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); |
14cf11af | 1689 | } |
8dad3f92 | 1690 | #endif /* CONFIG_8xx */ |
14cf11af | 1691 | |
172ae2e7 | 1692 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
3bffb652 DK |
1693 | static void handle_debug(struct pt_regs *regs, unsigned long debug_status) |
1694 | { | |
1695 | int changed = 0; | |
1696 | /* | |
1697 | * Determine the cause of the debug event, clear the | |
1698 | * event flags and send a trap to the handler. Torez | |
1699 | */ | |
1700 | if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) { | |
1701 | dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W); | |
1702 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
51ae8d4a | 1703 | current->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE; |
3bffb652 DK |
1704 | #endif |
1705 | do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT, | |
1706 | 5); | |
1707 | changed |= 0x01; | |
1708 | } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) { | |
1709 | dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W); | |
1710 | do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, TRAP_HWBKPT, | |
1711 | 6); | |
1712 | changed |= 0x01; | |
1713 | } else if (debug_status & DBSR_IAC1) { | |
51ae8d4a | 1714 | current->thread.debug.dbcr0 &= ~DBCR0_IAC1; |
3bffb652 DK |
1715 | dbcr_iac_range(current) &= ~DBCR_IAC12MODE; |
1716 | do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT, | |
1717 | 1); | |
1718 | changed |= 0x01; | |
1719 | } else if (debug_status & DBSR_IAC2) { | |
51ae8d4a | 1720 | current->thread.debug.dbcr0 &= ~DBCR0_IAC2; |
3bffb652 DK |
1721 | do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT, |
1722 | 2); | |
1723 | changed |= 0x01; | |
1724 | } else if (debug_status & DBSR_IAC3) { | |
51ae8d4a | 1725 | current->thread.debug.dbcr0 &= ~DBCR0_IAC3; |
3bffb652 DK |
1726 | dbcr_iac_range(current) &= ~DBCR_IAC34MODE; |
1727 | do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT, | |
1728 | 3); | |
1729 | changed |= 0x01; | |
1730 | } else if (debug_status & DBSR_IAC4) { | |
51ae8d4a | 1731 | current->thread.debug.dbcr0 &= ~DBCR0_IAC4; |
3bffb652 DK |
1732 | do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT, |
1733 | 4); | |
1734 | changed |= 0x01; | |
1735 | } | |
1736 | /* | |
1737 | * At the point this routine was called, the MSR(DE) was turned off. | |
1738 | * Check all other debug flags and see if that bit needs to be turned | |
1739 | * back on or not. | |
1740 | */ | |
51ae8d4a | 1741 | if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0, |
95791988 | 1742 | current->thread.debug.dbcr1)) |
3bffb652 DK |
1743 | regs->msr |= MSR_DE; |
1744 | else | |
1745 | /* Make sure the IDM flag is off */ | |
51ae8d4a | 1746 | current->thread.debug.dbcr0 &= ~DBCR0_IDM; |
3bffb652 DK |
1747 | |
1748 | if (changed & 0x01) | |
51ae8d4a | 1749 | mtspr(SPRN_DBCR0, current->thread.debug.dbcr0); |
3bffb652 | 1750 | } |
14cf11af | 1751 | |
03465f89 | 1752 | void DebugException(struct pt_regs *regs, unsigned long debug_status) |
14cf11af | 1753 | { |
51ae8d4a | 1754 | current->thread.debug.dbsr = debug_status; |
3bffb652 | 1755 | |
ec097c84 RM |
1756 | /* Hack alert: On BookE, Branch Taken stops on the branch itself, while |
1757 | * on server, it stops on the target of the branch. In order to simulate | |
1758 | * the server behaviour, we thus restart right away with a single step | |
1759 | * instead of stopping here when hitting a BT | |
1760 | */ | |
1761 | if (debug_status & DBSR_BT) { | |
1762 | regs->msr &= ~MSR_DE; | |
1763 | ||
1764 | /* Disable BT */ | |
1765 | mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT); | |
1766 | /* Clear the BT event */ | |
1767 | mtspr(SPRN_DBSR, DBSR_BT); | |
1768 | ||
1769 | /* Do the single step trick only when coming from userspace */ | |
1770 | if (user_mode(regs)) { | |
51ae8d4a BB |
1771 | current->thread.debug.dbcr0 &= ~DBCR0_BT; |
1772 | current->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC; | |
ec097c84 RM |
1773 | regs->msr |= MSR_DE; |
1774 | return; | |
1775 | } | |
1776 | ||
6cc89bad NR |
1777 | if (kprobe_post_handler(regs)) |
1778 | return; | |
1779 | ||
ec097c84 RM |
1780 | if (notify_die(DIE_SSTEP, "block_step", regs, 5, |
1781 | 5, SIGTRAP) == NOTIFY_STOP) { | |
1782 | return; | |
1783 | } | |
1784 | if (debugger_sstep(regs)) | |
1785 | return; | |
1786 | } else if (debug_status & DBSR_IC) { /* Instruction complete */ | |
14cf11af | 1787 | regs->msr &= ~MSR_DE; |
f8279621 KG |
1788 | |
1789 | /* Disable instruction completion */ | |
1790 | mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC); | |
1791 | /* Clear the instruction completion event */ | |
1792 | mtspr(SPRN_DBSR, DBSR_IC); | |
1793 | ||
6cc89bad NR |
1794 | if (kprobe_post_handler(regs)) |
1795 | return; | |
1796 | ||
f8279621 KG |
1797 | if (notify_die(DIE_SSTEP, "single_step", regs, 5, |
1798 | 5, SIGTRAP) == NOTIFY_STOP) { | |
1799 | return; | |
1800 | } | |
1801 | ||
1802 | if (debugger_sstep(regs)) | |
1803 | return; | |
1804 | ||
d6a61bfc | 1805 | if (user_mode(regs)) { |
51ae8d4a BB |
1806 | current->thread.debug.dbcr0 &= ~DBCR0_IC; |
1807 | if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0, | |
1808 | current->thread.debug.dbcr1)) | |
3bffb652 DK |
1809 | regs->msr |= MSR_DE; |
1810 | else | |
1811 | /* Make sure the IDM bit is off */ | |
51ae8d4a | 1812 | current->thread.debug.dbcr0 &= ~DBCR0_IDM; |
d6a61bfc | 1813 | } |
3bffb652 DK |
1814 | |
1815 | _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); | |
1816 | } else | |
1817 | handle_debug(regs, debug_status); | |
14cf11af | 1818 | } |
03465f89 | 1819 | NOKPROBE_SYMBOL(DebugException); |
172ae2e7 | 1820 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ |
14cf11af PM |
1821 | |
1822 | #if !defined(CONFIG_TAU_INT) | |
1823 | void TAUException(struct pt_regs *regs) | |
1824 | { | |
1825 | printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n", | |
1826 | regs->nip, regs->msr, regs->trap, print_tainted()); | |
1827 | } | |
1828 | #endif /* CONFIG_INT_TAU */ | |
14cf11af PM |
1829 | |
1830 | #ifdef CONFIG_ALTIVEC | |
dc1c1ca3 | 1831 | void altivec_assist_exception(struct pt_regs *regs) |
14cf11af PM |
1832 | { |
1833 | int err; | |
1834 | ||
14cf11af PM |
1835 | if (!user_mode(regs)) { |
1836 | printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode" | |
1837 | " at %lx\n", regs->nip); | |
8dad3f92 | 1838 | die("Kernel VMX/Altivec assist exception", regs, SIGILL); |
14cf11af PM |
1839 | } |
1840 | ||
dc1c1ca3 | 1841 | flush_altivec_to_thread(current); |
dc1c1ca3 | 1842 | |
eecff81d | 1843 | PPC_WARN_EMULATED(altivec, regs); |
14cf11af PM |
1844 | err = emulate_altivec(regs); |
1845 | if (err == 0) { | |
1846 | regs->nip += 4; /* skip emulated instruction */ | |
1847 | emulate_single_step(regs); | |
1848 | return; | |
1849 | } | |
1850 | ||
1851 | if (err == -EFAULT) { | |
1852 | /* got an error reading the instruction */ | |
1853 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); | |
1854 | } else { | |
1855 | /* didn't recognize the instruction */ | |
1856 | /* XXX quick hack for now: set the non-Java bit in the VSCR */ | |
76462232 CD |
1857 | printk_ratelimited(KERN_ERR "Unrecognized altivec instruction " |
1858 | "in %s at %lx\n", current->comm, regs->nip); | |
de79f7b9 | 1859 | current->thread.vr_state.vscr.u[3] |= 0x10000; |
14cf11af PM |
1860 | } |
1861 | } | |
1862 | #endif /* CONFIG_ALTIVEC */ | |
1863 | ||
14cf11af PM |
1864 | #ifdef CONFIG_FSL_BOOKE |
1865 | void CacheLockingException(struct pt_regs *regs, unsigned long address, | |
1866 | unsigned long error_code) | |
1867 | { | |
1868 | /* We treat cache locking instructions from the user | |
1869 | * as priv ops, in the future we could try to do | |
1870 | * something smarter | |
1871 | */ | |
1872 | if (error_code & (ESR_DLK|ESR_ILK)) | |
1873 | _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); | |
1874 | return; | |
1875 | } | |
1876 | #endif /* CONFIG_FSL_BOOKE */ | |
1877 | ||
1878 | #ifdef CONFIG_SPE | |
1879 | void SPEFloatingPointException(struct pt_regs *regs) | |
1880 | { | |
6a800f36 | 1881 | extern int do_spe_mathemu(struct pt_regs *regs); |
14cf11af PM |
1882 | unsigned long spefscr; |
1883 | int fpexc_mode; | |
1884 | int code = 0; | |
6a800f36 LY |
1885 | int err; |
1886 | ||
685659ee | 1887 | flush_spe_to_thread(current); |
14cf11af PM |
1888 | |
1889 | spefscr = current->thread.spefscr; | |
1890 | fpexc_mode = current->thread.fpexc_mode; | |
1891 | ||
14cf11af PM |
1892 | if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) { |
1893 | code = FPE_FLTOVF; | |
14cf11af PM |
1894 | } |
1895 | else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) { | |
1896 | code = FPE_FLTUND; | |
14cf11af PM |
1897 | } |
1898 | else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV)) | |
1899 | code = FPE_FLTDIV; | |
1900 | else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) { | |
1901 | code = FPE_FLTINV; | |
14cf11af PM |
1902 | } |
1903 | else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES)) | |
1904 | code = FPE_FLTRES; | |
1905 | ||
6a800f36 LY |
1906 | err = do_spe_mathemu(regs); |
1907 | if (err == 0) { | |
1908 | regs->nip += 4; /* skip emulated instruction */ | |
1909 | emulate_single_step(regs); | |
1910 | return; | |
1911 | } | |
1912 | ||
1913 | if (err == -EFAULT) { | |
1914 | /* got an error reading the instruction */ | |
1915 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); | |
1916 | } else if (err == -EINVAL) { | |
1917 | /* didn't recognize the instruction */ | |
1918 | printk(KERN_ERR "unrecognized spe instruction " | |
1919 | "in %s at %lx\n", current->comm, regs->nip); | |
1920 | } else { | |
1921 | _exception(SIGFPE, regs, code, regs->nip); | |
1922 | } | |
14cf11af | 1923 | |
14cf11af PM |
1924 | return; |
1925 | } | |
6a800f36 LY |
1926 | |
1927 | void SPEFloatingPointRoundException(struct pt_regs *regs) | |
1928 | { | |
1929 | extern int speround_handler(struct pt_regs *regs); | |
1930 | int err; | |
1931 | ||
1932 | preempt_disable(); | |
1933 | if (regs->msr & MSR_SPE) | |
1934 | giveup_spe(current); | |
1935 | preempt_enable(); | |
1936 | ||
1937 | regs->nip -= 4; | |
1938 | err = speround_handler(regs); | |
1939 | if (err == 0) { | |
1940 | regs->nip += 4; /* skip emulated instruction */ | |
1941 | emulate_single_step(regs); | |
1942 | return; | |
1943 | } | |
1944 | ||
1945 | if (err == -EFAULT) { | |
1946 | /* got an error reading the instruction */ | |
1947 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); | |
1948 | } else if (err == -EINVAL) { | |
1949 | /* didn't recognize the instruction */ | |
1950 | printk(KERN_ERR "unrecognized spe instruction " | |
1951 | "in %s at %lx\n", current->comm, regs->nip); | |
1952 | } else { | |
1953 | _exception(SIGFPE, regs, 0, regs->nip); | |
1954 | return; | |
1955 | } | |
1956 | } | |
14cf11af PM |
1957 | #endif |
1958 | ||
dc1c1ca3 SR |
1959 | /* |
1960 | * We enter here if we get an unrecoverable exception, that is, one | |
1961 | * that happened at a point where the RI (recoverable interrupt) bit | |
1962 | * in the MSR is 0. This indicates that SRR0/1 are live, and that | |
1963 | * we therefore lost state by taking this exception. | |
1964 | */ | |
1965 | void unrecoverable_exception(struct pt_regs *regs) | |
1966 | { | |
1967 | printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n", | |
1968 | regs->trap, regs->nip); | |
1969 | die("Unrecoverable exception", regs, SIGABRT); | |
1970 | } | |
dc1c1ca3 | 1971 | |
1e18c17a | 1972 | #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x) |
14cf11af PM |
1973 | /* |
1974 | * Default handler for a Watchdog exception, | |
1975 | * spins until a reboot occurs | |
1976 | */ | |
1977 | void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs) | |
1978 | { | |
1979 | /* Generic WatchdogHandler, implement your own */ | |
1980 | mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE)); | |
1981 | return; | |
1982 | } | |
1983 | ||
1984 | void WatchdogException(struct pt_regs *regs) | |
1985 | { | |
1986 | printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n"); | |
1987 | WatchdogHandler(regs); | |
1988 | } | |
1989 | #endif | |
dc1c1ca3 | 1990 | |
dc1c1ca3 SR |
1991 | /* |
1992 | * We enter here if we discover during exception entry that we are | |
1993 | * running in supervisor mode with a userspace value in the stack pointer. | |
1994 | */ | |
1995 | void kernel_bad_stack(struct pt_regs *regs) | |
1996 | { | |
1997 | printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n", | |
1998 | regs->gpr[1], regs->nip); | |
1999 | die("Bad kernel stack pointer", regs, SIGABRT); | |
2000 | } | |
14cf11af PM |
2001 | |
2002 | void __init trap_init(void) | |
2003 | { | |
2004 | } | |
80947e7c GU |
2005 | |
2006 | ||
2007 | #ifdef CONFIG_PPC_EMULATED_STATS | |
2008 | ||
2009 | #define WARN_EMULATED_SETUP(type) .type = { .name = #type } | |
2010 | ||
2011 | struct ppc_emulated ppc_emulated = { | |
2012 | #ifdef CONFIG_ALTIVEC | |
2013 | WARN_EMULATED_SETUP(altivec), | |
2014 | #endif | |
2015 | WARN_EMULATED_SETUP(dcba), | |
2016 | WARN_EMULATED_SETUP(dcbz), | |
2017 | WARN_EMULATED_SETUP(fp_pair), | |
2018 | WARN_EMULATED_SETUP(isel), | |
2019 | WARN_EMULATED_SETUP(mcrxr), | |
2020 | WARN_EMULATED_SETUP(mfpvr), | |
2021 | WARN_EMULATED_SETUP(multiple), | |
2022 | WARN_EMULATED_SETUP(popcntb), | |
2023 | WARN_EMULATED_SETUP(spe), | |
2024 | WARN_EMULATED_SETUP(string), | |
a3821b2a | 2025 | WARN_EMULATED_SETUP(sync), |
80947e7c GU |
2026 | WARN_EMULATED_SETUP(unaligned), |
2027 | #ifdef CONFIG_MATH_EMULATION | |
2028 | WARN_EMULATED_SETUP(math), | |
80947e7c GU |
2029 | #endif |
2030 | #ifdef CONFIG_VSX | |
2031 | WARN_EMULATED_SETUP(vsx), | |
2032 | #endif | |
efcac658 AK |
2033 | #ifdef CONFIG_PPC64 |
2034 | WARN_EMULATED_SETUP(mfdscr), | |
2035 | WARN_EMULATED_SETUP(mtdscr), | |
f83319d7 | 2036 | WARN_EMULATED_SETUP(lq_stq), |
efcac658 | 2037 | #endif |
80947e7c GU |
2038 | }; |
2039 | ||
2040 | u32 ppc_warn_emulated; | |
2041 | ||
2042 | void ppc_warn_emulated_print(const char *type) | |
2043 | { | |
76462232 CD |
2044 | pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm, |
2045 | type); | |
80947e7c GU |
2046 | } |
2047 | ||
2048 | static int __init ppc_warn_emulated_init(void) | |
2049 | { | |
2050 | struct dentry *dir, *d; | |
2051 | unsigned int i; | |
2052 | struct ppc_emulated_entry *entries = (void *)&ppc_emulated; | |
2053 | ||
2054 | if (!powerpc_debugfs_root) | |
2055 | return -ENODEV; | |
2056 | ||
2057 | dir = debugfs_create_dir("emulated_instructions", | |
2058 | powerpc_debugfs_root); | |
2059 | if (!dir) | |
2060 | return -ENOMEM; | |
2061 | ||
2062 | d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir, | |
2063 | &ppc_warn_emulated); | |
2064 | if (!d) | |
2065 | goto fail; | |
2066 | ||
2067 | for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) { | |
2068 | d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir, | |
2069 | (u32 *)&entries[i].val.counter); | |
2070 | if (!d) | |
2071 | goto fail; | |
2072 | } | |
2073 | ||
2074 | return 0; | |
2075 | ||
2076 | fail: | |
2077 | debugfs_remove_recursive(dir); | |
2078 | return -ENOMEM; | |
2079 | } | |
2080 | ||
2081 | device_initcall(ppc_warn_emulated_init); | |
2082 | ||
2083 | #endif /* CONFIG_PPC_EMULATED_STATS */ |