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14cf11af | 1 | /* |
14cf11af | 2 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) |
fe04b112 | 3 | * Copyright 2007-2010 Freescale Semiconductor, Inc. |
14cf11af PM |
4 | * |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version | |
8 | * 2 of the License, or (at your option) any later version. | |
9 | * | |
10 | * Modified by Cort Dougan (cort@cs.nmt.edu) | |
11 | * and Paul Mackerras (paulus@samba.org) | |
12 | */ | |
13 | ||
14 | /* | |
15 | * This file handles the architecture-dependent parts of hardware exceptions | |
16 | */ | |
17 | ||
14cf11af PM |
18 | #include <linux/errno.h> |
19 | #include <linux/sched.h> | |
b17b0153 | 20 | #include <linux/sched/debug.h> |
14cf11af PM |
21 | #include <linux/kernel.h> |
22 | #include <linux/mm.h> | |
23 | #include <linux/stddef.h> | |
24 | #include <linux/unistd.h> | |
8dad3f92 | 25 | #include <linux/ptrace.h> |
14cf11af | 26 | #include <linux/user.h> |
14cf11af | 27 | #include <linux/interrupt.h> |
14cf11af | 28 | #include <linux/init.h> |
8a39b05f PG |
29 | #include <linux/extable.h> |
30 | #include <linux/module.h> /* print_modules */ | |
8dad3f92 | 31 | #include <linux/prctl.h> |
14cf11af PM |
32 | #include <linux/delay.h> |
33 | #include <linux/kprobes.h> | |
cc532915 | 34 | #include <linux/kexec.h> |
5474c120 | 35 | #include <linux/backlight.h> |
73c9ceab | 36 | #include <linux/bug.h> |
1eeb66a1 | 37 | #include <linux/kdebug.h> |
76462232 | 38 | #include <linux/ratelimit.h> |
ba12eede | 39 | #include <linux/context_tracking.h> |
14cf11af | 40 | |
80947e7c | 41 | #include <asm/emulated_ops.h> |
14cf11af | 42 | #include <asm/pgtable.h> |
7c0f6ba6 | 43 | #include <linux/uaccess.h> |
7644d581 | 44 | #include <asm/debugfs.h> |
14cf11af | 45 | #include <asm/io.h> |
86417780 PM |
46 | #include <asm/machdep.h> |
47 | #include <asm/rtas.h> | |
f7f6f4fe | 48 | #include <asm/pmc.h> |
14cf11af | 49 | #include <asm/reg.h> |
14cf11af PM |
50 | #ifdef CONFIG_PMAC_BACKLIGHT |
51 | #include <asm/backlight.h> | |
52 | #endif | |
dc1c1ca3 | 53 | #ifdef CONFIG_PPC64 |
86417780 | 54 | #include <asm/firmware.h> |
dc1c1ca3 | 55 | #include <asm/processor.h> |
6ce6c629 | 56 | #include <asm/tm.h> |
dc1c1ca3 | 57 | #endif |
c0ce7d08 | 58 | #include <asm/kexec.h> |
16c57b36 | 59 | #include <asm/ppc-opcode.h> |
cce1f106 | 60 | #include <asm/rio.h> |
ebaeb5ae | 61 | #include <asm/fadump.h> |
ae3a197e | 62 | #include <asm/switch_to.h> |
f54db641 | 63 | #include <asm/tm.h> |
ae3a197e | 64 | #include <asm/debug.h> |
42f5b4ca | 65 | #include <asm/asm-prototypes.h> |
fd7bacbc | 66 | #include <asm/hmi.h> |
4e0e3435 | 67 | #include <sysdev/fsl_pci.h> |
6cc89bad | 68 | #include <asm/kprobes.h> |
dc1c1ca3 | 69 | |
da665885 | 70 | #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC_CORE) |
5be3492f AB |
71 | int (*__debugger)(struct pt_regs *regs) __read_mostly; |
72 | int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly; | |
73 | int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly; | |
74 | int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly; | |
75 | int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly; | |
9422de3e | 76 | int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly; |
5be3492f | 77 | int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly; |
14cf11af PM |
78 | |
79 | EXPORT_SYMBOL(__debugger); | |
80 | EXPORT_SYMBOL(__debugger_ipi); | |
81 | EXPORT_SYMBOL(__debugger_bpt); | |
82 | EXPORT_SYMBOL(__debugger_sstep); | |
83 | EXPORT_SYMBOL(__debugger_iabr_match); | |
9422de3e | 84 | EXPORT_SYMBOL(__debugger_break_match); |
14cf11af PM |
85 | EXPORT_SYMBOL(__debugger_fault_handler); |
86 | #endif | |
87 | ||
8b3c34cf MN |
88 | /* Transactional Memory trap debug */ |
89 | #ifdef TM_DEBUG_SW | |
90 | #define TM_DEBUG(x...) printk(KERN_INFO x) | |
91 | #else | |
92 | #define TM_DEBUG(x...) do { } while(0) | |
93 | #endif | |
94 | ||
14cf11af PM |
95 | /* |
96 | * Trap & Exception support | |
97 | */ | |
98 | ||
6031d9d9 | 99 | #ifdef CONFIG_PMAC_BACKLIGHT |
100 | static void pmac_backlight_unblank(void) | |
101 | { | |
102 | mutex_lock(&pmac_backlight_mutex); | |
103 | if (pmac_backlight) { | |
104 | struct backlight_properties *props; | |
105 | ||
106 | props = &pmac_backlight->props; | |
107 | props->brightness = props->max_brightness; | |
108 | props->power = FB_BLANK_UNBLANK; | |
109 | backlight_update_status(pmac_backlight); | |
110 | } | |
111 | mutex_unlock(&pmac_backlight_mutex); | |
112 | } | |
113 | #else | |
114 | static inline void pmac_backlight_unblank(void) { } | |
115 | #endif | |
116 | ||
760ca4dc AB |
117 | static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED; |
118 | static int die_owner = -1; | |
119 | static unsigned int die_nest_count; | |
120 | static int die_counter; | |
121 | ||
03465f89 | 122 | static unsigned long oops_begin(struct pt_regs *regs) |
14cf11af | 123 | { |
760ca4dc | 124 | int cpu; |
34c2a14f | 125 | unsigned long flags; |
14cf11af | 126 | |
293e4688 | 127 | oops_enter(); |
128 | ||
760ca4dc AB |
129 | /* racy, but better than risking deadlock. */ |
130 | raw_local_irq_save(flags); | |
131 | cpu = smp_processor_id(); | |
132 | if (!arch_spin_trylock(&die_lock)) { | |
133 | if (cpu == die_owner) | |
134 | /* nested oops. should stop eventually */; | |
135 | else | |
136 | arch_spin_lock(&die_lock); | |
34c2a14f | 137 | } |
760ca4dc AB |
138 | die_nest_count++; |
139 | die_owner = cpu; | |
140 | console_verbose(); | |
141 | bust_spinlocks(1); | |
142 | if (machine_is(powermac)) | |
143 | pmac_backlight_unblank(); | |
144 | return flags; | |
145 | } | |
03465f89 | 146 | NOKPROBE_SYMBOL(oops_begin); |
e8222502 | 147 | |
03465f89 | 148 | static void oops_end(unsigned long flags, struct pt_regs *regs, |
760ca4dc AB |
149 | int signr) |
150 | { | |
14cf11af | 151 | bust_spinlocks(0); |
373d4d09 | 152 | add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); |
760ca4dc | 153 | die_nest_count--; |
58154c8c AB |
154 | oops_exit(); |
155 | printk("\n"); | |
7458e8b2 | 156 | if (!die_nest_count) { |
760ca4dc | 157 | /* Nest count reaches zero, release the lock. */ |
7458e8b2 | 158 | die_owner = -1; |
760ca4dc | 159 | arch_spin_unlock(&die_lock); |
7458e8b2 | 160 | } |
760ca4dc | 161 | raw_local_irq_restore(flags); |
cc532915 | 162 | |
ebaeb5ae MS |
163 | crash_fadump(regs, "die oops"); |
164 | ||
9b00ac06 AB |
165 | /* |
166 | * A system reset (0x100) is a request to dump, so we always send | |
167 | * it through the crashdump code. | |
168 | */ | |
169 | if (kexec_should_crash(current) || (TRAP(regs) == 0x100)) { | |
cc532915 | 170 | crash_kexec(regs); |
9b00ac06 AB |
171 | |
172 | /* | |
173 | * We aren't the primary crash CPU. We need to send it | |
174 | * to a holding pattern to avoid it ending up in the panic | |
175 | * code. | |
176 | */ | |
177 | crash_kexec_secondary(regs); | |
178 | } | |
14cf11af | 179 | |
760ca4dc AB |
180 | if (!signr) |
181 | return; | |
182 | ||
58154c8c AB |
183 | /* |
184 | * While our oops output is serialised by a spinlock, output | |
185 | * from panic() called below can race and corrupt it. If we | |
186 | * know we are going to panic, delay for 1 second so we have a | |
187 | * chance to get clean backtraces from all CPUs that are oopsing. | |
188 | */ | |
189 | if (in_interrupt() || panic_on_oops || !current->pid || | |
190 | is_global_init(current)) { | |
191 | mdelay(MSEC_PER_SEC); | |
192 | } | |
193 | ||
14cf11af PM |
194 | if (in_interrupt()) |
195 | panic("Fatal exception in interrupt"); | |
cea6a4ba | 196 | if (panic_on_oops) |
012c437d | 197 | panic("Fatal exception"); |
760ca4dc AB |
198 | do_exit(signr); |
199 | } | |
03465f89 | 200 | NOKPROBE_SYMBOL(oops_end); |
cea6a4ba | 201 | |
03465f89 | 202 | static int __die(const char *str, struct pt_regs *regs, long err) |
760ca4dc AB |
203 | { |
204 | printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); | |
205 | #ifdef CONFIG_PREEMPT | |
206 | printk("PREEMPT "); | |
207 | #endif | |
208 | #ifdef CONFIG_SMP | |
209 | printk("SMP NR_CPUS=%d ", NR_CPUS); | |
210 | #endif | |
e7df0d88 JK |
211 | if (debug_pagealloc_enabled()) |
212 | printk("DEBUG_PAGEALLOC "); | |
760ca4dc AB |
213 | #ifdef CONFIG_NUMA |
214 | printk("NUMA "); | |
215 | #endif | |
216 | printk("%s\n", ppc_md.name ? ppc_md.name : ""); | |
217 | ||
218 | if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP) | |
219 | return 1; | |
220 | ||
221 | print_modules(); | |
222 | show_regs(regs); | |
14cf11af PM |
223 | |
224 | return 0; | |
225 | } | |
03465f89 | 226 | NOKPROBE_SYMBOL(__die); |
14cf11af | 227 | |
760ca4dc AB |
228 | void die(const char *str, struct pt_regs *regs, long err) |
229 | { | |
6f44b20e NP |
230 | unsigned long flags; |
231 | ||
232 | if (debugger(regs)) | |
233 | return; | |
760ca4dc | 234 | |
6f44b20e | 235 | flags = oops_begin(regs); |
760ca4dc AB |
236 | if (__die(str, regs, err)) |
237 | err = 0; | |
238 | oops_end(flags, regs, err); | |
239 | } | |
15770a13 | 240 | NOKPROBE_SYMBOL(die); |
760ca4dc | 241 | |
25baa35b ON |
242 | void user_single_step_siginfo(struct task_struct *tsk, |
243 | struct pt_regs *regs, siginfo_t *info) | |
244 | { | |
245 | memset(info, 0, sizeof(*info)); | |
246 | info->si_signo = SIGTRAP; | |
247 | info->si_code = TRAP_TRACE; | |
248 | info->si_addr = (void __user *)regs->nip; | |
249 | } | |
250 | ||
14cf11af PM |
251 | void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) |
252 | { | |
253 | siginfo_t info; | |
d0c3d534 OJ |
254 | const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \ |
255 | "at %08lx nip %08lx lr %08lx code %x\n"; | |
256 | const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \ | |
257 | "at %016lx nip %016lx lr %016lx code %x\n"; | |
14cf11af PM |
258 | |
259 | if (!user_mode(regs)) { | |
760ca4dc AB |
260 | die("Exception in kernel mode", regs, signr); |
261 | return; | |
262 | } | |
263 | ||
264 | if (show_unhandled_signals && unhandled_signal(current, signr)) { | |
76462232 CD |
265 | printk_ratelimited(regs->msr & MSR_64BIT ? fmt64 : fmt32, |
266 | current->comm, current->pid, signr, | |
267 | addr, regs->nip, regs->link, code); | |
268 | } | |
14cf11af | 269 | |
a3512b2d | 270 | if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs)) |
9f2f79e3 BH |
271 | local_irq_enable(); |
272 | ||
41ab5266 | 273 | current->thread.trap_nr = code; |
14cf11af PM |
274 | memset(&info, 0, sizeof(info)); |
275 | info.si_signo = signr; | |
276 | info.si_code = code; | |
277 | info.si_addr = (void __user *) addr; | |
278 | force_sig_info(signr, &info, current); | |
14cf11af PM |
279 | } |
280 | ||
14cf11af PM |
281 | void system_reset_exception(struct pt_regs *regs) |
282 | { | |
2b4f3ac5 NP |
283 | /* |
284 | * Avoid crashes in case of nested NMI exceptions. Recoverability | |
285 | * is determined by RI and in_nmi | |
286 | */ | |
287 | bool nested = in_nmi(); | |
288 | if (!nested) | |
289 | nmi_enter(); | |
290 | ||
14cf11af | 291 | /* See if any machine dependent calls */ |
c902be71 AB |
292 | if (ppc_md.system_reset_exception) { |
293 | if (ppc_md.system_reset_exception(regs)) | |
c4f3b52c | 294 | goto out; |
c902be71 | 295 | } |
14cf11af | 296 | |
8dad3f92 | 297 | die("System Reset", regs, SIGABRT); |
14cf11af | 298 | |
c4f3b52c NP |
299 | out: |
300 | #ifdef CONFIG_PPC_BOOK3S_64 | |
301 | BUG_ON(get_paca()->in_nmi == 0); | |
302 | if (get_paca()->in_nmi > 1) | |
303 | panic("Unrecoverable nested System Reset"); | |
304 | #endif | |
14cf11af PM |
305 | /* Must die if the interrupt is not recoverable */ |
306 | if (!(regs->msr & MSR_RI)) | |
307 | panic("Unrecoverable System Reset"); | |
308 | ||
2b4f3ac5 NP |
309 | if (!nested) |
310 | nmi_exit(); | |
311 | ||
14cf11af PM |
312 | /* What should we do here? We could issue a shutdown or hard reset. */ |
313 | } | |
1e9b4507 | 314 | |
f307939f | 315 | #ifdef CONFIG_PPC64 |
1e9b4507 MS |
316 | /* |
317 | * This function is called in real mode. Strictly no printk's please. | |
318 | * | |
319 | * regs->nip and regs->msr contains srr0 and ssr1. | |
320 | */ | |
321 | long machine_check_early(struct pt_regs *regs) | |
322 | { | |
4c703416 MS |
323 | long handled = 0; |
324 | ||
69111bac | 325 | __this_cpu_inc(irq_stat.mce_exceptions); |
e6654d5b | 326 | |
4c703416 MS |
327 | if (cur_cpu_spec && cur_cpu_spec->machine_check_early) |
328 | handled = cur_cpu_spec->machine_check_early(regs); | |
329 | return handled; | |
1e9b4507 MS |
330 | } |
331 | ||
0869b6fd MS |
332 | long hmi_exception_realmode(struct pt_regs *regs) |
333 | { | |
69111bac | 334 | __this_cpu_inc(irq_stat.hmi_exceptions); |
0869b6fd | 335 | |
fd7bacbc MS |
336 | wait_for_subcore_guest_exit(); |
337 | ||
0869b6fd MS |
338 | if (ppc_md.hmi_exception_early) |
339 | ppc_md.hmi_exception_early(regs); | |
340 | ||
fd7bacbc MS |
341 | wait_for_tb_resync(); |
342 | ||
0869b6fd MS |
343 | return 0; |
344 | } | |
345 | ||
14cf11af PM |
346 | #endif |
347 | ||
348 | /* | |
349 | * I/O accesses can cause machine checks on powermacs. | |
350 | * Check if the NIP corresponds to the address of a sync | |
351 | * instruction for which there is an entry in the exception | |
352 | * table. | |
353 | * Note that the 601 only takes a machine check on TEA | |
354 | * (transfer error ack) signal assertion, and does not | |
355 | * set any of the top 16 bits of SRR1. | |
356 | * -- paulus. | |
357 | */ | |
358 | static inline int check_io_access(struct pt_regs *regs) | |
359 | { | |
68a64357 | 360 | #ifdef CONFIG_PPC32 |
14cf11af PM |
361 | unsigned long msr = regs->msr; |
362 | const struct exception_table_entry *entry; | |
363 | unsigned int *nip = (unsigned int *)regs->nip; | |
364 | ||
365 | if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) | |
366 | && (entry = search_exception_tables(regs->nip)) != NULL) { | |
367 | /* | |
368 | * Check that it's a sync instruction, or somewhere | |
369 | * in the twi; isync; nop sequence that inb/inw/inl uses. | |
370 | * As the address is in the exception table | |
371 | * we should be able to read the instr there. | |
372 | * For the debug message, we look at the preceding | |
373 | * load or store. | |
374 | */ | |
ddc6cd0d | 375 | if (*nip == PPC_INST_NOP) |
14cf11af | 376 | nip -= 2; |
ddc6cd0d | 377 | else if (*nip == PPC_INST_ISYNC) |
14cf11af | 378 | --nip; |
ddc6cd0d | 379 | if (*nip == PPC_INST_SYNC || (*nip >> 26) == OP_TRAP) { |
14cf11af PM |
380 | unsigned int rb; |
381 | ||
382 | --nip; | |
383 | rb = (*nip >> 11) & 0x1f; | |
384 | printk(KERN_DEBUG "%s bad port %lx at %p\n", | |
385 | (*nip & 0x100)? "OUT to": "IN from", | |
386 | regs->gpr[rb] - _IO_BASE, nip); | |
387 | regs->msr |= MSR_RI; | |
61a92f70 | 388 | regs->nip = extable_fixup(entry); |
14cf11af PM |
389 | return 1; |
390 | } | |
391 | } | |
68a64357 | 392 | #endif /* CONFIG_PPC32 */ |
14cf11af PM |
393 | return 0; |
394 | } | |
395 | ||
172ae2e7 | 396 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
14cf11af PM |
397 | /* On 4xx, the reason for the machine check or program exception |
398 | is in the ESR. */ | |
399 | #define get_reason(regs) ((regs)->dsisr) | |
400 | #ifndef CONFIG_FSL_BOOKE | |
401 | #define get_mc_reason(regs) ((regs)->dsisr) | |
402 | #else | |
fe04b112 | 403 | #define get_mc_reason(regs) (mfspr(SPRN_MCSR)) |
14cf11af PM |
404 | #endif |
405 | #define REASON_FP ESR_FP | |
406 | #define REASON_ILLEGAL (ESR_PIL | ESR_PUO) | |
407 | #define REASON_PRIVILEGED ESR_PPR | |
408 | #define REASON_TRAP ESR_PTR | |
409 | ||
410 | /* single-step stuff */ | |
51ae8d4a BB |
411 | #define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC) |
412 | #define clear_single_step(regs) (current->thread.debug.dbcr0 &= ~DBCR0_IC) | |
14cf11af PM |
413 | |
414 | #else | |
415 | /* On non-4xx, the reason for the machine check or program | |
416 | exception is in the MSR. */ | |
417 | #define get_reason(regs) ((regs)->msr) | |
418 | #define get_mc_reason(regs) ((regs)->msr) | |
8b3c34cf | 419 | #define REASON_TM 0x200000 |
14cf11af PM |
420 | #define REASON_FP 0x100000 |
421 | #define REASON_ILLEGAL 0x80000 | |
422 | #define REASON_PRIVILEGED 0x40000 | |
423 | #define REASON_TRAP 0x20000 | |
424 | ||
425 | #define single_stepping(regs) ((regs)->msr & MSR_SE) | |
426 | #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE) | |
427 | #endif | |
428 | ||
47c0bd1a BH |
429 | #if defined(CONFIG_4xx) |
430 | int machine_check_4xx(struct pt_regs *regs) | |
14cf11af | 431 | { |
1a6a4ffe | 432 | unsigned long reason = get_mc_reason(regs); |
14cf11af | 433 | |
14cf11af PM |
434 | if (reason & ESR_IMCP) { |
435 | printk("Instruction"); | |
436 | mtspr(SPRN_ESR, reason & ~ESR_IMCP); | |
437 | } else | |
438 | printk("Data"); | |
439 | printk(" machine check in kernel mode.\n"); | |
47c0bd1a BH |
440 | |
441 | return 0; | |
442 | } | |
443 | ||
444 | int machine_check_440A(struct pt_regs *regs) | |
445 | { | |
446 | unsigned long reason = get_mc_reason(regs); | |
447 | ||
14cf11af PM |
448 | printk("Machine check in kernel mode.\n"); |
449 | if (reason & ESR_IMCP){ | |
450 | printk("Instruction Synchronous Machine Check exception\n"); | |
451 | mtspr(SPRN_ESR, reason & ~ESR_IMCP); | |
452 | } | |
453 | else { | |
454 | u32 mcsr = mfspr(SPRN_MCSR); | |
455 | if (mcsr & MCSR_IB) | |
456 | printk("Instruction Read PLB Error\n"); | |
457 | if (mcsr & MCSR_DRB) | |
458 | printk("Data Read PLB Error\n"); | |
459 | if (mcsr & MCSR_DWB) | |
460 | printk("Data Write PLB Error\n"); | |
461 | if (mcsr & MCSR_TLBP) | |
462 | printk("TLB Parity Error\n"); | |
463 | if (mcsr & MCSR_ICP){ | |
464 | flush_instruction_cache(); | |
465 | printk("I-Cache Parity Error\n"); | |
466 | } | |
467 | if (mcsr & MCSR_DCSP) | |
468 | printk("D-Cache Search Parity Error\n"); | |
469 | if (mcsr & MCSR_DCFP) | |
470 | printk("D-Cache Flush Parity Error\n"); | |
471 | if (mcsr & MCSR_IMPE) | |
472 | printk("Machine Check exception is imprecise\n"); | |
473 | ||
474 | /* Clear MCSR */ | |
475 | mtspr(SPRN_MCSR, mcsr); | |
476 | } | |
47c0bd1a BH |
477 | return 0; |
478 | } | |
fc5e7097 DK |
479 | |
480 | int machine_check_47x(struct pt_regs *regs) | |
481 | { | |
482 | unsigned long reason = get_mc_reason(regs); | |
483 | u32 mcsr; | |
484 | ||
485 | printk(KERN_ERR "Machine check in kernel mode.\n"); | |
486 | if (reason & ESR_IMCP) { | |
487 | printk(KERN_ERR | |
488 | "Instruction Synchronous Machine Check exception\n"); | |
489 | mtspr(SPRN_ESR, reason & ~ESR_IMCP); | |
490 | return 0; | |
491 | } | |
492 | mcsr = mfspr(SPRN_MCSR); | |
493 | if (mcsr & MCSR_IB) | |
494 | printk(KERN_ERR "Instruction Read PLB Error\n"); | |
495 | if (mcsr & MCSR_DRB) | |
496 | printk(KERN_ERR "Data Read PLB Error\n"); | |
497 | if (mcsr & MCSR_DWB) | |
498 | printk(KERN_ERR "Data Write PLB Error\n"); | |
499 | if (mcsr & MCSR_TLBP) | |
500 | printk(KERN_ERR "TLB Parity Error\n"); | |
501 | if (mcsr & MCSR_ICP) { | |
502 | flush_instruction_cache(); | |
503 | printk(KERN_ERR "I-Cache Parity Error\n"); | |
504 | } | |
505 | if (mcsr & MCSR_DCSP) | |
506 | printk(KERN_ERR "D-Cache Search Parity Error\n"); | |
507 | if (mcsr & PPC47x_MCSR_GPR) | |
508 | printk(KERN_ERR "GPR Parity Error\n"); | |
509 | if (mcsr & PPC47x_MCSR_FPR) | |
510 | printk(KERN_ERR "FPR Parity Error\n"); | |
511 | if (mcsr & PPC47x_MCSR_IPR) | |
512 | printk(KERN_ERR "Machine Check exception is imprecise\n"); | |
513 | ||
514 | /* Clear MCSR */ | |
515 | mtspr(SPRN_MCSR, mcsr); | |
516 | ||
517 | return 0; | |
518 | } | |
47c0bd1a | 519 | #elif defined(CONFIG_E500) |
fe04b112 SW |
520 | int machine_check_e500mc(struct pt_regs *regs) |
521 | { | |
522 | unsigned long mcsr = mfspr(SPRN_MCSR); | |
523 | unsigned long reason = mcsr; | |
524 | int recoverable = 1; | |
525 | ||
82a9a480 | 526 | if (reason & MCSR_LD) { |
cce1f106 SX |
527 | recoverable = fsl_rio_mcheck_exception(regs); |
528 | if (recoverable == 1) | |
529 | goto silent_out; | |
530 | } | |
531 | ||
fe04b112 SW |
532 | printk("Machine check in kernel mode.\n"); |
533 | printk("Caused by (from MCSR=%lx): ", reason); | |
534 | ||
535 | if (reason & MCSR_MCP) | |
536 | printk("Machine Check Signal\n"); | |
537 | ||
538 | if (reason & MCSR_ICPERR) { | |
539 | printk("Instruction Cache Parity Error\n"); | |
540 | ||
541 | /* | |
542 | * This is recoverable by invalidating the i-cache. | |
543 | */ | |
544 | mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI); | |
545 | while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI) | |
546 | ; | |
547 | ||
548 | /* | |
549 | * This will generally be accompanied by an instruction | |
550 | * fetch error report -- only treat MCSR_IF as fatal | |
551 | * if it wasn't due to an L1 parity error. | |
552 | */ | |
553 | reason &= ~MCSR_IF; | |
554 | } | |
555 | ||
556 | if (reason & MCSR_DCPERR_MC) { | |
557 | printk("Data Cache Parity Error\n"); | |
37caf9f2 KG |
558 | |
559 | /* | |
560 | * In write shadow mode we auto-recover from the error, but it | |
561 | * may still get logged and cause a machine check. We should | |
562 | * only treat the non-write shadow case as non-recoverable. | |
563 | */ | |
564 | if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS)) | |
565 | recoverable = 0; | |
fe04b112 SW |
566 | } |
567 | ||
568 | if (reason & MCSR_L2MMU_MHIT) { | |
569 | printk("Hit on multiple TLB entries\n"); | |
570 | recoverable = 0; | |
571 | } | |
572 | ||
573 | if (reason & MCSR_NMI) | |
574 | printk("Non-maskable interrupt\n"); | |
575 | ||
576 | if (reason & MCSR_IF) { | |
577 | printk("Instruction Fetch Error Report\n"); | |
578 | recoverable = 0; | |
579 | } | |
580 | ||
581 | if (reason & MCSR_LD) { | |
582 | printk("Load Error Report\n"); | |
583 | recoverable = 0; | |
584 | } | |
585 | ||
586 | if (reason & MCSR_ST) { | |
587 | printk("Store Error Report\n"); | |
588 | recoverable = 0; | |
589 | } | |
590 | ||
591 | if (reason & MCSR_LDG) { | |
592 | printk("Guarded Load Error Report\n"); | |
593 | recoverable = 0; | |
594 | } | |
595 | ||
596 | if (reason & MCSR_TLBSYNC) | |
597 | printk("Simultaneous tlbsync operations\n"); | |
598 | ||
599 | if (reason & MCSR_BSL2_ERR) { | |
600 | printk("Level 2 Cache Error\n"); | |
601 | recoverable = 0; | |
602 | } | |
603 | ||
604 | if (reason & MCSR_MAV) { | |
605 | u64 addr; | |
606 | ||
607 | addr = mfspr(SPRN_MCAR); | |
608 | addr |= (u64)mfspr(SPRN_MCARU) << 32; | |
609 | ||
610 | printk("Machine Check %s Address: %#llx\n", | |
611 | reason & MCSR_MEA ? "Effective" : "Physical", addr); | |
612 | } | |
613 | ||
cce1f106 | 614 | silent_out: |
fe04b112 SW |
615 | mtspr(SPRN_MCSR, mcsr); |
616 | return mfspr(SPRN_MCSR) == 0 && recoverable; | |
617 | } | |
618 | ||
47c0bd1a BH |
619 | int machine_check_e500(struct pt_regs *regs) |
620 | { | |
621 | unsigned long reason = get_mc_reason(regs); | |
622 | ||
cce1f106 SX |
623 | if (reason & MCSR_BUS_RBERR) { |
624 | if (fsl_rio_mcheck_exception(regs)) | |
625 | return 1; | |
4e0e3435 HJ |
626 | if (fsl_pci_mcheck_exception(regs)) |
627 | return 1; | |
cce1f106 SX |
628 | } |
629 | ||
14cf11af PM |
630 | printk("Machine check in kernel mode.\n"); |
631 | printk("Caused by (from MCSR=%lx): ", reason); | |
632 | ||
633 | if (reason & MCSR_MCP) | |
634 | printk("Machine Check Signal\n"); | |
635 | if (reason & MCSR_ICPERR) | |
636 | printk("Instruction Cache Parity Error\n"); | |
637 | if (reason & MCSR_DCP_PERR) | |
638 | printk("Data Cache Push Parity Error\n"); | |
639 | if (reason & MCSR_DCPERR) | |
640 | printk("Data Cache Parity Error\n"); | |
14cf11af PM |
641 | if (reason & MCSR_BUS_IAERR) |
642 | printk("Bus - Instruction Address Error\n"); | |
643 | if (reason & MCSR_BUS_RAERR) | |
644 | printk("Bus - Read Address Error\n"); | |
645 | if (reason & MCSR_BUS_WAERR) | |
646 | printk("Bus - Write Address Error\n"); | |
647 | if (reason & MCSR_BUS_IBERR) | |
648 | printk("Bus - Instruction Data Error\n"); | |
649 | if (reason & MCSR_BUS_RBERR) | |
650 | printk("Bus - Read Data Bus Error\n"); | |
651 | if (reason & MCSR_BUS_WBERR) | |
c1528339 | 652 | printk("Bus - Write Data Bus Error\n"); |
14cf11af PM |
653 | if (reason & MCSR_BUS_IPERR) |
654 | printk("Bus - Instruction Parity Error\n"); | |
655 | if (reason & MCSR_BUS_RPERR) | |
656 | printk("Bus - Read Parity Error\n"); | |
47c0bd1a BH |
657 | |
658 | return 0; | |
659 | } | |
4490c06b KG |
660 | |
661 | int machine_check_generic(struct pt_regs *regs) | |
662 | { | |
663 | return 0; | |
664 | } | |
47c0bd1a BH |
665 | #elif defined(CONFIG_E200) |
666 | int machine_check_e200(struct pt_regs *regs) | |
667 | { | |
668 | unsigned long reason = get_mc_reason(regs); | |
669 | ||
14cf11af PM |
670 | printk("Machine check in kernel mode.\n"); |
671 | printk("Caused by (from MCSR=%lx): ", reason); | |
672 | ||
673 | if (reason & MCSR_MCP) | |
674 | printk("Machine Check Signal\n"); | |
675 | if (reason & MCSR_CP_PERR) | |
676 | printk("Cache Push Parity Error\n"); | |
677 | if (reason & MCSR_CPERR) | |
678 | printk("Cache Parity Error\n"); | |
679 | if (reason & MCSR_EXCP_ERR) | |
680 | printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n"); | |
681 | if (reason & MCSR_BUS_IRERR) | |
682 | printk("Bus - Read Bus Error on instruction fetch\n"); | |
683 | if (reason & MCSR_BUS_DRERR) | |
684 | printk("Bus - Read Bus Error on data load\n"); | |
685 | if (reason & MCSR_BUS_WRERR) | |
686 | printk("Bus - Write Bus Error on buffered store or cache line push\n"); | |
47c0bd1a BH |
687 | |
688 | return 0; | |
689 | } | |
e627f8dc CL |
690 | #elif defined(CONFIG_PPC_8xx) |
691 | int machine_check_8xx(struct pt_regs *regs) | |
692 | { | |
693 | unsigned long reason = get_mc_reason(regs); | |
694 | ||
695 | pr_err("Machine check in kernel mode.\n"); | |
696 | pr_err("Caused by (from SRR1=%lx): ", reason); | |
697 | if (reason & 0x40000000) | |
698 | pr_err("Fetch error at address %lx\n", regs->nip); | |
699 | else | |
700 | pr_err("Data access error at address %lx\n", regs->dar); | |
701 | ||
702 | #ifdef CONFIG_PCI | |
703 | /* the qspan pci read routines can cause machine checks -- Cort | |
704 | * | |
705 | * yuck !!! that totally needs to go away ! There are better ways | |
706 | * to deal with that than having a wart in the mcheck handler. | |
707 | * -- BenH | |
708 | */ | |
709 | bad_page_fault(regs, regs->dar, SIGBUS); | |
710 | return 1; | |
711 | #else | |
712 | return 0; | |
713 | #endif | |
714 | } | |
47c0bd1a BH |
715 | #else |
716 | int machine_check_generic(struct pt_regs *regs) | |
717 | { | |
718 | unsigned long reason = get_mc_reason(regs); | |
719 | ||
14cf11af PM |
720 | printk("Machine check in kernel mode.\n"); |
721 | printk("Caused by (from SRR1=%lx): ", reason); | |
722 | switch (reason & 0x601F0000) { | |
723 | case 0x80000: | |
724 | printk("Machine check signal\n"); | |
725 | break; | |
726 | case 0: /* for 601 */ | |
727 | case 0x40000: | |
728 | case 0x140000: /* 7450 MSS error and TEA */ | |
729 | printk("Transfer error ack signal\n"); | |
730 | break; | |
731 | case 0x20000: | |
732 | printk("Data parity error signal\n"); | |
733 | break; | |
734 | case 0x10000: | |
735 | printk("Address parity error signal\n"); | |
736 | break; | |
737 | case 0x20000000: | |
738 | printk("L1 Data Cache error\n"); | |
739 | break; | |
740 | case 0x40000000: | |
741 | printk("L1 Instruction Cache error\n"); | |
742 | break; | |
743 | case 0x00100000: | |
744 | printk("L2 data cache parity error\n"); | |
745 | break; | |
746 | default: | |
747 | printk("Unknown values in msr\n"); | |
748 | } | |
75918a4b OJ |
749 | return 0; |
750 | } | |
47c0bd1a | 751 | #endif /* everything else */ |
75918a4b OJ |
752 | |
753 | void machine_check_exception(struct pt_regs *regs) | |
754 | { | |
ba12eede | 755 | enum ctx_state prev_state = exception_enter(); |
75918a4b OJ |
756 | int recover = 0; |
757 | ||
69111bac | 758 | __this_cpu_inc(irq_stat.mce_exceptions); |
89713ed1 | 759 | |
d93b0ac0 MS |
760 | add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE); |
761 | ||
47c0bd1a BH |
762 | /* See if any machine dependent calls. In theory, we would want |
763 | * to call the CPU first, and call the ppc_md. one if the CPU | |
764 | * one returns a positive number. However there is existing code | |
765 | * that assumes the board gets a first chance, so let's keep it | |
766 | * that way for now and fix things later. --BenH. | |
767 | */ | |
75918a4b OJ |
768 | if (ppc_md.machine_check_exception) |
769 | recover = ppc_md.machine_check_exception(regs); | |
47c0bd1a BH |
770 | else if (cur_cpu_spec->machine_check) |
771 | recover = cur_cpu_spec->machine_check(regs); | |
75918a4b | 772 | |
47c0bd1a | 773 | if (recover > 0) |
ba12eede | 774 | goto bail; |
75918a4b | 775 | |
a443506b | 776 | if (debugger_fault_handler(regs)) |
ba12eede | 777 | goto bail; |
75918a4b OJ |
778 | |
779 | if (check_io_access(regs)) | |
ba12eede | 780 | goto bail; |
75918a4b | 781 | |
8dad3f92 | 782 | die("Machine check", regs, SIGBUS); |
14cf11af PM |
783 | |
784 | /* Must die if the interrupt is not recoverable */ | |
785 | if (!(regs->msr & MSR_RI)) | |
786 | panic("Unrecoverable Machine check"); | |
ba12eede LZ |
787 | |
788 | bail: | |
789 | exception_exit(prev_state); | |
14cf11af PM |
790 | } |
791 | ||
792 | void SMIException(struct pt_regs *regs) | |
793 | { | |
794 | die("System Management Interrupt", regs, SIGABRT); | |
795 | } | |
796 | ||
0869b6fd MS |
797 | void handle_hmi_exception(struct pt_regs *regs) |
798 | { | |
799 | struct pt_regs *old_regs; | |
800 | ||
801 | old_regs = set_irq_regs(regs); | |
802 | irq_enter(); | |
803 | ||
804 | if (ppc_md.handle_hmi_exception) | |
805 | ppc_md.handle_hmi_exception(regs); | |
806 | ||
807 | irq_exit(); | |
808 | set_irq_regs(old_regs); | |
809 | } | |
810 | ||
dc1c1ca3 | 811 | void unknown_exception(struct pt_regs *regs) |
14cf11af | 812 | { |
ba12eede LZ |
813 | enum ctx_state prev_state = exception_enter(); |
814 | ||
14cf11af PM |
815 | printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", |
816 | regs->nip, regs->msr, regs->trap); | |
817 | ||
818 | _exception(SIGTRAP, regs, 0, 0); | |
ba12eede LZ |
819 | |
820 | exception_exit(prev_state); | |
14cf11af PM |
821 | } |
822 | ||
dc1c1ca3 | 823 | void instruction_breakpoint_exception(struct pt_regs *regs) |
14cf11af | 824 | { |
ba12eede LZ |
825 | enum ctx_state prev_state = exception_enter(); |
826 | ||
14cf11af PM |
827 | if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5, |
828 | 5, SIGTRAP) == NOTIFY_STOP) | |
ba12eede | 829 | goto bail; |
14cf11af | 830 | if (debugger_iabr_match(regs)) |
ba12eede | 831 | goto bail; |
14cf11af | 832 | _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); |
ba12eede LZ |
833 | |
834 | bail: | |
835 | exception_exit(prev_state); | |
14cf11af PM |
836 | } |
837 | ||
838 | void RunModeException(struct pt_regs *regs) | |
839 | { | |
840 | _exception(SIGTRAP, regs, 0, 0); | |
841 | } | |
842 | ||
03465f89 | 843 | void single_step_exception(struct pt_regs *regs) |
14cf11af | 844 | { |
ba12eede LZ |
845 | enum ctx_state prev_state = exception_enter(); |
846 | ||
2538c2d0 | 847 | clear_single_step(regs); |
14cf11af | 848 | |
6cc89bad NR |
849 | if (kprobe_post_handler(regs)) |
850 | return; | |
851 | ||
14cf11af PM |
852 | if (notify_die(DIE_SSTEP, "single_step", regs, 5, |
853 | 5, SIGTRAP) == NOTIFY_STOP) | |
ba12eede | 854 | goto bail; |
14cf11af | 855 | if (debugger_sstep(regs)) |
ba12eede | 856 | goto bail; |
14cf11af PM |
857 | |
858 | _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); | |
ba12eede LZ |
859 | |
860 | bail: | |
861 | exception_exit(prev_state); | |
14cf11af | 862 | } |
03465f89 | 863 | NOKPROBE_SYMBOL(single_step_exception); |
14cf11af PM |
864 | |
865 | /* | |
866 | * After we have successfully emulated an instruction, we have to | |
867 | * check if the instruction was being single-stepped, and if so, | |
868 | * pretend we got a single-step exception. This was pointed out | |
869 | * by Kumar Gala. -- paulus | |
870 | */ | |
8dad3f92 | 871 | static void emulate_single_step(struct pt_regs *regs) |
14cf11af | 872 | { |
2538c2d0 P |
873 | if (single_stepping(regs)) |
874 | single_step_exception(regs); | |
14cf11af PM |
875 | } |
876 | ||
5fad293b | 877 | static inline int __parse_fpscr(unsigned long fpscr) |
dc1c1ca3 | 878 | { |
5fad293b | 879 | int ret = 0; |
dc1c1ca3 SR |
880 | |
881 | /* Invalid operation */ | |
882 | if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX)) | |
5fad293b | 883 | ret = FPE_FLTINV; |
dc1c1ca3 SR |
884 | |
885 | /* Overflow */ | |
886 | else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX)) | |
5fad293b | 887 | ret = FPE_FLTOVF; |
dc1c1ca3 SR |
888 | |
889 | /* Underflow */ | |
890 | else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX)) | |
5fad293b | 891 | ret = FPE_FLTUND; |
dc1c1ca3 SR |
892 | |
893 | /* Divide by zero */ | |
894 | else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX)) | |
5fad293b | 895 | ret = FPE_FLTDIV; |
dc1c1ca3 SR |
896 | |
897 | /* Inexact result */ | |
898 | else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX)) | |
5fad293b KG |
899 | ret = FPE_FLTRES; |
900 | ||
901 | return ret; | |
902 | } | |
903 | ||
904 | static void parse_fpe(struct pt_regs *regs) | |
905 | { | |
906 | int code = 0; | |
907 | ||
908 | flush_fp_to_thread(current); | |
909 | ||
de79f7b9 | 910 | code = __parse_fpscr(current->thread.fp_state.fpscr); |
dc1c1ca3 SR |
911 | |
912 | _exception(SIGFPE, regs, code, regs->nip); | |
913 | } | |
914 | ||
915 | /* | |
916 | * Illegal instruction emulation support. Originally written to | |
14cf11af PM |
917 | * provide the PVR to user applications using the mfspr rd, PVR. |
918 | * Return non-zero if we can't emulate, or -EFAULT if the associated | |
919 | * memory access caused an access fault. Return zero on success. | |
920 | * | |
921 | * There are a couple of ways to do this, either "decode" the instruction | |
922 | * or directly match lots of bits. In this case, matching lots of | |
923 | * bits is faster and easier. | |
86417780 | 924 | * |
14cf11af | 925 | */ |
14cf11af PM |
926 | static int emulate_string_inst(struct pt_regs *regs, u32 instword) |
927 | { | |
928 | u8 rT = (instword >> 21) & 0x1f; | |
929 | u8 rA = (instword >> 16) & 0x1f; | |
930 | u8 NB_RB = (instword >> 11) & 0x1f; | |
931 | u32 num_bytes; | |
932 | unsigned long EA; | |
933 | int pos = 0; | |
934 | ||
935 | /* Early out if we are an invalid form of lswx */ | |
16c57b36 | 936 | if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX) |
14cf11af PM |
937 | if ((rT == rA) || (rT == NB_RB)) |
938 | return -EINVAL; | |
939 | ||
940 | EA = (rA == 0) ? 0 : regs->gpr[rA]; | |
941 | ||
16c57b36 KG |
942 | switch (instword & PPC_INST_STRING_MASK) { |
943 | case PPC_INST_LSWX: | |
944 | case PPC_INST_STSWX: | |
14cf11af PM |
945 | EA += NB_RB; |
946 | num_bytes = regs->xer & 0x7f; | |
947 | break; | |
16c57b36 KG |
948 | case PPC_INST_LSWI: |
949 | case PPC_INST_STSWI: | |
14cf11af PM |
950 | num_bytes = (NB_RB == 0) ? 32 : NB_RB; |
951 | break; | |
952 | default: | |
953 | return -EINVAL; | |
954 | } | |
955 | ||
956 | while (num_bytes != 0) | |
957 | { | |
958 | u8 val; | |
959 | u32 shift = 8 * (3 - (pos & 0x3)); | |
960 | ||
80aa0fb4 JY |
961 | /* if process is 32-bit, clear upper 32 bits of EA */ |
962 | if ((regs->msr & MSR_64BIT) == 0) | |
963 | EA &= 0xFFFFFFFF; | |
964 | ||
16c57b36 KG |
965 | switch ((instword & PPC_INST_STRING_MASK)) { |
966 | case PPC_INST_LSWX: | |
967 | case PPC_INST_LSWI: | |
14cf11af PM |
968 | if (get_user(val, (u8 __user *)EA)) |
969 | return -EFAULT; | |
970 | /* first time updating this reg, | |
971 | * zero it out */ | |
972 | if (pos == 0) | |
973 | regs->gpr[rT] = 0; | |
974 | regs->gpr[rT] |= val << shift; | |
975 | break; | |
16c57b36 KG |
976 | case PPC_INST_STSWI: |
977 | case PPC_INST_STSWX: | |
14cf11af PM |
978 | val = regs->gpr[rT] >> shift; |
979 | if (put_user(val, (u8 __user *)EA)) | |
980 | return -EFAULT; | |
981 | break; | |
982 | } | |
983 | /* move EA to next address */ | |
984 | EA += 1; | |
985 | num_bytes--; | |
986 | ||
987 | /* manage our position within the register */ | |
988 | if (++pos == 4) { | |
989 | pos = 0; | |
990 | if (++rT == 32) | |
991 | rT = 0; | |
992 | } | |
993 | } | |
994 | ||
995 | return 0; | |
996 | } | |
997 | ||
c3412dcb WS |
998 | static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword) |
999 | { | |
1000 | u32 ra,rs; | |
1001 | unsigned long tmp; | |
1002 | ||
1003 | ra = (instword >> 16) & 0x1f; | |
1004 | rs = (instword >> 21) & 0x1f; | |
1005 | ||
1006 | tmp = regs->gpr[rs]; | |
1007 | tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL); | |
1008 | tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL); | |
1009 | tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL; | |
1010 | regs->gpr[ra] = tmp; | |
1011 | ||
1012 | return 0; | |
1013 | } | |
1014 | ||
c1469f13 KG |
1015 | static int emulate_isel(struct pt_regs *regs, u32 instword) |
1016 | { | |
1017 | u8 rT = (instword >> 21) & 0x1f; | |
1018 | u8 rA = (instword >> 16) & 0x1f; | |
1019 | u8 rB = (instword >> 11) & 0x1f; | |
1020 | u8 BC = (instword >> 6) & 0x1f; | |
1021 | u8 bit; | |
1022 | unsigned long tmp; | |
1023 | ||
1024 | tmp = (rA == 0) ? 0 : regs->gpr[rA]; | |
1025 | bit = (regs->ccr >> (31 - BC)) & 0x1; | |
1026 | ||
1027 | regs->gpr[rT] = bit ? tmp : regs->gpr[rB]; | |
1028 | ||
1029 | return 0; | |
1030 | } | |
1031 | ||
6ce6c629 MN |
1032 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1033 | static inline bool tm_abort_check(struct pt_regs *regs, int cause) | |
1034 | { | |
1035 | /* If we're emulating a load/store in an active transaction, we cannot | |
1036 | * emulate it as the kernel operates in transaction suspended context. | |
1037 | * We need to abort the transaction. This creates a persistent TM | |
1038 | * abort so tell the user what caused it with a new code. | |
1039 | */ | |
1040 | if (MSR_TM_TRANSACTIONAL(regs->msr)) { | |
1041 | tm_enable(); | |
1042 | tm_abort(cause); | |
1043 | return true; | |
1044 | } | |
1045 | return false; | |
1046 | } | |
1047 | #else | |
1048 | static inline bool tm_abort_check(struct pt_regs *regs, int reason) | |
1049 | { | |
1050 | return false; | |
1051 | } | |
1052 | #endif | |
1053 | ||
14cf11af PM |
1054 | static int emulate_instruction(struct pt_regs *regs) |
1055 | { | |
1056 | u32 instword; | |
1057 | u32 rd; | |
1058 | ||
4288e343 | 1059 | if (!user_mode(regs)) |
14cf11af PM |
1060 | return -EINVAL; |
1061 | CHECK_FULL_REGS(regs); | |
1062 | ||
1063 | if (get_user(instword, (u32 __user *)(regs->nip))) | |
1064 | return -EFAULT; | |
1065 | ||
1066 | /* Emulate the mfspr rD, PVR. */ | |
16c57b36 | 1067 | if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) { |
eecff81d | 1068 | PPC_WARN_EMULATED(mfpvr, regs); |
14cf11af PM |
1069 | rd = (instword >> 21) & 0x1f; |
1070 | regs->gpr[rd] = mfspr(SPRN_PVR); | |
1071 | return 0; | |
1072 | } | |
1073 | ||
1074 | /* Emulating the dcba insn is just a no-op. */ | |
80947e7c | 1075 | if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) { |
eecff81d | 1076 | PPC_WARN_EMULATED(dcba, regs); |
14cf11af | 1077 | return 0; |
80947e7c | 1078 | } |
14cf11af PM |
1079 | |
1080 | /* Emulate the mcrxr insn. */ | |
16c57b36 | 1081 | if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) { |
86417780 | 1082 | int shift = (instword >> 21) & 0x1c; |
14cf11af PM |
1083 | unsigned long msk = 0xf0000000UL >> shift; |
1084 | ||
eecff81d | 1085 | PPC_WARN_EMULATED(mcrxr, regs); |
14cf11af PM |
1086 | regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); |
1087 | regs->xer &= ~0xf0000000UL; | |
1088 | return 0; | |
1089 | } | |
1090 | ||
1091 | /* Emulate load/store string insn. */ | |
80947e7c | 1092 | if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) { |
6ce6c629 MN |
1093 | if (tm_abort_check(regs, |
1094 | TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT)) | |
1095 | return -EINVAL; | |
eecff81d | 1096 | PPC_WARN_EMULATED(string, regs); |
14cf11af | 1097 | return emulate_string_inst(regs, instword); |
80947e7c | 1098 | } |
14cf11af | 1099 | |
c3412dcb | 1100 | /* Emulate the popcntb (Population Count Bytes) instruction. */ |
16c57b36 | 1101 | if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) { |
eecff81d | 1102 | PPC_WARN_EMULATED(popcntb, regs); |
c3412dcb WS |
1103 | return emulate_popcntb_inst(regs, instword); |
1104 | } | |
1105 | ||
c1469f13 | 1106 | /* Emulate isel (Integer Select) instruction */ |
16c57b36 | 1107 | if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) { |
eecff81d | 1108 | PPC_WARN_EMULATED(isel, regs); |
c1469f13 KG |
1109 | return emulate_isel(regs, instword); |
1110 | } | |
1111 | ||
9863c28a JY |
1112 | /* Emulate sync instruction variants */ |
1113 | if ((instword & PPC_INST_SYNC_MASK) == PPC_INST_SYNC) { | |
1114 | PPC_WARN_EMULATED(sync, regs); | |
1115 | asm volatile("sync"); | |
1116 | return 0; | |
1117 | } | |
1118 | ||
efcac658 AK |
1119 | #ifdef CONFIG_PPC64 |
1120 | /* Emulate the mfspr rD, DSCR. */ | |
73d2fb75 AB |
1121 | if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) == |
1122 | PPC_INST_MFSPR_DSCR_USER) || | |
1123 | ((instword & PPC_INST_MFSPR_DSCR_MASK) == | |
1124 | PPC_INST_MFSPR_DSCR)) && | |
efcac658 AK |
1125 | cpu_has_feature(CPU_FTR_DSCR)) { |
1126 | PPC_WARN_EMULATED(mfdscr, regs); | |
1127 | rd = (instword >> 21) & 0x1f; | |
1128 | regs->gpr[rd] = mfspr(SPRN_DSCR); | |
1129 | return 0; | |
1130 | } | |
1131 | /* Emulate the mtspr DSCR, rD. */ | |
73d2fb75 AB |
1132 | if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) == |
1133 | PPC_INST_MTSPR_DSCR_USER) || | |
1134 | ((instword & PPC_INST_MTSPR_DSCR_MASK) == | |
1135 | PPC_INST_MTSPR_DSCR)) && | |
efcac658 AK |
1136 | cpu_has_feature(CPU_FTR_DSCR)) { |
1137 | PPC_WARN_EMULATED(mtdscr, regs); | |
1138 | rd = (instword >> 21) & 0x1f; | |
00ca0de0 | 1139 | current->thread.dscr = regs->gpr[rd]; |
efcac658 | 1140 | current->thread.dscr_inherit = 1; |
00ca0de0 | 1141 | mtspr(SPRN_DSCR, current->thread.dscr); |
efcac658 AK |
1142 | return 0; |
1143 | } | |
1144 | #endif | |
1145 | ||
14cf11af PM |
1146 | return -EINVAL; |
1147 | } | |
1148 | ||
73c9ceab | 1149 | int is_valid_bugaddr(unsigned long addr) |
14cf11af | 1150 | { |
73c9ceab | 1151 | return is_kernel_addr(addr); |
14cf11af PM |
1152 | } |
1153 | ||
3a3b5aa6 KH |
1154 | #ifdef CONFIG_MATH_EMULATION |
1155 | static int emulate_math(struct pt_regs *regs) | |
1156 | { | |
1157 | int ret; | |
1158 | extern int do_mathemu(struct pt_regs *regs); | |
1159 | ||
1160 | ret = do_mathemu(regs); | |
1161 | if (ret >= 0) | |
1162 | PPC_WARN_EMULATED(math, regs); | |
1163 | ||
1164 | switch (ret) { | |
1165 | case 0: | |
1166 | emulate_single_step(regs); | |
1167 | return 0; | |
1168 | case 1: { | |
1169 | int code = 0; | |
de79f7b9 | 1170 | code = __parse_fpscr(current->thread.fp_state.fpscr); |
3a3b5aa6 KH |
1171 | _exception(SIGFPE, regs, code, regs->nip); |
1172 | return 0; | |
1173 | } | |
1174 | case -EFAULT: | |
1175 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
1176 | return 0; | |
1177 | } | |
1178 | ||
1179 | return -1; | |
1180 | } | |
1181 | #else | |
1182 | static inline int emulate_math(struct pt_regs *regs) { return -1; } | |
1183 | #endif | |
1184 | ||
03465f89 | 1185 | void program_check_exception(struct pt_regs *regs) |
14cf11af | 1186 | { |
ba12eede | 1187 | enum ctx_state prev_state = exception_enter(); |
14cf11af | 1188 | unsigned int reason = get_reason(regs); |
14cf11af | 1189 | |
aa42c69c | 1190 | /* We can now get here via a FP Unavailable exception if the core |
04903a30 | 1191 | * has no FPU, in that case the reason flags will be 0 */ |
14cf11af | 1192 | |
dc1c1ca3 SR |
1193 | if (reason & REASON_FP) { |
1194 | /* IEEE FP exception */ | |
1195 | parse_fpe(regs); | |
ba12eede | 1196 | goto bail; |
8dad3f92 PM |
1197 | } |
1198 | if (reason & REASON_TRAP) { | |
a4c3f909 | 1199 | unsigned long bugaddr; |
ba797b28 JW |
1200 | /* Debugger is first in line to stop recursive faults in |
1201 | * rcu_lock, notify_die, or atomic_notifier_call_chain */ | |
1202 | if (debugger_bpt(regs)) | |
ba12eede | 1203 | goto bail; |
ba797b28 | 1204 | |
6cc89bad NR |
1205 | if (kprobe_handler(regs)) |
1206 | goto bail; | |
1207 | ||
14cf11af | 1208 | /* trap exception */ |
dc1c1ca3 SR |
1209 | if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP) |
1210 | == NOTIFY_STOP) | |
ba12eede | 1211 | goto bail; |
73c9ceab | 1212 | |
a4c3f909 BS |
1213 | bugaddr = regs->nip; |
1214 | /* | |
1215 | * Fixup bugaddr for BUG_ON() in real mode | |
1216 | */ | |
1217 | if (!is_kernel_addr(bugaddr) && !(regs->msr & MSR_IR)) | |
1218 | bugaddr += PAGE_OFFSET; | |
1219 | ||
73c9ceab | 1220 | if (!(regs->msr & MSR_PR) && /* not user-mode */ |
a4c3f909 | 1221 | report_bug(bugaddr, regs) == BUG_TRAP_TYPE_WARN) { |
14cf11af | 1222 | regs->nip += 4; |
ba12eede | 1223 | goto bail; |
14cf11af | 1224 | } |
8dad3f92 | 1225 | _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); |
ba12eede | 1226 | goto bail; |
8dad3f92 | 1227 | } |
bc2a9408 MN |
1228 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1229 | if (reason & REASON_TM) { | |
1230 | /* This is a TM "Bad Thing Exception" program check. | |
1231 | * This occurs when: | |
1232 | * - An rfid/hrfid/mtmsrd attempts to cause an illegal | |
1233 | * transition in TM states. | |
1234 | * - A trechkpt is attempted when transactional. | |
1235 | * - A treclaim is attempted when non transactional. | |
1236 | * - A tend is illegally attempted. | |
1237 | * - writing a TM SPR when transactional. | |
1238 | */ | |
1239 | if (!user_mode(regs) && | |
1240 | report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) { | |
1241 | regs->nip += 4; | |
ba12eede | 1242 | goto bail; |
bc2a9408 MN |
1243 | } |
1244 | /* If usermode caused this, it's done something illegal and | |
1245 | * gets a SIGILL slap on the wrist. We call it an illegal | |
1246 | * operand to distinguish from the instruction just being bad | |
1247 | * (e.g. executing a 'tend' on a CPU without TM!); it's an | |
1248 | * illegal /placement/ of a valid instruction. | |
1249 | */ | |
1250 | if (user_mode(regs)) { | |
1251 | _exception(SIGILL, regs, ILL_ILLOPN, regs->nip); | |
ba12eede | 1252 | goto bail; |
bc2a9408 MN |
1253 | } else { |
1254 | printk(KERN_EMERG "Unexpected TM Bad Thing exception " | |
1255 | "at %lx (msr 0x%x)\n", regs->nip, reason); | |
1256 | die("Unrecoverable exception", regs, SIGABRT); | |
1257 | } | |
1258 | } | |
1259 | #endif | |
8dad3f92 | 1260 | |
b3f6a459 ME |
1261 | /* |
1262 | * If we took the program check in the kernel skip down to sending a | |
1263 | * SIGILL. The subsequent cases all relate to emulating instructions | |
1264 | * which we should only do for userspace. We also do not want to enable | |
1265 | * interrupts for kernel faults because that might lead to further | |
1266 | * faults, and loose the context of the original exception. | |
1267 | */ | |
1268 | if (!user_mode(regs)) | |
1269 | goto sigill; | |
1270 | ||
a3512b2d BH |
1271 | /* We restore the interrupt state now */ |
1272 | if (!arch_irq_disabled_regs(regs)) | |
1273 | local_irq_enable(); | |
cd8a5673 | 1274 | |
04903a30 KG |
1275 | /* (reason & REASON_ILLEGAL) would be the obvious thing here, |
1276 | * but there seems to be a hardware bug on the 405GP (RevD) | |
1277 | * that means ESR is sometimes set incorrectly - either to | |
1278 | * ESR_DST (!?) or 0. In the process of chasing this with the | |
1279 | * hardware people - not sure if it can happen on any illegal | |
1280 | * instruction or only on FP instructions, whether there is a | |
4e63f8ed BH |
1281 | * pattern to occurrences etc. -dgibson 31/Mar/2003 |
1282 | */ | |
3a3b5aa6 | 1283 | if (!emulate_math(regs)) |
ba12eede | 1284 | goto bail; |
04903a30 | 1285 | |
8dad3f92 PM |
1286 | /* Try to emulate it if we should. */ |
1287 | if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { | |
14cf11af PM |
1288 | switch (emulate_instruction(regs)) { |
1289 | case 0: | |
1290 | regs->nip += 4; | |
1291 | emulate_single_step(regs); | |
ba12eede | 1292 | goto bail; |
14cf11af PM |
1293 | case -EFAULT: |
1294 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
ba12eede | 1295 | goto bail; |
14cf11af PM |
1296 | } |
1297 | } | |
8dad3f92 | 1298 | |
b3f6a459 | 1299 | sigill: |
8dad3f92 PM |
1300 | if (reason & REASON_PRIVILEGED) |
1301 | _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); | |
1302 | else | |
1303 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
ba12eede LZ |
1304 | |
1305 | bail: | |
1306 | exception_exit(prev_state); | |
14cf11af | 1307 | } |
03465f89 | 1308 | NOKPROBE_SYMBOL(program_check_exception); |
14cf11af | 1309 | |
bf593907 PM |
1310 | /* |
1311 | * This occurs when running in hypervisor mode on POWER6 or later | |
1312 | * and an illegal instruction is encountered. | |
1313 | */ | |
03465f89 | 1314 | void emulation_assist_interrupt(struct pt_regs *regs) |
bf593907 PM |
1315 | { |
1316 | regs->msr |= REASON_ILLEGAL; | |
1317 | program_check_exception(regs); | |
1318 | } | |
03465f89 | 1319 | NOKPROBE_SYMBOL(emulation_assist_interrupt); |
bf593907 | 1320 | |
dc1c1ca3 | 1321 | void alignment_exception(struct pt_regs *regs) |
14cf11af | 1322 | { |
ba12eede | 1323 | enum ctx_state prev_state = exception_enter(); |
4393c4f6 | 1324 | int sig, code, fixed = 0; |
14cf11af | 1325 | |
a3512b2d BH |
1326 | /* We restore the interrupt state now */ |
1327 | if (!arch_irq_disabled_regs(regs)) | |
1328 | local_irq_enable(); | |
1329 | ||
6ce6c629 MN |
1330 | if (tm_abort_check(regs, TM_CAUSE_ALIGNMENT | TM_CAUSE_PERSISTENT)) |
1331 | goto bail; | |
1332 | ||
e9370ae1 PM |
1333 | /* we don't implement logging of alignment exceptions */ |
1334 | if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS)) | |
1335 | fixed = fix_alignment(regs); | |
14cf11af PM |
1336 | |
1337 | if (fixed == 1) { | |
1338 | regs->nip += 4; /* skip over emulated instruction */ | |
1339 | emulate_single_step(regs); | |
ba12eede | 1340 | goto bail; |
14cf11af PM |
1341 | } |
1342 | ||
dc1c1ca3 | 1343 | /* Operand address was bad */ |
14cf11af | 1344 | if (fixed == -EFAULT) { |
4393c4f6 BH |
1345 | sig = SIGSEGV; |
1346 | code = SEGV_ACCERR; | |
1347 | } else { | |
1348 | sig = SIGBUS; | |
1349 | code = BUS_ADRALN; | |
14cf11af | 1350 | } |
4393c4f6 BH |
1351 | if (user_mode(regs)) |
1352 | _exception(sig, regs, code, regs->dar); | |
1353 | else | |
1354 | bad_page_fault(regs, regs->dar, sig); | |
ba12eede LZ |
1355 | |
1356 | bail: | |
1357 | exception_exit(prev_state); | |
14cf11af PM |
1358 | } |
1359 | ||
f0f558b1 PM |
1360 | void slb_miss_bad_addr(struct pt_regs *regs) |
1361 | { | |
1362 | enum ctx_state prev_state = exception_enter(); | |
1363 | ||
1364 | if (user_mode(regs)) | |
1365 | _exception(SIGSEGV, regs, SEGV_BNDERR, regs->dar); | |
1366 | else | |
1367 | bad_page_fault(regs, regs->dar, SIGSEGV); | |
1368 | ||
1369 | exception_exit(prev_state); | |
1370 | } | |
1371 | ||
14cf11af PM |
1372 | void StackOverflow(struct pt_regs *regs) |
1373 | { | |
1374 | printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n", | |
1375 | current, regs->gpr[1]); | |
1376 | debugger(regs); | |
1377 | show_regs(regs); | |
1378 | panic("kernel stack overflow"); | |
1379 | } | |
1380 | ||
1381 | void nonrecoverable_exception(struct pt_regs *regs) | |
1382 | { | |
1383 | printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n", | |
1384 | regs->nip, regs->msr); | |
1385 | debugger(regs); | |
1386 | die("nonrecoverable exception", regs, SIGKILL); | |
1387 | } | |
1388 | ||
dc1c1ca3 SR |
1389 | void kernel_fp_unavailable_exception(struct pt_regs *regs) |
1390 | { | |
ba12eede LZ |
1391 | enum ctx_state prev_state = exception_enter(); |
1392 | ||
dc1c1ca3 SR |
1393 | printk(KERN_EMERG "Unrecoverable FP Unavailable Exception " |
1394 | "%lx at %lx\n", regs->trap, regs->nip); | |
1395 | die("Unrecoverable FP Unavailable Exception", regs, SIGABRT); | |
ba12eede LZ |
1396 | |
1397 | exception_exit(prev_state); | |
dc1c1ca3 | 1398 | } |
dc1c1ca3 SR |
1399 | |
1400 | void altivec_unavailable_exception(struct pt_regs *regs) | |
1401 | { | |
ba12eede LZ |
1402 | enum ctx_state prev_state = exception_enter(); |
1403 | ||
dc1c1ca3 SR |
1404 | if (user_mode(regs)) { |
1405 | /* A user program has executed an altivec instruction, | |
1406 | but this kernel doesn't support altivec. */ | |
1407 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
ba12eede | 1408 | goto bail; |
dc1c1ca3 | 1409 | } |
6c4841c2 | 1410 | |
dc1c1ca3 SR |
1411 | printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception " |
1412 | "%lx at %lx\n", regs->trap, regs->nip); | |
1413 | die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT); | |
ba12eede LZ |
1414 | |
1415 | bail: | |
1416 | exception_exit(prev_state); | |
dc1c1ca3 SR |
1417 | } |
1418 | ||
ce48b210 MN |
1419 | void vsx_unavailable_exception(struct pt_regs *regs) |
1420 | { | |
1421 | if (user_mode(regs)) { | |
1422 | /* A user program has executed an vsx instruction, | |
1423 | but this kernel doesn't support vsx. */ | |
1424 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
1425 | return; | |
1426 | } | |
1427 | ||
1428 | printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception " | |
1429 | "%lx at %lx\n", regs->trap, regs->nip); | |
1430 | die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT); | |
1431 | } | |
1432 | ||
2517617e | 1433 | #ifdef CONFIG_PPC64 |
172f7aaa CB |
1434 | static void tm_unavailable(struct pt_regs *regs) |
1435 | { | |
5d176f75 CB |
1436 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1437 | if (user_mode(regs)) { | |
1438 | current->thread.load_tm++; | |
1439 | regs->msr |= MSR_TM; | |
1440 | tm_enable(); | |
1441 | tm_restore_sprs(¤t->thread); | |
1442 | return; | |
1443 | } | |
1444 | #endif | |
172f7aaa CB |
1445 | pr_emerg("Unrecoverable TM Unavailable Exception " |
1446 | "%lx at %lx\n", regs->trap, regs->nip); | |
1447 | die("Unrecoverable TM Unavailable Exception", regs, SIGABRT); | |
1448 | } | |
1449 | ||
021424a1 | 1450 | void facility_unavailable_exception(struct pt_regs *regs) |
d0c0c9a1 | 1451 | { |
021424a1 | 1452 | static char *facility_strings[] = { |
2517617e MN |
1453 | [FSCR_FP_LG] = "FPU", |
1454 | [FSCR_VECVSX_LG] = "VMX/VSX", | |
1455 | [FSCR_DSCR_LG] = "DSCR", | |
1456 | [FSCR_PM_LG] = "PMU SPRs", | |
1457 | [FSCR_BHRB_LG] = "BHRB", | |
1458 | [FSCR_TM_LG] = "TM", | |
1459 | [FSCR_EBB_LG] = "EBB", | |
1460 | [FSCR_TAR_LG] = "TAR", | |
794464f4 | 1461 | [FSCR_MSGP_LG] = "MSGP", |
9b7ff0c6 | 1462 | [FSCR_SCV_LG] = "SCV", |
021424a1 | 1463 | }; |
2517617e | 1464 | char *facility = "unknown"; |
021424a1 | 1465 | u64 value; |
c952c1c4 | 1466 | u32 instword, rd; |
2517617e MN |
1467 | u8 status; |
1468 | bool hv; | |
021424a1 | 1469 | |
2517617e MN |
1470 | hv = (regs->trap == 0xf80); |
1471 | if (hv) | |
b14b6260 | 1472 | value = mfspr(SPRN_HFSCR); |
2517617e MN |
1473 | else |
1474 | value = mfspr(SPRN_FSCR); | |
1475 | ||
1476 | status = value >> 56; | |
1477 | if (status == FSCR_DSCR_LG) { | |
c952c1c4 AK |
1478 | /* |
1479 | * User is accessing the DSCR register using the problem | |
1480 | * state only SPR number (0x03) either through a mfspr or | |
1481 | * a mtspr instruction. If it is a write attempt through | |
1482 | * a mtspr, then we set the inherit bit. This also allows | |
1483 | * the user to write or read the register directly in the | |
1484 | * future by setting via the FSCR DSCR bit. But in case it | |
1485 | * is a read DSCR attempt through a mfspr instruction, we | |
1486 | * just emulate the instruction instead. This code path will | |
1487 | * always emulate all the mfspr instructions till the user | |
446957ba | 1488 | * has attempted at least one mtspr instruction. This way it |
c952c1c4 AK |
1489 | * preserves the same behaviour when the user is accessing |
1490 | * the DSCR through privilege level only SPR number (0x11) | |
1491 | * which is emulated through illegal instruction exception. | |
1492 | * We always leave HFSCR DSCR set. | |
2517617e | 1493 | */ |
c952c1c4 AK |
1494 | if (get_user(instword, (u32 __user *)(regs->nip))) { |
1495 | pr_err("Failed to fetch the user instruction\n"); | |
1496 | return; | |
1497 | } | |
1498 | ||
1499 | /* Write into DSCR (mtspr 0x03, RS) */ | |
1500 | if ((instword & PPC_INST_MTSPR_DSCR_USER_MASK) | |
1501 | == PPC_INST_MTSPR_DSCR_USER) { | |
1502 | rd = (instword >> 21) & 0x1f; | |
1503 | current->thread.dscr = regs->gpr[rd]; | |
1504 | current->thread.dscr_inherit = 1; | |
b57bd2de MN |
1505 | current->thread.fscr |= FSCR_DSCR; |
1506 | mtspr(SPRN_FSCR, current->thread.fscr); | |
c952c1c4 AK |
1507 | } |
1508 | ||
1509 | /* Read from DSCR (mfspr RT, 0x03) */ | |
1510 | if ((instword & PPC_INST_MFSPR_DSCR_USER_MASK) | |
1511 | == PPC_INST_MFSPR_DSCR_USER) { | |
1512 | if (emulate_instruction(regs)) { | |
1513 | pr_err("DSCR based mfspr emulation failed\n"); | |
1514 | return; | |
1515 | } | |
1516 | regs->nip += 4; | |
1517 | emulate_single_step(regs); | |
1518 | } | |
2517617e | 1519 | return; |
b14b6260 ME |
1520 | } |
1521 | ||
172f7aaa CB |
1522 | if (status == FSCR_TM_LG) { |
1523 | /* | |
1524 | * If we're here then the hardware is TM aware because it | |
1525 | * generated an exception with FSRM_TM set. | |
1526 | * | |
1527 | * If cpu_has_feature(CPU_FTR_TM) is false, then either firmware | |
1528 | * told us not to do TM, or the kernel is not built with TM | |
1529 | * support. | |
1530 | * | |
1531 | * If both of those things are true, then userspace can spam the | |
1532 | * console by triggering the printk() below just by continually | |
1533 | * doing tbegin (or any TM instruction). So in that case just | |
1534 | * send the process a SIGILL immediately. | |
1535 | */ | |
1536 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1537 | goto out; | |
1538 | ||
1539 | tm_unavailable(regs); | |
1540 | return; | |
1541 | } | |
1542 | ||
93c2ec0f BS |
1543 | if ((hv || status >= 2) && |
1544 | (status < ARRAY_SIZE(facility_strings)) && | |
2517617e MN |
1545 | facility_strings[status]) |
1546 | facility = facility_strings[status]; | |
021424a1 | 1547 | |
d0c0c9a1 MN |
1548 | /* We restore the interrupt state now */ |
1549 | if (!arch_irq_disabled_regs(regs)) | |
1550 | local_irq_enable(); | |
1551 | ||
93c2ec0f BS |
1552 | pr_err_ratelimited("%sFacility '%s' unavailable (%d), exception at 0x%lx, MSR=%lx\n", |
1553 | hv ? "Hypervisor " : "", facility, status, regs->nip, regs->msr); | |
d0c0c9a1 | 1554 | |
172f7aaa | 1555 | out: |
d0c0c9a1 MN |
1556 | if (user_mode(regs)) { |
1557 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
1558 | return; | |
1559 | } | |
1560 | ||
021424a1 | 1561 | die("Unexpected facility unavailable exception", regs, SIGABRT); |
d0c0c9a1 | 1562 | } |
2517617e | 1563 | #endif |
d0c0c9a1 | 1564 | |
f54db641 MN |
1565 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1566 | ||
f54db641 MN |
1567 | void fp_unavailable_tm(struct pt_regs *regs) |
1568 | { | |
1569 | /* Note: This does not handle any kind of FP laziness. */ | |
1570 | ||
1571 | TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n", | |
1572 | regs->nip, regs->msr); | |
f54db641 MN |
1573 | |
1574 | /* We can only have got here if the task started using FP after | |
1575 | * beginning the transaction. So, the transactional regs are just a | |
1576 | * copy of the checkpointed ones. But, we still need to recheckpoint | |
1577 | * as we're enabling FP for the process; it will return, abort the | |
1578 | * transaction, and probably retry but now with FP enabled. So the | |
1579 | * checkpointed FP registers need to be loaded. | |
1580 | */ | |
d31626f7 | 1581 | tm_reclaim_current(TM_CAUSE_FAC_UNAV); |
f54db641 MN |
1582 | /* Reclaim didn't save out any FPRs to transact_fprs. */ |
1583 | ||
1584 | /* Enable FP for the task: */ | |
1585 | regs->msr |= (MSR_FP | current->thread.fpexc_mode); | |
1586 | ||
1587 | /* This loads and recheckpoints the FP registers from | |
1588 | * thread.fpr[]. They will remain in registers after the | |
1589 | * checkpoint so we don't need to reload them after. | |
3ac8ff1c PM |
1590 | * If VMX is in use, the VRs now hold checkpointed values, |
1591 | * so we don't want to load the VRs from the thread_struct. | |
f54db641 | 1592 | */ |
3ac8ff1c PM |
1593 | tm_recheckpoint(¤t->thread, MSR_FP); |
1594 | ||
1595 | /* If VMX is in use, get the transactional values back */ | |
1596 | if (regs->msr & MSR_VEC) { | |
dc310669 CB |
1597 | msr_check_and_set(MSR_VEC); |
1598 | load_vr_state(¤t->thread.vr_state); | |
3ac8ff1c PM |
1599 | /* At this point all the VSX state is loaded, so enable it */ |
1600 | regs->msr |= MSR_VSX; | |
1601 | } | |
f54db641 MN |
1602 | } |
1603 | ||
f54db641 MN |
1604 | void altivec_unavailable_tm(struct pt_regs *regs) |
1605 | { | |
1606 | /* See the comments in fp_unavailable_tm(). This function operates | |
1607 | * the same way. | |
1608 | */ | |
1609 | ||
1610 | TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx," | |
1611 | "MSR=%lx\n", | |
1612 | regs->nip, regs->msr); | |
d31626f7 | 1613 | tm_reclaim_current(TM_CAUSE_FAC_UNAV); |
f54db641 | 1614 | regs->msr |= MSR_VEC; |
3ac8ff1c | 1615 | tm_recheckpoint(¤t->thread, MSR_VEC); |
f54db641 | 1616 | current->thread.used_vr = 1; |
3ac8ff1c PM |
1617 | |
1618 | if (regs->msr & MSR_FP) { | |
dc310669 CB |
1619 | msr_check_and_set(MSR_FP); |
1620 | load_fp_state(¤t->thread.fp_state); | |
3ac8ff1c PM |
1621 | regs->msr |= MSR_VSX; |
1622 | } | |
f54db641 | 1623 | } |
f54db641 | 1624 | |
f54db641 MN |
1625 | void vsx_unavailable_tm(struct pt_regs *regs) |
1626 | { | |
3ac8ff1c PM |
1627 | unsigned long orig_msr = regs->msr; |
1628 | ||
f54db641 MN |
1629 | /* See the comments in fp_unavailable_tm(). This works similarly, |
1630 | * though we're loading both FP and VEC registers in here. | |
1631 | * | |
1632 | * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC | |
1633 | * regs. Either way, set MSR_VSX. | |
1634 | */ | |
1635 | ||
1636 | TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx," | |
1637 | "MSR=%lx\n", | |
1638 | regs->nip, regs->msr); | |
1639 | ||
3ac8ff1c PM |
1640 | current->thread.used_vsr = 1; |
1641 | ||
1642 | /* If FP and VMX are already loaded, we have all the state we need */ | |
1643 | if ((orig_msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC)) { | |
1644 | regs->msr |= MSR_VSX; | |
1645 | return; | |
1646 | } | |
1647 | ||
f54db641 | 1648 | /* This reclaims FP and/or VR regs if they're already enabled */ |
d31626f7 | 1649 | tm_reclaim_current(TM_CAUSE_FAC_UNAV); |
f54db641 MN |
1650 | |
1651 | regs->msr |= MSR_VEC | MSR_FP | current->thread.fpexc_mode | | |
1652 | MSR_VSX; | |
3ac8ff1c PM |
1653 | |
1654 | /* This loads & recheckpoints FP and VRs; but we have | |
1655 | * to be sure not to overwrite previously-valid state. | |
1656 | */ | |
1657 | tm_recheckpoint(¤t->thread, regs->msr & ~orig_msr); | |
1658 | ||
dc310669 CB |
1659 | msr_check_and_set(orig_msr & (MSR_FP | MSR_VEC)); |
1660 | ||
3ac8ff1c | 1661 | if (orig_msr & MSR_FP) |
dc310669 | 1662 | load_fp_state(¤t->thread.fp_state); |
3ac8ff1c | 1663 | if (orig_msr & MSR_VEC) |
dc310669 | 1664 | load_vr_state(¤t->thread.vr_state); |
f54db641 | 1665 | } |
f54db641 MN |
1666 | #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ |
1667 | ||
dc1c1ca3 SR |
1668 | void performance_monitor_exception(struct pt_regs *regs) |
1669 | { | |
69111bac | 1670 | __this_cpu_inc(irq_stat.pmu_irqs); |
89713ed1 | 1671 | |
dc1c1ca3 SR |
1672 | perf_irq(regs); |
1673 | } | |
dc1c1ca3 | 1674 | |
8dad3f92 | 1675 | #ifdef CONFIG_8xx |
14cf11af PM |
1676 | void SoftwareEmulation(struct pt_regs *regs) |
1677 | { | |
14cf11af PM |
1678 | CHECK_FULL_REGS(regs); |
1679 | ||
1680 | if (!user_mode(regs)) { | |
1681 | debugger(regs); | |
1eb2819d LC |
1682 | die("Kernel Mode Unimplemented Instruction or SW FPU Emulation", |
1683 | regs, SIGFPE); | |
14cf11af PM |
1684 | } |
1685 | ||
3a3b5aa6 | 1686 | if (!emulate_math(regs)) |
5fad293b | 1687 | return; |
3a3b5aa6 | 1688 | |
5dd57a13 | 1689 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); |
14cf11af | 1690 | } |
8dad3f92 | 1691 | #endif /* CONFIG_8xx */ |
14cf11af | 1692 | |
172ae2e7 | 1693 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
3bffb652 DK |
1694 | static void handle_debug(struct pt_regs *regs, unsigned long debug_status) |
1695 | { | |
1696 | int changed = 0; | |
1697 | /* | |
1698 | * Determine the cause of the debug event, clear the | |
1699 | * event flags and send a trap to the handler. Torez | |
1700 | */ | |
1701 | if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) { | |
1702 | dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W); | |
1703 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
51ae8d4a | 1704 | current->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE; |
3bffb652 DK |
1705 | #endif |
1706 | do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT, | |
1707 | 5); | |
1708 | changed |= 0x01; | |
1709 | } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) { | |
1710 | dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W); | |
1711 | do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, TRAP_HWBKPT, | |
1712 | 6); | |
1713 | changed |= 0x01; | |
1714 | } else if (debug_status & DBSR_IAC1) { | |
51ae8d4a | 1715 | current->thread.debug.dbcr0 &= ~DBCR0_IAC1; |
3bffb652 DK |
1716 | dbcr_iac_range(current) &= ~DBCR_IAC12MODE; |
1717 | do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT, | |
1718 | 1); | |
1719 | changed |= 0x01; | |
1720 | } else if (debug_status & DBSR_IAC2) { | |
51ae8d4a | 1721 | current->thread.debug.dbcr0 &= ~DBCR0_IAC2; |
3bffb652 DK |
1722 | do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT, |
1723 | 2); | |
1724 | changed |= 0x01; | |
1725 | } else if (debug_status & DBSR_IAC3) { | |
51ae8d4a | 1726 | current->thread.debug.dbcr0 &= ~DBCR0_IAC3; |
3bffb652 DK |
1727 | dbcr_iac_range(current) &= ~DBCR_IAC34MODE; |
1728 | do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT, | |
1729 | 3); | |
1730 | changed |= 0x01; | |
1731 | } else if (debug_status & DBSR_IAC4) { | |
51ae8d4a | 1732 | current->thread.debug.dbcr0 &= ~DBCR0_IAC4; |
3bffb652 DK |
1733 | do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT, |
1734 | 4); | |
1735 | changed |= 0x01; | |
1736 | } | |
1737 | /* | |
1738 | * At the point this routine was called, the MSR(DE) was turned off. | |
1739 | * Check all other debug flags and see if that bit needs to be turned | |
1740 | * back on or not. | |
1741 | */ | |
51ae8d4a | 1742 | if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0, |
95791988 | 1743 | current->thread.debug.dbcr1)) |
3bffb652 DK |
1744 | regs->msr |= MSR_DE; |
1745 | else | |
1746 | /* Make sure the IDM flag is off */ | |
51ae8d4a | 1747 | current->thread.debug.dbcr0 &= ~DBCR0_IDM; |
3bffb652 DK |
1748 | |
1749 | if (changed & 0x01) | |
51ae8d4a | 1750 | mtspr(SPRN_DBCR0, current->thread.debug.dbcr0); |
3bffb652 | 1751 | } |
14cf11af | 1752 | |
03465f89 | 1753 | void DebugException(struct pt_regs *regs, unsigned long debug_status) |
14cf11af | 1754 | { |
51ae8d4a | 1755 | current->thread.debug.dbsr = debug_status; |
3bffb652 | 1756 | |
ec097c84 RM |
1757 | /* Hack alert: On BookE, Branch Taken stops on the branch itself, while |
1758 | * on server, it stops on the target of the branch. In order to simulate | |
1759 | * the server behaviour, we thus restart right away with a single step | |
1760 | * instead of stopping here when hitting a BT | |
1761 | */ | |
1762 | if (debug_status & DBSR_BT) { | |
1763 | regs->msr &= ~MSR_DE; | |
1764 | ||
1765 | /* Disable BT */ | |
1766 | mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT); | |
1767 | /* Clear the BT event */ | |
1768 | mtspr(SPRN_DBSR, DBSR_BT); | |
1769 | ||
1770 | /* Do the single step trick only when coming from userspace */ | |
1771 | if (user_mode(regs)) { | |
51ae8d4a BB |
1772 | current->thread.debug.dbcr0 &= ~DBCR0_BT; |
1773 | current->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC; | |
ec097c84 RM |
1774 | regs->msr |= MSR_DE; |
1775 | return; | |
1776 | } | |
1777 | ||
6cc89bad NR |
1778 | if (kprobe_post_handler(regs)) |
1779 | return; | |
1780 | ||
ec097c84 RM |
1781 | if (notify_die(DIE_SSTEP, "block_step", regs, 5, |
1782 | 5, SIGTRAP) == NOTIFY_STOP) { | |
1783 | return; | |
1784 | } | |
1785 | if (debugger_sstep(regs)) | |
1786 | return; | |
1787 | } else if (debug_status & DBSR_IC) { /* Instruction complete */ | |
14cf11af | 1788 | regs->msr &= ~MSR_DE; |
f8279621 KG |
1789 | |
1790 | /* Disable instruction completion */ | |
1791 | mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC); | |
1792 | /* Clear the instruction completion event */ | |
1793 | mtspr(SPRN_DBSR, DBSR_IC); | |
1794 | ||
6cc89bad NR |
1795 | if (kprobe_post_handler(regs)) |
1796 | return; | |
1797 | ||
f8279621 KG |
1798 | if (notify_die(DIE_SSTEP, "single_step", regs, 5, |
1799 | 5, SIGTRAP) == NOTIFY_STOP) { | |
1800 | return; | |
1801 | } | |
1802 | ||
1803 | if (debugger_sstep(regs)) | |
1804 | return; | |
1805 | ||
d6a61bfc | 1806 | if (user_mode(regs)) { |
51ae8d4a BB |
1807 | current->thread.debug.dbcr0 &= ~DBCR0_IC; |
1808 | if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0, | |
1809 | current->thread.debug.dbcr1)) | |
3bffb652 DK |
1810 | regs->msr |= MSR_DE; |
1811 | else | |
1812 | /* Make sure the IDM bit is off */ | |
51ae8d4a | 1813 | current->thread.debug.dbcr0 &= ~DBCR0_IDM; |
d6a61bfc | 1814 | } |
3bffb652 DK |
1815 | |
1816 | _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); | |
1817 | } else | |
1818 | handle_debug(regs, debug_status); | |
14cf11af | 1819 | } |
03465f89 | 1820 | NOKPROBE_SYMBOL(DebugException); |
172ae2e7 | 1821 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ |
14cf11af PM |
1822 | |
1823 | #if !defined(CONFIG_TAU_INT) | |
1824 | void TAUException(struct pt_regs *regs) | |
1825 | { | |
1826 | printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n", | |
1827 | regs->nip, regs->msr, regs->trap, print_tainted()); | |
1828 | } | |
1829 | #endif /* CONFIG_INT_TAU */ | |
14cf11af PM |
1830 | |
1831 | #ifdef CONFIG_ALTIVEC | |
dc1c1ca3 | 1832 | void altivec_assist_exception(struct pt_regs *regs) |
14cf11af PM |
1833 | { |
1834 | int err; | |
1835 | ||
14cf11af PM |
1836 | if (!user_mode(regs)) { |
1837 | printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode" | |
1838 | " at %lx\n", regs->nip); | |
8dad3f92 | 1839 | die("Kernel VMX/Altivec assist exception", regs, SIGILL); |
14cf11af PM |
1840 | } |
1841 | ||
dc1c1ca3 | 1842 | flush_altivec_to_thread(current); |
dc1c1ca3 | 1843 | |
eecff81d | 1844 | PPC_WARN_EMULATED(altivec, regs); |
14cf11af PM |
1845 | err = emulate_altivec(regs); |
1846 | if (err == 0) { | |
1847 | regs->nip += 4; /* skip emulated instruction */ | |
1848 | emulate_single_step(regs); | |
1849 | return; | |
1850 | } | |
1851 | ||
1852 | if (err == -EFAULT) { | |
1853 | /* got an error reading the instruction */ | |
1854 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); | |
1855 | } else { | |
1856 | /* didn't recognize the instruction */ | |
1857 | /* XXX quick hack for now: set the non-Java bit in the VSCR */ | |
76462232 CD |
1858 | printk_ratelimited(KERN_ERR "Unrecognized altivec instruction " |
1859 | "in %s at %lx\n", current->comm, regs->nip); | |
de79f7b9 | 1860 | current->thread.vr_state.vscr.u[3] |= 0x10000; |
14cf11af PM |
1861 | } |
1862 | } | |
1863 | #endif /* CONFIG_ALTIVEC */ | |
1864 | ||
14cf11af PM |
1865 | #ifdef CONFIG_FSL_BOOKE |
1866 | void CacheLockingException(struct pt_regs *regs, unsigned long address, | |
1867 | unsigned long error_code) | |
1868 | { | |
1869 | /* We treat cache locking instructions from the user | |
1870 | * as priv ops, in the future we could try to do | |
1871 | * something smarter | |
1872 | */ | |
1873 | if (error_code & (ESR_DLK|ESR_ILK)) | |
1874 | _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); | |
1875 | return; | |
1876 | } | |
1877 | #endif /* CONFIG_FSL_BOOKE */ | |
1878 | ||
1879 | #ifdef CONFIG_SPE | |
1880 | void SPEFloatingPointException(struct pt_regs *regs) | |
1881 | { | |
6a800f36 | 1882 | extern int do_spe_mathemu(struct pt_regs *regs); |
14cf11af PM |
1883 | unsigned long spefscr; |
1884 | int fpexc_mode; | |
1885 | int code = 0; | |
6a800f36 LY |
1886 | int err; |
1887 | ||
685659ee | 1888 | flush_spe_to_thread(current); |
14cf11af PM |
1889 | |
1890 | spefscr = current->thread.spefscr; | |
1891 | fpexc_mode = current->thread.fpexc_mode; | |
1892 | ||
14cf11af PM |
1893 | if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) { |
1894 | code = FPE_FLTOVF; | |
14cf11af PM |
1895 | } |
1896 | else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) { | |
1897 | code = FPE_FLTUND; | |
14cf11af PM |
1898 | } |
1899 | else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV)) | |
1900 | code = FPE_FLTDIV; | |
1901 | else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) { | |
1902 | code = FPE_FLTINV; | |
14cf11af PM |
1903 | } |
1904 | else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES)) | |
1905 | code = FPE_FLTRES; | |
1906 | ||
6a800f36 LY |
1907 | err = do_spe_mathemu(regs); |
1908 | if (err == 0) { | |
1909 | regs->nip += 4; /* skip emulated instruction */ | |
1910 | emulate_single_step(regs); | |
1911 | return; | |
1912 | } | |
1913 | ||
1914 | if (err == -EFAULT) { | |
1915 | /* got an error reading the instruction */ | |
1916 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); | |
1917 | } else if (err == -EINVAL) { | |
1918 | /* didn't recognize the instruction */ | |
1919 | printk(KERN_ERR "unrecognized spe instruction " | |
1920 | "in %s at %lx\n", current->comm, regs->nip); | |
1921 | } else { | |
1922 | _exception(SIGFPE, regs, code, regs->nip); | |
1923 | } | |
14cf11af | 1924 | |
14cf11af PM |
1925 | return; |
1926 | } | |
6a800f36 LY |
1927 | |
1928 | void SPEFloatingPointRoundException(struct pt_regs *regs) | |
1929 | { | |
1930 | extern int speround_handler(struct pt_regs *regs); | |
1931 | int err; | |
1932 | ||
1933 | preempt_disable(); | |
1934 | if (regs->msr & MSR_SPE) | |
1935 | giveup_spe(current); | |
1936 | preempt_enable(); | |
1937 | ||
1938 | regs->nip -= 4; | |
1939 | err = speround_handler(regs); | |
1940 | if (err == 0) { | |
1941 | regs->nip += 4; /* skip emulated instruction */ | |
1942 | emulate_single_step(regs); | |
1943 | return; | |
1944 | } | |
1945 | ||
1946 | if (err == -EFAULT) { | |
1947 | /* got an error reading the instruction */ | |
1948 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); | |
1949 | } else if (err == -EINVAL) { | |
1950 | /* didn't recognize the instruction */ | |
1951 | printk(KERN_ERR "unrecognized spe instruction " | |
1952 | "in %s at %lx\n", current->comm, regs->nip); | |
1953 | } else { | |
1954 | _exception(SIGFPE, regs, 0, regs->nip); | |
1955 | return; | |
1956 | } | |
1957 | } | |
14cf11af PM |
1958 | #endif |
1959 | ||
dc1c1ca3 SR |
1960 | /* |
1961 | * We enter here if we get an unrecoverable exception, that is, one | |
1962 | * that happened at a point where the RI (recoverable interrupt) bit | |
1963 | * in the MSR is 0. This indicates that SRR0/1 are live, and that | |
1964 | * we therefore lost state by taking this exception. | |
1965 | */ | |
1966 | void unrecoverable_exception(struct pt_regs *regs) | |
1967 | { | |
1968 | printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n", | |
1969 | regs->trap, regs->nip); | |
1970 | die("Unrecoverable exception", regs, SIGABRT); | |
1971 | } | |
15770a13 | 1972 | NOKPROBE_SYMBOL(unrecoverable_exception); |
dc1c1ca3 | 1973 | |
1e18c17a | 1974 | #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x) |
14cf11af PM |
1975 | /* |
1976 | * Default handler for a Watchdog exception, | |
1977 | * spins until a reboot occurs | |
1978 | */ | |
1979 | void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs) | |
1980 | { | |
1981 | /* Generic WatchdogHandler, implement your own */ | |
1982 | mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE)); | |
1983 | return; | |
1984 | } | |
1985 | ||
1986 | void WatchdogException(struct pt_regs *regs) | |
1987 | { | |
1988 | printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n"); | |
1989 | WatchdogHandler(regs); | |
1990 | } | |
1991 | #endif | |
dc1c1ca3 | 1992 | |
dc1c1ca3 SR |
1993 | /* |
1994 | * We enter here if we discover during exception entry that we are | |
1995 | * running in supervisor mode with a userspace value in the stack pointer. | |
1996 | */ | |
1997 | void kernel_bad_stack(struct pt_regs *regs) | |
1998 | { | |
1999 | printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n", | |
2000 | regs->gpr[1], regs->nip); | |
2001 | die("Bad kernel stack pointer", regs, SIGABRT); | |
2002 | } | |
15770a13 | 2003 | NOKPROBE_SYMBOL(kernel_bad_stack); |
14cf11af PM |
2004 | |
2005 | void __init trap_init(void) | |
2006 | { | |
2007 | } | |
80947e7c GU |
2008 | |
2009 | ||
2010 | #ifdef CONFIG_PPC_EMULATED_STATS | |
2011 | ||
2012 | #define WARN_EMULATED_SETUP(type) .type = { .name = #type } | |
2013 | ||
2014 | struct ppc_emulated ppc_emulated = { | |
2015 | #ifdef CONFIG_ALTIVEC | |
2016 | WARN_EMULATED_SETUP(altivec), | |
2017 | #endif | |
2018 | WARN_EMULATED_SETUP(dcba), | |
2019 | WARN_EMULATED_SETUP(dcbz), | |
2020 | WARN_EMULATED_SETUP(fp_pair), | |
2021 | WARN_EMULATED_SETUP(isel), | |
2022 | WARN_EMULATED_SETUP(mcrxr), | |
2023 | WARN_EMULATED_SETUP(mfpvr), | |
2024 | WARN_EMULATED_SETUP(multiple), | |
2025 | WARN_EMULATED_SETUP(popcntb), | |
2026 | WARN_EMULATED_SETUP(spe), | |
2027 | WARN_EMULATED_SETUP(string), | |
a3821b2a | 2028 | WARN_EMULATED_SETUP(sync), |
80947e7c GU |
2029 | WARN_EMULATED_SETUP(unaligned), |
2030 | #ifdef CONFIG_MATH_EMULATION | |
2031 | WARN_EMULATED_SETUP(math), | |
80947e7c GU |
2032 | #endif |
2033 | #ifdef CONFIG_VSX | |
2034 | WARN_EMULATED_SETUP(vsx), | |
2035 | #endif | |
efcac658 AK |
2036 | #ifdef CONFIG_PPC64 |
2037 | WARN_EMULATED_SETUP(mfdscr), | |
2038 | WARN_EMULATED_SETUP(mtdscr), | |
f83319d7 | 2039 | WARN_EMULATED_SETUP(lq_stq), |
efcac658 | 2040 | #endif |
80947e7c GU |
2041 | }; |
2042 | ||
2043 | u32 ppc_warn_emulated; | |
2044 | ||
2045 | void ppc_warn_emulated_print(const char *type) | |
2046 | { | |
76462232 CD |
2047 | pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm, |
2048 | type); | |
80947e7c GU |
2049 | } |
2050 | ||
2051 | static int __init ppc_warn_emulated_init(void) | |
2052 | { | |
2053 | struct dentry *dir, *d; | |
2054 | unsigned int i; | |
2055 | struct ppc_emulated_entry *entries = (void *)&ppc_emulated; | |
2056 | ||
2057 | if (!powerpc_debugfs_root) | |
2058 | return -ENODEV; | |
2059 | ||
2060 | dir = debugfs_create_dir("emulated_instructions", | |
2061 | powerpc_debugfs_root); | |
2062 | if (!dir) | |
2063 | return -ENOMEM; | |
2064 | ||
2065 | d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir, | |
2066 | &ppc_warn_emulated); | |
2067 | if (!d) | |
2068 | goto fail; | |
2069 | ||
2070 | for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) { | |
2071 | d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir, | |
2072 | (u32 *)&entries[i].val.counter); | |
2073 | if (!d) | |
2074 | goto fail; | |
2075 | } | |
2076 | ||
2077 | return 0; | |
2078 | ||
2079 | fail: | |
2080 | debugfs_remove_recursive(dir); | |
2081 | return -ENOMEM; | |
2082 | } | |
2083 | ||
2084 | device_initcall(ppc_warn_emulated_init); | |
2085 | ||
2086 | #endif /* CONFIG_PPC_EMULATED_STATS */ |