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Commit | Line | Data |
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7f853352 | 1 | /* |
25985edc | 2 | * udbg for NS16550 compatible serial ports |
7f853352 MM |
3 | * |
4 | * Copyright (C) 2001-2005 PPC 64 Team, IBM Corp | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
7f853352 | 11 | #include <linux/types.h> |
188d2ce7 | 12 | #include <asm/udbg.h> |
7f853352 | 13 | #include <asm/io.h> |
a0496d45 | 14 | #include <asm/reg_a2.h> |
7f853352 MM |
15 | |
16 | extern u8 real_readb(volatile u8 __iomem *addr); | |
17 | extern void real_writeb(u8 data, volatile u8 __iomem *addr); | |
39c870d5 OJ |
18 | extern u8 real_205_readb(volatile u8 __iomem *addr); |
19 | extern void real_205_writeb(u8 data, volatile u8 __iomem *addr); | |
7f853352 | 20 | |
30925748 BH |
21 | #define UART_RBR 0 |
22 | #define UART_IER 1 | |
23 | #define UART_FCR 2 | |
24 | #define UART_LCR 3 | |
25 | #define UART_MCR 4 | |
26 | #define UART_LSR 5 | |
27 | #define UART_MSR 6 | |
28 | #define UART_SCR 7 | |
29 | #define UART_THR UART_RBR | |
30 | #define UART_IIR UART_FCR | |
31 | #define UART_DLL UART_RBR | |
32 | #define UART_DLM UART_IER | |
33 | #define UART_DLAB UART_LCR | |
7f853352 MM |
34 | |
35 | #define LSR_DR 0x01 /* Data ready */ | |
36 | #define LSR_OE 0x02 /* Overrun */ | |
37 | #define LSR_PE 0x04 /* Parity error */ | |
38 | #define LSR_FE 0x08 /* Framing error */ | |
39 | #define LSR_BI 0x10 /* Break */ | |
40 | #define LSR_THRE 0x20 /* Xmit holding register empty */ | |
41 | #define LSR_TEMT 0x40 /* Xmitter empty */ | |
42 | #define LSR_ERR 0x80 /* Error */ | |
43 | ||
463ce0e1 BH |
44 | #define LCR_DLAB 0x80 |
45 | ||
30925748 BH |
46 | static u8 (*udbg_uart_in)(unsigned int reg); |
47 | static void (*udbg_uart_out)(unsigned int reg, u8 data); | |
7f853352 | 48 | |
30925748 | 49 | static void udbg_uart_flush(void) |
7f853352 | 50 | { |
30925748 BH |
51 | if (!udbg_uart_in) |
52 | return; | |
53 | ||
54 | /* wait for idle */ | |
55 | while ((udbg_uart_in(UART_LSR) & LSR_THRE) == 0) | |
56 | cpu_relax(); | |
af9c7249 AK |
57 | } |
58 | ||
30925748 | 59 | static void udbg_uart_putc(char c) |
af9c7249 | 60 | { |
30925748 BH |
61 | if (!udbg_uart_out) |
62 | return; | |
63 | ||
64 | if (c == '\n') | |
65 | udbg_uart_putc('\r'); | |
66 | udbg_uart_flush(); | |
67 | udbg_uart_out(UART_THR, c); | |
7f853352 MM |
68 | } |
69 | ||
30925748 | 70 | static int udbg_uart_getc_poll(void) |
7f853352 | 71 | { |
cd32e2dc AB |
72 | if (!udbg_uart_in) |
73 | return -1; | |
74 | ||
75 | if (!(udbg_uart_in(UART_LSR) & LSR_DR)) | |
30925748 | 76 | return udbg_uart_in(UART_RBR); |
cd32e2dc | 77 | |
7f853352 MM |
78 | return -1; |
79 | } | |
80 | ||
30925748 | 81 | static int udbg_uart_getc(void) |
7f853352 | 82 | { |
30925748 BH |
83 | if (!udbg_uart_in) |
84 | return -1; | |
85 | /* wait for char */ | |
86 | while (!(udbg_uart_in(UART_LSR) & LSR_DR)) | |
87 | cpu_relax(); | |
88 | return udbg_uart_in(UART_RBR); | |
89 | } | |
90 | ||
91 | static void udbg_use_uart(void) | |
92 | { | |
93 | udbg_putc = udbg_uart_putc; | |
94 | udbg_flush = udbg_uart_flush; | |
95 | udbg_getc = udbg_uart_getc; | |
96 | udbg_getc_poll = udbg_uart_getc_poll; | |
7f853352 MM |
97 | } |
98 | ||
30925748 | 99 | void udbg_uart_setup(unsigned int speed, unsigned int clock) |
7f853352 | 100 | { |
171505da | 101 | unsigned int dll, base_bauds; |
463ce0e1 | 102 | |
30925748 BH |
103 | if (!udbg_uart_out) |
104 | return; | |
105 | ||
171505da BH |
106 | if (clock == 0) |
107 | clock = 1843200; | |
463ce0e1 BH |
108 | if (speed == 0) |
109 | speed = 9600; | |
171505da BH |
110 | |
111 | base_bauds = clock / 16; | |
463ce0e1 | 112 | dll = base_bauds / speed; |
7f853352 | 113 | |
30925748 BH |
114 | udbg_uart_out(UART_LCR, 0x00); |
115 | udbg_uart_out(UART_IER, 0xff); | |
116 | udbg_uart_out(UART_IER, 0x00); | |
117 | udbg_uart_out(UART_LCR, LCR_DLAB); | |
118 | udbg_uart_out(UART_DLL, dll & 0xff); | |
119 | udbg_uart_out(UART_DLM, dll >> 8); | |
120 | /* 8 data, 1 stop, no parity */ | |
121 | udbg_uart_out(UART_LCR, 0x3); | |
122 | /* RTS/DTR */ | |
123 | udbg_uart_out(UART_MCR, 0x3); | |
124 | /* Clear & enable FIFOs */ | |
125 | udbg_uart_out(UART_FCR, 0x7); | |
7f853352 MM |
126 | } |
127 | ||
30925748 | 128 | unsigned int udbg_probe_uart_speed(unsigned int clock) |
463ce0e1 BH |
129 | { |
130 | unsigned int dll, dlm, divisor, prescaler, speed; | |
131 | u8 old_lcr; | |
463ce0e1 | 132 | |
30925748 | 133 | old_lcr = udbg_uart_in(UART_LCR); |
463ce0e1 BH |
134 | |
135 | /* select divisor latch registers. */ | |
30925748 | 136 | udbg_uart_out(UART_LCR, old_lcr | LCR_DLAB); |
463ce0e1 BH |
137 | |
138 | /* now, read the divisor */ | |
30925748 BH |
139 | dll = udbg_uart_in(UART_DLL); |
140 | dlm = udbg_uart_in(UART_DLM); | |
463ce0e1 BH |
141 | divisor = dlm << 8 | dll; |
142 | ||
143 | /* check prescaling */ | |
30925748 | 144 | if (udbg_uart_in(UART_MCR) & 0x80) |
463ce0e1 BH |
145 | prescaler = 4; |
146 | else | |
147 | prescaler = 1; | |
148 | ||
149 | /* restore the LCR */ | |
30925748 | 150 | udbg_uart_out(UART_LCR, old_lcr); |
463ce0e1 BH |
151 | |
152 | /* calculate speed */ | |
153 | speed = (clock / prescaler) / (divisor * 16); | |
154 | ||
155 | /* sanity check */ | |
bb5e6491 | 156 | if (speed > (clock / 16)) |
463ce0e1 BH |
157 | speed = 9600; |
158 | ||
159 | return speed; | |
160 | } | |
161 | ||
30925748 BH |
162 | static union { |
163 | unsigned char __iomem *mmio_base; | |
164 | unsigned long pio_base; | |
165 | } udbg_uart; | |
166 | ||
167 | static unsigned int udbg_uart_stride = 1; | |
168 | ||
169 | static u8 udbg_uart_in_pio(unsigned int reg) | |
7f853352 | 170 | { |
30925748 | 171 | return inb(udbg_uart.pio_base + (reg * udbg_uart_stride)); |
af9c7249 AK |
172 | } |
173 | ||
30925748 | 174 | static void udbg_uart_out_pio(unsigned int reg, u8 data) |
af9c7249 | 175 | { |
30925748 | 176 | outb(data, udbg_uart.pio_base + (reg * udbg_uart_stride)); |
7f853352 MM |
177 | } |
178 | ||
30925748 | 179 | void udbg_uart_init_pio(unsigned long port, unsigned int stride) |
7f853352 | 180 | { |
30925748 BH |
181 | if (!port) |
182 | return; | |
183 | udbg_uart.pio_base = port; | |
184 | udbg_uart_stride = stride; | |
185 | udbg_uart_in = udbg_uart_in_pio; | |
186 | udbg_uart_out = udbg_uart_out_pio; | |
187 | udbg_use_uart(); | |
188 | } | |
7f853352 | 189 | |
30925748 BH |
190 | static u8 udbg_uart_in_mmio(unsigned int reg) |
191 | { | |
192 | return in_8(udbg_uart.mmio_base + (reg * udbg_uart_stride)); | |
7f853352 | 193 | } |
39c870d5 | 194 | |
30925748 | 195 | static void udbg_uart_out_mmio(unsigned int reg, u8 data) |
39c870d5 | 196 | { |
30925748 BH |
197 | out_8(udbg_uart.mmio_base + (reg * udbg_uart_stride), data); |
198 | } | |
199 | ||
200 | ||
201 | void udbg_uart_init_mmio(void __iomem *addr, unsigned int stride) | |
202 | { | |
203 | if (!addr) | |
204 | return; | |
205 | udbg_uart.mmio_base = addr; | |
206 | udbg_uart_stride = stride; | |
207 | udbg_uart_in = udbg_uart_in_mmio; | |
208 | udbg_uart_out = udbg_uart_out_mmio; | |
209 | udbg_use_uart(); | |
af9c7249 AK |
210 | } |
211 | ||
30925748 BH |
212 | #ifdef CONFIG_PPC_MAPLE |
213 | ||
214 | #define UDBG_UART_MAPLE_ADDR ((void __iomem *)0xf40003f8) | |
215 | ||
216 | static u8 udbg_uart_in_maple(unsigned int reg) | |
af9c7249 | 217 | { |
30925748 | 218 | return real_readb(UDBG_UART_MAPLE_ADDR + reg); |
39c870d5 OJ |
219 | } |
220 | ||
30925748 | 221 | static void udbg_uart_out_maple(unsigned int reg, u8 val) |
39c870d5 | 222 | { |
30925748 BH |
223 | real_writeb(val, UDBG_UART_MAPLE_ADDR + reg); |
224 | } | |
39c870d5 | 225 | |
30925748 BH |
226 | void __init udbg_init_maple_realmode(void) |
227 | { | |
228 | udbg_uart_in = udbg_uart_in_maple; | |
229 | udbg_uart_out = udbg_uart_out_maple; | |
230 | udbg_use_uart(); | |
39c870d5 | 231 | } |
30925748 | 232 | |
39c870d5 | 233 | #endif /* CONFIG_PPC_MAPLE */ |
d9b55a03 | 234 | |
30925748 BH |
235 | #ifdef CONFIG_PPC_PASEMI |
236 | ||
237 | #define UDBG_UART_PAS_ADDR ((void __iomem *)0xfcff03f8UL) | |
d9b55a03 | 238 | |
30925748 | 239 | static u8 udbg_uart_in_pas(unsigned int reg) |
d9b55a03 | 240 | { |
30925748 | 241 | return real_205_readb(UDBG_UART_PAS_ADDR + reg); |
af9c7249 AK |
242 | } |
243 | ||
30925748 | 244 | static void udbg_uart_out_pas(unsigned int reg, u8 val) |
af9c7249 | 245 | { |
30925748 | 246 | real_205_writeb(val, UDBG_UART_PAS_ADDR + reg); |
d9b55a03 DG |
247 | } |
248 | ||
30925748 | 249 | void __init udbg_init_pas_realmode(void) |
70dea47d | 250 | { |
30925748 BH |
251 | udbg_uart_in = udbg_uart_in_pas; |
252 | udbg_uart_out = udbg_uart_out_pas; | |
253 | udbg_use_uart(); | |
70dea47d HB |
254 | } |
255 | ||
30925748 BH |
256 | #endif /* CONFIG_PPC_PASEMI */ |
257 | ||
258 | #ifdef CONFIG_PPC_EARLY_DEBUG_44x | |
259 | ||
260 | #include <platforms/44x/44x.h> | |
261 | ||
262 | static u8 udbg_uart_in_44x_as1(unsigned int reg) | |
d9b55a03 | 263 | { |
30925748 BH |
264 | return as1_readb((void __iomem *)PPC44x_EARLY_DEBUG_VIRTADDR + reg); |
265 | } | |
d9b55a03 | 266 | |
30925748 BH |
267 | static void udbg_uart_out_44x_as1(unsigned int reg, u8 val) |
268 | { | |
269 | as1_writeb(val, (void __iomem *)PPC44x_EARLY_DEBUG_VIRTADDR + reg); | |
d9b55a03 | 270 | } |
9dae8afd | 271 | |
30925748 | 272 | void __init udbg_init_44x_as1(void) |
9dae8afd | 273 | { |
30925748 BH |
274 | udbg_uart_in = udbg_uart_in_44x_as1; |
275 | udbg_uart_out = udbg_uart_out_44x_as1; | |
276 | udbg_use_uart(); | |
af9c7249 AK |
277 | } |
278 | ||
30925748 BH |
279 | #endif /* CONFIG_PPC_EARLY_DEBUG_44x */ |
280 | ||
281 | #ifdef CONFIG_PPC_EARLY_DEBUG_40x | |
282 | ||
283 | static u8 udbg_uart_in_40x(unsigned int reg) | |
af9c7249 | 284 | { |
30925748 BH |
285 | return real_readb((void __iomem *)CONFIG_PPC_EARLY_DEBUG_40x_PHYSADDR |
286 | + reg); | |
9dae8afd BH |
287 | } |
288 | ||
30925748 | 289 | static void udbg_uart_out_40x(unsigned int reg, u8 val) |
9dae8afd | 290 | { |
30925748 BH |
291 | real_writeb(val, (void __iomem *)CONFIG_PPC_EARLY_DEBUG_40x_PHYSADDR |
292 | + reg); | |
9dae8afd BH |
293 | } |
294 | ||
295 | void __init udbg_init_40x_realmode(void) | |
296 | { | |
30925748 BH |
297 | udbg_uart_in = udbg_uart_in_40x; |
298 | udbg_uart_out = udbg_uart_out_40x; | |
299 | udbg_use_uart(); | |
9dae8afd | 300 | } |
30925748 | 301 | |
9dae8afd | 302 | #endif /* CONFIG_PPC_EARLY_DEBUG_40x */ |