[mirror_ubuntu-zesty-kernel.git] / arch / powerpc / kernel / vdso64 / sigtramp.S

/*
 * Signal trampoline for 64 bits processes in a ppc64 kernel for
 * use in the vDSO
 *
 * Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org), IBM Corp.
 * Copyright (C) 2004 Alan Modra (amodra@au.ibm.com)), IBM Corp.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */
#include <asm/processor.h>
#include <asm/ppc_asm.h>
#include <asm/unistd.h>
#include <asm/vdso.h>
#include <asm/ptrace.h>		/* XXX for __SIGNAL_FRAMESIZE */

	.text

/* The nop here is a hack.  The dwarf2 unwind routines subtract 1 from
   the return address to get an address in the middle of the presumed
   call instruction.  Since we don't have a call here, we artificially
   extend the range covered by the unwind info by padding before the
   real start.  */
	nop
	.balign 8
V_FUNCTION_BEGIN(__kernel_sigtramp_rt64)
.Lsigrt_start = . - 4
	addi	r1, r1, __SIGNAL_FRAMESIZE
	li	r0,__NR_rt_sigreturn
	sc
.Lsigrt_end:
V_FUNCTION_END(__kernel_sigtramp_rt64)
/* The ".balign 8" above and the following zeros mimic the old stack
   trampoline layout.  The last magic value is the ucontext pointer,
   chosen in such a way that older libgcc unwind code returns a zero
   for a sigcontext pointer.  */
	.long 0,0,0
	.quad 0,-21*8

/* Register r1 can be found at offset 8 of a pt_regs structure.
   A pointer to the pt_regs is stored in memory at the old sp plus PTREGS.  */
#define cfa_save \
  .byte 0x0f;			/* DW_CFA_def_cfa_expression */		\
  .uleb128 9f - 1f;		/*   length */				\
1:									\
  .byte 0x71; .sleb128 PTREGS;	/*     DW_OP_breg1 */			\
  .byte 0x06;			/*     DW_OP_deref */			\
  .byte 0x23; .uleb128 RSIZE;	/*     DW_OP_plus_uconst */		\
  .byte 0x06;			/*     DW_OP_deref */			\
9:

/* Register REGNO can be found at offset OFS of a pt_regs structure.
   A pointer to the pt_regs is stored in memory at the old sp plus PTREGS.  */
#define rsave(regno, ofs) \
  .byte 0x10;			/* DW_CFA_expression */			\
  .uleb128 regno;		/*   regno */				\
  .uleb128 9f - 1f;		/*   length */				\
1:									\
  .byte 0x71; .sleb128 PTREGS;	/*     DW_OP_breg1 */			\
  .byte 0x06;			/*     DW_OP_deref */			\
  .ifne ofs;								\
    .byte 0x23; .uleb128 ofs;	/*     DW_OP_plus_uconst */		\
  .endif;								\
9:

/* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
   of the VMX reg struct.  A pointer to the VMX reg struct is at VREGS in
   the pt_regs struct.  This macro is for REGNO == 0, and contains
   'subroutines' that the other macros jump to.  */
#define vsave_msr0(regno) \
  .byte 0x10;			/* DW_CFA_expression */			\
  .uleb128 regno + 77;		/*   regno */				\
  .uleb128 9f - 1f;		/*   length */				\
1:									\
  .byte 0x30 + regno;		/*     DW_OP_lit0 */			\
2:									\
  .byte 0x40;			/*     DW_OP_lit16 */			\
  .byte 0x1e;			/*     DW_OP_mul */			\
3:									\
  .byte 0x71; .sleb128 PTREGS;	/*     DW_OP_breg1 */			\
  .byte 0x06;			/*     DW_OP_deref */			\
  .byte 0x12;			/*     DW_OP_dup */			\
  .byte 0x23;			/*     DW_OP_plus_uconst */		\
    .uleb128 33*RSIZE;		/*       msr offset */			\
  .byte 0x06;			/*     DW_OP_deref */			\
  .byte 0x0c; .long 1 << 25;	/*     DW_OP_const4u */			\
  .byte 0x1a;			/*     DW_OP_and */			\
  .byte 0x12;			/*     DW_OP_dup, ret 0 if bra taken */	\
  .byte 0x30;			/*     DW_OP_lit0 */			\
  .byte 0x29;			/*     DW_OP_eq */			\
  .byte 0x28; .short 0x7fff;	/*     DW_OP_bra to end */		\
  .byte 0x13;			/*     DW_OP_drop, pop the 0 */		\
  .byte 0x23; .uleb128 VREGS;	/*     DW_OP_plus_uconst */		\
  .byte 0x06;			/*     DW_OP_deref */			\
  .byte 0x22;			/*     DW_OP_plus */			\
  .byte 0x2f; .short 0x7fff;	/*     DW_OP_skip to end */		\
9:

/* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
   of the VMX reg struct.  REGNO is 1 thru 31.  */
#define vsave_msr1(regno) \
  .byte 0x10;			/* DW_CFA_expression */			\
  .uleb128 regno + 77;		/*   regno */				\
  .uleb128 9f - 1f;		/*   length */				\
1:									\
  .byte 0x30 + regno;		/*     DW_OP_lit n */			\
  .byte 0x2f; .short 2b - 9f;	/*     DW_OP_skip */			\
9:

/* If msr bit 1<<25 is set, then VMX register REGNO is at offset OFS of
   the VMX save block.  */
#define vsave_msr2(regno, ofs) \
  .byte 0x10;			/* DW_CFA_expression */			\
  .uleb128 regno + 77;		/*   regno */				\
  .uleb128 9f - 1f;		/*   length */				\
1:									\
  .byte 0x0a; .short ofs;	/*     DW_OP_const2u */			\
  .byte 0x2f; .short 3b - 9f;	/*     DW_OP_skip */			\
9:

/* VMX register REGNO is at offset OFS of the VMX save area.  */
#define vsave(regno, ofs) \
  .byte 0x10;			/* DW_CFA_expression */			\
  .uleb128 regno + 77;		/*   regno */				\
  .uleb128 9f - 1f;		/*   length */				\
1:									\
  .byte 0x71; .sleb128 PTREGS;	/*     DW_OP_breg1 */			\
  .byte 0x06;			/*     DW_OP_deref */			\
  .byte 0x23; .uleb128 VREGS;	/*     DW_OP_plus_uconst */		\
  .byte 0x06;			/*     DW_OP_deref */			\
  .byte 0x23; .uleb128 ofs;	/*     DW_OP_plus_uconst */		\
9:

/* This is where the pt_regs pointer can be found on the stack.  */
#define PTREGS	128+168+56

/* Size of regs.  */
#define RSIZE	8

/* Size of CR reg in DWARF unwind info. */
#define CRSIZE	4

/* Offset of CR reg within a full word. */
#ifdef __LITTLE_ENDIAN__
#define CROFF 0
#else
#define CROFF (RSIZE - CRSIZE)
#endif

/* This is the offset of the VMX reg pointer.  */
#define VREGS	48*RSIZE+33*8

/* Describe where general purpose regs are saved.  */
#define EH_FRAME_GEN \
  cfa_save;								\
  rsave ( 0,  0*RSIZE);							\
  rsave ( 2,  2*RSIZE);							\
  rsave ( 3,  3*RSIZE);							\
  rsave ( 4,  4*RSIZE);							\
  rsave ( 5,  5*RSIZE);							\
  rsave ( 6,  6*RSIZE);							\
  rsave ( 7,  7*RSIZE);							\
  rsave ( 8,  8*RSIZE);							\
  rsave ( 9,  9*RSIZE);							\
  rsave (10, 10*RSIZE);							\
  rsave (11, 11*RSIZE);							\
  rsave (12, 12*RSIZE);							\
  rsave (13, 13*RSIZE);							\
  rsave (14, 14*RSIZE);							\
  rsave (15, 15*RSIZE);							\
  rsave (16, 16*RSIZE);							\
  rsave (17, 17*RSIZE);							\
  rsave (18, 18*RSIZE);							\
  rsave (19, 19*RSIZE);							\
  rsave (20, 20*RSIZE);							\
  rsave (21, 21*RSIZE);							\
  rsave (22, 22*RSIZE);							\
  rsave (23, 23*RSIZE);							\
  rsave (24, 24*RSIZE);							\
  rsave (25, 25*RSIZE);							\
  rsave (26, 26*RSIZE);							\
  rsave (27, 27*RSIZE);							\
  rsave (28, 28*RSIZE);							\
  rsave (29, 29*RSIZE);							\
  rsave (30, 30*RSIZE);							\
  rsave (31, 31*RSIZE);							\
  rsave (67, 32*RSIZE);		/* ap, used as temp for nip */		\
  rsave (65, 36*RSIZE);		/* lr */				\
  rsave (68, 38*RSIZE + CROFF);	/* cr fields */				\
  rsave (69, 38*RSIZE + CROFF);						\
  rsave (70, 38*RSIZE + CROFF);						\
  rsave (71, 38*RSIZE + CROFF);						\
  rsave (72, 38*RSIZE + CROFF);						\
  rsave (73, 38*RSIZE + CROFF);						\
  rsave (74, 38*RSIZE + CROFF);						\
  rsave (75, 38*RSIZE + CROFF)

/* Describe where the FP regs are saved.  */
#define EH_FRAME_FP \
  rsave (32, 48*RSIZE +  0*8);						\
  rsave (33, 48*RSIZE +  1*8);						\
  rsave (34, 48*RSIZE +  2*8);						\
  rsave (35, 48*RSIZE +  3*8);						\
  rsave (36, 48*RSIZE +  4*8);						\
  rsave (37, 48*RSIZE +  5*8);						\
  rsave (38, 48*RSIZE +  6*8);						\
  rsave (39, 48*RSIZE +  7*8);						\
  rsave (40, 48*RSIZE +  8*8);						\
  rsave (41, 48*RSIZE +  9*8);						\
  rsave (42, 48*RSIZE + 10*8);						\
  rsave (43, 48*RSIZE + 11*8);						\
  rsave (44, 48*RSIZE + 12*8);						\
  rsave (45, 48*RSIZE + 13*8);						\
  rsave (46, 48*RSIZE + 14*8);						\
  rsave (47, 48*RSIZE + 15*8);						\
  rsave (48, 48*RSIZE + 16*8);						\
  rsave (49, 48*RSIZE + 17*8);						\
  rsave (50, 48*RSIZE + 18*8);						\
  rsave (51, 48*RSIZE + 19*8);						\
  rsave (52, 48*RSIZE + 20*8);						\
  rsave (53, 48*RSIZE + 21*8);						\
  rsave (54, 48*RSIZE + 22*8);						\
  rsave (55, 48*RSIZE + 23*8);						\
  rsave (56, 48*RSIZE + 24*8);						\
  rsave (57, 48*RSIZE + 25*8);						\
  rsave (58, 48*RSIZE + 26*8);						\
  rsave (59, 48*RSIZE + 27*8);						\
  rsave (60, 48*RSIZE + 28*8);						\
  rsave (61, 48*RSIZE + 29*8);						\
  rsave (62, 48*RSIZE + 30*8);						\
  rsave (63, 48*RSIZE + 31*8)

/* Describe where the VMX regs are saved.  */
#ifdef CONFIG_ALTIVEC
#define EH_FRAME_VMX \
  vsave_msr0 ( 0);							\
  vsave_msr1 ( 1);							\
  vsave_msr1 ( 2);							\
  vsave_msr1 ( 3);							\
  vsave_msr1 ( 4);							\
  vsave_msr1 ( 5);							\
  vsave_msr1 ( 6);							\
  vsave_msr1 ( 7);							\
  vsave_msr1 ( 8);							\
  vsave_msr1 ( 9);							\
  vsave_msr1 (10);							\
  vsave_msr1 (11);							\
  vsave_msr1 (12);							\
  vsave_msr1 (13);							\
  vsave_msr1 (14);							\
  vsave_msr1 (15);							\
  vsave_msr1 (16);							\
  vsave_msr1 (17);							\
  vsave_msr1 (18);							\
  vsave_msr1 (19);							\
  vsave_msr1 (20);							\
  vsave_msr1 (21);							\
  vsave_msr1 (22);							\
  vsave_msr1 (23);							\
  vsave_msr1 (24);							\
  vsave_msr1 (25);							\
  vsave_msr1 (26);							\
  vsave_msr1 (27);							\
  vsave_msr1 (28);							\
  vsave_msr1 (29);							\
  vsave_msr1 (30);							\
  vsave_msr1 (31);							\
  vsave_msr2 (33, 32*16+12);						\
  vsave      (32, 33*16)
#else
#define EH_FRAME_VMX
#endif

	.section .eh_frame,"a",@progbits
.Lcie:
	.long .Lcie_end - .Lcie_start
.Lcie_start:
	.long 0			/* CIE ID */
	.byte 1			/* Version number */
	.string "zRS"		/* NUL-terminated augmentation string */
	.uleb128 4		/* Code alignment factor */
	.sleb128 -8		/* Data alignment factor */
	.byte 67		/* Return address register column, ap */
	.uleb128 1		/* Augmentation value length */
	.byte 0x14		/* DW_EH_PE_pcrel | DW_EH_PE_udata8. */
	.byte 0x0c,1,0		/* DW_CFA_def_cfa: r1 ofs 0 */
	.balign 8
.Lcie_end:

	.long .Lfde0_end - .Lfde0_start
.Lfde0_start:
	.long .Lfde0_start - .Lcie	/* CIE pointer. */
	.quad .Lsigrt_start - .		/* PC start, length */
	.quad .Lsigrt_end - .Lsigrt_start
	.uleb128 0			/* Augmentation */
	EH_FRAME_GEN
	EH_FRAME_FP
	EH_FRAME_VMX
# Do we really need to describe the frame at this point?  ie. will
# we ever have some call chain that returns somewhere past the addi?
# I don't think so, since gcc doesn't support async signals.
#	.byte 0x41		/* DW_CFA_advance_loc 1*4 */
#undef PTREGS
#define PTREGS 168+56
#	EH_FRAME_GEN
#	EH_FRAME_FP
#	EH_FRAME_VMX
	.balign 8
.Lfde0_end:
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Signal trampoline for 64 bits processes in a ppc64 kernel for
	3	* use in the vDSO
	4	*
	5	* Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org), IBM Corp.
	6	* Copyright (C) 2004 Alan Modra (amodra@au.ibm.com)), IBM Corp.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License
	10	* as published by the Free Software Foundation; either version
	11	* 2 of the License, or (at your option) any later version.
	12	*/
1da177e4 LT	13	#include <asm/processor.h>
	14	#include <asm/ppc_asm.h>
	15	#include <asm/unistd.h>
	16	#include <asm/vdso.h>
b60fc8bb	17	#include <asm/ptrace.h> /* XXX for __SIGNAL_FRAMESIZE */
1da177e4 LT	18
	19	.text
	20
	21	/* The nop here is a hack. The dwarf2 unwind routines subtract 1 from
	22	the return address to get an address in the middle of the presumed
25985edc	23	call instruction. Since we don't have a call here, we artificially
1da177e4 LT	24	extend the range covered by the unwind info by padding before the
	25	real start. */
	26	nop
	27	.balign 8
	28	V_FUNCTION_BEGIN(__kernel_sigtramp_rt64)
	29	.Lsigrt_start = . - 4
	30	addi r1, r1, __SIGNAL_FRAMESIZE
	31	li r0,__NR_rt_sigreturn
	32	sc
	33	.Lsigrt_end:
	34	V_FUNCTION_END(__kernel_sigtramp_rt64)
	35	/* The ".balign 8" above and the following zeros mimic the old stack
	36	trampoline layout. The last magic value is the ucontext pointer,
	37	chosen in such a way that older libgcc unwind code returns a zero
	38	for a sigcontext pointer. */
	39	.long 0,0,0
	40	.quad 0,-21*8
	41
	42	/* Register r1 can be found at offset 8 of a pt_regs structure.
	43	A pointer to the pt_regs is stored in memory at the old sp plus PTREGS. */
	44	#define cfa_save \
	45	.byte 0x0f; /* DW_CFA_def_cfa_expression */ \
	46	.uleb128 9f - 1f; /* length */ \
	47	1: \
	48	.byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \
	49	.byte 0x06; /* DW_OP_deref */ \
	50	.byte 0x23; .uleb128 RSIZE; /* DW_OP_plus_uconst */ \
	51	.byte 0x06; /* DW_OP_deref */ \
	52	9:
	53
	54	/* Register REGNO can be found at offset OFS of a pt_regs structure.
	55	A pointer to the pt_regs is stored in memory at the old sp plus PTREGS. */
	56	#define rsave(regno, ofs) \
	57	.byte 0x10; /* DW_CFA_expression */ \
	58	.uleb128 regno; /* regno */ \
	59	.uleb128 9f - 1f; /* length */ \
	60	1: \
	61	.byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \
	62	.byte 0x06; /* DW_OP_deref */ \
	63	.ifne ofs; \
	64	.byte 0x23; .uleb128 ofs; /* DW_OP_plus_uconst */ \
	65	.endif; \
	66	9:
	67
	68	/* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
	69	of the VMX reg struct. A pointer to the VMX reg struct is at VREGS in
	70	the pt_regs struct. This macro is for REGNO == 0, and contains
	71	'subroutines' that the other macros jump to. */
	72	#define vsave_msr0(regno) \
	73	.byte 0x10; /* DW_CFA_expression */ \
	74	.uleb128 regno + 77; /* regno */ \
	75	.uleb128 9f - 1f; /* length */ \
	76	1: \
	77	.byte 0x30 + regno; /* DW_OP_lit0 */ \
	78	2: \
	79	.byte 0x40; /* DW_OP_lit16 */ \
	80	.byte 0x1e; /* DW_OP_mul */ \
	81	3: \
	82	.byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \
	83	.byte 0x06; /* DW_OP_deref */ \
	84	.byte 0x12; /* DW_OP_dup */ \
	85	.byte 0x23; /* DW_OP_plus_uconst */ \
	86	.uleb128 33RSIZE; / msr offset */ \
	87	.byte 0x06; /* DW_OP_deref */ \
88	.byte 0x0c; .long 1 << 25; /* DW_OP_const4u */ \
89	.byte 0x1a; /* DW_OP_and */ \
90	.byte 0x12; /* DW_OP_dup, ret 0 if bra taken */ \
91	.byte 0x30; /* DW_OP_lit0 */ \
92	.byte 0x29; /* DW_OP_eq */ \
93	.byte 0x28; .short 0x7fff; /* DW_OP_bra to end */ \
94	.byte 0x13; /* DW_OP_drop, pop the 0 */ \
95	.byte 0x23; .uleb128 VREGS; /* DW_OP_plus_uconst */ \
96	.byte 0x06; /* DW_OP_deref */ \
97	.byte 0x22; /* DW_OP_plus */ \
98	.byte 0x2f; .short 0x7fff; /* DW_OP_skip to end */ \
99	9:
100
101	/* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
102	of the VMX reg struct. REGNO is 1 thru 31. */
103	#define vsave_msr1(regno) \
104	.byte 0x10; /* DW_CFA_expression */ \
105	.uleb128 regno + 77; /* regno */ \
106	.uleb128 9f - 1f; /* length */ \
107	1: \
108	.byte 0x30 + regno; /* DW_OP_lit n */ \
109	.byte 0x2f; .short 2b - 9f; /* DW_OP_skip */ \
110	9:
111
112	/* If msr bit 1<<25 is set, then VMX register REGNO is at offset OFS of
113	the VMX save block. */
114	#define vsave_msr2(regno, ofs) \
115	.byte 0x10; /* DW_CFA_expression */ \
116	.uleb128 regno + 77; /* regno */ \
117	.uleb128 9f - 1f; /* length */ \
118	1: \
119	.byte 0x0a; .short ofs; /* DW_OP_const2u */ \
120	.byte 0x2f; .short 3b - 9f; /* DW_OP_skip */ \
121	9:
122
123	/* VMX register REGNO is at offset OFS of the VMX save area. */
124	#define vsave(regno, ofs) \
125	.byte 0x10; /* DW_CFA_expression */ \
126	.uleb128 regno + 77; /* regno */ \
127	.uleb128 9f - 1f; /* length */ \
128	1: \
129	.byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \
130	.byte 0x06; /* DW_OP_deref */ \
131	.byte 0x23; .uleb128 VREGS; /* DW_OP_plus_uconst */ \
132	.byte 0x06; /* DW_OP_deref */ \
133	.byte 0x23; .uleb128 ofs; /* DW_OP_plus_uconst */ \
134	9:
135
136	/* This is where the pt_regs pointer can be found on the stack. */
081c11a5	137	#define PTREGS 128+168+56
1da177e4 LT	138
1da177e4 LT	139	/* Size of regs. */
081c11a5 BH	140	#define RSIZE 8
	141
	142	/* Size of CR reg in DWARF unwind info. */
	143	#define CRSIZE 4
1da177e4	144
28027082 UW	145	/* Offset of CR reg within a full word. */
	146	#ifdef __LITTLE_ENDIAN__
	147	#define CROFF 0
	148	#else
	149	#define CROFF (RSIZE - CRSIZE)
	150	#endif
	151
1da177e4	152	/* This is the offset of the VMX reg pointer. */
081c11a5	153	#define VREGS 48RSIZE+338
1da177e4 LT	154
	155	/* Describe where general purpose regs are saved. */
	156	#define EH_FRAME_GEN \
	157	cfa_save; \
	158	rsave ( 0, 0*RSIZE); \
	159	rsave ( 2, 2*RSIZE); \
	160	rsave ( 3, 3*RSIZE); \
	161	rsave ( 4, 4*RSIZE); \
	162	rsave ( 5, 5*RSIZE); \
	163	rsave ( 6, 6*RSIZE); \
	164	rsave ( 7, 7*RSIZE); \
	165	rsave ( 8, 8*RSIZE); \
	166	rsave ( 9, 9*RSIZE); \
	167	rsave (10, 10*RSIZE); \
	168	rsave (11, 11*RSIZE); \
	169	rsave (12, 12*RSIZE); \
	170	rsave (13, 13*RSIZE); \
	171	rsave (14, 14*RSIZE); \
	172	rsave (15, 15*RSIZE); \
	173	rsave (16, 16*RSIZE); \
	174	rsave (17, 17*RSIZE); \
	175	rsave (18, 18*RSIZE); \
	176	rsave (19, 19*RSIZE); \
	177	rsave (20, 20*RSIZE); \
	178	rsave (21, 21*RSIZE); \
	179	rsave (22, 22*RSIZE); \
	180	rsave (23, 23*RSIZE); \
	181	rsave (24, 24*RSIZE); \
	182	rsave (25, 25*RSIZE); \
	183	rsave (26, 26*RSIZE); \
	184	rsave (27, 27*RSIZE); \
	185	rsave (28, 28*RSIZE); \
	186	rsave (29, 29*RSIZE); \
	187	rsave (30, 30*RSIZE); \
	188	rsave (31, 31*RSIZE); \
	189	rsave (67, 32RSIZE); / ap, used as temp for nip */ \
	190	rsave (65, 36RSIZE); / lr */ \
28027082 UW	191	rsave (68, 38RSIZE + CROFF); / cr fields */ \
	192	rsave (69, 38*RSIZE + CROFF); \
	193	rsave (70, 38*RSIZE + CROFF); \
	194	rsave (71, 38*RSIZE + CROFF); \
	195	rsave (72, 38*RSIZE + CROFF); \
	196	rsave (73, 38*RSIZE + CROFF); \
	197	rsave (74, 38*RSIZE + CROFF); \
	198	rsave (75, 38*RSIZE + CROFF)
1da177e4 LT	199
	200	/* Describe where the FP regs are saved. */
	201	#define EH_FRAME_FP \
	202	rsave (32, 48RSIZE + 08); \
	203	rsave (33, 48RSIZE + 18); \
	204	rsave (34, 48RSIZE + 28); \
	205	rsave (35, 48RSIZE + 38); \
	206	rsave (36, 48RSIZE + 48); \
	207	rsave (37, 48RSIZE + 58); \
	208	rsave (38, 48RSIZE + 68); \
	209	rsave (39, 48RSIZE + 78); \
	210	rsave (40, 48RSIZE + 88); \
	211	rsave (41, 48RSIZE + 98); \
	212	rsave (42, 48RSIZE + 108); \
	213	rsave (43, 48RSIZE + 118); \
	214	rsave (44, 48RSIZE + 128); \
	215	rsave (45, 48RSIZE + 138); \
	216	rsave (46, 48RSIZE + 148); \
	217	rsave (47, 48RSIZE + 158); \
	218	rsave (48, 48RSIZE + 168); \
	219	rsave (49, 48RSIZE + 178); \
	220	rsave (50, 48RSIZE + 188); \
	221	rsave (51, 48RSIZE + 198); \
	222	rsave (52, 48RSIZE + 208); \
	223	rsave (53, 48RSIZE + 218); \
	224	rsave (54, 48RSIZE + 228); \
	225	rsave (55, 48RSIZE + 238); \
	226	rsave (56, 48RSIZE + 248); \
	227	rsave (57, 48RSIZE + 258); \
	228	rsave (58, 48RSIZE + 268); \
	229	rsave (59, 48RSIZE + 278); \
	230	rsave (60, 48RSIZE + 288); \
	231	rsave (61, 48RSIZE + 298); \
	232	rsave (62, 48RSIZE + 308); \
	233	rsave (63, 48RSIZE + 318)
	234
	235	/* Describe where the VMX regs are saved. */
	236	#ifdef CONFIG_ALTIVEC
	237	#define EH_FRAME_VMX \
	238	vsave_msr0 ( 0); \
	239	vsave_msr1 ( 1); \
	240	vsave_msr1 ( 2); \
	241	vsave_msr1 ( 3); \
	242	vsave_msr1 ( 4); \
	243	vsave_msr1 ( 5); \
	244	vsave_msr1 ( 6); \
	245	vsave_msr1 ( 7); \
	246	vsave_msr1 ( 8); \
	247	vsave_msr1 ( 9); \
	248	vsave_msr1 (10); \
	249	vsave_msr1 (11); \
	250	vsave_msr1 (12); \
	251	vsave_msr1 (13); \
	252	vsave_msr1 (14); \
	253	vsave_msr1 (15); \
	254	vsave_msr1 (16); \
	255	vsave_msr1 (17); \
	256	vsave_msr1 (18); \
	257	vsave_msr1 (19); \
	258	vsave_msr1 (20); \
	259	vsave_msr1 (21); \
	260	vsave_msr1 (22); \
	261	vsave_msr1 (23); \
	262	vsave_msr1 (24); \
263	vsave_msr1 (25); \
264	vsave_msr1 (26); \
265	vsave_msr1 (27); \
266	vsave_msr1 (28); \
267	vsave_msr1 (29); \
268	vsave_msr1 (30); \
269	vsave_msr1 (31); \
270	vsave_msr2 (33, 32*16+12); \
271	vsave (32, 33*16)
272	#else
273	#define EH_FRAME_VMX
274	#endif
275
276	.section .eh_frame,"a",@progbits
277	.Lcie:
278	.long .Lcie_end - .Lcie_start
279	.Lcie_start:
280	.long 0 /* CIE ID */
281	.byte 1 /* Version number */
da2e9e1f	282	.string "zRS" /* NUL-terminated augmentation string */
1da177e4 LT	283	.uleb128 4 /* Code alignment factor */
	284	.sleb128 -8 /* Data alignment factor */
	285	.byte 67 /* Return address register column, ap */
	286	.uleb128 1 /* Augmentation value length */
	287	.byte 0x14 /* DW_EH_PE_pcrel \| DW_EH_PE_udata8. */
	288	.byte 0x0c,1,0 /* DW_CFA_def_cfa: r1 ofs 0 */
	289	.balign 8
	290	.Lcie_end:
	291
	292	.long .Lfde0_end - .Lfde0_start
	293	.Lfde0_start:
	294	.long .Lfde0_start - .Lcie /* CIE pointer. */
	295	.quad .Lsigrt_start - . /* PC start, length */
	296	.quad .Lsigrt_end - .Lsigrt_start
	297	.uleb128 0 /* Augmentation */
	298	EH_FRAME_GEN
	299	EH_FRAME_FP
	300	EH_FRAME_VMX
	301	# Do we really need to describe the frame at this point? ie. will
	302	# we ever have some call chain that returns somewhere past the addi?
	303	# I don't think so, since gcc doesn't support async signals.
	304	# .byte 0x41 /* DW_CFA_advance_loc 14 /
	305	#undef PTREGS
	306	#define PTREGS 168+56
	307	# EH_FRAME_GEN
	308	# EH_FRAME_FP
	309	# EH_FRAME_VMX
	310	.balign 8
	311	.Lfde0_end: