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de56a948 PM |
1 | /* |
2 | * This program is free software; you can redistribute it and/or modify | |
3 | * it under the terms of the GNU General Public License, version 2, as | |
4 | * published by the Free Software Foundation. | |
5 | * | |
6 | * This program is distributed in the hope that it will be useful, | |
7 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
8 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
9 | * GNU General Public License for more details. | |
10 | * | |
11 | * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com> | |
12 | * | |
13 | * Derived from book3s_rmhandlers.S and other files, which are: | |
14 | * | |
15 | * Copyright SUSE Linux Products GmbH 2009 | |
16 | * | |
17 | * Authors: Alexander Graf <agraf@suse.de> | |
18 | */ | |
19 | ||
20 | #include <asm/ppc_asm.h> | |
21 | #include <asm/kvm_asm.h> | |
22 | #include <asm/reg.h> | |
177339d7 | 23 | #include <asm/mmu.h> |
de56a948 | 24 | #include <asm/page.h> |
177339d7 PM |
25 | #include <asm/ptrace.h> |
26 | #include <asm/hvcall.h> | |
de56a948 PM |
27 | #include <asm/asm-offsets.h> |
28 | #include <asm/exception-64s.h> | |
f0888f70 | 29 | #include <asm/kvm_book3s_asm.h> |
f64e8084 | 30 | #include <asm/book3s/64/mmu-hash.h> |
e4e38121 | 31 | #include <asm/tm.h> |
fd7bacbc | 32 | #include <asm/opal.h> |
5af50993 | 33 | #include <asm/xive-regs.h> |
e4e38121 | 34 | |
2f272463 PM |
35 | /* Sign-extend HDEC if not on POWER9 */ |
36 | #define EXTEND_HDEC(reg) \ | |
37 | BEGIN_FTR_SECTION; \ | |
38 | extsw reg, reg; \ | |
39 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300) | |
40 | ||
e4e38121 | 41 | #define VCPU_GPRS_TM(reg) (((reg) * ULONG_SIZE) + VCPU_GPR_TM) |
de56a948 | 42 | |
e0b7ec05 PM |
43 | /* Values in HSTATE_NAPPING(r13) */ |
44 | #define NAPPING_CEDE 1 | |
45 | #define NAPPING_NOVCPU 2 | |
46 | ||
7ceaa6dc PM |
47 | /* Stack frame offsets for kvmppc_hv_entry */ |
48 | #define SFS 144 | |
49 | #define STACK_SLOT_TRAP (SFS-4) | |
50 | #define STACK_SLOT_TID (SFS-16) | |
51 | #define STACK_SLOT_PSSCR (SFS-24) | |
52 | #define STACK_SLOT_PID (SFS-32) | |
53 | #define STACK_SLOT_IAMR (SFS-40) | |
54 | #define STACK_SLOT_CIABR (SFS-48) | |
55 | #define STACK_SLOT_DAWR (SFS-56) | |
56 | #define STACK_SLOT_DAWRX (SFS-64) | |
57 | ||
de56a948 | 58 | /* |
19ccb76a | 59 | * Call kvmppc_hv_entry in real mode. |
de56a948 PM |
60 | * Must be called with interrupts hard-disabled. |
61 | * | |
62 | * Input Registers: | |
63 | * | |
64 | * LR = return address to continue at after eventually re-enabling MMU | |
65 | */ | |
6ed179b6 | 66 | _GLOBAL_TOC(kvmppc_hv_entry_trampoline) |
218309b7 PM |
67 | mflr r0 |
68 | std r0, PPC_LR_STKOFF(r1) | |
69 | stdu r1, -112(r1) | |
de56a948 | 70 | mfmsr r10 |
218309b7 | 71 | LOAD_REG_ADDR(r5, kvmppc_call_hv_entry) |
de56a948 PM |
72 | li r0,MSR_RI |
73 | andc r0,r10,r0 | |
74 | li r6,MSR_IR | MSR_DR | |
75 | andc r6,r10,r6 | |
76 | mtmsrd r0,1 /* clear RI in MSR */ | |
77 | mtsrr0 r5 | |
78 | mtsrr1 r6 | |
79 | RFI | |
80 | ||
218309b7 | 81 | kvmppc_call_hv_entry: |
e0b7ec05 | 82 | ld r4, HSTATE_KVM_VCPU(r13) |
218309b7 PM |
83 | bl kvmppc_hv_entry |
84 | ||
85 | /* Back from guest - restore host state and return to caller */ | |
86 | ||
eee7ff9d | 87 | BEGIN_FTR_SECTION |
218309b7 PM |
88 | /* Restore host DABR and DABRX */ |
89 | ld r5,HSTATE_DABR(r13) | |
90 | li r6,7 | |
91 | mtspr SPRN_DABR,r5 | |
92 | mtspr SPRN_DABRX,r6 | |
eee7ff9d | 93 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) |
218309b7 PM |
94 | |
95 | /* Restore SPRG3 */ | |
9d378dfa SW |
96 | ld r3,PACA_SPRG_VDSO(r13) |
97 | mtspr SPRN_SPRG_VDSO_WRITE,r3 | |
218309b7 | 98 | |
218309b7 PM |
99 | /* Reload the host's PMU registers */ |
100 | ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */ | |
101 | lbz r4, LPPACA_PMCINUSE(r3) | |
102 | cmpwi r4, 0 | |
103 | beq 23f /* skip if not */ | |
9bc01a9b | 104 | BEGIN_FTR_SECTION |
9a4fc4ea | 105 | ld r3, HSTATE_MMCR0(r13) |
9bc01a9b PM |
106 | andi. r4, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO |
107 | cmpwi r4, MMCR0_PMAO | |
108 | beql kvmppc_fix_pmao | |
109 | END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG) | |
9a4fc4ea ME |
110 | lwz r3, HSTATE_PMC1(r13) |
111 | lwz r4, HSTATE_PMC2(r13) | |
112 | lwz r5, HSTATE_PMC3(r13) | |
113 | lwz r6, HSTATE_PMC4(r13) | |
114 | lwz r8, HSTATE_PMC5(r13) | |
115 | lwz r9, HSTATE_PMC6(r13) | |
218309b7 PM |
116 | mtspr SPRN_PMC1, r3 |
117 | mtspr SPRN_PMC2, r4 | |
118 | mtspr SPRN_PMC3, r5 | |
119 | mtspr SPRN_PMC4, r6 | |
120 | mtspr SPRN_PMC5, r8 | |
121 | mtspr SPRN_PMC6, r9 | |
9a4fc4ea ME |
122 | ld r3, HSTATE_MMCR0(r13) |
123 | ld r4, HSTATE_MMCR1(r13) | |
124 | ld r5, HSTATE_MMCRA(r13) | |
125 | ld r6, HSTATE_SIAR(r13) | |
126 | ld r7, HSTATE_SDAR(r13) | |
218309b7 PM |
127 | mtspr SPRN_MMCR1, r4 |
128 | mtspr SPRN_MMCRA, r5 | |
72cde5a8 PM |
129 | mtspr SPRN_SIAR, r6 |
130 | mtspr SPRN_SDAR, r7 | |
131 | BEGIN_FTR_SECTION | |
9a4fc4ea ME |
132 | ld r8, HSTATE_MMCR2(r13) |
133 | ld r9, HSTATE_SIER(r13) | |
72cde5a8 PM |
134 | mtspr SPRN_MMCR2, r8 |
135 | mtspr SPRN_SIER, r9 | |
136 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) | |
218309b7 PM |
137 | mtspr SPRN_MMCR0, r3 |
138 | isync | |
139 | 23: | |
140 | ||
e0b7ec05 PM |
141 | /* |
142 | * Reload DEC. HDEC interrupts were disabled when | |
143 | * we reloaded the host's LPCR value. | |
144 | */ | |
145 | ld r3, HSTATE_DECEXP(r13) | |
146 | mftb r4 | |
147 | subf r4, r4, r3 | |
148 | mtspr SPRN_DEC, r4 | |
149 | ||
b4deba5c PM |
150 | /* hwthread_req may have got set by cede or no vcpu, so clear it */ |
151 | li r0, 0 | |
152 | stb r0, HSTATE_HWTHREAD_REQ(r13) | |
153 | ||
218309b7 PM |
154 | /* |
155 | * For external and machine check interrupts, we need | |
156 | * to call the Linux handler to process the interrupt. | |
157 | * We do that by jumping to absolute address 0x500 for | |
158 | * external interrupts, or the machine_check_fwnmi label | |
159 | * for machine checks (since firmware might have patched | |
160 | * the vector area at 0x200). The [h]rfid at the end of the | |
161 | * handler will return to the book3s_hv_interrupts.S code. | |
162 | * For other interrupts we do the rfid to get back | |
163 | * to the book3s_hv_interrupts.S code here. | |
164 | */ | |
165 | ld r8, 112+PPC_LR_STKOFF(r1) | |
166 | addi r1, r1, 112 | |
167 | ld r7, HSTATE_HOST_MSR(r13) | |
168 | ||
53af3ba2 PM |
169 | /* |
170 | * If we came back from the guest via a relocation-on interrupt, | |
171 | * we will be in virtual mode at this point, which makes it a | |
172 | * little easier to get back to the caller. | |
173 | */ | |
174 | mfmsr r0 | |
175 | andi. r0, r0, MSR_IR /* in real mode? */ | |
176 | bne .Lvirt_return | |
177 | ||
218309b7 PM |
178 | cmpwi cr1, r12, BOOK3S_INTERRUPT_MACHINE_CHECK |
179 | cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL | |
218309b7 | 180 | beq 11f |
70aa3961 GS |
181 | cmpwi r12, BOOK3S_INTERRUPT_H_DOORBELL |
182 | beq 15f /* Invoke the H_DOORBELL handler */ | |
0869b6fd MS |
183 | cmpwi cr2, r12, BOOK3S_INTERRUPT_HMI |
184 | beq cr2, 14f /* HMI check */ | |
218309b7 PM |
185 | |
186 | /* RFI into the highmem handler, or branch to interrupt handler */ | |
187 | mfmsr r6 | |
188 | li r0, MSR_RI | |
189 | andc r6, r6, r0 | |
190 | mtmsrd r6, 1 /* Clear RI in MSR */ | |
191 | mtsrr0 r8 | |
192 | mtsrr1 r7 | |
218309b7 PM |
193 | beq cr1, 13f /* machine check */ |
194 | RFI | |
195 | ||
196 | /* On POWER7, we have external interrupts set to use HSRR0/1 */ | |
197 | 11: mtspr SPRN_HSRR0, r8 | |
198 | mtspr SPRN_HSRR1, r7 | |
199 | ba 0x500 | |
200 | ||
201 | 13: b machine_check_fwnmi | |
202 | ||
0869b6fd MS |
203 | 14: mtspr SPRN_HSRR0, r8 |
204 | mtspr SPRN_HSRR1, r7 | |
205 | b hmi_exception_after_realmode | |
206 | ||
70aa3961 GS |
207 | 15: mtspr SPRN_HSRR0, r8 |
208 | mtspr SPRN_HSRR1, r7 | |
209 | ba 0xe80 | |
210 | ||
53af3ba2 PM |
211 | /* Virtual-mode return - can't get here for HMI or machine check */ |
212 | .Lvirt_return: | |
213 | cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL | |
214 | beq 16f | |
215 | cmpwi r12, BOOK3S_INTERRUPT_H_DOORBELL | |
216 | beq 17f | |
217 | andi. r0, r7, MSR_EE /* were interrupts hard-enabled? */ | |
218 | beq 18f | |
219 | mtmsrd r7, 1 /* if so then re-enable them */ | |
220 | 18: mtlr r8 | |
221 | blr | |
222 | ||
223 | 16: mtspr SPRN_HSRR0, r8 /* jump to reloc-on external vector */ | |
224 | mtspr SPRN_HSRR1, r7 | |
225 | b exc_virt_0x4500_hardware_interrupt | |
226 | ||
227 | 17: mtspr SPRN_HSRR0, r8 | |
228 | mtspr SPRN_HSRR1, r7 | |
229 | b exc_virt_0x4e80_h_doorbell | |
230 | ||
e0b7ec05 PM |
231 | kvmppc_primary_no_guest: |
232 | /* We handle this much like a ceded vcpu */ | |
fd6d53b1 | 233 | /* put the HDEC into the DEC, since HDEC interrupts don't wake us */ |
2f272463 PM |
234 | /* HDEC may be larger than DEC for arch >= v3.00, but since the */ |
235 | /* HDEC value came from DEC in the first place, it will fit */ | |
fd6d53b1 PM |
236 | mfspr r3, SPRN_HDEC |
237 | mtspr SPRN_DEC, r3 | |
6af27c84 PM |
238 | /* |
239 | * Make sure the primary has finished the MMU switch. | |
240 | * We should never get here on a secondary thread, but | |
241 | * check it for robustness' sake. | |
242 | */ | |
243 | ld r5, HSTATE_KVM_VCORE(r13) | |
244 | 65: lbz r0, VCORE_IN_GUEST(r5) | |
245 | cmpwi r0, 0 | |
246 | beq 65b | |
247 | /* Set LPCR. */ | |
248 | ld r8,VCORE_LPCR(r5) | |
249 | mtspr SPRN_LPCR,r8 | |
250 | isync | |
e0b7ec05 PM |
251 | /* set our bit in napping_threads */ |
252 | ld r5, HSTATE_KVM_VCORE(r13) | |
253 | lbz r7, HSTATE_PTID(r13) | |
254 | li r0, 1 | |
255 | sld r0, r0, r7 | |
256 | addi r6, r5, VCORE_NAPPING_THREADS | |
257 | 1: lwarx r3, 0, r6 | |
258 | or r3, r3, r0 | |
259 | stwcx. r3, 0, r6 | |
260 | bne 1b | |
7d6c40da | 261 | /* order napping_threads update vs testing entry_exit_map */ |
e0b7ec05 PM |
262 | isync |
263 | li r12, 0 | |
264 | lwz r7, VCORE_ENTRY_EXIT(r5) | |
265 | cmpwi r7, 0x100 | |
266 | bge kvm_novcpu_exit /* another thread already exiting */ | |
267 | li r3, NAPPING_NOVCPU | |
268 | stb r3, HSTATE_NAPPING(r13) | |
e0b7ec05 | 269 | |
ccc07772 | 270 | li r3, 0 /* Don't wake on privileged (OS) doorbell */ |
e0b7ec05 PM |
271 | b kvm_do_nap |
272 | ||
37f55d30 SW |
273 | /* |
274 | * kvm_novcpu_wakeup | |
275 | * Entered from kvm_start_guest if kvm_hstate.napping is set | |
276 | * to NAPPING_NOVCPU | |
277 | * r2 = kernel TOC | |
278 | * r13 = paca | |
279 | */ | |
e0b7ec05 PM |
280 | kvm_novcpu_wakeup: |
281 | ld r1, HSTATE_HOST_R1(r13) | |
282 | ld r5, HSTATE_KVM_VCORE(r13) | |
283 | li r0, 0 | |
284 | stb r0, HSTATE_NAPPING(r13) | |
e0b7ec05 | 285 | |
e3bbbbfa PM |
286 | /* check the wake reason */ |
287 | bl kvmppc_check_wake_reason | |
6af27c84 | 288 | |
37f55d30 SW |
289 | /* |
290 | * Restore volatile registers since we could have called | |
291 | * a C routine in kvmppc_check_wake_reason. | |
292 | * r5 = VCORE | |
293 | */ | |
294 | ld r5, HSTATE_KVM_VCORE(r13) | |
295 | ||
e0b7ec05 | 296 | /* see if any other thread is already exiting */ |
e0b7ec05 PM |
297 | lwz r0, VCORE_ENTRY_EXIT(r5) |
298 | cmpwi r0, 0x100 | |
299 | bge kvm_novcpu_exit | |
300 | ||
301 | /* clear our bit in napping_threads */ | |
302 | lbz r7, HSTATE_PTID(r13) | |
303 | li r0, 1 | |
304 | sld r0, r0, r7 | |
305 | addi r6, r5, VCORE_NAPPING_THREADS | |
e3bbbbfa PM |
306 | 4: lwarx r7, 0, r6 |
307 | andc r7, r7, r0 | |
308 | stwcx. r7, 0, r6 | |
e0b7ec05 PM |
309 | bne 4b |
310 | ||
e3bbbbfa | 311 | /* See if the wake reason means we need to exit */ |
e0b7ec05 PM |
312 | cmpdi r3, 0 |
313 | bge kvm_novcpu_exit | |
e0b7ec05 | 314 | |
fd6d53b1 PM |
315 | /* See if our timeslice has expired (HDEC is negative) */ |
316 | mfspr r0, SPRN_HDEC | |
2f272463 | 317 | EXTEND_HDEC(r0) |
fd6d53b1 | 318 | li r12, BOOK3S_INTERRUPT_HV_DECREMENTER |
2f272463 | 319 | cmpdi r0, 0 |
fd6d53b1 PM |
320 | blt kvm_novcpu_exit |
321 | ||
e0b7ec05 PM |
322 | /* Got an IPI but other vcpus aren't yet exiting, must be a latecomer */ |
323 | ld r4, HSTATE_KVM_VCPU(r13) | |
324 | cmpdi r4, 0 | |
b6c295df PM |
325 | beq kvmppc_primary_no_guest |
326 | ||
327 | #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING | |
328 | addi r3, r4, VCPU_TB_RMENTRY | |
329 | bl kvmhv_start_timing | |
330 | #endif | |
331 | b kvmppc_got_guest | |
e0b7ec05 PM |
332 | |
333 | kvm_novcpu_exit: | |
6af27c84 PM |
334 | #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING |
335 | ld r4, HSTATE_KVM_VCPU(r13) | |
336 | cmpdi r4, 0 | |
337 | beq 13f | |
338 | addi r3, r4, VCPU_TB_RMEXIT | |
339 | bl kvmhv_accumulate_time | |
340 | #endif | |
eddb60fb | 341 | 13: mr r3, r12 |
7ceaa6dc | 342 | stw r12, STACK_SLOT_TRAP(r1) |
eddb60fb PM |
343 | bl kvmhv_commence_exit |
344 | nop | |
7ceaa6dc | 345 | lwz r12, STACK_SLOT_TRAP(r1) |
6af27c84 | 346 | b kvmhv_switch_to_host |
e0b7ec05 | 347 | |
371fefd6 | 348 | /* |
e0b7ec05 | 349 | * We come in here when wakened from nap mode. |
371fefd6 PM |
350 | * Relocation is off and most register values are lost. |
351 | * r13 points to the PACA. | |
352 | */ | |
353 | .globl kvm_start_guest | |
354 | kvm_start_guest: | |
fd17dc7b PM |
355 | |
356 | /* Set runlatch bit the minute you wake up from nap */ | |
1f09c3ed PM |
357 | mfspr r0, SPRN_CTRLF |
358 | ori r0, r0, 1 | |
359 | mtspr SPRN_CTRLT, r0 | |
fd17dc7b | 360 | |
19ccb76a PM |
361 | ld r2,PACATOC(r13) |
362 | ||
f0888f70 PM |
363 | li r0,KVM_HWTHREAD_IN_KVM |
364 | stb r0,HSTATE_HWTHREAD_STATE(r13) | |
371fefd6 | 365 | |
f0888f70 PM |
366 | /* NV GPR values from power7_idle() will no longer be valid */ |
367 | li r0,1 | |
368 | stb r0,PACA_NAPSTATELOST(r13) | |
371fefd6 | 369 | |
4619ac88 PM |
370 | /* were we napping due to cede? */ |
371 | lbz r0,HSTATE_NAPPING(r13) | |
e0b7ec05 PM |
372 | cmpwi r0,NAPPING_CEDE |
373 | beq kvm_end_cede | |
374 | cmpwi r0,NAPPING_NOVCPU | |
375 | beq kvm_novcpu_wakeup | |
376 | ||
377 | ld r1,PACAEMERGSP(r13) | |
378 | subi r1,r1,STACK_FRAME_OVERHEAD | |
4619ac88 PM |
379 | |
380 | /* | |
381 | * We weren't napping due to cede, so this must be a secondary | |
382 | * thread being woken up to run a guest, or being woken up due | |
383 | * to a stray IPI. (Or due to some machine check or hypervisor | |
384 | * maintenance interrupt while the core is in KVM.) | |
385 | */ | |
f0888f70 PM |
386 | |
387 | /* Check the wake reason in SRR1 to see why we got here */ | |
e3bbbbfa | 388 | bl kvmppc_check_wake_reason |
37f55d30 SW |
389 | /* |
390 | * kvmppc_check_wake_reason could invoke a C routine, but we | |
391 | * have no volatile registers to restore when we return. | |
392 | */ | |
393 | ||
e3bbbbfa PM |
394 | cmpdi r3, 0 |
395 | bge kvm_no_guest | |
371fefd6 | 396 | |
b4deba5c PM |
397 | /* get vcore pointer, NULL if we have nothing to run */ |
398 | ld r5,HSTATE_KVM_VCORE(r13) | |
399 | cmpdi r5,0 | |
400 | /* if we have no vcore to run, go back to sleep */ | |
7b444c67 | 401 | beq kvm_no_guest |
f0888f70 | 402 | |
56548fc0 PM |
403 | kvm_secondary_got_guest: |
404 | ||
e0b7ec05 | 405 | /* Set HSTATE_DSCR(r13) to something sensible */ |
1db36525 | 406 | ld r6, PACA_DSCR_DEFAULT(r13) |
e0b7ec05 | 407 | std r6, HSTATE_DSCR(r13) |
2fde6d20 | 408 | |
b4deba5c PM |
409 | /* On thread 0 of a subcore, set HDEC to max */ |
410 | lbz r4, HSTATE_PTID(r13) | |
411 | cmpwi r4, 0 | |
412 | bne 63f | |
2f272463 PM |
413 | LOAD_REG_ADDR(r6, decrementer_max) |
414 | ld r6, 0(r6) | |
b4deba5c PM |
415 | mtspr SPRN_HDEC, r6 |
416 | /* and set per-LPAR registers, if doing dynamic micro-threading */ | |
417 | ld r6, HSTATE_SPLIT_MODE(r13) | |
418 | cmpdi r6, 0 | |
419 | beq 63f | |
420 | ld r0, KVM_SPLIT_RPR(r6) | |
421 | mtspr SPRN_RPR, r0 | |
422 | ld r0, KVM_SPLIT_PMMAR(r6) | |
423 | mtspr SPRN_PMMAR, r0 | |
424 | ld r0, KVM_SPLIT_LDBAR(r6) | |
425 | mtspr SPRN_LDBAR, r0 | |
426 | isync | |
427 | 63: | |
428 | /* Order load of vcpu after load of vcore */ | |
5d5b99cd | 429 | lwsync |
b4deba5c | 430 | ld r4, HSTATE_KVM_VCPU(r13) |
e0b7ec05 | 431 | bl kvmppc_hv_entry |
218309b7 PM |
432 | |
433 | /* Back from the guest, go back to nap */ | |
b4deba5c | 434 | /* Clear our vcpu and vcore pointers so we don't come back in early */ |
218309b7 | 435 | li r0, 0 |
b4deba5c | 436 | std r0, HSTATE_KVM_VCPU(r13) |
f019b7ad | 437 | /* |
b4deba5c | 438 | * Once we clear HSTATE_KVM_VCORE(r13), the code in |
5d5b99cd PM |
439 | * kvmppc_run_core() is going to assume that all our vcpu |
440 | * state is visible in memory. This lwsync makes sure | |
441 | * that that is true. | |
f019b7ad | 442 | */ |
218309b7 | 443 | lwsync |
b4deba5c | 444 | std r0, HSTATE_KVM_VCORE(r13) |
218309b7 | 445 | |
fd7bacbc MS |
446 | /* |
447 | * All secondaries exiting guest will fall through this path. | |
448 | * Before proceeding, just check for HMI interrupt and | |
449 | * invoke opal hmi handler. By now we are sure that the | |
450 | * primary thread on this core/subcore has already made partition | |
451 | * switch/TB resync and we are good to call opal hmi handler. | |
452 | */ | |
453 | cmpwi r12, BOOK3S_INTERRUPT_HMI | |
454 | bne kvm_no_guest | |
455 | ||
456 | li r3,0 /* NULL argument */ | |
457 | bl hmi_exception_realmode | |
56548fc0 PM |
458 | /* |
459 | * At this point we have finished executing in the guest. | |
460 | * We need to wait for hwthread_req to become zero, since | |
461 | * we may not turn on the MMU while hwthread_req is non-zero. | |
462 | * While waiting we also need to check if we get given a vcpu to run. | |
463 | */ | |
218309b7 | 464 | kvm_no_guest: |
56548fc0 PM |
465 | lbz r3, HSTATE_HWTHREAD_REQ(r13) |
466 | cmpwi r3, 0 | |
467 | bne 53f | |
468 | HMT_MEDIUM | |
469 | li r0, KVM_HWTHREAD_IN_KERNEL | |
218309b7 | 470 | stb r0, HSTATE_HWTHREAD_STATE(r13) |
56548fc0 PM |
471 | /* need to recheck hwthread_req after a barrier, to avoid race */ |
472 | sync | |
473 | lbz r3, HSTATE_HWTHREAD_REQ(r13) | |
474 | cmpwi r3, 0 | |
475 | bne 54f | |
476 | /* | |
5fa6b6bd | 477 | * We jump to pnv_wakeup_loss, which will return to the caller |
56548fc0 PM |
478 | * of power7_nap in the powernv cpu offline loop. The value we |
479 | * put in r3 becomes the return value for power7_nap. | |
480 | */ | |
218309b7 PM |
481 | li r3, LPCR_PECE0 |
482 | mfspr r4, SPRN_LPCR | |
483 | rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1 | |
484 | mtspr SPRN_LPCR, r4 | |
56548fc0 | 485 | li r3, 0 |
5fa6b6bd | 486 | b pnv_wakeup_loss |
56548fc0 PM |
487 | |
488 | 53: HMT_LOW | |
b4deba5c PM |
489 | ld r5, HSTATE_KVM_VCORE(r13) |
490 | cmpdi r5, 0 | |
491 | bne 60f | |
492 | ld r3, HSTATE_SPLIT_MODE(r13) | |
493 | cmpdi r3, 0 | |
494 | beq kvm_no_guest | |
495 | lbz r0, KVM_SPLIT_DO_NAP(r3) | |
496 | cmpwi r0, 0 | |
56548fc0 PM |
497 | beq kvm_no_guest |
498 | HMT_MEDIUM | |
b4deba5c PM |
499 | b kvm_unsplit_nap |
500 | 60: HMT_MEDIUM | |
56548fc0 PM |
501 | b kvm_secondary_got_guest |
502 | ||
503 | 54: li r0, KVM_HWTHREAD_IN_KVM | |
504 | stb r0, HSTATE_HWTHREAD_STATE(r13) | |
505 | b kvm_no_guest | |
218309b7 | 506 | |
b4deba5c PM |
507 | /* |
508 | * Here the primary thread is trying to return the core to | |
509 | * whole-core mode, so we need to nap. | |
510 | */ | |
511 | kvm_unsplit_nap: | |
fd7bacbc MS |
512 | /* |
513 | * When secondaries are napping in kvm_unsplit_nap() with | |
514 | * hwthread_req = 1, HMI goes ignored even though subcores are | |
515 | * already exited the guest. Hence HMI keeps waking up secondaries | |
516 | * from nap in a loop and secondaries always go back to nap since | |
517 | * no vcore is assigned to them. This makes impossible for primary | |
518 | * thread to get hold of secondary threads resulting into a soft | |
519 | * lockup in KVM path. | |
520 | * | |
521 | * Let us check if HMI is pending and handle it before we go to nap. | |
522 | */ | |
523 | cmpwi r12, BOOK3S_INTERRUPT_HMI | |
524 | bne 55f | |
525 | li r3, 0 /* NULL argument */ | |
526 | bl hmi_exception_realmode | |
527 | 55: | |
7f235328 GS |
528 | /* |
529 | * Ensure that secondary doesn't nap when it has | |
530 | * its vcore pointer set. | |
531 | */ | |
532 | sync /* matches smp_mb() before setting split_info.do_nap */ | |
533 | ld r0, HSTATE_KVM_VCORE(r13) | |
534 | cmpdi r0, 0 | |
535 | bne kvm_no_guest | |
b4deba5c PM |
536 | /* clear any pending message */ |
537 | BEGIN_FTR_SECTION | |
538 | lis r6, (PPC_DBELL_SERVER << (63-36))@h | |
539 | PPC_MSGCLR(6) | |
540 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) | |
541 | /* Set kvm_split_mode.napped[tid] = 1 */ | |
542 | ld r3, HSTATE_SPLIT_MODE(r13) | |
543 | li r0, 1 | |
544 | lhz r4, PACAPACAINDEX(r13) | |
545 | clrldi r4, r4, 61 /* micro-threading => P8 => 8 threads/core */ | |
546 | addi r4, r4, KVM_SPLIT_NAPPED | |
547 | stbx r0, r3, r4 | |
548 | /* Check the do_nap flag again after setting napped[] */ | |
549 | sync | |
550 | lbz r0, KVM_SPLIT_DO_NAP(r3) | |
551 | cmpwi r0, 0 | |
552 | beq 57f | |
553 | li r3, (LPCR_PECEDH | LPCR_PECE0) >> 4 | |
bf53c88e PM |
554 | mfspr r5, SPRN_LPCR |
555 | rlwimi r5, r3, 4, (LPCR_PECEDP | LPCR_PECEDH | LPCR_PECE0 | LPCR_PECE1) | |
556 | b kvm_nap_sequence | |
b4deba5c PM |
557 | |
558 | 57: li r0, 0 | |
559 | stbx r0, r3, r4 | |
560 | b kvm_no_guest | |
561 | ||
218309b7 PM |
562 | /****************************************************************************** |
563 | * * | |
564 | * Entry code * | |
565 | * * | |
566 | *****************************************************************************/ | |
567 | ||
de56a948 PM |
568 | .global kvmppc_hv_entry |
569 | kvmppc_hv_entry: | |
570 | ||
571 | /* Required state: | |
572 | * | |
e0b7ec05 | 573 | * R4 = vcpu pointer (or NULL) |
de56a948 PM |
574 | * MSR = ~IR|DR |
575 | * R13 = PACA | |
576 | * R1 = host R1 | |
06a29e42 | 577 | * R2 = TOC |
de56a948 | 578 | * all other volatile GPRS = free |
f4c51f84 | 579 | * Does not preserve non-volatile GPRs or CR fields |
de56a948 PM |
580 | */ |
581 | mflr r0 | |
218309b7 | 582 | std r0, PPC_LR_STKOFF(r1) |
7ceaa6dc | 583 | stdu r1, -SFS(r1) |
de56a948 | 584 | |
de56a948 PM |
585 | /* Save R1 in the PACA */ |
586 | std r1, HSTATE_HOST_R1(r13) | |
587 | ||
44a3add8 PM |
588 | li r6, KVM_GUEST_MODE_HOST_HV |
589 | stb r6, HSTATE_IN_GUEST(r13) | |
590 | ||
b6c295df PM |
591 | #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING |
592 | /* Store initial timestamp */ | |
593 | cmpdi r4, 0 | |
594 | beq 1f | |
595 | addi r3, r4, VCPU_TB_RMENTRY | |
596 | bl kvmhv_start_timing | |
597 | 1: | |
598 | #endif | |
f4c51f84 PM |
599 | |
600 | /* Use cr7 as an indication of radix mode */ | |
601 | ld r5, HSTATE_KVM_VCORE(r13) | |
602 | ld r9, VCORE_KVM(r5) /* pointer to struct kvm */ | |
603 | lbz r0, KVM_RADIX(r9) | |
604 | cmpwi cr7, r0, 0 | |
605 | ||
606 | /* Clear out SLB if hash */ | |
607 | bne cr7, 2f | |
de56a948 PM |
608 | li r6,0 |
609 | slbmte r6,r6 | |
610 | slbia | |
611 | ptesync | |
f4c51f84 | 612 | 2: |
9e368f29 | 613 | /* |
c17b98cf | 614 | * POWER7/POWER8 host -> guest partition switch code. |
9e368f29 PM |
615 | * We don't have to lock against concurrent tlbies, |
616 | * but we do have to coordinate across hardware threads. | |
617 | */ | |
7d6c40da | 618 | /* Set bit in entry map iff exit map is zero. */ |
7d6c40da PM |
619 | li r7, 1 |
620 | lbz r6, HSTATE_PTID(r13) | |
621 | sld r7, r7, r6 | |
f4c51f84 PM |
622 | addi r8, r5, VCORE_ENTRY_EXIT |
623 | 21: lwarx r3, 0, r8 | |
7d6c40da | 624 | cmpwi r3, 0x100 /* any threads starting to exit? */ |
371fefd6 | 625 | bge secondary_too_late /* if so we're too late to the party */ |
7d6c40da | 626 | or r3, r3, r7 |
f4c51f84 | 627 | stwcx. r3, 0, r8 |
371fefd6 PM |
628 | bne 21b |
629 | ||
630 | /* Primary thread switches to guest partition. */ | |
371fefd6 | 631 | cmpwi r6,0 |
6af27c84 | 632 | bne 10f |
de56a948 | 633 | lwz r7,KVM_LPID(r9) |
7a84084c PM |
634 | BEGIN_FTR_SECTION |
635 | ld r6,KVM_SDR1(r9) | |
de56a948 PM |
636 | li r0,LPID_RSVD /* switch to reserved LPID */ |
637 | mtspr SPRN_LPID,r0 | |
638 | ptesync | |
639 | mtspr SPRN_SDR1,r6 /* switch to partition page table */ | |
7a84084c | 640 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300) |
de56a948 PM |
641 | mtspr SPRN_LPID,r7 |
642 | isync | |
1b400ba0 PM |
643 | |
644 | /* See if we need to flush the TLB */ | |
645 | lhz r6,PACAPACAINDEX(r13) /* test_bit(cpu, need_tlb_flush) */ | |
a29ebeaf PM |
646 | BEGIN_FTR_SECTION |
647 | /* | |
648 | * On POWER9, individual threads can come in here, but the | |
649 | * TLB is shared between the 4 threads in a core, hence | |
650 | * invalidating on one thread invalidates for all. | |
651 | * Thus we make all 4 threads use the same bit here. | |
652 | */ | |
653 | clrrdi r6,r6,2 | |
654 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) | |
1b400ba0 PM |
655 | clrldi r7,r6,64-6 /* extract bit number (6 bits) */ |
656 | srdi r6,r6,6 /* doubleword number */ | |
657 | sldi r6,r6,3 /* address offset */ | |
658 | add r6,r6,r9 | |
659 | addi r6,r6,KVM_NEED_FLUSH /* dword in kvm->arch.need_tlb_flush */ | |
a29ebeaf PM |
660 | li r8,1 |
661 | sld r8,r8,r7 | |
1b400ba0 | 662 | ld r7,0(r6) |
a29ebeaf | 663 | and. r7,r7,r8 |
1b400ba0 | 664 | beq 22f |
ca252055 | 665 | /* Flush the TLB of any entries for this LPID */ |
a29ebeaf PM |
666 | lwz r0,KVM_TLB_SETS(r9) |
667 | mtctr r0 | |
1b400ba0 PM |
668 | li r7,0x800 /* IS field = 0b10 */ |
669 | ptesync | |
a29ebeaf PM |
670 | li r0,0 /* RS for P9 version of tlbiel */ |
671 | bne cr7, 29f | |
672 | 28: tlbiel r7 /* On P9, rs=0, RIC=0, PRS=0, R=0 */ | |
1b400ba0 PM |
673 | addi r7,r7,0x1000 |
674 | bdnz 28b | |
a29ebeaf PM |
675 | b 30f |
676 | 29: PPC_TLBIEL(7,0,2,1,1) /* for radix, RIC=2, PRS=1, R=1 */ | |
677 | addi r7,r7,0x1000 | |
678 | bdnz 29b | |
679 | 30: ptesync | |
680 | 23: ldarx r7,0,r6 /* clear the bit after TLB flushed */ | |
681 | andc r7,r7,r8 | |
682 | stdcx. r7,0,r6 | |
683 | bne 23b | |
1b400ba0 | 684 | |
93b0f4dc PM |
685 | /* Add timebase offset onto timebase */ |
686 | 22: ld r8,VCORE_TB_OFFSET(r5) | |
687 | cmpdi r8,0 | |
688 | beq 37f | |
689 | mftb r6 /* current host timebase */ | |
690 | add r8,r8,r6 | |
691 | mtspr SPRN_TBU40,r8 /* update upper 40 bits */ | |
692 | mftb r7 /* check if lower 24 bits overflowed */ | |
693 | clrldi r6,r6,40 | |
694 | clrldi r7,r7,40 | |
695 | cmpld r7,r6 | |
696 | bge 37f | |
697 | addis r8,r8,0x100 /* if so, increment upper 40 bits */ | |
698 | mtspr SPRN_TBU40,r8 | |
699 | ||
388cc6e1 PM |
700 | /* Load guest PCR value to select appropriate compat mode */ |
701 | 37: ld r7, VCORE_PCR(r5) | |
702 | cmpdi r7, 0 | |
703 | beq 38f | |
704 | mtspr SPRN_PCR, r7 | |
705 | 38: | |
b005255e MN |
706 | |
707 | BEGIN_FTR_SECTION | |
88b02cf9 | 708 | /* DPDES and VTB are shared between threads */ |
b005255e | 709 | ld r8, VCORE_DPDES(r5) |
88b02cf9 | 710 | ld r7, VCORE_VTB(r5) |
b005255e | 711 | mtspr SPRN_DPDES, r8 |
88b02cf9 | 712 | mtspr SPRN_VTB, r7 |
b005255e MN |
713 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) |
714 | ||
fd7bacbc MS |
715 | /* Mark the subcore state as inside guest */ |
716 | bl kvmppc_subcore_enter_guest | |
717 | nop | |
718 | ld r5, HSTATE_KVM_VCORE(r13) | |
719 | ld r4, HSTATE_KVM_VCPU(r13) | |
388cc6e1 | 720 | li r0,1 |
371fefd6 | 721 | stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */ |
9e368f29 | 722 | |
e0b7ec05 | 723 | /* Do we have a guest vcpu to run? */ |
6af27c84 | 724 | 10: cmpdi r4, 0 |
e0b7ec05 PM |
725 | beq kvmppc_primary_no_guest |
726 | kvmppc_got_guest: | |
de56a948 | 727 | |
f4c51f84 | 728 | /* Load up guest SLB entries (N.B. slb_max will be 0 for radix) */ |
e0b7ec05 | 729 | lwz r5,VCPU_SLB_MAX(r4) |
de56a948 PM |
730 | cmpwi r5,0 |
731 | beq 9f | |
732 | mtctr r5 | |
733 | addi r6,r4,VCPU_SLB | |
734 | 1: ld r8,VCPU_SLB_E(r6) | |
735 | ld r9,VCPU_SLB_V(r6) | |
736 | slbmte r9,r8 | |
737 | addi r6,r6,VCPU_SLB_SIZE | |
738 | bdnz 1b | |
739 | 9: | |
e0b7ec05 PM |
740 | /* Increment yield count if they have a VPA */ |
741 | ld r3, VCPU_VPA(r4) | |
742 | cmpdi r3, 0 | |
743 | beq 25f | |
0865a583 AG |
744 | li r6, LPPACA_YIELDCOUNT |
745 | LWZX_BE r5, r3, r6 | |
e0b7ec05 | 746 | addi r5, r5, 1 |
0865a583 | 747 | STWX_BE r5, r3, r6 |
e0b7ec05 PM |
748 | li r6, 1 |
749 | stb r6, VCPU_VPA_DIRTY(r4) | |
750 | 25: | |
751 | ||
e0b7ec05 PM |
752 | /* Save purr/spurr */ |
753 | mfspr r5,SPRN_PURR | |
754 | mfspr r6,SPRN_SPURR | |
755 | std r5,HSTATE_PURR(r13) | |
756 | std r6,HSTATE_SPURR(r13) | |
757 | ld r7,VCPU_PURR(r4) | |
758 | ld r8,VCPU_SPURR(r4) | |
759 | mtspr SPRN_PURR,r7 | |
760 | mtspr SPRN_SPURR,r8 | |
e0b7ec05 | 761 | |
e9cf1e08 PM |
762 | /* Save host values of some registers */ |
763 | BEGIN_FTR_SECTION | |
764 | mfspr r5, SPRN_TIDR | |
765 | mfspr r6, SPRN_PSSCR | |
f4c51f84 | 766 | mfspr r7, SPRN_PID |
4c3bb4cc | 767 | mfspr r8, SPRN_IAMR |
e9cf1e08 PM |
768 | std r5, STACK_SLOT_TID(r1) |
769 | std r6, STACK_SLOT_PSSCR(r1) | |
f4c51f84 | 770 | std r7, STACK_SLOT_PID(r1) |
4c3bb4cc | 771 | std r8, STACK_SLOT_IAMR(r1) |
e9cf1e08 | 772 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) |
7ceaa6dc PM |
773 | BEGIN_FTR_SECTION |
774 | mfspr r5, SPRN_CIABR | |
775 | mfspr r6, SPRN_DAWR | |
776 | mfspr r7, SPRN_DAWRX | |
777 | std r5, STACK_SLOT_CIABR(r1) | |
778 | std r6, STACK_SLOT_DAWR(r1) | |
779 | std r7, STACK_SLOT_DAWRX(r1) | |
780 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) | |
e9cf1e08 | 781 | |
e0b7ec05 PM |
782 | BEGIN_FTR_SECTION |
783 | /* Set partition DABR */ | |
784 | /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */ | |
8563bf52 | 785 | lwz r5,VCPU_DABRX(r4) |
e0b7ec05 PM |
786 | ld r6,VCPU_DABR(r4) |
787 | mtspr SPRN_DABRX,r5 | |
788 | mtspr SPRN_DABR,r6 | |
e0b7ec05 | 789 | isync |
e0b7ec05 PM |
790 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) |
791 | ||
e4e38121 MN |
792 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
793 | BEGIN_FTR_SECTION | |
f024ee09 PM |
794 | bl kvmppc_restore_tm |
795 | END_FTR_SECTION_IFSET(CPU_FTR_TM) | |
e4e38121 MN |
796 | #endif |
797 | ||
e0b7ec05 PM |
798 | /* Load guest PMU registers */ |
799 | /* R4 is live here (vcpu pointer) */ | |
800 | li r3, 1 | |
801 | sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */ | |
802 | mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */ | |
803 | isync | |
9bc01a9b PM |
804 | BEGIN_FTR_SECTION |
805 | ld r3, VCPU_MMCR(r4) | |
806 | andi. r5, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO | |
807 | cmpwi r5, MMCR0_PMAO | |
808 | beql kvmppc_fix_pmao | |
809 | END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG) | |
e0b7ec05 PM |
810 | lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */ |
811 | lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */ | |
812 | lwz r6, VCPU_PMC + 8(r4) | |
813 | lwz r7, VCPU_PMC + 12(r4) | |
814 | lwz r8, VCPU_PMC + 16(r4) | |
815 | lwz r9, VCPU_PMC + 20(r4) | |
e0b7ec05 PM |
816 | mtspr SPRN_PMC1, r3 |
817 | mtspr SPRN_PMC2, r5 | |
818 | mtspr SPRN_PMC3, r6 | |
819 | mtspr SPRN_PMC4, r7 | |
820 | mtspr SPRN_PMC5, r8 | |
821 | mtspr SPRN_PMC6, r9 | |
e0b7ec05 PM |
822 | ld r3, VCPU_MMCR(r4) |
823 | ld r5, VCPU_MMCR + 8(r4) | |
824 | ld r6, VCPU_MMCR + 16(r4) | |
825 | ld r7, VCPU_SIAR(r4) | |
826 | ld r8, VCPU_SDAR(r4) | |
827 | mtspr SPRN_MMCR1, r5 | |
828 | mtspr SPRN_MMCRA, r6 | |
829 | mtspr SPRN_SIAR, r7 | |
830 | mtspr SPRN_SDAR, r8 | |
b005255e MN |
831 | BEGIN_FTR_SECTION |
832 | ld r5, VCPU_MMCR + 24(r4) | |
833 | ld r6, VCPU_SIER(r4) | |
83677f55 PM |
834 | mtspr SPRN_MMCR2, r5 |
835 | mtspr SPRN_SIER, r6 | |
836 | BEGIN_FTR_SECTION_NESTED(96) | |
b005255e MN |
837 | lwz r7, VCPU_PMC + 24(r4) |
838 | lwz r8, VCPU_PMC + 28(r4) | |
839 | ld r9, VCPU_MMCR + 32(r4) | |
b005255e MN |
840 | mtspr SPRN_SPMC1, r7 |
841 | mtspr SPRN_SPMC2, r8 | |
842 | mtspr SPRN_MMCRS, r9 | |
83677f55 | 843 | END_FTR_SECTION_NESTED(CPU_FTR_ARCH_300, 0, 96) |
b005255e | 844 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) |
e0b7ec05 PM |
845 | mtspr SPRN_MMCR0, r3 |
846 | isync | |
847 | ||
848 | /* Load up FP, VMX and VSX registers */ | |
849 | bl kvmppc_load_fp | |
850 | ||
851 | ld r14, VCPU_GPR(R14)(r4) | |
852 | ld r15, VCPU_GPR(R15)(r4) | |
853 | ld r16, VCPU_GPR(R16)(r4) | |
854 | ld r17, VCPU_GPR(R17)(r4) | |
855 | ld r18, VCPU_GPR(R18)(r4) | |
856 | ld r19, VCPU_GPR(R19)(r4) | |
857 | ld r20, VCPU_GPR(R20)(r4) | |
858 | ld r21, VCPU_GPR(R21)(r4) | |
859 | ld r22, VCPU_GPR(R22)(r4) | |
860 | ld r23, VCPU_GPR(R23)(r4) | |
861 | ld r24, VCPU_GPR(R24)(r4) | |
862 | ld r25, VCPU_GPR(R25)(r4) | |
863 | ld r26, VCPU_GPR(R26)(r4) | |
864 | ld r27, VCPU_GPR(R27)(r4) | |
865 | ld r28, VCPU_GPR(R28)(r4) | |
866 | ld r29, VCPU_GPR(R29)(r4) | |
867 | ld r30, VCPU_GPR(R30)(r4) | |
868 | ld r31, VCPU_GPR(R31)(r4) | |
869 | ||
e0b7ec05 PM |
870 | /* Switch DSCR to guest value */ |
871 | ld r5, VCPU_DSCR(r4) | |
872 | mtspr SPRN_DSCR, r5 | |
e0b7ec05 | 873 | |
b005255e | 874 | BEGIN_FTR_SECTION |
c17b98cf | 875 | /* Skip next section on POWER7 */ |
b005255e MN |
876 | b 8f |
877 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) | |
b005255e MN |
878 | /* Load up POWER8-specific registers */ |
879 | ld r5, VCPU_IAMR(r4) | |
880 | lwz r6, VCPU_PSPB(r4) | |
881 | ld r7, VCPU_FSCR(r4) | |
882 | mtspr SPRN_IAMR, r5 | |
883 | mtspr SPRN_PSPB, r6 | |
884 | mtspr SPRN_FSCR, r7 | |
885 | ld r5, VCPU_DAWR(r4) | |
886 | ld r6, VCPU_DAWRX(r4) | |
887 | ld r7, VCPU_CIABR(r4) | |
888 | ld r8, VCPU_TAR(r4) | |
889 | mtspr SPRN_DAWR, r5 | |
890 | mtspr SPRN_DAWRX, r6 | |
891 | mtspr SPRN_CIABR, r7 | |
892 | mtspr SPRN_TAR, r8 | |
893 | ld r5, VCPU_IC(r4) | |
7b490411 | 894 | ld r8, VCPU_EBBHR(r4) |
88b02cf9 | 895 | mtspr SPRN_IC, r5 |
b005255e MN |
896 | mtspr SPRN_EBBHR, r8 |
897 | ld r5, VCPU_EBBRR(r4) | |
898 | ld r6, VCPU_BESCR(r4) | |
83677f55 PM |
899 | lwz r7, VCPU_GUEST_PID(r4) |
900 | ld r8, VCPU_WORT(r4) | |
b005255e MN |
901 | mtspr SPRN_EBBRR, r5 |
902 | mtspr SPRN_BESCR, r6 | |
83677f55 PM |
903 | mtspr SPRN_PID, r7 |
904 | mtspr SPRN_WORT, r8 | |
f11f6f79 PM |
905 | BEGIN_FTR_SECTION |
906 | PPC_INVALIDATE_ERAT | |
907 | END_FTR_SECTION_IFSET(CPU_FTR_POWER9_DD1) | |
83677f55 | 908 | BEGIN_FTR_SECTION |
e9cf1e08 | 909 | /* POWER8-only registers */ |
b005255e MN |
910 | ld r5, VCPU_TCSCR(r4) |
911 | ld r6, VCPU_ACOP(r4) | |
83677f55 PM |
912 | ld r7, VCPU_CSIGR(r4) |
913 | ld r8, VCPU_TACR(r4) | |
b005255e MN |
914 | mtspr SPRN_TCSCR, r5 |
915 | mtspr SPRN_ACOP, r6 | |
83677f55 PM |
916 | mtspr SPRN_CSIGR, r7 |
917 | mtspr SPRN_TACR, r8 | |
e9cf1e08 PM |
918 | FTR_SECTION_ELSE |
919 | /* POWER9-only registers */ | |
920 | ld r5, VCPU_TID(r4) | |
921 | ld r6, VCPU_PSSCR(r4) | |
922 | oris r6, r6, PSSCR_EC@h /* This makes stop trap to HV */ | |
923 | mtspr SPRN_TIDR, r5 | |
924 | mtspr SPRN_PSSCR, r6 | |
925 | ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300) | |
b005255e MN |
926 | 8: |
927 | ||
e0b7ec05 PM |
928 | /* |
929 | * Set the decrementer to the guest decrementer. | |
930 | */ | |
931 | ld r8,VCPU_DEC_EXPIRES(r4) | |
c5fb80d3 PM |
932 | /* r8 is a host timebase value here, convert to guest TB */ |
933 | ld r5,HSTATE_KVM_VCORE(r13) | |
934 | ld r6,VCORE_TB_OFFSET(r5) | |
935 | add r8,r8,r6 | |
e0b7ec05 PM |
936 | mftb r7 |
937 | subf r3,r7,r8 | |
938 | mtspr SPRN_DEC,r3 | |
939 | stw r3,VCPU_DEC(r4) | |
940 | ||
941 | ld r5, VCPU_SPRG0(r4) | |
942 | ld r6, VCPU_SPRG1(r4) | |
943 | ld r7, VCPU_SPRG2(r4) | |
944 | ld r8, VCPU_SPRG3(r4) | |
945 | mtspr SPRN_SPRG0, r5 | |
946 | mtspr SPRN_SPRG1, r6 | |
947 | mtspr SPRN_SPRG2, r7 | |
948 | mtspr SPRN_SPRG3, r8 | |
949 | ||
950 | /* Load up DAR and DSISR */ | |
951 | ld r5, VCPU_DAR(r4) | |
952 | lwz r6, VCPU_DSISR(r4) | |
953 | mtspr SPRN_DAR, r5 | |
954 | mtspr SPRN_DSISR, r6 | |
955 | ||
e0b7ec05 PM |
956 | /* Restore AMR and UAMOR, set AMOR to all 1s */ |
957 | ld r5,VCPU_AMR(r4) | |
958 | ld r6,VCPU_UAMOR(r4) | |
959 | li r7,-1 | |
960 | mtspr SPRN_AMR,r5 | |
961 | mtspr SPRN_UAMOR,r6 | |
962 | mtspr SPRN_AMOR,r7 | |
de56a948 PM |
963 | |
964 | /* Restore state of CTRL run bit; assume 1 on entry */ | |
965 | lwz r5,VCPU_CTRL(r4) | |
966 | andi. r5,r5,1 | |
967 | bne 4f | |
968 | mfspr r6,SPRN_CTRLF | |
969 | clrrdi r6,r6,1 | |
970 | mtspr SPRN_CTRLT,r6 | |
971 | 4: | |
6af27c84 PM |
972 | /* Secondary threads wait for primary to have done partition switch */ |
973 | ld r5, HSTATE_KVM_VCORE(r13) | |
974 | lbz r6, HSTATE_PTID(r13) | |
975 | cmpwi r6, 0 | |
976 | beq 21f | |
977 | lbz r0, VCORE_IN_GUEST(r5) | |
978 | cmpwi r0, 0 | |
979 | bne 21f | |
980 | HMT_LOW | |
b4deba5c PM |
981 | 20: lwz r3, VCORE_ENTRY_EXIT(r5) |
982 | cmpwi r3, 0x100 | |
983 | bge no_switch_exit | |
984 | lbz r0, VCORE_IN_GUEST(r5) | |
6af27c84 PM |
985 | cmpwi r0, 0 |
986 | beq 20b | |
987 | HMT_MEDIUM | |
988 | 21: | |
989 | /* Set LPCR. */ | |
990 | ld r8,VCORE_LPCR(r5) | |
991 | mtspr SPRN_LPCR,r8 | |
992 | isync | |
993 | ||
994 | /* Check if HDEC expires soon */ | |
995 | mfspr r3, SPRN_HDEC | |
2f272463 PM |
996 | EXTEND_HDEC(r3) |
997 | cmpdi r3, 512 /* 1 microsecond */ | |
6af27c84 PM |
998 | blt hdec_soon |
999 | ||
5af50993 BH |
1000 | #ifdef CONFIG_KVM_XICS |
1001 | /* We are entering the guest on that thread, push VCPU to XIVE */ | |
1002 | ld r10, HSTATE_XIVE_TIMA_PHYS(r13) | |
1003 | cmpldi cr0, r10, r0 | |
1004 | beq no_xive | |
1005 | ld r11, VCPU_XIVE_SAVED_STATE(r4) | |
1006 | li r9, TM_QW1_OS | |
1007 | stdcix r11,r9,r10 | |
1008 | eieio | |
1009 | lwz r11, VCPU_XIVE_CAM_WORD(r4) | |
1010 | li r9, TM_QW1_OS + TM_WORD2 | |
1011 | stwcix r11,r9,r10 | |
1012 | li r9, 1 | |
1013 | stw r9, VCPU_XIVE_PUSHED(r4) | |
1014 | no_xive: | |
1015 | #endif /* CONFIG_KVM_XICS */ | |
1016 | ||
37f55d30 | 1017 | deliver_guest_interrupt: |
de56a948 | 1018 | ld r6, VCPU_CTR(r4) |
c63517c2 | 1019 | ld r7, VCPU_XER(r4) |
de56a948 PM |
1020 | |
1021 | mtctr r6 | |
1022 | mtxer r7 | |
1023 | ||
e3bbbbfa | 1024 | kvmppc_cede_reentry: /* r4 = vcpu, r13 = paca */ |
4619ac88 PM |
1025 | ld r10, VCPU_PC(r4) |
1026 | ld r11, VCPU_MSR(r4) | |
de56a948 PM |
1027 | ld r6, VCPU_SRR0(r4) |
1028 | ld r7, VCPU_SRR1(r4) | |
e3bbbbfa PM |
1029 | mtspr SPRN_SRR0, r6 |
1030 | mtspr SPRN_SRR1, r7 | |
de56a948 | 1031 | |
4619ac88 | 1032 | /* r11 = vcpu->arch.msr & ~MSR_HV */ |
de56a948 PM |
1033 | rldicl r11, r11, 63 - MSR_HV_LG, 1 |
1034 | rotldi r11, r11, 1 + MSR_HV_LG | |
1035 | ori r11, r11, MSR_ME | |
1036 | ||
19ccb76a | 1037 | /* Check if we can deliver an external or decrementer interrupt now */ |
e3bbbbfa PM |
1038 | ld r0, VCPU_PENDING_EXC(r4) |
1039 | rldicl r0, r0, 64 - BOOK3S_IRQPRIO_EXTERNAL_LEVEL, 63 | |
1040 | cmpdi cr1, r0, 0 | |
1041 | andi. r8, r11, MSR_EE | |
e3bbbbfa PM |
1042 | mfspr r8, SPRN_LPCR |
1043 | /* Insert EXTERNAL_LEVEL bit into LPCR at the MER bit position */ | |
1044 | rldimi r8, r0, LPCR_MER_SH, 63 - LPCR_MER_SH | |
1045 | mtspr SPRN_LPCR, r8 | |
19ccb76a | 1046 | isync |
19ccb76a | 1047 | beq 5f |
e3bbbbfa PM |
1048 | li r0, BOOK3S_INTERRUPT_EXTERNAL |
1049 | bne cr1, 12f | |
1050 | mfspr r0, SPRN_DEC | |
1051 | cmpwi r0, 0 | |
1052 | li r0, BOOK3S_INTERRUPT_DECREMENTER | |
1053 | bge 5f | |
19ccb76a | 1054 | |
e3bbbbfa | 1055 | 12: mtspr SPRN_SRR0, r10 |
19ccb76a | 1056 | mr r10,r0 |
e3bbbbfa | 1057 | mtspr SPRN_SRR1, r11 |
e4e38121 MN |
1058 | mr r9, r4 |
1059 | bl kvmppc_msr_interrupt | |
e3bbbbfa | 1060 | 5: |
19ccb76a | 1061 | |
27025a60 LPF |
1062 | /* |
1063 | * Required state: | |
1064 | * R4 = vcpu | |
1065 | * R10: value for HSRR0 | |
1066 | * R11: value for HSRR1 | |
1067 | * R13 = PACA | |
1068 | */ | |
de56a948 | 1069 | fast_guest_return: |
4619ac88 PM |
1070 | li r0,0 |
1071 | stb r0,VCPU_CEDED(r4) /* cancel cede */ | |
de56a948 PM |
1072 | mtspr SPRN_HSRR0,r10 |
1073 | mtspr SPRN_HSRR1,r11 | |
1074 | ||
1075 | /* Activate guest mode, so faults get handled by KVM */ | |
44a3add8 | 1076 | li r9, KVM_GUEST_MODE_GUEST_HV |
de56a948 PM |
1077 | stb r9, HSTATE_IN_GUEST(r13) |
1078 | ||
b6c295df PM |
1079 | #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING |
1080 | /* Accumulate timing */ | |
1081 | addi r3, r4, VCPU_TB_GUEST | |
1082 | bl kvmhv_accumulate_time | |
1083 | #endif | |
1084 | ||
de56a948 PM |
1085 | /* Enter guest */ |
1086 | ||
0acb9111 PM |
1087 | BEGIN_FTR_SECTION |
1088 | ld r5, VCPU_CFAR(r4) | |
1089 | mtspr SPRN_CFAR, r5 | |
1090 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
4b8473c9 PM |
1091 | BEGIN_FTR_SECTION |
1092 | ld r0, VCPU_PPR(r4) | |
1093 | END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) | |
0acb9111 | 1094 | |
de56a948 PM |
1095 | ld r5, VCPU_LR(r4) |
1096 | lwz r6, VCPU_CR(r4) | |
1097 | mtlr r5 | |
1098 | mtcr r6 | |
1099 | ||
c75df6f9 MN |
1100 | ld r1, VCPU_GPR(R1)(r4) |
1101 | ld r2, VCPU_GPR(R2)(r4) | |
1102 | ld r3, VCPU_GPR(R3)(r4) | |
1103 | ld r5, VCPU_GPR(R5)(r4) | |
1104 | ld r6, VCPU_GPR(R6)(r4) | |
1105 | ld r7, VCPU_GPR(R7)(r4) | |
1106 | ld r8, VCPU_GPR(R8)(r4) | |
1107 | ld r9, VCPU_GPR(R9)(r4) | |
1108 | ld r10, VCPU_GPR(R10)(r4) | |
1109 | ld r11, VCPU_GPR(R11)(r4) | |
1110 | ld r12, VCPU_GPR(R12)(r4) | |
1111 | ld r13, VCPU_GPR(R13)(r4) | |
1112 | ||
4b8473c9 PM |
1113 | BEGIN_FTR_SECTION |
1114 | mtspr SPRN_PPR, r0 | |
1115 | END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) | |
1116 | ld r0, VCPU_GPR(R0)(r4) | |
c75df6f9 | 1117 | ld r4, VCPU_GPR(R4)(r4) |
de56a948 PM |
1118 | |
1119 | hrfid | |
1120 | b . | |
1121 | ||
b6c295df | 1122 | secondary_too_late: |
6af27c84 | 1123 | li r12, 0 |
b6c295df PM |
1124 | cmpdi r4, 0 |
1125 | beq 11f | |
6af27c84 PM |
1126 | stw r12, VCPU_TRAP(r4) |
1127 | #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING | |
b6c295df PM |
1128 | addi r3, r4, VCPU_TB_RMEXIT |
1129 | bl kvmhv_accumulate_time | |
6af27c84 | 1130 | #endif |
b6c295df PM |
1131 | 11: b kvmhv_switch_to_host |
1132 | ||
b4deba5c PM |
1133 | no_switch_exit: |
1134 | HMT_MEDIUM | |
1135 | li r12, 0 | |
1136 | b 12f | |
b6c295df | 1137 | hdec_soon: |
6af27c84 | 1138 | li r12, BOOK3S_INTERRUPT_HV_DECREMENTER |
b4deba5c | 1139 | 12: stw r12, VCPU_TRAP(r4) |
6af27c84 PM |
1140 | mr r9, r4 |
1141 | #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING | |
b6c295df PM |
1142 | addi r3, r4, VCPU_TB_RMEXIT |
1143 | bl kvmhv_accumulate_time | |
b6c295df | 1144 | #endif |
6af27c84 | 1145 | b guest_exit_cont |
b6c295df | 1146 | |
de56a948 PM |
1147 | /****************************************************************************** |
1148 | * * | |
1149 | * Exit code * | |
1150 | * * | |
1151 | *****************************************************************************/ | |
1152 | ||
1153 | /* | |
1154 | * We come here from the first-level interrupt handlers. | |
1155 | */ | |
dd96b2c2 AK |
1156 | .globl kvmppc_interrupt_hv |
1157 | kvmppc_interrupt_hv: | |
de56a948 PM |
1158 | /* |
1159 | * Register contents: | |
d3918e7f | 1160 | * R12 = (guest CR << 32) | interrupt vector |
de56a948 | 1161 | * R13 = PACA |
d3918e7f | 1162 | * guest R12 saved in shadow VCPU SCRATCH0 |
a97a65d5 | 1163 | * guest CTR saved in shadow VCPU SCRATCH1 if RELOCATABLE |
de56a948 PM |
1164 | * guest R13 saved in SPRN_SCRATCH0 |
1165 | */ | |
a97a65d5 | 1166 | std r9, HSTATE_SCRATCH2(r13) |
44a3add8 PM |
1167 | lbz r9, HSTATE_IN_GUEST(r13) |
1168 | cmpwi r9, KVM_GUEST_MODE_HOST_HV | |
1169 | beq kvmppc_bad_host_intr | |
dd96b2c2 AK |
1170 | #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE |
1171 | cmpwi r9, KVM_GUEST_MODE_GUEST | |
a97a65d5 | 1172 | ld r9, HSTATE_SCRATCH2(r13) |
dd96b2c2 AK |
1173 | beq kvmppc_interrupt_pr |
1174 | #endif | |
44a3add8 PM |
1175 | /* We're now back in the host but in guest MMU context */ |
1176 | li r9, KVM_GUEST_MODE_HOST_HV | |
1177 | stb r9, HSTATE_IN_GUEST(r13) | |
1178 | ||
de56a948 PM |
1179 | ld r9, HSTATE_KVM_VCPU(r13) |
1180 | ||
1181 | /* Save registers */ | |
1182 | ||
c75df6f9 MN |
1183 | std r0, VCPU_GPR(R0)(r9) |
1184 | std r1, VCPU_GPR(R1)(r9) | |
1185 | std r2, VCPU_GPR(R2)(r9) | |
1186 | std r3, VCPU_GPR(R3)(r9) | |
1187 | std r4, VCPU_GPR(R4)(r9) | |
1188 | std r5, VCPU_GPR(R5)(r9) | |
1189 | std r6, VCPU_GPR(R6)(r9) | |
1190 | std r7, VCPU_GPR(R7)(r9) | |
1191 | std r8, VCPU_GPR(R8)(r9) | |
a97a65d5 | 1192 | ld r0, HSTATE_SCRATCH2(r13) |
c75df6f9 MN |
1193 | std r0, VCPU_GPR(R9)(r9) |
1194 | std r10, VCPU_GPR(R10)(r9) | |
1195 | std r11, VCPU_GPR(R11)(r9) | |
de56a948 | 1196 | ld r3, HSTATE_SCRATCH0(r13) |
c75df6f9 | 1197 | std r3, VCPU_GPR(R12)(r9) |
d3918e7f NP |
1198 | /* CR is in the high half of r12 */ |
1199 | srdi r4, r12, 32 | |
de56a948 | 1200 | stw r4, VCPU_CR(r9) |
0acb9111 PM |
1201 | BEGIN_FTR_SECTION |
1202 | ld r3, HSTATE_CFAR(r13) | |
1203 | std r3, VCPU_CFAR(r9) | |
1204 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
4b8473c9 PM |
1205 | BEGIN_FTR_SECTION |
1206 | ld r4, HSTATE_PPR(r13) | |
1207 | std r4, VCPU_PPR(r9) | |
1208 | END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) | |
de56a948 PM |
1209 | |
1210 | /* Restore R1/R2 so we can handle faults */ | |
1211 | ld r1, HSTATE_HOST_R1(r13) | |
1212 | ld r2, PACATOC(r13) | |
1213 | ||
1214 | mfspr r10, SPRN_SRR0 | |
1215 | mfspr r11, SPRN_SRR1 | |
1216 | std r10, VCPU_SRR0(r9) | |
1217 | std r11, VCPU_SRR1(r9) | |
d3918e7f NP |
1218 | /* trap is in the low half of r12, clear CR from the high half */ |
1219 | clrldi r12, r12, 32 | |
de56a948 PM |
1220 | andi. r0, r12, 2 /* need to read HSRR0/1? */ |
1221 | beq 1f | |
1222 | mfspr r10, SPRN_HSRR0 | |
1223 | mfspr r11, SPRN_HSRR1 | |
1224 | clrrdi r12, r12, 2 | |
1225 | 1: std r10, VCPU_PC(r9) | |
1226 | std r11, VCPU_MSR(r9) | |
1227 | ||
1228 | GET_SCRATCH0(r3) | |
1229 | mflr r4 | |
c75df6f9 | 1230 | std r3, VCPU_GPR(R13)(r9) |
de56a948 PM |
1231 | std r4, VCPU_LR(r9) |
1232 | ||
de56a948 PM |
1233 | stw r12,VCPU_TRAP(r9) |
1234 | ||
b6c295df PM |
1235 | #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING |
1236 | addi r3, r9, VCPU_TB_RMINTR | |
1237 | mr r4, r9 | |
1238 | bl kvmhv_accumulate_time | |
1239 | ld r5, VCPU_GPR(R5)(r9) | |
1240 | ld r6, VCPU_GPR(R6)(r9) | |
1241 | ld r7, VCPU_GPR(R7)(r9) | |
1242 | ld r8, VCPU_GPR(R8)(r9) | |
1243 | #endif | |
1244 | ||
4a157d61 | 1245 | /* Save HEIR (HV emulation assist reg) in emul_inst |
697d3899 PM |
1246 | if this is an HEI (HV emulation interrupt, e40) */ |
1247 | li r3,KVM_INST_FETCH_FAILED | |
2bf27601 | 1248 | stw r3,VCPU_LAST_INST(r9) |
697d3899 PM |
1249 | cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST |
1250 | bne 11f | |
1251 | mfspr r3,SPRN_HEIR | |
4a157d61 | 1252 | 11: stw r3,VCPU_HEIR(r9) |
697d3899 PM |
1253 | |
1254 | /* these are volatile across C function calls */ | |
a97a65d5 NP |
1255 | #ifdef CONFIG_RELOCATABLE |
1256 | ld r3, HSTATE_SCRATCH1(r13) | |
1257 | mtctr r3 | |
1258 | #else | |
697d3899 | 1259 | mfctr r3 |
a97a65d5 | 1260 | #endif |
697d3899 PM |
1261 | mfxer r4 |
1262 | std r3, VCPU_CTR(r9) | |
c63517c2 | 1263 | std r4, VCPU_XER(r9) |
697d3899 | 1264 | |
697d3899 PM |
1265 | /* If this is a page table miss then see if it's theirs or ours */ |
1266 | cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE | |
1267 | beq kvmppc_hdsi | |
342d3db7 PM |
1268 | cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE |
1269 | beq kvmppc_hisi | |
697d3899 | 1270 | |
de56a948 PM |
1271 | /* See if this is a leftover HDEC interrupt */ |
1272 | cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER | |
1273 | bne 2f | |
1274 | mfspr r3,SPRN_HDEC | |
1275 | cmpwi r3,0 | |
1f09c3ed PM |
1276 | mr r4,r9 |
1277 | bge fast_guest_return | |
de56a948 | 1278 | 2: |
697d3899 | 1279 | /* See if this is an hcall we can handle in real mode */ |
a8606e20 PM |
1280 | cmpwi r12,BOOK3S_INTERRUPT_SYSCALL |
1281 | beq hcall_try_real_mode | |
de56a948 | 1282 | |
66feed61 PM |
1283 | /* Hypervisor doorbell - exit only if host IPI flag set */ |
1284 | cmpwi r12, BOOK3S_INTERRUPT_H_DOORBELL | |
1285 | bne 3f | |
1286 | lbz r0, HSTATE_HOST_IPI(r13) | |
06554d9f | 1287 | cmpwi r0, 0 |
66feed61 PM |
1288 | beq 4f |
1289 | b guest_exit_cont | |
1290 | 3: | |
54695c30 BH |
1291 | /* External interrupt ? */ |
1292 | cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL | |
1f09c3ed | 1293 | bne+ guest_exit_cont |
54695c30 BH |
1294 | |
1295 | /* External interrupt, first check for host_ipi. If this is | |
1296 | * set, we know the host wants us out so let's do it now | |
1297 | */ | |
c934243c | 1298 | bl kvmppc_read_intr |
37f55d30 SW |
1299 | |
1300 | /* | |
1301 | * Restore the active volatile registers after returning from | |
1302 | * a C function. | |
1303 | */ | |
1304 | ld r9, HSTATE_KVM_VCPU(r13) | |
1305 | li r12, BOOK3S_INTERRUPT_EXTERNAL | |
1306 | ||
1307 | /* | |
1308 | * kvmppc_read_intr return codes: | |
1309 | * | |
1310 | * Exit to host (r3 > 0) | |
1311 | * 1 An interrupt is pending that needs to be handled by the host | |
1312 | * Exit guest and return to host by branching to guest_exit_cont | |
1313 | * | |
f7af5209 SW |
1314 | * 2 Passthrough that needs completion in the host |
1315 | * Exit guest and return to host by branching to guest_exit_cont | |
1316 | * However, we also set r12 to BOOK3S_INTERRUPT_HV_RM_HARD | |
1317 | * to indicate to the host to complete handling the interrupt | |
1318 | * | |
37f55d30 SW |
1319 | * Before returning to guest, we check if any CPU is heading out |
1320 | * to the host and if so, we head out also. If no CPUs are heading | |
1321 | * check return values <= 0. | |
1322 | * | |
1323 | * Return to guest (r3 <= 0) | |
1324 | * 0 No external interrupt is pending | |
1325 | * -1 A guest wakeup IPI (which has now been cleared) | |
1326 | * In either case, we return to guest to deliver any pending | |
1327 | * guest interrupts. | |
e3c13e56 SW |
1328 | * |
1329 | * -2 A PCI passthrough external interrupt was handled | |
1330 | * (interrupt was delivered directly to guest) | |
1331 | * Return to guest to deliver any pending guest interrupts. | |
37f55d30 SW |
1332 | */ |
1333 | ||
f7af5209 SW |
1334 | cmpdi r3, 1 |
1335 | ble 1f | |
1336 | ||
1337 | /* Return code = 2 */ | |
1338 | li r12, BOOK3S_INTERRUPT_HV_RM_HARD | |
1339 | stw r12, VCPU_TRAP(r9) | |
1340 | b guest_exit_cont | |
1341 | ||
1342 | 1: /* Return code <= 1 */ | |
c934243c | 1343 | cmpdi r3, 0 |
1f09c3ed | 1344 | bgt guest_exit_cont |
54695c30 | 1345 | |
37f55d30 | 1346 | /* Return code <= 0 */ |
66feed61 | 1347 | 4: ld r5, HSTATE_KVM_VCORE(r13) |
4619ac88 PM |
1348 | lwz r0, VCORE_ENTRY_EXIT(r5) |
1349 | cmpwi r0, 0x100 | |
e3bbbbfa | 1350 | mr r4, r9 |
1f09c3ed | 1351 | blt deliver_guest_interrupt |
de56a948 | 1352 | |
b4072df4 | 1353 | guest_exit_cont: /* r9 = vcpu, r12 = trap, r13 = paca */ |
5af50993 BH |
1354 | #ifdef CONFIG_KVM_XICS |
1355 | /* We are exiting, pull the VP from the XIVE */ | |
1356 | lwz r0, VCPU_XIVE_PUSHED(r9) | |
1357 | cmpwi cr0, r0, 0 | |
1358 | beq 1f | |
1359 | li r7, TM_SPC_PULL_OS_CTX | |
1360 | li r6, TM_QW1_OS | |
1361 | mfmsr r0 | |
1362 | andi. r0, r0, MSR_IR /* in real mode? */ | |
1363 | beq 2f | |
1364 | ld r10, HSTATE_XIVE_TIMA_VIRT(r13) | |
1365 | cmpldi cr0, r10, 0 | |
1366 | beq 1f | |
1367 | /* First load to pull the context, we ignore the value */ | |
1368 | lwzx r11, r7, r10 | |
1369 | eieio | |
1370 | /* Second load to recover the context state (Words 0 and 1) */ | |
1371 | ldx r11, r6, r10 | |
1372 | b 3f | |
1373 | 2: ld r10, HSTATE_XIVE_TIMA_PHYS(r13) | |
1374 | cmpldi cr0, r10, 0 | |
1375 | beq 1f | |
1376 | /* First load to pull the context, we ignore the value */ | |
1377 | lwzcix r11, r7, r10 | |
1378 | eieio | |
1379 | /* Second load to recover the context state (Words 0 and 1) */ | |
1380 | ldcix r11, r6, r10 | |
1381 | 3: std r11, VCPU_XIVE_SAVED_STATE(r9) | |
1382 | /* Fixup some of the state for the next load */ | |
1383 | li r10, 0 | |
1384 | li r0, 0xff | |
1385 | stw r10, VCPU_XIVE_PUSHED(r9) | |
1386 | stb r10, (VCPU_XIVE_SAVED_STATE+3)(r9) | |
1387 | stb r0, (VCPU_XIVE_SAVED_STATE+4)(r9) | |
1388 | 1: | |
1389 | #endif /* CONFIG_KVM_XICS */ | |
de56a948 | 1390 | /* Save more register state */ |
de56a948 PM |
1391 | mfdar r6 |
1392 | mfdsisr r7 | |
de56a948 PM |
1393 | std r6, VCPU_DAR(r9) |
1394 | stw r7, VCPU_DSISR(r9) | |
697d3899 | 1395 | /* don't overwrite fault_dar/fault_dsisr if HDSI */ |
de56a948 | 1396 | cmpwi r12,BOOK3S_INTERRUPT_H_DATA_STORAGE |
6af27c84 | 1397 | beq mc_cont |
697d3899 | 1398 | std r6, VCPU_FAULT_DAR(r9) |
de56a948 PM |
1399 | stw r7, VCPU_FAULT_DSISR(r9) |
1400 | ||
b4072df4 PM |
1401 | /* See if it is a machine check */ |
1402 | cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK | |
1403 | beq machine_check_realmode | |
1404 | mc_cont: | |
b6c295df PM |
1405 | #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING |
1406 | addi r3, r9, VCPU_TB_RMEXIT | |
1407 | mr r4, r9 | |
1408 | bl kvmhv_accumulate_time | |
1409 | #endif | |
b4072df4 | 1410 | |
7e022e71 | 1411 | mr r3, r12 |
6af27c84 PM |
1412 | /* Increment exit count, poke other threads to exit */ |
1413 | bl kvmhv_commence_exit | |
eddb60fb PM |
1414 | nop |
1415 | ld r9, HSTATE_KVM_VCPU(r13) | |
1416 | lwz r12, VCPU_TRAP(r9) | |
6af27c84 | 1417 | |
ec257165 PM |
1418 | /* Stop others sending VCPU interrupts to this physical CPU */ |
1419 | li r0, -1 | |
1420 | stw r0, VCPU_CPU(r9) | |
1421 | stw r0, VCPU_THREAD_CPU(r9) | |
1422 | ||
de56a948 | 1423 | /* Save guest CTRL register, set runlatch to 1 */ |
6af27c84 | 1424 | mfspr r6,SPRN_CTRLF |
de56a948 PM |
1425 | stw r6,VCPU_CTRL(r9) |
1426 | andi. r0,r6,1 | |
1427 | bne 4f | |
1428 | ori r6,r6,1 | |
1429 | mtspr SPRN_CTRLT,r6 | |
1430 | 4: | |
1431 | /* Read the guest SLB and save it away */ | |
f4c51f84 PM |
1432 | ld r5, VCPU_KVM(r9) |
1433 | lbz r0, KVM_RADIX(r5) | |
1434 | cmpwi r0, 0 | |
1435 | li r5, 0 | |
1436 | bne 3f /* for radix, save 0 entries */ | |
de56a948 PM |
1437 | lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */ |
1438 | mtctr r0 | |
1439 | li r6,0 | |
1440 | addi r7,r9,VCPU_SLB | |
de56a948 PM |
1441 | 1: slbmfee r8,r6 |
1442 | andis. r0,r8,SLB_ESID_V@h | |
1443 | beq 2f | |
1444 | add r8,r8,r6 /* put index in */ | |
1445 | slbmfev r3,r6 | |
1446 | std r8,VCPU_SLB_E(r7) | |
1447 | std r3,VCPU_SLB_V(r7) | |
1448 | addi r7,r7,VCPU_SLB_SIZE | |
1449 | addi r5,r5,1 | |
1450 | 2: addi r6,r6,1 | |
1451 | bdnz 1b | |
f4c51f84 | 1452 | 3: stw r5,VCPU_SLB_MAX(r9) |
de56a948 PM |
1453 | |
1454 | /* | |
1455 | * Save the guest PURR/SPURR | |
1456 | */ | |
1457 | mfspr r5,SPRN_PURR | |
1458 | mfspr r6,SPRN_SPURR | |
1459 | ld r7,VCPU_PURR(r9) | |
1460 | ld r8,VCPU_SPURR(r9) | |
1461 | std r5,VCPU_PURR(r9) | |
1462 | std r6,VCPU_SPURR(r9) | |
1463 | subf r5,r7,r5 | |
1464 | subf r6,r8,r6 | |
1465 | ||
1466 | /* | |
1467 | * Restore host PURR/SPURR and add guest times | |
1468 | * so that the time in the guest gets accounted. | |
1469 | */ | |
1470 | ld r3,HSTATE_PURR(r13) | |
1471 | ld r4,HSTATE_SPURR(r13) | |
1472 | add r3,r3,r5 | |
1473 | add r4,r4,r6 | |
1474 | mtspr SPRN_PURR,r3 | |
1475 | mtspr SPRN_SPURR,r4 | |
1476 | ||
e0b7ec05 PM |
1477 | /* Save DEC */ |
1478 | mfspr r5,SPRN_DEC | |
1479 | mftb r6 | |
1480 | extsw r5,r5 | |
1481 | add r5,r5,r6 | |
c5fb80d3 PM |
1482 | /* r5 is a guest timebase value here, convert to host TB */ |
1483 | ld r3,HSTATE_KVM_VCORE(r13) | |
1484 | ld r4,VCORE_TB_OFFSET(r3) | |
1485 | subf r5,r4,r5 | |
e0b7ec05 PM |
1486 | std r5,VCPU_DEC_EXPIRES(r9) |
1487 | ||
b005255e MN |
1488 | BEGIN_FTR_SECTION |
1489 | b 8f | |
1490 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) | |
b005255e MN |
1491 | /* Save POWER8-specific registers */ |
1492 | mfspr r5, SPRN_IAMR | |
1493 | mfspr r6, SPRN_PSPB | |
1494 | mfspr r7, SPRN_FSCR | |
1495 | std r5, VCPU_IAMR(r9) | |
1496 | stw r6, VCPU_PSPB(r9) | |
1497 | std r7, VCPU_FSCR(r9) | |
1498 | mfspr r5, SPRN_IC | |
b005255e MN |
1499 | mfspr r7, SPRN_TAR |
1500 | std r5, VCPU_IC(r9) | |
b005255e | 1501 | std r7, VCPU_TAR(r9) |
7b490411 | 1502 | mfspr r8, SPRN_EBBHR |
b005255e MN |
1503 | std r8, VCPU_EBBHR(r9) |
1504 | mfspr r5, SPRN_EBBRR | |
1505 | mfspr r6, SPRN_BESCR | |
83677f55 PM |
1506 | mfspr r7, SPRN_PID |
1507 | mfspr r8, SPRN_WORT | |
b005255e MN |
1508 | std r5, VCPU_EBBRR(r9) |
1509 | std r6, VCPU_BESCR(r9) | |
83677f55 PM |
1510 | stw r7, VCPU_GUEST_PID(r9) |
1511 | std r8, VCPU_WORT(r9) | |
1512 | BEGIN_FTR_SECTION | |
b005255e MN |
1513 | mfspr r5, SPRN_TCSCR |
1514 | mfspr r6, SPRN_ACOP | |
83677f55 PM |
1515 | mfspr r7, SPRN_CSIGR |
1516 | mfspr r8, SPRN_TACR | |
b005255e MN |
1517 | std r5, VCPU_TCSCR(r9) |
1518 | std r6, VCPU_ACOP(r9) | |
83677f55 PM |
1519 | std r7, VCPU_CSIGR(r9) |
1520 | std r8, VCPU_TACR(r9) | |
e9cf1e08 PM |
1521 | FTR_SECTION_ELSE |
1522 | mfspr r5, SPRN_TIDR | |
1523 | mfspr r6, SPRN_PSSCR | |
1524 | std r5, VCPU_TID(r9) | |
1525 | rldicl r6, r6, 4, 50 /* r6 &= PSSCR_GUEST_VIS */ | |
1526 | rotldi r6, r6, 60 | |
1527 | std r6, VCPU_PSSCR(r9) | |
1528 | ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300) | |
ccec4456 PM |
1529 | /* |
1530 | * Restore various registers to 0, where non-zero values | |
1531 | * set by the guest could disrupt the host. | |
1532 | */ | |
1533 | li r0, 0 | |
4c3bb4cc | 1534 | mtspr SPRN_PSPB, r0 |
ccec4456 | 1535 | mtspr SPRN_WORT, r0 |
83677f55 | 1536 | BEGIN_FTR_SECTION |
4c3bb4cc | 1537 | mtspr SPRN_IAMR, r0 |
83677f55 | 1538 | mtspr SPRN_TCSCR, r0 |
ccec4456 PM |
1539 | /* Set MMCRS to 1<<31 to freeze and disable the SPMC counters */ |
1540 | li r0, 1 | |
1541 | sldi r0, r0, 31 | |
1542 | mtspr SPRN_MMCRS, r0 | |
83677f55 | 1543 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300) |
b005255e MN |
1544 | 8: |
1545 | ||
e0b7ec05 | 1546 | /* Save and reset AMR and UAMOR before turning on the MMU */ |
e0b7ec05 PM |
1547 | mfspr r5,SPRN_AMR |
1548 | mfspr r6,SPRN_UAMOR | |
1549 | std r5,VCPU_AMR(r9) | |
1550 | std r6,VCPU_UAMOR(r9) | |
1551 | li r6,0 | |
1552 | mtspr SPRN_AMR,r6 | |
4c3bb4cc | 1553 | mtspr SPRN_UAMOR, r6 |
e0b7ec05 PM |
1554 | |
1555 | /* Switch DSCR back to host value */ | |
e0b7ec05 PM |
1556 | mfspr r8, SPRN_DSCR |
1557 | ld r7, HSTATE_DSCR(r13) | |
1558 | std r8, VCPU_DSCR(r9) | |
1559 | mtspr SPRN_DSCR, r7 | |
e0b7ec05 PM |
1560 | |
1561 | /* Save non-volatile GPRs */ | |
1562 | std r14, VCPU_GPR(R14)(r9) | |
1563 | std r15, VCPU_GPR(R15)(r9) | |
1564 | std r16, VCPU_GPR(R16)(r9) | |
1565 | std r17, VCPU_GPR(R17)(r9) | |
1566 | std r18, VCPU_GPR(R18)(r9) | |
1567 | std r19, VCPU_GPR(R19)(r9) | |
1568 | std r20, VCPU_GPR(R20)(r9) | |
1569 | std r21, VCPU_GPR(R21)(r9) | |
1570 | std r22, VCPU_GPR(R22)(r9) | |
1571 | std r23, VCPU_GPR(R23)(r9) | |
1572 | std r24, VCPU_GPR(R24)(r9) | |
1573 | std r25, VCPU_GPR(R25)(r9) | |
1574 | std r26, VCPU_GPR(R26)(r9) | |
1575 | std r27, VCPU_GPR(R27)(r9) | |
1576 | std r28, VCPU_GPR(R28)(r9) | |
1577 | std r29, VCPU_GPR(R29)(r9) | |
1578 | std r30, VCPU_GPR(R30)(r9) | |
1579 | std r31, VCPU_GPR(R31)(r9) | |
1580 | ||
1581 | /* Save SPRGs */ | |
1582 | mfspr r3, SPRN_SPRG0 | |
1583 | mfspr r4, SPRN_SPRG1 | |
1584 | mfspr r5, SPRN_SPRG2 | |
1585 | mfspr r6, SPRN_SPRG3 | |
1586 | std r3, VCPU_SPRG0(r9) | |
1587 | std r4, VCPU_SPRG1(r9) | |
1588 | std r5, VCPU_SPRG2(r9) | |
1589 | std r6, VCPU_SPRG3(r9) | |
1590 | ||
1591 | /* save FP state */ | |
1592 | mr r3, r9 | |
1593 | bl kvmppc_save_fp | |
de56a948 | 1594 | |
0a8eccef PM |
1595 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1596 | BEGIN_FTR_SECTION | |
f024ee09 PM |
1597 | bl kvmppc_save_tm |
1598 | END_FTR_SECTION_IFSET(CPU_FTR_TM) | |
0a8eccef PM |
1599 | #endif |
1600 | ||
e0b7ec05 PM |
1601 | /* Increment yield count if they have a VPA */ |
1602 | ld r8, VCPU_VPA(r9) /* do they have a VPA? */ | |
1603 | cmpdi r8, 0 | |
1604 | beq 25f | |
0865a583 AG |
1605 | li r4, LPPACA_YIELDCOUNT |
1606 | LWZX_BE r3, r8, r4 | |
e0b7ec05 | 1607 | addi r3, r3, 1 |
0865a583 | 1608 | STWX_BE r3, r8, r4 |
e0b7ec05 PM |
1609 | li r3, 1 |
1610 | stb r3, VCPU_VPA_DIRTY(r9) | |
1611 | 25: | |
1612 | /* Save PMU registers if requested */ | |
1613 | /* r8 and cr0.eq are live here */ | |
9bc01a9b PM |
1614 | BEGIN_FTR_SECTION |
1615 | /* | |
1616 | * POWER8 seems to have a hardware bug where setting | |
1617 | * MMCR0[PMAE] along with MMCR0[PMC1CE] and/or MMCR0[PMCjCE] | |
1618 | * when some counters are already negative doesn't seem | |
1619 | * to cause a performance monitor alert (and hence interrupt). | |
1620 | * The effect of this is that when saving the PMU state, | |
1621 | * if there is no PMU alert pending when we read MMCR0 | |
1622 | * before freezing the counters, but one becomes pending | |
1623 | * before we read the counters, we lose it. | |
1624 | * To work around this, we need a way to freeze the counters | |
1625 | * before reading MMCR0. Normally, freezing the counters | |
1626 | * is done by writing MMCR0 (to set MMCR0[FC]) which | |
1627 | * unavoidably writes MMCR0[PMA0] as well. On POWER8, | |
1628 | * we can also freeze the counters using MMCR2, by writing | |
1629 | * 1s to all the counter freeze condition bits (there are | |
1630 | * 9 bits each for 6 counters). | |
1631 | */ | |
1632 | li r3, -1 /* set all freeze bits */ | |
1633 | clrrdi r3, r3, 10 | |
1634 | mfspr r10, SPRN_MMCR2 | |
1635 | mtspr SPRN_MMCR2, r3 | |
1636 | isync | |
1637 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) | |
e0b7ec05 PM |
1638 | li r3, 1 |
1639 | sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */ | |
1640 | mfspr r4, SPRN_MMCR0 /* save MMCR0 */ | |
1641 | mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */ | |
1642 | mfspr r6, SPRN_MMCRA | |
c17b98cf | 1643 | /* Clear MMCRA in order to disable SDAR updates */ |
e0b7ec05 PM |
1644 | li r7, 0 |
1645 | mtspr SPRN_MMCRA, r7 | |
e0b7ec05 PM |
1646 | isync |
1647 | beq 21f /* if no VPA, save PMU stuff anyway */ | |
1648 | lbz r7, LPPACA_PMCINUSE(r8) | |
1649 | cmpwi r7, 0 /* did they ask for PMU stuff to be saved? */ | |
1650 | bne 21f | |
1651 | std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */ | |
1652 | b 22f | |
1653 | 21: mfspr r5, SPRN_MMCR1 | |
1654 | mfspr r7, SPRN_SIAR | |
1655 | mfspr r8, SPRN_SDAR | |
1656 | std r4, VCPU_MMCR(r9) | |
1657 | std r5, VCPU_MMCR + 8(r9) | |
1658 | std r6, VCPU_MMCR + 16(r9) | |
9bc01a9b PM |
1659 | BEGIN_FTR_SECTION |
1660 | std r10, VCPU_MMCR + 24(r9) | |
1661 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) | |
e0b7ec05 PM |
1662 | std r7, VCPU_SIAR(r9) |
1663 | std r8, VCPU_SDAR(r9) | |
1664 | mfspr r3, SPRN_PMC1 | |
1665 | mfspr r4, SPRN_PMC2 | |
1666 | mfspr r5, SPRN_PMC3 | |
1667 | mfspr r6, SPRN_PMC4 | |
1668 | mfspr r7, SPRN_PMC5 | |
1669 | mfspr r8, SPRN_PMC6 | |
e0b7ec05 PM |
1670 | stw r3, VCPU_PMC(r9) |
1671 | stw r4, VCPU_PMC + 4(r9) | |
1672 | stw r5, VCPU_PMC + 8(r9) | |
1673 | stw r6, VCPU_PMC + 12(r9) | |
1674 | stw r7, VCPU_PMC + 16(r9) | |
1675 | stw r8, VCPU_PMC + 20(r9) | |
b005255e | 1676 | BEGIN_FTR_SECTION |
b005255e | 1677 | mfspr r5, SPRN_SIER |
83677f55 PM |
1678 | std r5, VCPU_SIER(r9) |
1679 | BEGIN_FTR_SECTION_NESTED(96) | |
b005255e MN |
1680 | mfspr r6, SPRN_SPMC1 |
1681 | mfspr r7, SPRN_SPMC2 | |
1682 | mfspr r8, SPRN_MMCRS | |
b005255e MN |
1683 | stw r6, VCPU_PMC + 24(r9) |
1684 | stw r7, VCPU_PMC + 28(r9) | |
1685 | std r8, VCPU_MMCR + 32(r9) | |
1686 | lis r4, 0x8000 | |
1687 | mtspr SPRN_MMCRS, r4 | |
83677f55 | 1688 | END_FTR_SECTION_NESTED(CPU_FTR_ARCH_300, 0, 96) |
b005255e | 1689 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) |
e0b7ec05 | 1690 | 22: |
de56a948 PM |
1691 | /* Clear out SLB */ |
1692 | li r5,0 | |
1693 | slbmte r5,r5 | |
1694 | slbia | |
1695 | ptesync | |
1696 | ||
e9cf1e08 | 1697 | /* Restore host values of some registers */ |
7ceaa6dc PM |
1698 | BEGIN_FTR_SECTION |
1699 | ld r5, STACK_SLOT_CIABR(r1) | |
1700 | ld r6, STACK_SLOT_DAWR(r1) | |
1701 | ld r7, STACK_SLOT_DAWRX(r1) | |
1702 | mtspr SPRN_CIABR, r5 | |
1703 | mtspr SPRN_DAWR, r6 | |
1704 | mtspr SPRN_DAWRX, r7 | |
1705 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) | |
e9cf1e08 PM |
1706 | BEGIN_FTR_SECTION |
1707 | ld r5, STACK_SLOT_TID(r1) | |
1708 | ld r6, STACK_SLOT_PSSCR(r1) | |
f4c51f84 | 1709 | ld r7, STACK_SLOT_PID(r1) |
4c3bb4cc | 1710 | ld r8, STACK_SLOT_IAMR(r1) |
e9cf1e08 PM |
1711 | mtspr SPRN_TIDR, r5 |
1712 | mtspr SPRN_PSSCR, r6 | |
f4c51f84 | 1713 | mtspr SPRN_PID, r7 |
4c3bb4cc | 1714 | mtspr SPRN_IAMR, r8 |
e9cf1e08 | 1715 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) |
f11f6f79 PM |
1716 | BEGIN_FTR_SECTION |
1717 | PPC_INVALIDATE_ERAT | |
1718 | END_FTR_SECTION_IFSET(CPU_FTR_POWER9_DD1) | |
e9cf1e08 | 1719 | |
9e368f29 | 1720 | /* |
c17b98cf | 1721 | * POWER7/POWER8 guest -> host partition switch code. |
9e368f29 PM |
1722 | * We don't have to lock against tlbies but we do |
1723 | * have to coordinate the hardware threads. | |
1724 | */ | |
b6c295df | 1725 | kvmhv_switch_to_host: |
371fefd6 | 1726 | /* Secondary threads wait for primary to do partition switch */ |
6af27c84 | 1727 | ld r5,HSTATE_KVM_VCORE(r13) |
e0b7ec05 PM |
1728 | ld r4,VCORE_KVM(r5) /* pointer to struct kvm */ |
1729 | lbz r3,HSTATE_PTID(r13) | |
371fefd6 PM |
1730 | cmpwi r3,0 |
1731 | beq 15f | |
1732 | HMT_LOW | |
1733 | 13: lbz r3,VCORE_IN_GUEST(r5) | |
1734 | cmpwi r3,0 | |
1735 | bne 13b | |
1736 | HMT_MEDIUM | |
1737 | b 16f | |
1738 | ||
1739 | /* Primary thread waits for all the secondaries to exit guest */ | |
1740 | 15: lwz r3,VCORE_ENTRY_EXIT(r5) | |
b4deba5c | 1741 | rlwinm r0,r3,32-8,0xff |
371fefd6 PM |
1742 | clrldi r3,r3,56 |
1743 | cmpw r3,r0 | |
1744 | bne 15b | |
1745 | isync | |
1746 | ||
b4deba5c PM |
1747 | /* Did we actually switch to the guest at all? */ |
1748 | lbz r6, VCORE_IN_GUEST(r5) | |
1749 | cmpwi r6, 0 | |
1750 | beq 19f | |
1751 | ||
371fefd6 | 1752 | /* Primary thread switches back to host partition */ |
de56a948 | 1753 | lwz r7,KVM_HOST_LPID(r4) |
7a84084c PM |
1754 | BEGIN_FTR_SECTION |
1755 | ld r6,KVM_HOST_SDR1(r4) | |
de56a948 PM |
1756 | li r8,LPID_RSVD /* switch to reserved LPID */ |
1757 | mtspr SPRN_LPID,r8 | |
1758 | ptesync | |
7a84084c PM |
1759 | mtspr SPRN_SDR1,r6 /* switch to host page table */ |
1760 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300) | |
de56a948 PM |
1761 | mtspr SPRN_LPID,r7 |
1762 | isync | |
93b0f4dc | 1763 | |
b005255e | 1764 | BEGIN_FTR_SECTION |
88b02cf9 | 1765 | /* DPDES and VTB are shared between threads */ |
b005255e | 1766 | mfspr r7, SPRN_DPDES |
88b02cf9 | 1767 | mfspr r8, SPRN_VTB |
b005255e | 1768 | std r7, VCORE_DPDES(r5) |
88b02cf9 | 1769 | std r8, VCORE_VTB(r5) |
b005255e MN |
1770 | /* clear DPDES so we don't get guest doorbells in the host */ |
1771 | li r8, 0 | |
1772 | mtspr SPRN_DPDES, r8 | |
1773 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) | |
1774 | ||
fd7bacbc MS |
1775 | /* If HMI, call kvmppc_realmode_hmi_handler() */ |
1776 | cmpwi r12, BOOK3S_INTERRUPT_HMI | |
1777 | bne 27f | |
1778 | bl kvmppc_realmode_hmi_handler | |
1779 | nop | |
1780 | li r12, BOOK3S_INTERRUPT_HMI | |
1781 | /* | |
1782 | * At this point kvmppc_realmode_hmi_handler would have resync-ed | |
1783 | * the TB. Hence it is not required to subtract guest timebase | |
1784 | * offset from timebase. So, skip it. | |
1785 | * | |
1786 | * Also, do not call kvmppc_subcore_exit_guest() because it has | |
1787 | * been invoked as part of kvmppc_realmode_hmi_handler(). | |
1788 | */ | |
1789 | b 30f | |
1790 | ||
1791 | 27: | |
93b0f4dc PM |
1792 | /* Subtract timebase offset from timebase */ |
1793 | ld r8,VCORE_TB_OFFSET(r5) | |
1794 | cmpdi r8,0 | |
1795 | beq 17f | |
c5fb80d3 | 1796 | mftb r6 /* current guest timebase */ |
93b0f4dc PM |
1797 | subf r8,r8,r6 |
1798 | mtspr SPRN_TBU40,r8 /* update upper 40 bits */ | |
1799 | mftb r7 /* check if lower 24 bits overflowed */ | |
1800 | clrldi r6,r6,40 | |
1801 | clrldi r7,r7,40 | |
1802 | cmpld r7,r6 | |
1803 | bge 17f | |
1804 | addis r8,r8,0x100 /* if so, increment upper 40 bits */ | |
1805 | mtspr SPRN_TBU40,r8 | |
1806 | ||
fd7bacbc MS |
1807 | 17: bl kvmppc_subcore_exit_guest |
1808 | nop | |
1809 | 30: ld r5,HSTATE_KVM_VCORE(r13) | |
1810 | ld r4,VCORE_KVM(r5) /* pointer to struct kvm */ | |
1811 | ||
388cc6e1 | 1812 | /* Reset PCR */ |
fd7bacbc | 1813 | ld r0, VCORE_PCR(r5) |
388cc6e1 PM |
1814 | cmpdi r0, 0 |
1815 | beq 18f | |
1816 | li r0, 0 | |
1817 | mtspr SPRN_PCR, r0 | |
1818 | 18: | |
93b0f4dc | 1819 | /* Signal secondary CPUs to continue */ |
371fefd6 | 1820 | stb r0,VCORE_IN_GUEST(r5) |
b4deba5c | 1821 | 19: lis r8,0x7fff /* MAX_INT@h */ |
de56a948 PM |
1822 | mtspr SPRN_HDEC,r8 |
1823 | ||
371fefd6 | 1824 | 16: ld r8,KVM_HOST_LPCR(r4) |
de56a948 PM |
1825 | mtspr SPRN_LPCR,r8 |
1826 | isync | |
1827 | ||
1828 | /* load host SLB entries */ | |
f4c51f84 PM |
1829 | BEGIN_MMU_FTR_SECTION |
1830 | b 0f | |
1831 | END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX) | |
c17b98cf | 1832 | ld r8,PACA_SLBSHADOWPTR(r13) |
de56a948 PM |
1833 | |
1834 | .rept SLB_NUM_BOLTED | |
0865a583 AG |
1835 | li r3, SLBSHADOW_SAVEAREA |
1836 | LDX_BE r5, r8, r3 | |
1837 | addi r3, r3, 8 | |
1838 | LDX_BE r6, r8, r3 | |
de56a948 PM |
1839 | andis. r7,r5,SLB_ESID_V@h |
1840 | beq 1f | |
1841 | slbmte r6,r5 | |
1842 | 1: addi r8,r8,16 | |
1843 | .endr | |
f4c51f84 | 1844 | 0: |
b6c295df PM |
1845 | #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING |
1846 | /* Finish timing, if we have a vcpu */ | |
1847 | ld r4, HSTATE_KVM_VCPU(r13) | |
1848 | cmpdi r4, 0 | |
1849 | li r3, 0 | |
1850 | beq 2f | |
1851 | bl kvmhv_accumulate_time | |
1852 | 2: | |
1853 | #endif | |
44a3add8 PM |
1854 | /* Unset guest mode */ |
1855 | li r0, KVM_GUEST_MODE_NONE | |
1856 | stb r0, HSTATE_IN_GUEST(r13) | |
1857 | ||
7ceaa6dc PM |
1858 | ld r0, SFS+PPC_LR_STKOFF(r1) |
1859 | addi r1, r1, SFS | |
218309b7 PM |
1860 | mtlr r0 |
1861 | blr | |
b4072df4 | 1862 | |
697d3899 PM |
1863 | /* |
1864 | * Check whether an HDSI is an HPTE not found fault or something else. | |
1865 | * If it is an HPTE not found fault that is due to the guest accessing | |
1866 | * a page that they have mapped but which we have paged out, then | |
1867 | * we continue on with the guest exit path. In all other cases, | |
1868 | * reflect the HDSI to the guest as a DSI. | |
1869 | */ | |
1870 | kvmppc_hdsi: | |
f4c51f84 PM |
1871 | ld r3, VCPU_KVM(r9) |
1872 | lbz r0, KVM_RADIX(r3) | |
1873 | cmpwi r0, 0 | |
697d3899 PM |
1874 | mfspr r4, SPRN_HDAR |
1875 | mfspr r6, SPRN_HDSISR | |
f4c51f84 | 1876 | bne .Lradix_hdsi /* on radix, just save DAR/DSISR/ASDR */ |
4cf302bc PM |
1877 | /* HPTE not found fault or protection fault? */ |
1878 | andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h | |
697d3899 | 1879 | beq 1f /* if not, send it to the guest */ |
4e5acdc2 PM |
1880 | andi. r0, r11, MSR_DR /* data relocation enabled? */ |
1881 | beq 3f | |
ef8c640c PM |
1882 | BEGIN_FTR_SECTION |
1883 | mfspr r5, SPRN_ASDR /* on POWER9, use ASDR to get VSID */ | |
1884 | b 4f | |
1885 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) | |
697d3899 | 1886 | clrrdi r0, r4, 28 |
c75df6f9 | 1887 | PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */ |
cf29b215 PM |
1888 | li r0, BOOK3S_INTERRUPT_DATA_SEGMENT |
1889 | bne 7f /* if no SLB entry found */ | |
697d3899 PM |
1890 | 4: std r4, VCPU_FAULT_DAR(r9) |
1891 | stw r6, VCPU_FAULT_DSISR(r9) | |
1892 | ||
1893 | /* Search the hash table. */ | |
1894 | mr r3, r9 /* vcpu pointer */ | |
342d3db7 | 1895 | li r7, 1 /* data fault */ |
b1576fec | 1896 | bl kvmppc_hpte_hv_fault |
697d3899 PM |
1897 | ld r9, HSTATE_KVM_VCPU(r13) |
1898 | ld r10, VCPU_PC(r9) | |
1899 | ld r11, VCPU_MSR(r9) | |
1900 | li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE | |
1901 | cmpdi r3, 0 /* retry the instruction */ | |
1902 | beq 6f | |
1903 | cmpdi r3, -1 /* handle in kernel mode */ | |
b4072df4 | 1904 | beq guest_exit_cont |
697d3899 PM |
1905 | cmpdi r3, -2 /* MMIO emulation; need instr word */ |
1906 | beq 2f | |
1907 | ||
cf29b215 | 1908 | /* Synthesize a DSI (or DSegI) for the guest */ |
697d3899 PM |
1909 | ld r4, VCPU_FAULT_DAR(r9) |
1910 | mr r6, r3 | |
cf29b215 | 1911 | 1: li r0, BOOK3S_INTERRUPT_DATA_STORAGE |
697d3899 | 1912 | mtspr SPRN_DSISR, r6 |
cf29b215 | 1913 | 7: mtspr SPRN_DAR, r4 |
697d3899 PM |
1914 | mtspr SPRN_SRR0, r10 |
1915 | mtspr SPRN_SRR1, r11 | |
cf29b215 | 1916 | mr r10, r0 |
e4e38121 | 1917 | bl kvmppc_msr_interrupt |
b4072df4 | 1918 | fast_interrupt_c_return: |
697d3899 | 1919 | 6: ld r7, VCPU_CTR(r9) |
c63517c2 | 1920 | ld r8, VCPU_XER(r9) |
697d3899 PM |
1921 | mtctr r7 |
1922 | mtxer r8 | |
1923 | mr r4, r9 | |
1924 | b fast_guest_return | |
1925 | ||
1926 | 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */ | |
1927 | ld r5, KVM_VRMA_SLB_V(r5) | |
1928 | b 4b | |
1929 | ||
1930 | /* If this is for emulated MMIO, load the instruction word */ | |
1931 | 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */ | |
1932 | ||
1933 | /* Set guest mode to 'jump over instruction' so if lwz faults | |
1934 | * we'll just continue at the next IP. */ | |
1935 | li r0, KVM_GUEST_MODE_SKIP | |
1936 | stb r0, HSTATE_IN_GUEST(r13) | |
1937 | ||
1938 | /* Do the access with MSR:DR enabled */ | |
1939 | mfmsr r3 | |
1940 | ori r4, r3, MSR_DR /* Enable paging for data */ | |
1941 | mtmsrd r4 | |
1942 | lwz r8, 0(r10) | |
1943 | mtmsrd r3 | |
1944 | ||
1945 | /* Store the result */ | |
1946 | stw r8, VCPU_LAST_INST(r9) | |
1947 | ||
1948 | /* Unset guest mode. */ | |
44a3add8 | 1949 | li r0, KVM_GUEST_MODE_HOST_HV |
697d3899 | 1950 | stb r0, HSTATE_IN_GUEST(r13) |
b4072df4 | 1951 | b guest_exit_cont |
de56a948 | 1952 | |
f4c51f84 PM |
1953 | .Lradix_hdsi: |
1954 | std r4, VCPU_FAULT_DAR(r9) | |
1955 | stw r6, VCPU_FAULT_DSISR(r9) | |
1956 | .Lradix_hisi: | |
1957 | mfspr r5, SPRN_ASDR | |
1958 | std r5, VCPU_FAULT_GPA(r9) | |
1959 | b guest_exit_cont | |
1960 | ||
342d3db7 PM |
1961 | /* |
1962 | * Similarly for an HISI, reflect it to the guest as an ISI unless | |
1963 | * it is an HPTE not found fault for a page that we have paged out. | |
1964 | */ | |
1965 | kvmppc_hisi: | |
f4c51f84 PM |
1966 | ld r3, VCPU_KVM(r9) |
1967 | lbz r0, KVM_RADIX(r3) | |
1968 | cmpwi r0, 0 | |
1969 | bne .Lradix_hisi /* for radix, just save ASDR */ | |
342d3db7 PM |
1970 | andis. r0, r11, SRR1_ISI_NOPT@h |
1971 | beq 1f | |
4e5acdc2 PM |
1972 | andi. r0, r11, MSR_IR /* instruction relocation enabled? */ |
1973 | beq 3f | |
ef8c640c PM |
1974 | BEGIN_FTR_SECTION |
1975 | mfspr r5, SPRN_ASDR /* on POWER9, use ASDR to get VSID */ | |
1976 | b 4f | |
1977 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) | |
342d3db7 | 1978 | clrrdi r0, r10, 28 |
c75df6f9 | 1979 | PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */ |
cf29b215 PM |
1980 | li r0, BOOK3S_INTERRUPT_INST_SEGMENT |
1981 | bne 7f /* if no SLB entry found */ | |
342d3db7 PM |
1982 | 4: |
1983 | /* Search the hash table. */ | |
1984 | mr r3, r9 /* vcpu pointer */ | |
1985 | mr r4, r10 | |
1986 | mr r6, r11 | |
1987 | li r7, 0 /* instruction fault */ | |
b1576fec | 1988 | bl kvmppc_hpte_hv_fault |
342d3db7 PM |
1989 | ld r9, HSTATE_KVM_VCPU(r13) |
1990 | ld r10, VCPU_PC(r9) | |
1991 | ld r11, VCPU_MSR(r9) | |
1992 | li r12, BOOK3S_INTERRUPT_H_INST_STORAGE | |
1993 | cmpdi r3, 0 /* retry the instruction */ | |
b4072df4 | 1994 | beq fast_interrupt_c_return |
342d3db7 | 1995 | cmpdi r3, -1 /* handle in kernel mode */ |
b4072df4 | 1996 | beq guest_exit_cont |
342d3db7 | 1997 | |
cf29b215 | 1998 | /* Synthesize an ISI (or ISegI) for the guest */ |
342d3db7 | 1999 | mr r11, r3 |
cf29b215 PM |
2000 | 1: li r0, BOOK3S_INTERRUPT_INST_STORAGE |
2001 | 7: mtspr SPRN_SRR0, r10 | |
342d3db7 | 2002 | mtspr SPRN_SRR1, r11 |
cf29b215 | 2003 | mr r10, r0 |
e4e38121 | 2004 | bl kvmppc_msr_interrupt |
b4072df4 | 2005 | b fast_interrupt_c_return |
342d3db7 PM |
2006 | |
2007 | 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */ | |
2008 | ld r5, KVM_VRMA_SLB_V(r6) | |
2009 | b 4b | |
2010 | ||
a8606e20 PM |
2011 | /* |
2012 | * Try to handle an hcall in real mode. | |
2013 | * Returns to the guest if we handle it, or continues on up to | |
2014 | * the kernel if we can't (i.e. if we don't have a handler for | |
2015 | * it, or if the handler returns H_TOO_HARD). | |
1f09c3ed PM |
2016 | * |
2017 | * r5 - r8 contain hcall args, | |
2018 | * r9 = vcpu, r10 = pc, r11 = msr, r12 = trap, r13 = paca | |
a8606e20 | 2019 | */ |
a8606e20 | 2020 | hcall_try_real_mode: |
c75df6f9 | 2021 | ld r3,VCPU_GPR(R3)(r9) |
a8606e20 | 2022 | andi. r0,r11,MSR_PR |
27025a60 LPF |
2023 | /* sc 1 from userspace - reflect to guest syscall */ |
2024 | bne sc_1_fast_return | |
a8606e20 PM |
2025 | clrrdi r3,r3,2 |
2026 | cmpldi r3,hcall_real_table_end - hcall_real_table | |
b4072df4 | 2027 | bge guest_exit_cont |
699a0ea0 PM |
2028 | /* See if this hcall is enabled for in-kernel handling */ |
2029 | ld r4, VCPU_KVM(r9) | |
2030 | srdi r0, r3, 8 /* r0 = (r3 / 4) >> 6 */ | |
2031 | sldi r0, r0, 3 /* index into kvm->arch.enabled_hcalls[] */ | |
2032 | add r4, r4, r0 | |
2033 | ld r0, KVM_ENABLED_HCALLS(r4) | |
2034 | rlwinm r4, r3, 32-2, 0x3f /* r4 = (r3 / 4) & 0x3f */ | |
2035 | srd r0, r0, r4 | |
2036 | andi. r0, r0, 1 | |
2037 | beq guest_exit_cont | |
2038 | /* Get pointer to handler, if any, and call it */ | |
a8606e20 | 2039 | LOAD_REG_ADDR(r4, hcall_real_table) |
4baa1d87 | 2040 | lwax r3,r3,r4 |
a8606e20 | 2041 | cmpwi r3,0 |
b4072df4 | 2042 | beq guest_exit_cont |
05a308c7 AB |
2043 | add r12,r3,r4 |
2044 | mtctr r12 | |
a8606e20 | 2045 | mr r3,r9 /* get vcpu pointer */ |
c75df6f9 | 2046 | ld r4,VCPU_GPR(R4)(r9) |
a8606e20 PM |
2047 | bctrl |
2048 | cmpdi r3,H_TOO_HARD | |
2049 | beq hcall_real_fallback | |
2050 | ld r4,HSTATE_KVM_VCPU(r13) | |
c75df6f9 | 2051 | std r3,VCPU_GPR(R3)(r4) |
a8606e20 PM |
2052 | ld r10,VCPU_PC(r4) |
2053 | ld r11,VCPU_MSR(r4) | |
2054 | b fast_guest_return | |
2055 | ||
27025a60 LPF |
2056 | sc_1_fast_return: |
2057 | mtspr SPRN_SRR0,r10 | |
2058 | mtspr SPRN_SRR1,r11 | |
2059 | li r10, BOOK3S_INTERRUPT_SYSCALL | |
e4e38121 | 2060 | bl kvmppc_msr_interrupt |
27025a60 LPF |
2061 | mr r4,r9 |
2062 | b fast_guest_return | |
2063 | ||
a8606e20 PM |
2064 | /* We've attempted a real mode hcall, but it's punted it back |
2065 | * to userspace. We need to restore some clobbered volatiles | |
2066 | * before resuming the pass-it-to-qemu path */ | |
2067 | hcall_real_fallback: | |
2068 | li r12,BOOK3S_INTERRUPT_SYSCALL | |
2069 | ld r9, HSTATE_KVM_VCPU(r13) | |
a8606e20 | 2070 | |
b4072df4 | 2071 | b guest_exit_cont |
a8606e20 PM |
2072 | |
2073 | .globl hcall_real_table | |
2074 | hcall_real_table: | |
2075 | .long 0 /* 0 - unused */ | |
c1fb0194 AB |
2076 | .long DOTSYM(kvmppc_h_remove) - hcall_real_table |
2077 | .long DOTSYM(kvmppc_h_enter) - hcall_real_table | |
2078 | .long DOTSYM(kvmppc_h_read) - hcall_real_table | |
cdeee518 PM |
2079 | .long DOTSYM(kvmppc_h_clear_mod) - hcall_real_table |
2080 | .long DOTSYM(kvmppc_h_clear_ref) - hcall_real_table | |
c1fb0194 AB |
2081 | .long DOTSYM(kvmppc_h_protect) - hcall_real_table |
2082 | .long DOTSYM(kvmppc_h_get_tce) - hcall_real_table | |
31217db7 | 2083 | .long DOTSYM(kvmppc_rm_h_put_tce) - hcall_real_table |
a8606e20 | 2084 | .long 0 /* 0x24 - H_SET_SPRG0 */ |
c1fb0194 | 2085 | .long DOTSYM(kvmppc_h_set_dabr) - hcall_real_table |
a8606e20 PM |
2086 | .long 0 /* 0x2c */ |
2087 | .long 0 /* 0x30 */ | |
2088 | .long 0 /* 0x34 */ | |
2089 | .long 0 /* 0x38 */ | |
2090 | .long 0 /* 0x3c */ | |
2091 | .long 0 /* 0x40 */ | |
2092 | .long 0 /* 0x44 */ | |
2093 | .long 0 /* 0x48 */ | |
2094 | .long 0 /* 0x4c */ | |
2095 | .long 0 /* 0x50 */ | |
2096 | .long 0 /* 0x54 */ | |
2097 | .long 0 /* 0x58 */ | |
2098 | .long 0 /* 0x5c */ | |
2099 | .long 0 /* 0x60 */ | |
e7d26f28 | 2100 | #ifdef CONFIG_KVM_XICS |
c1fb0194 AB |
2101 | .long DOTSYM(kvmppc_rm_h_eoi) - hcall_real_table |
2102 | .long DOTSYM(kvmppc_rm_h_cppr) - hcall_real_table | |
2103 | .long DOTSYM(kvmppc_rm_h_ipi) - hcall_real_table | |
5af50993 | 2104 | .long DOTSYM(kvmppc_rm_h_ipoll) - hcall_real_table |
c1fb0194 | 2105 | .long DOTSYM(kvmppc_rm_h_xirr) - hcall_real_table |
e7d26f28 BH |
2106 | #else |
2107 | .long 0 /* 0x64 - H_EOI */ | |
2108 | .long 0 /* 0x68 - H_CPPR */ | |
2109 | .long 0 /* 0x6c - H_IPI */ | |
2110 | .long 0 /* 0x70 - H_IPOLL */ | |
2111 | .long 0 /* 0x74 - H_XIRR */ | |
2112 | #endif | |
a8606e20 PM |
2113 | .long 0 /* 0x78 */ |
2114 | .long 0 /* 0x7c */ | |
2115 | .long 0 /* 0x80 */ | |
2116 | .long 0 /* 0x84 */ | |
2117 | .long 0 /* 0x88 */ | |
2118 | .long 0 /* 0x8c */ | |
2119 | .long 0 /* 0x90 */ | |
2120 | .long 0 /* 0x94 */ | |
2121 | .long 0 /* 0x98 */ | |
2122 | .long 0 /* 0x9c */ | |
2123 | .long 0 /* 0xa0 */ | |
2124 | .long 0 /* 0xa4 */ | |
2125 | .long 0 /* 0xa8 */ | |
2126 | .long 0 /* 0xac */ | |
2127 | .long 0 /* 0xb0 */ | |
2128 | .long 0 /* 0xb4 */ | |
2129 | .long 0 /* 0xb8 */ | |
2130 | .long 0 /* 0xbc */ | |
2131 | .long 0 /* 0xc0 */ | |
2132 | .long 0 /* 0xc4 */ | |
2133 | .long 0 /* 0xc8 */ | |
2134 | .long 0 /* 0xcc */ | |
2135 | .long 0 /* 0xd0 */ | |
2136 | .long 0 /* 0xd4 */ | |
2137 | .long 0 /* 0xd8 */ | |
2138 | .long 0 /* 0xdc */ | |
c1fb0194 | 2139 | .long DOTSYM(kvmppc_h_cede) - hcall_real_table |
90fd09f8 | 2140 | .long DOTSYM(kvmppc_rm_h_confer) - hcall_real_table |
a8606e20 PM |
2141 | .long 0 /* 0xe8 */ |
2142 | .long 0 /* 0xec */ | |
2143 | .long 0 /* 0xf0 */ | |
2144 | .long 0 /* 0xf4 */ | |
2145 | .long 0 /* 0xf8 */ | |
2146 | .long 0 /* 0xfc */ | |
2147 | .long 0 /* 0x100 */ | |
2148 | .long 0 /* 0x104 */ | |
2149 | .long 0 /* 0x108 */ | |
2150 | .long 0 /* 0x10c */ | |
2151 | .long 0 /* 0x110 */ | |
2152 | .long 0 /* 0x114 */ | |
2153 | .long 0 /* 0x118 */ | |
2154 | .long 0 /* 0x11c */ | |
2155 | .long 0 /* 0x120 */ | |
c1fb0194 | 2156 | .long DOTSYM(kvmppc_h_bulk_remove) - hcall_real_table |
8563bf52 PM |
2157 | .long 0 /* 0x128 */ |
2158 | .long 0 /* 0x12c */ | |
2159 | .long 0 /* 0x130 */ | |
c1fb0194 | 2160 | .long DOTSYM(kvmppc_h_set_xdabr) - hcall_real_table |
31217db7 | 2161 | .long DOTSYM(kvmppc_rm_h_stuff_tce) - hcall_real_table |
d3695aa4 | 2162 | .long DOTSYM(kvmppc_rm_h_put_tce_indirect) - hcall_real_table |
e928e9cb ME |
2163 | .long 0 /* 0x140 */ |
2164 | .long 0 /* 0x144 */ | |
2165 | .long 0 /* 0x148 */ | |
2166 | .long 0 /* 0x14c */ | |
2167 | .long 0 /* 0x150 */ | |
2168 | .long 0 /* 0x154 */ | |
2169 | .long 0 /* 0x158 */ | |
2170 | .long 0 /* 0x15c */ | |
2171 | .long 0 /* 0x160 */ | |
2172 | .long 0 /* 0x164 */ | |
2173 | .long 0 /* 0x168 */ | |
2174 | .long 0 /* 0x16c */ | |
2175 | .long 0 /* 0x170 */ | |
2176 | .long 0 /* 0x174 */ | |
2177 | .long 0 /* 0x178 */ | |
2178 | .long 0 /* 0x17c */ | |
2179 | .long 0 /* 0x180 */ | |
2180 | .long 0 /* 0x184 */ | |
2181 | .long 0 /* 0x188 */ | |
2182 | .long 0 /* 0x18c */ | |
2183 | .long 0 /* 0x190 */ | |
2184 | .long 0 /* 0x194 */ | |
2185 | .long 0 /* 0x198 */ | |
2186 | .long 0 /* 0x19c */ | |
2187 | .long 0 /* 0x1a0 */ | |
2188 | .long 0 /* 0x1a4 */ | |
2189 | .long 0 /* 0x1a8 */ | |
2190 | .long 0 /* 0x1ac */ | |
2191 | .long 0 /* 0x1b0 */ | |
2192 | .long 0 /* 0x1b4 */ | |
2193 | .long 0 /* 0x1b8 */ | |
2194 | .long 0 /* 0x1bc */ | |
2195 | .long 0 /* 0x1c0 */ | |
2196 | .long 0 /* 0x1c4 */ | |
2197 | .long 0 /* 0x1c8 */ | |
2198 | .long 0 /* 0x1cc */ | |
2199 | .long 0 /* 0x1d0 */ | |
2200 | .long 0 /* 0x1d4 */ | |
2201 | .long 0 /* 0x1d8 */ | |
2202 | .long 0 /* 0x1dc */ | |
2203 | .long 0 /* 0x1e0 */ | |
2204 | .long 0 /* 0x1e4 */ | |
2205 | .long 0 /* 0x1e8 */ | |
2206 | .long 0 /* 0x1ec */ | |
2207 | .long 0 /* 0x1f0 */ | |
2208 | .long 0 /* 0x1f4 */ | |
2209 | .long 0 /* 0x1f8 */ | |
2210 | .long 0 /* 0x1fc */ | |
2211 | .long 0 /* 0x200 */ | |
2212 | .long 0 /* 0x204 */ | |
2213 | .long 0 /* 0x208 */ | |
2214 | .long 0 /* 0x20c */ | |
2215 | .long 0 /* 0x210 */ | |
2216 | .long 0 /* 0x214 */ | |
2217 | .long 0 /* 0x218 */ | |
2218 | .long 0 /* 0x21c */ | |
2219 | .long 0 /* 0x220 */ | |
2220 | .long 0 /* 0x224 */ | |
2221 | .long 0 /* 0x228 */ | |
2222 | .long 0 /* 0x22c */ | |
2223 | .long 0 /* 0x230 */ | |
2224 | .long 0 /* 0x234 */ | |
2225 | .long 0 /* 0x238 */ | |
2226 | .long 0 /* 0x23c */ | |
2227 | .long 0 /* 0x240 */ | |
2228 | .long 0 /* 0x244 */ | |
2229 | .long 0 /* 0x248 */ | |
2230 | .long 0 /* 0x24c */ | |
2231 | .long 0 /* 0x250 */ | |
2232 | .long 0 /* 0x254 */ | |
2233 | .long 0 /* 0x258 */ | |
2234 | .long 0 /* 0x25c */ | |
2235 | .long 0 /* 0x260 */ | |
2236 | .long 0 /* 0x264 */ | |
2237 | .long 0 /* 0x268 */ | |
2238 | .long 0 /* 0x26c */ | |
2239 | .long 0 /* 0x270 */ | |
2240 | .long 0 /* 0x274 */ | |
2241 | .long 0 /* 0x278 */ | |
2242 | .long 0 /* 0x27c */ | |
2243 | .long 0 /* 0x280 */ | |
2244 | .long 0 /* 0x284 */ | |
2245 | .long 0 /* 0x288 */ | |
2246 | .long 0 /* 0x28c */ | |
2247 | .long 0 /* 0x290 */ | |
2248 | .long 0 /* 0x294 */ | |
2249 | .long 0 /* 0x298 */ | |
2250 | .long 0 /* 0x29c */ | |
2251 | .long 0 /* 0x2a0 */ | |
2252 | .long 0 /* 0x2a4 */ | |
2253 | .long 0 /* 0x2a8 */ | |
2254 | .long 0 /* 0x2ac */ | |
2255 | .long 0 /* 0x2b0 */ | |
2256 | .long 0 /* 0x2b4 */ | |
2257 | .long 0 /* 0x2b8 */ | |
2258 | .long 0 /* 0x2bc */ | |
2259 | .long 0 /* 0x2c0 */ | |
2260 | .long 0 /* 0x2c4 */ | |
2261 | .long 0 /* 0x2c8 */ | |
2262 | .long 0 /* 0x2cc */ | |
2263 | .long 0 /* 0x2d0 */ | |
2264 | .long 0 /* 0x2d4 */ | |
2265 | .long 0 /* 0x2d8 */ | |
2266 | .long 0 /* 0x2dc */ | |
2267 | .long 0 /* 0x2e0 */ | |
2268 | .long 0 /* 0x2e4 */ | |
2269 | .long 0 /* 0x2e8 */ | |
2270 | .long 0 /* 0x2ec */ | |
2271 | .long 0 /* 0x2f0 */ | |
2272 | .long 0 /* 0x2f4 */ | |
2273 | .long 0 /* 0x2f8 */ | |
5af50993 BH |
2274 | #ifdef CONFIG_KVM_XICS |
2275 | .long DOTSYM(kvmppc_rm_h_xirr_x) - hcall_real_table | |
2276 | #else | |
2277 | .long 0 /* 0x2fc - H_XIRR_X*/ | |
2278 | #endif | |
e928e9cb | 2279 | .long DOTSYM(kvmppc_h_random) - hcall_real_table |
ae2113a4 | 2280 | .globl hcall_real_table_end |
a8606e20 PM |
2281 | hcall_real_table_end: |
2282 | ||
8563bf52 PM |
2283 | _GLOBAL(kvmppc_h_set_xdabr) |
2284 | andi. r0, r5, DABRX_USER | DABRX_KERNEL | |
2285 | beq 6f | |
2286 | li r0, DABRX_USER | DABRX_KERNEL | DABRX_BTI | |
2287 | andc. r0, r5, r0 | |
2288 | beq 3f | |
2289 | 6: li r3, H_PARAMETER | |
2290 | blr | |
2291 | ||
a8606e20 | 2292 | _GLOBAL(kvmppc_h_set_dabr) |
8563bf52 PM |
2293 | li r5, DABRX_USER | DABRX_KERNEL |
2294 | 3: | |
eee7ff9d MN |
2295 | BEGIN_FTR_SECTION |
2296 | b 2f | |
2297 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) | |
a8606e20 | 2298 | std r4,VCPU_DABR(r3) |
8563bf52 PM |
2299 | stw r5, VCPU_DABRX(r3) |
2300 | mtspr SPRN_DABRX, r5 | |
8943633c PM |
2301 | /* Work around P7 bug where DABR can get corrupted on mtspr */ |
2302 | 1: mtspr SPRN_DABR,r4 | |
2303 | mfspr r5, SPRN_DABR | |
2304 | cmpd r4, r5 | |
2305 | bne 1b | |
2306 | isync | |
a8606e20 PM |
2307 | li r3,0 |
2308 | blr | |
2309 | ||
8563bf52 PM |
2310 | /* Emulate H_SET_DABR/X on P8 for the sake of compat mode guests */ |
2311 | 2: rlwimi r5, r4, 5, DAWRX_DR | DAWRX_DW | |
760a7364 | 2312 | rlwimi r5, r4, 2, DAWRX_WT |
8563bf52 PM |
2313 | clrrdi r4, r4, 3 |
2314 | std r4, VCPU_DAWR(r3) | |
2315 | std r5, VCPU_DAWRX(r3) | |
2316 | mtspr SPRN_DAWR, r4 | |
2317 | mtspr SPRN_DAWRX, r5 | |
2318 | li r3, 0 | |
a8606e20 PM |
2319 | blr |
2320 | ||
1f09c3ed | 2321 | _GLOBAL(kvmppc_h_cede) /* r3 = vcpu pointer, r11 = msr, r13 = paca */ |
19ccb76a PM |
2322 | ori r11,r11,MSR_EE |
2323 | std r11,VCPU_MSR(r3) | |
2324 | li r0,1 | |
2325 | stb r0,VCPU_CEDED(r3) | |
2326 | sync /* order setting ceded vs. testing prodded */ | |
2327 | lbz r5,VCPU_PRODDED(r3) | |
2328 | cmpwi r5,0 | |
04f995a5 | 2329 | bne kvm_cede_prodded |
6af27c84 PM |
2330 | li r12,0 /* set trap to 0 to say hcall is handled */ |
2331 | stw r12,VCPU_TRAP(r3) | |
19ccb76a | 2332 | li r0,H_SUCCESS |
c75df6f9 | 2333 | std r0,VCPU_GPR(R3)(r3) |
19ccb76a PM |
2334 | |
2335 | /* | |
2336 | * Set our bit in the bitmask of napping threads unless all the | |
2337 | * other threads are already napping, in which case we send this | |
2338 | * up to the host. | |
2339 | */ | |
2340 | ld r5,HSTATE_KVM_VCORE(r13) | |
e0b7ec05 | 2341 | lbz r6,HSTATE_PTID(r13) |
19ccb76a PM |
2342 | lwz r8,VCORE_ENTRY_EXIT(r5) |
2343 | clrldi r8,r8,56 | |
2344 | li r0,1 | |
2345 | sld r0,r0,r6 | |
2346 | addi r6,r5,VCORE_NAPPING_THREADS | |
2347 | 31: lwarx r4,0,r6 | |
2348 | or r4,r4,r0 | |
7d6c40da PM |
2349 | cmpw r4,r8 |
2350 | beq kvm_cede_exit | |
19ccb76a PM |
2351 | stwcx. r4,0,r6 |
2352 | bne 31b | |
7d6c40da | 2353 | /* order napping_threads update vs testing entry_exit_map */ |
f019b7ad | 2354 | isync |
e0b7ec05 | 2355 | li r0,NAPPING_CEDE |
19ccb76a | 2356 | stb r0,HSTATE_NAPPING(r13) |
19ccb76a PM |
2357 | lwz r7,VCORE_ENTRY_EXIT(r5) |
2358 | cmpwi r7,0x100 | |
2359 | bge 33f /* another thread already exiting */ | |
2360 | ||
2361 | /* | |
2362 | * Although not specifically required by the architecture, POWER7 | |
2363 | * preserves the following registers in nap mode, even if an SMT mode | |
2364 | * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3, | |
2365 | * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR. | |
2366 | */ | |
2367 | /* Save non-volatile GPRs */ | |
c75df6f9 MN |
2368 | std r14, VCPU_GPR(R14)(r3) |
2369 | std r15, VCPU_GPR(R15)(r3) | |
2370 | std r16, VCPU_GPR(R16)(r3) | |
2371 | std r17, VCPU_GPR(R17)(r3) | |
2372 | std r18, VCPU_GPR(R18)(r3) | |
2373 | std r19, VCPU_GPR(R19)(r3) | |
2374 | std r20, VCPU_GPR(R20)(r3) | |
2375 | std r21, VCPU_GPR(R21)(r3) | |
2376 | std r22, VCPU_GPR(R22)(r3) | |
2377 | std r23, VCPU_GPR(R23)(r3) | |
2378 | std r24, VCPU_GPR(R24)(r3) | |
2379 | std r25, VCPU_GPR(R25)(r3) | |
2380 | std r26, VCPU_GPR(R26)(r3) | |
2381 | std r27, VCPU_GPR(R27)(r3) | |
2382 | std r28, VCPU_GPR(R28)(r3) | |
2383 | std r29, VCPU_GPR(R29)(r3) | |
2384 | std r30, VCPU_GPR(R30)(r3) | |
2385 | std r31, VCPU_GPR(R31)(r3) | |
19ccb76a PM |
2386 | |
2387 | /* save FP state */ | |
595e4f7e | 2388 | bl kvmppc_save_fp |
19ccb76a | 2389 | |
93d17397 PM |
2390 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
2391 | BEGIN_FTR_SECTION | |
2392 | ld r9, HSTATE_KVM_VCPU(r13) | |
2393 | bl kvmppc_save_tm | |
2394 | END_FTR_SECTION_IFSET(CPU_FTR_TM) | |
2395 | #endif | |
2396 | ||
fd6d53b1 PM |
2397 | /* |
2398 | * Set DEC to the smaller of DEC and HDEC, so that we wake | |
2399 | * no later than the end of our timeslice (HDEC interrupts | |
2400 | * don't wake us from nap). | |
2401 | */ | |
2402 | mfspr r3, SPRN_DEC | |
2403 | mfspr r4, SPRN_HDEC | |
2404 | mftb r5 | |
2f272463 PM |
2405 | extsw r3, r3 |
2406 | EXTEND_HDEC(r4) | |
2407 | cmpd r3, r4 | |
fd6d53b1 PM |
2408 | ble 67f |
2409 | mtspr SPRN_DEC, r4 | |
2410 | 67: | |
2411 | /* save expiry time of guest decrementer */ | |
fd6d53b1 PM |
2412 | add r3, r3, r5 |
2413 | ld r4, HSTATE_KVM_VCPU(r13) | |
2414 | ld r5, HSTATE_KVM_VCORE(r13) | |
2415 | ld r6, VCORE_TB_OFFSET(r5) | |
2416 | subf r3, r6, r3 /* convert to host TB value */ | |
2417 | std r3, VCPU_DEC_EXPIRES(r4) | |
2418 | ||
b6c295df PM |
2419 | #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING |
2420 | ld r4, HSTATE_KVM_VCPU(r13) | |
2421 | addi r3, r4, VCPU_TB_CEDE | |
2422 | bl kvmhv_accumulate_time | |
2423 | #endif | |
2424 | ||
ccc07772 PM |
2425 | lis r3, LPCR_PECEDP@h /* Do wake on privileged doorbell */ |
2426 | ||
19ccb76a | 2427 | /* |
aa31e843 | 2428 | * Take a nap until a decrementer or external or doobell interrupt |
ccc07772 | 2429 | * occurs, with PECE1 and PECE0 set in LPCR. |
66feed61 | 2430 | * On POWER8, set PECEDH, and if we are ceding, also set PECEDP. |
ccc07772 | 2431 | * Also clear the runlatch bit before napping. |
19ccb76a | 2432 | */ |
56548fc0 | 2433 | kvm_do_nap: |
1f09c3ed PM |
2434 | mfspr r0, SPRN_CTRLF |
2435 | clrrdi r0, r0, 1 | |
2436 | mtspr SPRN_CTRLT, r0 | |
582b910e | 2437 | |
f0888f70 PM |
2438 | li r0,1 |
2439 | stb r0,HSTATE_HWTHREAD_REQ(r13) | |
19ccb76a PM |
2440 | mfspr r5,SPRN_LPCR |
2441 | ori r5,r5,LPCR_PECE0 | LPCR_PECE1 | |
aa31e843 | 2442 | BEGIN_FTR_SECTION |
66feed61 | 2443 | ori r5, r5, LPCR_PECEDH |
ccc07772 | 2444 | rlwimi r5, r3, 0, LPCR_PECEDP |
aa31e843 | 2445 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) |
bf53c88e PM |
2446 | |
2447 | kvm_nap_sequence: /* desired LPCR value in r5 */ | |
2448 | BEGIN_FTR_SECTION | |
2449 | /* | |
2450 | * PSSCR bits: exit criterion = 1 (wakeup based on LPCR at sreset) | |
2451 | * enable state loss = 1 (allow SMT mode switch) | |
2452 | * requested level = 0 (just stop dispatching) | |
2453 | */ | |
2454 | lis r3, (PSSCR_EC | PSSCR_ESL)@h | |
2455 | mtspr SPRN_PSSCR, r3 | |
2456 | /* Set LPCR_PECE_HVEE bit to enable wakeup by HV interrupts */ | |
2457 | li r4, LPCR_PECE_HVEE@higher | |
2458 | sldi r4, r4, 32 | |
2459 | or r5, r5, r4 | |
2460 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) | |
19ccb76a PM |
2461 | mtspr SPRN_LPCR,r5 |
2462 | isync | |
2463 | li r0, 0 | |
2464 | std r0, HSTATE_SCRATCH0(r13) | |
2465 | ptesync | |
2466 | ld r0, HSTATE_SCRATCH0(r13) | |
2467 | 1: cmpd r0, r0 | |
2468 | bne 1b | |
bf53c88e | 2469 | BEGIN_FTR_SECTION |
19ccb76a | 2470 | nap |
bf53c88e PM |
2471 | FTR_SECTION_ELSE |
2472 | PPC_STOP | |
2473 | ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300) | |
19ccb76a PM |
2474 | b . |
2475 | ||
e3bbbbfa PM |
2476 | 33: mr r4, r3 |
2477 | li r3, 0 | |
2478 | li r12, 0 | |
2479 | b 34f | |
2480 | ||
19ccb76a | 2481 | kvm_end_cede: |
4619ac88 PM |
2482 | /* get vcpu pointer */ |
2483 | ld r4, HSTATE_KVM_VCPU(r13) | |
2484 | ||
19ccb76a PM |
2485 | /* Woken by external or decrementer interrupt */ |
2486 | ld r1, HSTATE_HOST_R1(r13) | |
19ccb76a | 2487 | |
b6c295df PM |
2488 | #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING |
2489 | addi r3, r4, VCPU_TB_RMINTR | |
2490 | bl kvmhv_accumulate_time | |
2491 | #endif | |
2492 | ||
93d17397 PM |
2493 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
2494 | BEGIN_FTR_SECTION | |
2495 | bl kvmppc_restore_tm | |
2496 | END_FTR_SECTION_IFSET(CPU_FTR_TM) | |
2497 | #endif | |
2498 | ||
19ccb76a PM |
2499 | /* load up FP state */ |
2500 | bl kvmppc_load_fp | |
2501 | ||
fd6d53b1 PM |
2502 | /* Restore guest decrementer */ |
2503 | ld r3, VCPU_DEC_EXPIRES(r4) | |
2504 | ld r5, HSTATE_KVM_VCORE(r13) | |
2505 | ld r6, VCORE_TB_OFFSET(r5) | |
2506 | add r3, r3, r6 /* convert host TB to guest TB value */ | |
2507 | mftb r7 | |
2508 | subf r3, r7, r3 | |
2509 | mtspr SPRN_DEC, r3 | |
2510 | ||
19ccb76a | 2511 | /* Load NV GPRS */ |
c75df6f9 MN |
2512 | ld r14, VCPU_GPR(R14)(r4) |
2513 | ld r15, VCPU_GPR(R15)(r4) | |
2514 | ld r16, VCPU_GPR(R16)(r4) | |
2515 | ld r17, VCPU_GPR(R17)(r4) | |
2516 | ld r18, VCPU_GPR(R18)(r4) | |
2517 | ld r19, VCPU_GPR(R19)(r4) | |
2518 | ld r20, VCPU_GPR(R20)(r4) | |
2519 | ld r21, VCPU_GPR(R21)(r4) | |
2520 | ld r22, VCPU_GPR(R22)(r4) | |
2521 | ld r23, VCPU_GPR(R23)(r4) | |
2522 | ld r24, VCPU_GPR(R24)(r4) | |
2523 | ld r25, VCPU_GPR(R25)(r4) | |
2524 | ld r26, VCPU_GPR(R26)(r4) | |
2525 | ld r27, VCPU_GPR(R27)(r4) | |
2526 | ld r28, VCPU_GPR(R28)(r4) | |
2527 | ld r29, VCPU_GPR(R29)(r4) | |
2528 | ld r30, VCPU_GPR(R30)(r4) | |
2529 | ld r31, VCPU_GPR(R31)(r4) | |
37f55d30 | 2530 | |
e3bbbbfa PM |
2531 | /* Check the wake reason in SRR1 to see why we got here */ |
2532 | bl kvmppc_check_wake_reason | |
19ccb76a | 2533 | |
37f55d30 SW |
2534 | /* |
2535 | * Restore volatile registers since we could have called a | |
2536 | * C routine in kvmppc_check_wake_reason | |
2537 | * r4 = VCPU | |
2538 | * r3 tells us whether we need to return to host or not | |
2539 | * WARNING: it gets checked further down: | |
2540 | * should not modify r3 until this check is done. | |
2541 | */ | |
2542 | ld r4, HSTATE_KVM_VCPU(r13) | |
2543 | ||
19ccb76a | 2544 | /* clear our bit in vcore->napping_threads */ |
e3bbbbfa PM |
2545 | 34: ld r5,HSTATE_KVM_VCORE(r13) |
2546 | lbz r7,HSTATE_PTID(r13) | |
19ccb76a | 2547 | li r0,1 |
e3bbbbfa | 2548 | sld r0,r0,r7 |
19ccb76a PM |
2549 | addi r6,r5,VCORE_NAPPING_THREADS |
2550 | 32: lwarx r7,0,r6 | |
2551 | andc r7,r7,r0 | |
2552 | stwcx. r7,0,r6 | |
2553 | bne 32b | |
2554 | li r0,0 | |
2555 | stb r0,HSTATE_NAPPING(r13) | |
2556 | ||
37f55d30 | 2557 | /* See if the wake reason saved in r3 means we need to exit */ |
e3bbbbfa | 2558 | stw r12, VCPU_TRAP(r4) |
4619ac88 | 2559 | mr r9, r4 |
e3bbbbfa PM |
2560 | cmpdi r3, 0 |
2561 | bgt guest_exit_cont | |
4619ac88 | 2562 | |
19ccb76a PM |
2563 | /* see if any other thread is already exiting */ |
2564 | lwz r0,VCORE_ENTRY_EXIT(r5) | |
2565 | cmpwi r0,0x100 | |
e3bbbbfa | 2566 | bge guest_exit_cont |
19ccb76a | 2567 | |
e3bbbbfa | 2568 | b kvmppc_cede_reentry /* if not go back to guest */ |
19ccb76a PM |
2569 | |
2570 | /* cede when already previously prodded case */ | |
04f995a5 PM |
2571 | kvm_cede_prodded: |
2572 | li r0,0 | |
19ccb76a PM |
2573 | stb r0,VCPU_PRODDED(r3) |
2574 | sync /* order testing prodded vs. clearing ceded */ | |
2575 | stb r0,VCPU_CEDED(r3) | |
2576 | li r3,H_SUCCESS | |
2577 | blr | |
2578 | ||
2579 | /* we've ceded but we want to give control to the host */ | |
04f995a5 | 2580 | kvm_cede_exit: |
6af27c84 PM |
2581 | ld r9, HSTATE_KVM_VCPU(r13) |
2582 | b guest_exit_cont | |
19ccb76a | 2583 | |
b4072df4 PM |
2584 | /* Try to handle a machine check in real mode */ |
2585 | machine_check_realmode: | |
2586 | mr r3, r9 /* get vcpu pointer */ | |
b1576fec | 2587 | bl kvmppc_realmode_machine_check |
b4072df4 | 2588 | nop |
b4072df4 PM |
2589 | ld r9, HSTATE_KVM_VCPU(r13) |
2590 | li r12, BOOK3S_INTERRUPT_MACHINE_CHECK | |
74845bc2 MS |
2591 | /* |
2592 | * Deliver unhandled/fatal (e.g. UE) MCE errors to guest through | |
2593 | * machine check interrupt (set HSRR0 to 0x200). And for handled | |
2594 | * errors (no-fatal), just go back to guest execution with current | |
2595 | * HSRR0 instead of exiting guest. This new approach will inject | |
2596 | * machine check to guest for fatal error causing guest to crash. | |
2597 | * | |
2598 | * The old code used to return to host for unhandled errors which | |
2599 | * was causing guest to hang with soft lockups inside guest and | |
2600 | * makes it difficult to recover guest instance. | |
966d713e MS |
2601 | * |
2602 | * if we receive machine check with MSR(RI=0) then deliver it to | |
2603 | * guest as machine check causing guest to crash. | |
74845bc2 | 2604 | */ |
74845bc2 | 2605 | ld r11, VCPU_MSR(r9) |
1c9e3d51 PM |
2606 | rldicl. r0, r11, 64-MSR_HV_LG, 63 /* check if it happened in HV mode */ |
2607 | bne mc_cont /* if so, exit to host */ | |
966d713e MS |
2608 | andi. r10, r11, MSR_RI /* check for unrecoverable exception */ |
2609 | beq 1f /* Deliver a machine check to guest */ | |
2610 | ld r10, VCPU_PC(r9) | |
2611 | cmpdi r3, 0 /* Did we handle MCE ? */ | |
74845bc2 | 2612 | bne 2f /* Continue guest execution. */ |
b4072df4 | 2613 | /* If not, deliver a machine check. SRR0/1 are already set */ |
966d713e | 2614 | 1: li r10, BOOK3S_INTERRUPT_MACHINE_CHECK |
e4e38121 | 2615 | bl kvmppc_msr_interrupt |
74845bc2 | 2616 | 2: b fast_interrupt_c_return |
b4072df4 | 2617 | |
e3bbbbfa PM |
2618 | /* |
2619 | * Check the reason we woke from nap, and take appropriate action. | |
1f09c3ed | 2620 | * Returns (in r3): |
e3bbbbfa PM |
2621 | * 0 if nothing needs to be done |
2622 | * 1 if something happened that needs to be handled by the host | |
66feed61 | 2623 | * -1 if there was a guest wakeup (IPI or msgsnd) |
e3c13e56 SW |
2624 | * -2 if we handled a PCI passthrough interrupt (returned by |
2625 | * kvmppc_read_intr only) | |
e3bbbbfa PM |
2626 | * |
2627 | * Also sets r12 to the interrupt vector for any interrupt that needs | |
2628 | * to be handled now by the host (0x500 for external interrupt), or zero. | |
37f55d30 SW |
2629 | * Modifies all volatile registers (since it may call a C function). |
2630 | * This routine calls kvmppc_read_intr, a C function, if an external | |
2631 | * interrupt is pending. | |
e3bbbbfa PM |
2632 | */ |
2633 | kvmppc_check_wake_reason: | |
2634 | mfspr r6, SPRN_SRR1 | |
aa31e843 PM |
2635 | BEGIN_FTR_SECTION |
2636 | rlwinm r6, r6, 45-31, 0xf /* extract wake reason field (P8) */ | |
2637 | FTR_SECTION_ELSE | |
2638 | rlwinm r6, r6, 45-31, 0xe /* P7 wake reason field is 3 bits */ | |
2639 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S) | |
2640 | cmpwi r6, 8 /* was it an external interrupt? */ | |
37f55d30 | 2641 | beq 7f /* if so, see what it was */ |
e3bbbbfa PM |
2642 | li r3, 0 |
2643 | li r12, 0 | |
2644 | cmpwi r6, 6 /* was it the decrementer? */ | |
2645 | beq 0f | |
aa31e843 PM |
2646 | BEGIN_FTR_SECTION |
2647 | cmpwi r6, 5 /* privileged doorbell? */ | |
2648 | beq 0f | |
5d00f66b PM |
2649 | cmpwi r6, 3 /* hypervisor doorbell? */ |
2650 | beq 3f | |
aa31e843 | 2651 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) |
fd7bacbc MS |
2652 | cmpwi r6, 0xa /* Hypervisor maintenance ? */ |
2653 | beq 4f | |
e3bbbbfa PM |
2654 | li r3, 1 /* anything else, return 1 */ |
2655 | 0: blr | |
2656 | ||
5d00f66b PM |
2657 | /* hypervisor doorbell */ |
2658 | 3: li r12, BOOK3S_INTERRUPT_H_DOORBELL | |
70aa3961 GS |
2659 | |
2660 | /* | |
2661 | * Clear the doorbell as we will invoke the handler | |
2662 | * explicitly in the guest exit path. | |
2663 | */ | |
2664 | lis r6, (PPC_DBELL_SERVER << (63-36))@h | |
2665 | PPC_MSGCLR(6) | |
66feed61 | 2666 | /* see if it's a host IPI */ |
5d00f66b | 2667 | li r3, 1 |
66feed61 PM |
2668 | lbz r0, HSTATE_HOST_IPI(r13) |
2669 | cmpwi r0, 0 | |
2670 | bnelr | |
70aa3961 | 2671 | /* if not, return -1 */ |
66feed61 | 2672 | li r3, -1 |
5d00f66b PM |
2673 | blr |
2674 | ||
fd7bacbc MS |
2675 | /* Woken up due to Hypervisor maintenance interrupt */ |
2676 | 4: li r12, BOOK3S_INTERRUPT_HMI | |
2677 | li r3, 1 | |
2678 | blr | |
2679 | ||
37f55d30 SW |
2680 | /* external interrupt - create a stack frame so we can call C */ |
2681 | 7: mflr r0 | |
2682 | std r0, PPC_LR_STKOFF(r1) | |
2683 | stdu r1, -PPC_MIN_STKFRM(r1) | |
2684 | bl kvmppc_read_intr | |
2685 | nop | |
2686 | li r12, BOOK3S_INTERRUPT_EXTERNAL | |
f7af5209 SW |
2687 | cmpdi r3, 1 |
2688 | ble 1f | |
2689 | ||
2690 | /* | |
2691 | * Return code of 2 means PCI passthrough interrupt, but | |
2692 | * we need to return back to host to complete handling the | |
2693 | * interrupt. Trap reason is expected in r12 by guest | |
2694 | * exit code. | |
2695 | */ | |
2696 | li r12, BOOK3S_INTERRUPT_HV_RM_HARD | |
2697 | 1: | |
37f55d30 SW |
2698 | ld r0, PPC_MIN_STKFRM+PPC_LR_STKOFF(r1) |
2699 | addi r1, r1, PPC_MIN_STKFRM | |
2700 | mtlr r0 | |
2701 | blr | |
371fefd6 | 2702 | |
de56a948 PM |
2703 | /* |
2704 | * Save away FP, VMX and VSX registers. | |
2705 | * r3 = vcpu pointer | |
595e4f7e PM |
2706 | * N.B. r30 and r31 are volatile across this function, |
2707 | * thus it is not callable from C. | |
a8606e20 | 2708 | */ |
595e4f7e PM |
2709 | kvmppc_save_fp: |
2710 | mflr r30 | |
2711 | mr r31,r3 | |
8943633c PM |
2712 | mfmsr r5 |
2713 | ori r8,r5,MSR_FP | |
de56a948 PM |
2714 | #ifdef CONFIG_ALTIVEC |
2715 | BEGIN_FTR_SECTION | |
2716 | oris r8,r8,MSR_VEC@h | |
2717 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
2718 | #endif | |
2719 | #ifdef CONFIG_VSX | |
2720 | BEGIN_FTR_SECTION | |
2721 | oris r8,r8,MSR_VSX@h | |
2722 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
2723 | #endif | |
2724 | mtmsrd r8 | |
595e4f7e | 2725 | addi r3,r3,VCPU_FPRS |
9bf163f8 | 2726 | bl store_fp_state |
de56a948 PM |
2727 | #ifdef CONFIG_ALTIVEC |
2728 | BEGIN_FTR_SECTION | |
595e4f7e | 2729 | addi r3,r31,VCPU_VRS |
9bf163f8 | 2730 | bl store_vr_state |
de56a948 PM |
2731 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) |
2732 | #endif | |
2733 | mfspr r6,SPRN_VRSAVE | |
e724f080 | 2734 | stw r6,VCPU_VRSAVE(r31) |
595e4f7e | 2735 | mtlr r30 |
de56a948 PM |
2736 | blr |
2737 | ||
2738 | /* | |
2739 | * Load up FP, VMX and VSX registers | |
2740 | * r4 = vcpu pointer | |
595e4f7e PM |
2741 | * N.B. r30 and r31 are volatile across this function, |
2742 | * thus it is not callable from C. | |
de56a948 | 2743 | */ |
de56a948 | 2744 | kvmppc_load_fp: |
595e4f7e PM |
2745 | mflr r30 |
2746 | mr r31,r4 | |
de56a948 PM |
2747 | mfmsr r9 |
2748 | ori r8,r9,MSR_FP | |
2749 | #ifdef CONFIG_ALTIVEC | |
2750 | BEGIN_FTR_SECTION | |
2751 | oris r8,r8,MSR_VEC@h | |
2752 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
2753 | #endif | |
2754 | #ifdef CONFIG_VSX | |
2755 | BEGIN_FTR_SECTION | |
2756 | oris r8,r8,MSR_VSX@h | |
2757 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
2758 | #endif | |
2759 | mtmsrd r8 | |
595e4f7e | 2760 | addi r3,r4,VCPU_FPRS |
9bf163f8 | 2761 | bl load_fp_state |
de56a948 PM |
2762 | #ifdef CONFIG_ALTIVEC |
2763 | BEGIN_FTR_SECTION | |
595e4f7e | 2764 | addi r3,r31,VCPU_VRS |
9bf163f8 | 2765 | bl load_vr_state |
de56a948 PM |
2766 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) |
2767 | #endif | |
e724f080 | 2768 | lwz r7,VCPU_VRSAVE(r31) |
de56a948 | 2769 | mtspr SPRN_VRSAVE,r7 |
595e4f7e PM |
2770 | mtlr r30 |
2771 | mr r4,r31 | |
de56a948 | 2772 | blr |
44a3add8 | 2773 | |
f024ee09 PM |
2774 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
2775 | /* | |
2776 | * Save transactional state and TM-related registers. | |
2777 | * Called with r9 pointing to the vcpu struct. | |
2778 | * This can modify all checkpointed registers, but | |
2779 | * restores r1, r2 and r9 (vcpu pointer) before exit. | |
2780 | */ | |
2781 | kvmppc_save_tm: | |
2782 | mflr r0 | |
2783 | std r0, PPC_LR_STKOFF(r1) | |
2784 | ||
2785 | /* Turn on TM. */ | |
2786 | mfmsr r8 | |
2787 | li r0, 1 | |
2788 | rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG | |
2789 | mtmsrd r8 | |
2790 | ||
2791 | ld r5, VCPU_MSR(r9) | |
2792 | rldicl. r5, r5, 64 - MSR_TS_S_LG, 62 | |
2793 | beq 1f /* TM not active in guest. */ | |
2794 | ||
2795 | std r1, HSTATE_HOST_R1(r13) | |
2796 | li r3, TM_CAUSE_KVM_RESCHED | |
2797 | ||
2798 | /* Clear the MSR RI since r1, r13 are all going to be foobar. */ | |
2799 | li r5, 0 | |
2800 | mtmsrd r5, 1 | |
2801 | ||
2802 | /* All GPRs are volatile at this point. */ | |
2803 | TRECLAIM(R3) | |
2804 | ||
2805 | /* Temporarily store r13 and r9 so we have some regs to play with */ | |
2806 | SET_SCRATCH0(r13) | |
2807 | GET_PACA(r13) | |
2808 | std r9, PACATMSCRATCH(r13) | |
2809 | ld r9, HSTATE_KVM_VCPU(r13) | |
2810 | ||
2811 | /* Get a few more GPRs free. */ | |
2812 | std r29, VCPU_GPRS_TM(29)(r9) | |
2813 | std r30, VCPU_GPRS_TM(30)(r9) | |
2814 | std r31, VCPU_GPRS_TM(31)(r9) | |
2815 | ||
2816 | /* Save away PPR and DSCR soon so don't run with user values. */ | |
2817 | mfspr r31, SPRN_PPR | |
2818 | HMT_MEDIUM | |
2819 | mfspr r30, SPRN_DSCR | |
2820 | ld r29, HSTATE_DSCR(r13) | |
2821 | mtspr SPRN_DSCR, r29 | |
2822 | ||
2823 | /* Save all but r9, r13 & r29-r31 */ | |
2824 | reg = 0 | |
2825 | .rept 29 | |
2826 | .if (reg != 9) && (reg != 13) | |
2827 | std reg, VCPU_GPRS_TM(reg)(r9) | |
2828 | .endif | |
2829 | reg = reg + 1 | |
2830 | .endr | |
2831 | /* ... now save r13 */ | |
2832 | GET_SCRATCH0(r4) | |
2833 | std r4, VCPU_GPRS_TM(13)(r9) | |
2834 | /* ... and save r9 */ | |
2835 | ld r4, PACATMSCRATCH(r13) | |
2836 | std r4, VCPU_GPRS_TM(9)(r9) | |
2837 | ||
2838 | /* Reload stack pointer and TOC. */ | |
2839 | ld r1, HSTATE_HOST_R1(r13) | |
2840 | ld r2, PACATOC(r13) | |
2841 | ||
2842 | /* Set MSR RI now we have r1 and r13 back. */ | |
2843 | li r5, MSR_RI | |
2844 | mtmsrd r5, 1 | |
2845 | ||
2846 | /* Save away checkpinted SPRs. */ | |
2847 | std r31, VCPU_PPR_TM(r9) | |
2848 | std r30, VCPU_DSCR_TM(r9) | |
2849 | mflr r5 | |
2850 | mfcr r6 | |
2851 | mfctr r7 | |
2852 | mfspr r8, SPRN_AMR | |
2853 | mfspr r10, SPRN_TAR | |
0d808df0 | 2854 | mfxer r11 |
f024ee09 PM |
2855 | std r5, VCPU_LR_TM(r9) |
2856 | stw r6, VCPU_CR_TM(r9) | |
2857 | std r7, VCPU_CTR_TM(r9) | |
2858 | std r8, VCPU_AMR_TM(r9) | |
2859 | std r10, VCPU_TAR_TM(r9) | |
0d808df0 | 2860 | std r11, VCPU_XER_TM(r9) |
f024ee09 PM |
2861 | |
2862 | /* Restore r12 as trap number. */ | |
2863 | lwz r12, VCPU_TRAP(r9) | |
2864 | ||
2865 | /* Save FP/VSX. */ | |
2866 | addi r3, r9, VCPU_FPRS_TM | |
2867 | bl store_fp_state | |
2868 | addi r3, r9, VCPU_VRS_TM | |
2869 | bl store_vr_state | |
2870 | mfspr r6, SPRN_VRSAVE | |
2871 | stw r6, VCPU_VRSAVE_TM(r9) | |
2872 | 1: | |
2873 | /* | |
2874 | * We need to save these SPRs after the treclaim so that the software | |
2875 | * error code is recorded correctly in the TEXASR. Also the user may | |
2876 | * change these outside of a transaction, so they must always be | |
2877 | * context switched. | |
2878 | */ | |
2879 | mfspr r5, SPRN_TFHAR | |
2880 | mfspr r6, SPRN_TFIAR | |
2881 | mfspr r7, SPRN_TEXASR | |
2882 | std r5, VCPU_TFHAR(r9) | |
2883 | std r6, VCPU_TFIAR(r9) | |
2884 | std r7, VCPU_TEXASR(r9) | |
2885 | ||
2886 | ld r0, PPC_LR_STKOFF(r1) | |
2887 | mtlr r0 | |
2888 | blr | |
2889 | ||
2890 | /* | |
2891 | * Restore transactional state and TM-related registers. | |
2892 | * Called with r4 pointing to the vcpu struct. | |
2893 | * This potentially modifies all checkpointed registers. | |
2894 | * It restores r1, r2, r4 from the PACA. | |
2895 | */ | |
2896 | kvmppc_restore_tm: | |
2897 | mflr r0 | |
2898 | std r0, PPC_LR_STKOFF(r1) | |
2899 | ||
2900 | /* Turn on TM/FP/VSX/VMX so we can restore them. */ | |
2901 | mfmsr r5 | |
2902 | li r6, MSR_TM >> 32 | |
2903 | sldi r6, r6, 32 | |
2904 | or r5, r5, r6 | |
2905 | ori r5, r5, MSR_FP | |
2906 | oris r5, r5, (MSR_VEC | MSR_VSX)@h | |
2907 | mtmsrd r5 | |
2908 | ||
2909 | /* | |
2910 | * The user may change these outside of a transaction, so they must | |
2911 | * always be context switched. | |
2912 | */ | |
2913 | ld r5, VCPU_TFHAR(r4) | |
2914 | ld r6, VCPU_TFIAR(r4) | |
2915 | ld r7, VCPU_TEXASR(r4) | |
2916 | mtspr SPRN_TFHAR, r5 | |
2917 | mtspr SPRN_TFIAR, r6 | |
2918 | mtspr SPRN_TEXASR, r7 | |
2919 | ||
2920 | ld r5, VCPU_MSR(r4) | |
2921 | rldicl. r5, r5, 64 - MSR_TS_S_LG, 62 | |
2922 | beqlr /* TM not active in guest */ | |
2923 | std r1, HSTATE_HOST_R1(r13) | |
2924 | ||
2925 | /* Make sure the failure summary is set, otherwise we'll program check | |
2926 | * when we trechkpt. It's possible that this might have been not set | |
2927 | * on a kvmppc_set_one_reg() call but we shouldn't let this crash the | |
2928 | * host. | |
2929 | */ | |
2930 | oris r7, r7, (TEXASR_FS)@h | |
2931 | mtspr SPRN_TEXASR, r7 | |
2932 | ||
2933 | /* | |
2934 | * We need to load up the checkpointed state for the guest. | |
2935 | * We need to do this early as it will blow away any GPRs, VSRs and | |
2936 | * some SPRs. | |
2937 | */ | |
2938 | ||
2939 | mr r31, r4 | |
2940 | addi r3, r31, VCPU_FPRS_TM | |
2941 | bl load_fp_state | |
2942 | addi r3, r31, VCPU_VRS_TM | |
2943 | bl load_vr_state | |
2944 | mr r4, r31 | |
2945 | lwz r7, VCPU_VRSAVE_TM(r4) | |
2946 | mtspr SPRN_VRSAVE, r7 | |
2947 | ||
2948 | ld r5, VCPU_LR_TM(r4) | |
2949 | lwz r6, VCPU_CR_TM(r4) | |
2950 | ld r7, VCPU_CTR_TM(r4) | |
2951 | ld r8, VCPU_AMR_TM(r4) | |
2952 | ld r9, VCPU_TAR_TM(r4) | |
0d808df0 | 2953 | ld r10, VCPU_XER_TM(r4) |
f024ee09 PM |
2954 | mtlr r5 |
2955 | mtcr r6 | |
2956 | mtctr r7 | |
2957 | mtspr SPRN_AMR, r8 | |
2958 | mtspr SPRN_TAR, r9 | |
0d808df0 | 2959 | mtxer r10 |
f024ee09 PM |
2960 | |
2961 | /* | |
2962 | * Load up PPR and DSCR values but don't put them in the actual SPRs | |
2963 | * till the last moment to avoid running with userspace PPR and DSCR for | |
2964 | * too long. | |
2965 | */ | |
2966 | ld r29, VCPU_DSCR_TM(r4) | |
2967 | ld r30, VCPU_PPR_TM(r4) | |
2968 | ||
2969 | std r2, PACATMSCRATCH(r13) /* Save TOC */ | |
2970 | ||
2971 | /* Clear the MSR RI since r1, r13 are all going to be foobar. */ | |
2972 | li r5, 0 | |
2973 | mtmsrd r5, 1 | |
2974 | ||
2975 | /* Load GPRs r0-r28 */ | |
2976 | reg = 0 | |
2977 | .rept 29 | |
2978 | ld reg, VCPU_GPRS_TM(reg)(r31) | |
2979 | reg = reg + 1 | |
2980 | .endr | |
2981 | ||
2982 | mtspr SPRN_DSCR, r29 | |
2983 | mtspr SPRN_PPR, r30 | |
2984 | ||
2985 | /* Load final GPRs */ | |
2986 | ld 29, VCPU_GPRS_TM(29)(r31) | |
2987 | ld 30, VCPU_GPRS_TM(30)(r31) | |
2988 | ld 31, VCPU_GPRS_TM(31)(r31) | |
2989 | ||
2990 | /* TM checkpointed state is now setup. All GPRs are now volatile. */ | |
2991 | TRECHKPT | |
2992 | ||
2993 | /* Now let's get back the state we need. */ | |
2994 | HMT_MEDIUM | |
2995 | GET_PACA(r13) | |
2996 | ld r29, HSTATE_DSCR(r13) | |
2997 | mtspr SPRN_DSCR, r29 | |
2998 | ld r4, HSTATE_KVM_VCPU(r13) | |
2999 | ld r1, HSTATE_HOST_R1(r13) | |
3000 | ld r2, PACATMSCRATCH(r13) | |
3001 | ||
3002 | /* Set the MSR RI since we have our registers back. */ | |
3003 | li r5, MSR_RI | |
3004 | mtmsrd r5, 1 | |
3005 | ||
3006 | ld r0, PPC_LR_STKOFF(r1) | |
3007 | mtlr r0 | |
3008 | blr | |
3009 | #endif | |
3010 | ||
44a3add8 PM |
3011 | /* |
3012 | * We come here if we get any exception or interrupt while we are | |
3013 | * executing host real mode code while in guest MMU context. | |
3014 | * For now just spin, but we should do something better. | |
3015 | */ | |
3016 | kvmppc_bad_host_intr: | |
3017 | b . | |
e4e38121 MN |
3018 | |
3019 | /* | |
3020 | * This mimics the MSR transition on IRQ delivery. The new guest MSR is taken | |
3021 | * from VCPU_INTR_MSR and is modified based on the required TM state changes. | |
3022 | * r11 has the guest MSR value (in/out) | |
3023 | * r9 has a vcpu pointer (in) | |
3024 | * r0 is used as a scratch register | |
3025 | */ | |
3026 | kvmppc_msr_interrupt: | |
3027 | rldicl r0, r11, 64 - MSR_TS_S_LG, 62 | |
3028 | cmpwi r0, 2 /* Check if we are in transactional state.. */ | |
3029 | ld r11, VCPU_INTR_MSR(r9) | |
3030 | bne 1f | |
3031 | /* ... if transactional, change to suspended */ | |
3032 | li r0, 1 | |
3033 | 1: rldimi r11, r0, MSR_TS_S_LG, 63 - MSR_TS_T_LG | |
3034 | blr | |
9bc01a9b PM |
3035 | |
3036 | /* | |
3037 | * This works around a hardware bug on POWER8E processors, where | |
3038 | * writing a 1 to the MMCR0[PMAO] bit doesn't generate a | |
3039 | * performance monitor interrupt. Instead, when we need to have | |
3040 | * an interrupt pending, we have to arrange for a counter to overflow. | |
3041 | */ | |
3042 | kvmppc_fix_pmao: | |
3043 | li r3, 0 | |
3044 | mtspr SPRN_MMCR2, r3 | |
3045 | lis r3, (MMCR0_PMXE | MMCR0_FCECE)@h | |
3046 | ori r3, r3, MMCR0_PMCjCE | MMCR0_C56RUN | |
3047 | mtspr SPRN_MMCR0, r3 | |
3048 | lis r3, 0x7fff | |
3049 | ori r3, r3, 0xffff | |
3050 | mtspr SPRN_PMC6, r3 | |
3051 | isync | |
3052 | blr | |
b6c295df PM |
3053 | |
3054 | #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING | |
3055 | /* | |
3056 | * Start timing an activity | |
3057 | * r3 = pointer to time accumulation struct, r4 = vcpu | |
3058 | */ | |
3059 | kvmhv_start_timing: | |
3060 | ld r5, HSTATE_KVM_VCORE(r13) | |
3061 | lbz r6, VCORE_IN_GUEST(r5) | |
3062 | cmpwi r6, 0 | |
3063 | beq 5f /* if in guest, need to */ | |
3064 | ld r6, VCORE_TB_OFFSET(r5) /* subtract timebase offset */ | |
3065 | 5: mftb r5 | |
3066 | subf r5, r6, r5 | |
3067 | std r3, VCPU_CUR_ACTIVITY(r4) | |
3068 | std r5, VCPU_ACTIVITY_START(r4) | |
3069 | blr | |
3070 | ||
3071 | /* | |
3072 | * Accumulate time to one activity and start another. | |
3073 | * r3 = pointer to new time accumulation struct, r4 = vcpu | |
3074 | */ | |
3075 | kvmhv_accumulate_time: | |
3076 | ld r5, HSTATE_KVM_VCORE(r13) | |
3077 | lbz r8, VCORE_IN_GUEST(r5) | |
3078 | cmpwi r8, 0 | |
3079 | beq 4f /* if in guest, need to */ | |
3080 | ld r8, VCORE_TB_OFFSET(r5) /* subtract timebase offset */ | |
3081 | 4: ld r5, VCPU_CUR_ACTIVITY(r4) | |
3082 | ld r6, VCPU_ACTIVITY_START(r4) | |
3083 | std r3, VCPU_CUR_ACTIVITY(r4) | |
3084 | mftb r7 | |
3085 | subf r7, r8, r7 | |
3086 | std r7, VCPU_ACTIVITY_START(r4) | |
3087 | cmpdi r5, 0 | |
3088 | beqlr | |
3089 | subf r3, r6, r7 | |
3090 | ld r8, TAS_SEQCOUNT(r5) | |
3091 | cmpdi r8, 0 | |
3092 | addi r8, r8, 1 | |
3093 | std r8, TAS_SEQCOUNT(r5) | |
3094 | lwsync | |
3095 | ld r7, TAS_TOTAL(r5) | |
3096 | add r7, r7, r3 | |
3097 | std r7, TAS_TOTAL(r5) | |
3098 | ld r6, TAS_MIN(r5) | |
3099 | ld r7, TAS_MAX(r5) | |
3100 | beq 3f | |
3101 | cmpd r3, r6 | |
3102 | bge 1f | |
3103 | 3: std r3, TAS_MIN(r5) | |
3104 | 1: cmpd r3, r7 | |
3105 | ble 2f | |
3106 | std r3, TAS_MAX(r5) | |
3107 | 2: lwsync | |
3108 | addi r8, r8, 1 | |
3109 | std r8, TAS_SEQCOUNT(r5) | |
3110 | blr | |
3111 | #endif |