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de56a948 PM |
1 | /* |
2 | * This program is free software; you can redistribute it and/or modify | |
3 | * it under the terms of the GNU General Public License, version 2, as | |
4 | * published by the Free Software Foundation. | |
5 | * | |
6 | * This program is distributed in the hope that it will be useful, | |
7 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
8 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
9 | * GNU General Public License for more details. | |
10 | * | |
11 | * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com> | |
12 | * | |
13 | * Derived from book3s_rmhandlers.S and other files, which are: | |
14 | * | |
15 | * Copyright SUSE Linux Products GmbH 2009 | |
16 | * | |
17 | * Authors: Alexander Graf <agraf@suse.de> | |
18 | */ | |
19 | ||
20 | #include <asm/ppc_asm.h> | |
21 | #include <asm/kvm_asm.h> | |
22 | #include <asm/reg.h> | |
177339d7 | 23 | #include <asm/mmu.h> |
de56a948 | 24 | #include <asm/page.h> |
177339d7 PM |
25 | #include <asm/ptrace.h> |
26 | #include <asm/hvcall.h> | |
de56a948 PM |
27 | #include <asm/asm-offsets.h> |
28 | #include <asm/exception-64s.h> | |
f0888f70 | 29 | #include <asm/kvm_book3s_asm.h> |
b4072df4 | 30 | #include <asm/mmu-hash64.h> |
e4e38121 MN |
31 | #include <asm/tm.h> |
32 | ||
33 | #define VCPU_GPRS_TM(reg) (((reg) * ULONG_SIZE) + VCPU_GPR_TM) | |
de56a948 | 34 | |
7ffcf8ec AB |
35 | #ifdef __LITTLE_ENDIAN__ |
36 | #error Need to fix lppaca and SLB shadow accesses in little endian mode | |
37 | #endif | |
38 | ||
e0b7ec05 PM |
39 | /* Values in HSTATE_NAPPING(r13) */ |
40 | #define NAPPING_CEDE 1 | |
41 | #define NAPPING_NOVCPU 2 | |
42 | ||
de56a948 | 43 | /* |
19ccb76a | 44 | * Call kvmppc_hv_entry in real mode. |
de56a948 PM |
45 | * Must be called with interrupts hard-disabled. |
46 | * | |
47 | * Input Registers: | |
48 | * | |
49 | * LR = return address to continue at after eventually re-enabling MMU | |
50 | */ | |
51 | _GLOBAL(kvmppc_hv_entry_trampoline) | |
218309b7 PM |
52 | mflr r0 |
53 | std r0, PPC_LR_STKOFF(r1) | |
54 | stdu r1, -112(r1) | |
de56a948 | 55 | mfmsr r10 |
218309b7 | 56 | LOAD_REG_ADDR(r5, kvmppc_call_hv_entry) |
de56a948 PM |
57 | li r0,MSR_RI |
58 | andc r0,r10,r0 | |
59 | li r6,MSR_IR | MSR_DR | |
60 | andc r6,r10,r6 | |
61 | mtmsrd r0,1 /* clear RI in MSR */ | |
62 | mtsrr0 r5 | |
63 | mtsrr1 r6 | |
64 | RFI | |
65 | ||
218309b7 | 66 | kvmppc_call_hv_entry: |
e0b7ec05 | 67 | ld r4, HSTATE_KVM_VCPU(r13) |
218309b7 PM |
68 | bl kvmppc_hv_entry |
69 | ||
70 | /* Back from guest - restore host state and return to caller */ | |
71 | ||
eee7ff9d | 72 | BEGIN_FTR_SECTION |
218309b7 PM |
73 | /* Restore host DABR and DABRX */ |
74 | ld r5,HSTATE_DABR(r13) | |
75 | li r6,7 | |
76 | mtspr SPRN_DABR,r5 | |
77 | mtspr SPRN_DABRX,r6 | |
eee7ff9d | 78 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) |
218309b7 PM |
79 | |
80 | /* Restore SPRG3 */ | |
9d378dfa SW |
81 | ld r3,PACA_SPRG_VDSO(r13) |
82 | mtspr SPRN_SPRG_VDSO_WRITE,r3 | |
218309b7 | 83 | |
218309b7 PM |
84 | /* Reload the host's PMU registers */ |
85 | ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */ | |
86 | lbz r4, LPPACA_PMCINUSE(r3) | |
87 | cmpwi r4, 0 | |
88 | beq 23f /* skip if not */ | |
9bc01a9b PM |
89 | BEGIN_FTR_SECTION |
90 | ld r3, HSTATE_MMCR(r13) | |
91 | andi. r4, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO | |
92 | cmpwi r4, MMCR0_PMAO | |
93 | beql kvmppc_fix_pmao | |
94 | END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG) | |
218309b7 PM |
95 | lwz r3, HSTATE_PMC(r13) |
96 | lwz r4, HSTATE_PMC + 4(r13) | |
97 | lwz r5, HSTATE_PMC + 8(r13) | |
98 | lwz r6, HSTATE_PMC + 12(r13) | |
99 | lwz r8, HSTATE_PMC + 16(r13) | |
100 | lwz r9, HSTATE_PMC + 20(r13) | |
101 | BEGIN_FTR_SECTION | |
102 | lwz r10, HSTATE_PMC + 24(r13) | |
103 | lwz r11, HSTATE_PMC + 28(r13) | |
104 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
105 | mtspr SPRN_PMC1, r3 | |
106 | mtspr SPRN_PMC2, r4 | |
107 | mtspr SPRN_PMC3, r5 | |
108 | mtspr SPRN_PMC4, r6 | |
109 | mtspr SPRN_PMC5, r8 | |
110 | mtspr SPRN_PMC6, r9 | |
111 | BEGIN_FTR_SECTION | |
112 | mtspr SPRN_PMC7, r10 | |
113 | mtspr SPRN_PMC8, r11 | |
114 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
115 | ld r3, HSTATE_MMCR(r13) | |
116 | ld r4, HSTATE_MMCR + 8(r13) | |
117 | ld r5, HSTATE_MMCR + 16(r13) | |
72cde5a8 PM |
118 | ld r6, HSTATE_MMCR + 24(r13) |
119 | ld r7, HSTATE_MMCR + 32(r13) | |
218309b7 PM |
120 | mtspr SPRN_MMCR1, r4 |
121 | mtspr SPRN_MMCRA, r5 | |
72cde5a8 PM |
122 | mtspr SPRN_SIAR, r6 |
123 | mtspr SPRN_SDAR, r7 | |
124 | BEGIN_FTR_SECTION | |
125 | ld r8, HSTATE_MMCR + 40(r13) | |
126 | ld r9, HSTATE_MMCR + 48(r13) | |
127 | mtspr SPRN_MMCR2, r8 | |
128 | mtspr SPRN_SIER, r9 | |
129 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) | |
218309b7 PM |
130 | mtspr SPRN_MMCR0, r3 |
131 | isync | |
132 | 23: | |
133 | ||
e0b7ec05 PM |
134 | /* |
135 | * Reload DEC. HDEC interrupts were disabled when | |
136 | * we reloaded the host's LPCR value. | |
137 | */ | |
138 | ld r3, HSTATE_DECEXP(r13) | |
139 | mftb r4 | |
140 | subf r4, r4, r3 | |
141 | mtspr SPRN_DEC, r4 | |
142 | ||
218309b7 PM |
143 | /* |
144 | * For external and machine check interrupts, we need | |
145 | * to call the Linux handler to process the interrupt. | |
146 | * We do that by jumping to absolute address 0x500 for | |
147 | * external interrupts, or the machine_check_fwnmi label | |
148 | * for machine checks (since firmware might have patched | |
149 | * the vector area at 0x200). The [h]rfid at the end of the | |
150 | * handler will return to the book3s_hv_interrupts.S code. | |
151 | * For other interrupts we do the rfid to get back | |
152 | * to the book3s_hv_interrupts.S code here. | |
153 | */ | |
154 | ld r8, 112+PPC_LR_STKOFF(r1) | |
155 | addi r1, r1, 112 | |
156 | ld r7, HSTATE_HOST_MSR(r13) | |
157 | ||
158 | cmpwi cr1, r12, BOOK3S_INTERRUPT_MACHINE_CHECK | |
159 | cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL | |
160 | BEGIN_FTR_SECTION | |
161 | beq 11f | |
162 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) | |
163 | ||
164 | /* RFI into the highmem handler, or branch to interrupt handler */ | |
165 | mfmsr r6 | |
166 | li r0, MSR_RI | |
167 | andc r6, r6, r0 | |
168 | mtmsrd r6, 1 /* Clear RI in MSR */ | |
169 | mtsrr0 r8 | |
170 | mtsrr1 r7 | |
171 | beqa 0x500 /* external interrupt (PPC970) */ | |
172 | beq cr1, 13f /* machine check */ | |
173 | RFI | |
174 | ||
175 | /* On POWER7, we have external interrupts set to use HSRR0/1 */ | |
176 | 11: mtspr SPRN_HSRR0, r8 | |
177 | mtspr SPRN_HSRR1, r7 | |
178 | ba 0x500 | |
179 | ||
180 | 13: b machine_check_fwnmi | |
181 | ||
e0b7ec05 PM |
182 | kvmppc_primary_no_guest: |
183 | /* We handle this much like a ceded vcpu */ | |
184 | /* set our bit in napping_threads */ | |
185 | ld r5, HSTATE_KVM_VCORE(r13) | |
186 | lbz r7, HSTATE_PTID(r13) | |
187 | li r0, 1 | |
188 | sld r0, r0, r7 | |
189 | addi r6, r5, VCORE_NAPPING_THREADS | |
190 | 1: lwarx r3, 0, r6 | |
191 | or r3, r3, r0 | |
192 | stwcx. r3, 0, r6 | |
193 | bne 1b | |
194 | /* order napping_threads update vs testing entry_exit_count */ | |
195 | isync | |
196 | li r12, 0 | |
197 | lwz r7, VCORE_ENTRY_EXIT(r5) | |
198 | cmpwi r7, 0x100 | |
199 | bge kvm_novcpu_exit /* another thread already exiting */ | |
200 | li r3, NAPPING_NOVCPU | |
201 | stb r3, HSTATE_NAPPING(r13) | |
202 | li r3, 1 | |
203 | stb r3, HSTATE_HWTHREAD_REQ(r13) | |
204 | ||
205 | b kvm_do_nap | |
206 | ||
207 | kvm_novcpu_wakeup: | |
208 | ld r1, HSTATE_HOST_R1(r13) | |
209 | ld r5, HSTATE_KVM_VCORE(r13) | |
210 | li r0, 0 | |
211 | stb r0, HSTATE_NAPPING(r13) | |
212 | stb r0, HSTATE_HWTHREAD_REQ(r13) | |
213 | ||
e3bbbbfa PM |
214 | /* check the wake reason */ |
215 | bl kvmppc_check_wake_reason | |
216 | ||
e0b7ec05 | 217 | /* see if any other thread is already exiting */ |
e0b7ec05 PM |
218 | lwz r0, VCORE_ENTRY_EXIT(r5) |
219 | cmpwi r0, 0x100 | |
220 | bge kvm_novcpu_exit | |
221 | ||
222 | /* clear our bit in napping_threads */ | |
223 | lbz r7, HSTATE_PTID(r13) | |
224 | li r0, 1 | |
225 | sld r0, r0, r7 | |
226 | addi r6, r5, VCORE_NAPPING_THREADS | |
e3bbbbfa PM |
227 | 4: lwarx r7, 0, r6 |
228 | andc r7, r7, r0 | |
229 | stwcx. r7, 0, r6 | |
e0b7ec05 PM |
230 | bne 4b |
231 | ||
e3bbbbfa | 232 | /* See if the wake reason means we need to exit */ |
e0b7ec05 PM |
233 | cmpdi r3, 0 |
234 | bge kvm_novcpu_exit | |
e0b7ec05 PM |
235 | |
236 | /* Got an IPI but other vcpus aren't yet exiting, must be a latecomer */ | |
237 | ld r4, HSTATE_KVM_VCPU(r13) | |
238 | cmpdi r4, 0 | |
239 | bne kvmppc_got_guest | |
240 | ||
241 | kvm_novcpu_exit: | |
242 | b hdec_soon | |
243 | ||
371fefd6 | 244 | /* |
e0b7ec05 | 245 | * We come in here when wakened from nap mode. |
371fefd6 PM |
246 | * Relocation is off and most register values are lost. |
247 | * r13 points to the PACA. | |
248 | */ | |
249 | .globl kvm_start_guest | |
250 | kvm_start_guest: | |
fd17dc7b PM |
251 | |
252 | /* Set runlatch bit the minute you wake up from nap */ | |
253 | mfspr r1, SPRN_CTRLF | |
254 | ori r1, r1, 1 | |
255 | mtspr SPRN_CTRLT, r1 | |
256 | ||
19ccb76a PM |
257 | ld r2,PACATOC(r13) |
258 | ||
f0888f70 PM |
259 | li r0,KVM_HWTHREAD_IN_KVM |
260 | stb r0,HSTATE_HWTHREAD_STATE(r13) | |
371fefd6 | 261 | |
f0888f70 PM |
262 | /* NV GPR values from power7_idle() will no longer be valid */ |
263 | li r0,1 | |
264 | stb r0,PACA_NAPSTATELOST(r13) | |
371fefd6 | 265 | |
4619ac88 PM |
266 | /* were we napping due to cede? */ |
267 | lbz r0,HSTATE_NAPPING(r13) | |
e0b7ec05 PM |
268 | cmpwi r0,NAPPING_CEDE |
269 | beq kvm_end_cede | |
270 | cmpwi r0,NAPPING_NOVCPU | |
271 | beq kvm_novcpu_wakeup | |
272 | ||
273 | ld r1,PACAEMERGSP(r13) | |
274 | subi r1,r1,STACK_FRAME_OVERHEAD | |
4619ac88 PM |
275 | |
276 | /* | |
277 | * We weren't napping due to cede, so this must be a secondary | |
278 | * thread being woken up to run a guest, or being woken up due | |
279 | * to a stray IPI. (Or due to some machine check or hypervisor | |
280 | * maintenance interrupt while the core is in KVM.) | |
281 | */ | |
f0888f70 PM |
282 | |
283 | /* Check the wake reason in SRR1 to see why we got here */ | |
e3bbbbfa PM |
284 | bl kvmppc_check_wake_reason |
285 | cmpdi r3, 0 | |
286 | bge kvm_no_guest | |
371fefd6 | 287 | |
4619ac88 | 288 | /* get vcpu pointer, NULL if we have no vcpu to run */ |
7b444c67 PM |
289 | ld r4,HSTATE_KVM_VCPU(r13) |
290 | cmpdi r4,0 | |
f0888f70 | 291 | /* if we have no vcpu to run, go back to sleep */ |
7b444c67 | 292 | beq kvm_no_guest |
f0888f70 | 293 | |
e0b7ec05 PM |
294 | /* Set HSTATE_DSCR(r13) to something sensible */ |
295 | LOAD_REG_ADDR(r6, dscr_default) | |
296 | ld r6, 0(r6) | |
297 | std r6, HSTATE_DSCR(r13) | |
2fde6d20 | 298 | |
e0b7ec05 | 299 | bl kvmppc_hv_entry |
218309b7 PM |
300 | |
301 | /* Back from the guest, go back to nap */ | |
302 | /* Clear our vcpu pointer so we don't come back in early */ | |
303 | li r0, 0 | |
304 | std r0, HSTATE_KVM_VCPU(r13) | |
f019b7ad PM |
305 | /* |
306 | * Make sure we clear HSTATE_KVM_VCPU(r13) before incrementing | |
307 | * the nap_count, because once the increment to nap_count is | |
308 | * visible we could be given another vcpu. | |
309 | */ | |
218309b7 | 310 | lwsync |
218309b7 PM |
311 | |
312 | /* increment the nap count and then go to nap mode */ | |
313 | ld r4, HSTATE_KVM_VCORE(r13) | |
314 | addi r4, r4, VCORE_NAP_COUNT | |
218309b7 PM |
315 | 51: lwarx r3, 0, r4 |
316 | addi r3, r3, 1 | |
317 | stwcx. r3, 0, r4 | |
318 | bne 51b | |
319 | ||
320 | kvm_no_guest: | |
321 | li r0, KVM_HWTHREAD_IN_NAP | |
322 | stb r0, HSTATE_HWTHREAD_STATE(r13) | |
e0b7ec05 | 323 | kvm_do_nap: |
582b910e PM |
324 | /* Clear the runlatch bit before napping */ |
325 | mfspr r2, SPRN_CTRLF | |
326 | clrrdi r2, r2, 1 | |
327 | mtspr SPRN_CTRLT, r2 | |
328 | ||
218309b7 PM |
329 | li r3, LPCR_PECE0 |
330 | mfspr r4, SPRN_LPCR | |
331 | rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1 | |
332 | mtspr SPRN_LPCR, r4 | |
333 | isync | |
334 | std r0, HSTATE_SCRATCH0(r13) | |
335 | ptesync | |
336 | ld r0, HSTATE_SCRATCH0(r13) | |
337 | 1: cmpd r0, r0 | |
338 | bne 1b | |
339 | nap | |
340 | b . | |
341 | ||
342 | /****************************************************************************** | |
343 | * * | |
344 | * Entry code * | |
345 | * * | |
346 | *****************************************************************************/ | |
347 | ||
de56a948 PM |
348 | .global kvmppc_hv_entry |
349 | kvmppc_hv_entry: | |
350 | ||
351 | /* Required state: | |
352 | * | |
e0b7ec05 | 353 | * R4 = vcpu pointer (or NULL) |
de56a948 PM |
354 | * MSR = ~IR|DR |
355 | * R13 = PACA | |
356 | * R1 = host R1 | |
357 | * all other volatile GPRS = free | |
358 | */ | |
359 | mflr r0 | |
218309b7 PM |
360 | std r0, PPC_LR_STKOFF(r1) |
361 | stdu r1, -112(r1) | |
de56a948 | 362 | |
de56a948 PM |
363 | /* Save R1 in the PACA */ |
364 | std r1, HSTATE_HOST_R1(r13) | |
365 | ||
44a3add8 PM |
366 | li r6, KVM_GUEST_MODE_HOST_HV |
367 | stb r6, HSTATE_IN_GUEST(r13) | |
368 | ||
de56a948 PM |
369 | /* Clear out SLB */ |
370 | li r6,0 | |
371 | slbmte r6,r6 | |
372 | slbia | |
373 | ptesync | |
374 | ||
9e368f29 PM |
375 | BEGIN_FTR_SECTION |
376 | b 30f | |
377 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
378 | /* | |
379 | * POWER7 host -> guest partition switch code. | |
380 | * We don't have to lock against concurrent tlbies, | |
381 | * but we do have to coordinate across hardware threads. | |
382 | */ | |
371fefd6 PM |
383 | /* Increment entry count iff exit count is zero. */ |
384 | ld r5,HSTATE_KVM_VCORE(r13) | |
385 | addi r9,r5,VCORE_ENTRY_EXIT | |
386 | 21: lwarx r3,0,r9 | |
387 | cmpwi r3,0x100 /* any threads starting to exit? */ | |
388 | bge secondary_too_late /* if so we're too late to the party */ | |
389 | addi r3,r3,1 | |
390 | stwcx. r3,0,r9 | |
391 | bne 21b | |
392 | ||
393 | /* Primary thread switches to guest partition. */ | |
e0b7ec05 PM |
394 | ld r9,VCORE_KVM(r5) /* pointer to struct kvm */ |
395 | lbz r6,HSTATE_PTID(r13) | |
371fefd6 PM |
396 | cmpwi r6,0 |
397 | bne 20f | |
de56a948 PM |
398 | ld r6,KVM_SDR1(r9) |
399 | lwz r7,KVM_LPID(r9) | |
400 | li r0,LPID_RSVD /* switch to reserved LPID */ | |
401 | mtspr SPRN_LPID,r0 | |
402 | ptesync | |
403 | mtspr SPRN_SDR1,r6 /* switch to partition page table */ | |
404 | mtspr SPRN_LPID,r7 | |
405 | isync | |
1b400ba0 PM |
406 | |
407 | /* See if we need to flush the TLB */ | |
408 | lhz r6,PACAPACAINDEX(r13) /* test_bit(cpu, need_tlb_flush) */ | |
409 | clrldi r7,r6,64-6 /* extract bit number (6 bits) */ | |
410 | srdi r6,r6,6 /* doubleword number */ | |
411 | sldi r6,r6,3 /* address offset */ | |
412 | add r6,r6,r9 | |
413 | addi r6,r6,KVM_NEED_FLUSH /* dword in kvm->arch.need_tlb_flush */ | |
371fefd6 | 414 | li r0,1 |
1b400ba0 PM |
415 | sld r0,r0,r7 |
416 | ld r7,0(r6) | |
417 | and. r7,r7,r0 | |
418 | beq 22f | |
419 | 23: ldarx r7,0,r6 /* if set, clear the bit */ | |
420 | andc r7,r7,r0 | |
421 | stdcx. r7,0,r6 | |
422 | bne 23b | |
ca252055 PM |
423 | /* Flush the TLB of any entries for this LPID */ |
424 | /* use arch 2.07S as a proxy for POWER8 */ | |
425 | BEGIN_FTR_SECTION | |
426 | li r6,512 /* POWER8 has 512 sets */ | |
427 | FTR_SECTION_ELSE | |
428 | li r6,128 /* POWER7 has 128 sets */ | |
429 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S) | |
1b400ba0 PM |
430 | mtctr r6 |
431 | li r7,0x800 /* IS field = 0b10 */ | |
432 | ptesync | |
433 | 28: tlbiel r7 | |
434 | addi r7,r7,0x1000 | |
435 | bdnz 28b | |
436 | ptesync | |
437 | ||
93b0f4dc PM |
438 | /* Add timebase offset onto timebase */ |
439 | 22: ld r8,VCORE_TB_OFFSET(r5) | |
440 | cmpdi r8,0 | |
441 | beq 37f | |
442 | mftb r6 /* current host timebase */ | |
443 | add r8,r8,r6 | |
444 | mtspr SPRN_TBU40,r8 /* update upper 40 bits */ | |
445 | mftb r7 /* check if lower 24 bits overflowed */ | |
446 | clrldi r6,r6,40 | |
447 | clrldi r7,r7,40 | |
448 | cmpld r7,r6 | |
449 | bge 37f | |
450 | addis r8,r8,0x100 /* if so, increment upper 40 bits */ | |
451 | mtspr SPRN_TBU40,r8 | |
452 | ||
388cc6e1 PM |
453 | /* Load guest PCR value to select appropriate compat mode */ |
454 | 37: ld r7, VCORE_PCR(r5) | |
455 | cmpdi r7, 0 | |
456 | beq 38f | |
457 | mtspr SPRN_PCR, r7 | |
458 | 38: | |
b005255e MN |
459 | |
460 | BEGIN_FTR_SECTION | |
461 | /* DPDES is shared between threads */ | |
462 | ld r8, VCORE_DPDES(r5) | |
463 | mtspr SPRN_DPDES, r8 | |
464 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) | |
465 | ||
388cc6e1 | 466 | li r0,1 |
371fefd6 PM |
467 | stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */ |
468 | b 10f | |
469 | ||
470 | /* Secondary threads wait for primary to have done partition switch */ | |
471 | 20: lbz r0,VCORE_IN_GUEST(r5) | |
472 | cmpwi r0,0 | |
473 | beq 20b | |
aa04b4cc | 474 | |
19ccb76a | 475 | /* Set LPCR and RMOR. */ |
a0144e2a | 476 | 10: ld r8,VCORE_LPCR(r5) |
19ccb76a | 477 | mtspr SPRN_LPCR,r8 |
aa04b4cc PM |
478 | ld r8,KVM_RMOR(r9) |
479 | mtspr SPRN_RMOR,r8 | |
de56a948 PM |
480 | isync |
481 | ||
482 | /* Check if HDEC expires soon */ | |
483 | mfspr r3,SPRN_HDEC | |
e0b7ec05 | 484 | cmpwi r3,512 /* 1 microsecond */ |
de56a948 | 485 | li r12,BOOK3S_INTERRUPT_HV_DECREMENTER |
de56a948 | 486 | blt hdec_soon |
9e368f29 PM |
487 | b 31f |
488 | ||
489 | /* | |
490 | * PPC970 host -> guest partition switch code. | |
491 | * We have to lock against concurrent tlbies, | |
492 | * using native_tlbie_lock to lock against host tlbies | |
493 | * and kvm->arch.tlbie_lock to lock against guest tlbies. | |
494 | * We also have to invalidate the TLB since its | |
495 | * entries aren't tagged with the LPID. | |
496 | */ | |
e0b7ec05 PM |
497 | 30: ld r5,HSTATE_KVM_VCORE(r13) |
498 | ld r9,VCORE_KVM(r5) /* pointer to struct kvm */ | |
9e368f29 PM |
499 | |
500 | /* first take native_tlbie_lock */ | |
501 | .section ".toc","aw" | |
502 | toc_tlbie_lock: | |
503 | .tc native_tlbie_lock[TC],native_tlbie_lock | |
504 | .previous | |
505 | ld r3,toc_tlbie_lock@toc(2) | |
54bb7f4b | 506 | #ifdef __BIG_ENDIAN__ |
9e368f29 | 507 | lwz r8,PACA_LOCK_TOKEN(r13) |
54bb7f4b AB |
508 | #else |
509 | lwz r8,PACAPACAINDEX(r13) | |
510 | #endif | |
9e368f29 PM |
511 | 24: lwarx r0,0,r3 |
512 | cmpwi r0,0 | |
513 | bne 24b | |
514 | stwcx. r8,0,r3 | |
515 | bne 24b | |
516 | isync | |
517 | ||
a0144e2a PM |
518 | ld r5,HSTATE_KVM_VCORE(r13) |
519 | ld r7,VCORE_LPCR(r5) /* use vcore->lpcr to store HID4 */ | |
9e368f29 PM |
520 | li r0,0x18f |
521 | rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */ | |
522 | or r0,r7,r0 | |
523 | ptesync | |
524 | sync | |
525 | mtspr SPRN_HID4,r0 /* switch to reserved LPID */ | |
526 | isync | |
527 | li r0,0 | |
528 | stw r0,0(r3) /* drop native_tlbie_lock */ | |
529 | ||
530 | /* invalidate the whole TLB */ | |
531 | li r0,256 | |
532 | mtctr r0 | |
533 | li r6,0 | |
534 | 25: tlbiel r6 | |
535 | addi r6,r6,0x1000 | |
536 | bdnz 25b | |
537 | ptesync | |
538 | ||
539 | /* Take the guest's tlbie_lock */ | |
540 | addi r3,r9,KVM_TLBIE_LOCK | |
541 | 24: lwarx r0,0,r3 | |
542 | cmpwi r0,0 | |
543 | bne 24b | |
544 | stwcx. r8,0,r3 | |
545 | bne 24b | |
546 | isync | |
547 | ld r6,KVM_SDR1(r9) | |
548 | mtspr SPRN_SDR1,r6 /* switch to partition page table */ | |
549 | ||
550 | /* Set up HID4 with the guest's LPID etc. */ | |
551 | sync | |
552 | mtspr SPRN_HID4,r7 | |
553 | isync | |
554 | ||
555 | /* drop the guest's tlbie_lock */ | |
556 | li r0,0 | |
557 | stw r0,0(r3) | |
558 | ||
559 | /* Check if HDEC expires soon */ | |
560 | mfspr r3,SPRN_HDEC | |
561 | cmpwi r3,10 | |
562 | li r12,BOOK3S_INTERRUPT_HV_DECREMENTER | |
9e368f29 PM |
563 | blt hdec_soon |
564 | ||
565 | /* Enable HDEC interrupts */ | |
566 | mfspr r0,SPRN_HID0 | |
567 | li r3,1 | |
568 | rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1 | |
569 | sync | |
570 | mtspr SPRN_HID0,r0 | |
571 | mfspr r0,SPRN_HID0 | |
572 | mfspr r0,SPRN_HID0 | |
573 | mfspr r0,SPRN_HID0 | |
574 | mfspr r0,SPRN_HID0 | |
575 | mfspr r0,SPRN_HID0 | |
576 | mfspr r0,SPRN_HID0 | |
e0b7ec05 PM |
577 | 31: |
578 | /* Do we have a guest vcpu to run? */ | |
579 | cmpdi r4, 0 | |
580 | beq kvmppc_primary_no_guest | |
581 | kvmppc_got_guest: | |
de56a948 PM |
582 | |
583 | /* Load up guest SLB entries */ | |
e0b7ec05 | 584 | lwz r5,VCPU_SLB_MAX(r4) |
de56a948 PM |
585 | cmpwi r5,0 |
586 | beq 9f | |
587 | mtctr r5 | |
588 | addi r6,r4,VCPU_SLB | |
589 | 1: ld r8,VCPU_SLB_E(r6) | |
590 | ld r9,VCPU_SLB_V(r6) | |
591 | slbmte r9,r8 | |
592 | addi r6,r6,VCPU_SLB_SIZE | |
593 | bdnz 1b | |
594 | 9: | |
e0b7ec05 PM |
595 | /* Increment yield count if they have a VPA */ |
596 | ld r3, VCPU_VPA(r4) | |
597 | cmpdi r3, 0 | |
598 | beq 25f | |
599 | lwz r5, LPPACA_YIELDCOUNT(r3) | |
600 | addi r5, r5, 1 | |
601 | stw r5, LPPACA_YIELDCOUNT(r3) | |
602 | li r6, 1 | |
603 | stb r6, VCPU_VPA_DIRTY(r4) | |
604 | 25: | |
605 | ||
606 | BEGIN_FTR_SECTION | |
607 | /* Save purr/spurr */ | |
608 | mfspr r5,SPRN_PURR | |
609 | mfspr r6,SPRN_SPURR | |
610 | std r5,HSTATE_PURR(r13) | |
611 | std r6,HSTATE_SPURR(r13) | |
612 | ld r7,VCPU_PURR(r4) | |
613 | ld r8,VCPU_SPURR(r4) | |
614 | mtspr SPRN_PURR,r7 | |
615 | mtspr SPRN_SPURR,r8 | |
616 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) | |
617 | ||
618 | BEGIN_FTR_SECTION | |
619 | /* Set partition DABR */ | |
620 | /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */ | |
8563bf52 | 621 | lwz r5,VCPU_DABRX(r4) |
e0b7ec05 PM |
622 | ld r6,VCPU_DABR(r4) |
623 | mtspr SPRN_DABRX,r5 | |
624 | mtspr SPRN_DABR,r6 | |
625 | BEGIN_FTR_SECTION_NESTED(89) | |
626 | isync | |
627 | END_FTR_SECTION_NESTED(CPU_FTR_ARCH_206, CPU_FTR_ARCH_206, 89) | |
628 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) | |
629 | ||
e4e38121 MN |
630 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
631 | BEGIN_FTR_SECTION | |
632 | b skip_tm | |
633 | END_FTR_SECTION_IFCLR(CPU_FTR_TM) | |
634 | ||
635 | /* Turn on TM/FP/VSX/VMX so we can restore them. */ | |
636 | mfmsr r5 | |
637 | li r6, MSR_TM >> 32 | |
638 | sldi r6, r6, 32 | |
639 | or r5, r5, r6 | |
640 | ori r5, r5, MSR_FP | |
641 | oris r5, r5, (MSR_VEC | MSR_VSX)@h | |
642 | mtmsrd r5 | |
643 | ||
644 | /* | |
645 | * The user may change these outside of a transaction, so they must | |
646 | * always be context switched. | |
647 | */ | |
648 | ld r5, VCPU_TFHAR(r4) | |
649 | ld r6, VCPU_TFIAR(r4) | |
650 | ld r7, VCPU_TEXASR(r4) | |
651 | mtspr SPRN_TFHAR, r5 | |
652 | mtspr SPRN_TFIAR, r6 | |
653 | mtspr SPRN_TEXASR, r7 | |
654 | ||
655 | ld r5, VCPU_MSR(r4) | |
656 | rldicl. r5, r5, 64 - MSR_TS_S_LG, 62 | |
657 | beq skip_tm /* TM not active in guest */ | |
658 | ||
659 | /* Make sure the failure summary is set, otherwise we'll program check | |
660 | * when we trechkpt. It's possible that this might have been not set | |
661 | * on a kvmppc_set_one_reg() call but we shouldn't let this crash the | |
662 | * host. | |
663 | */ | |
664 | oris r7, r7, (TEXASR_FS)@h | |
665 | mtspr SPRN_TEXASR, r7 | |
666 | ||
667 | /* | |
668 | * We need to load up the checkpointed state for the guest. | |
669 | * We need to do this early as it will blow away any GPRs, VSRs and | |
670 | * some SPRs. | |
671 | */ | |
672 | ||
673 | mr r31, r4 | |
674 | addi r3, r31, VCPU_FPRS_TM | |
675 | bl .load_fp_state | |
676 | addi r3, r31, VCPU_VRS_TM | |
677 | bl .load_vr_state | |
678 | mr r4, r31 | |
679 | lwz r7, VCPU_VRSAVE_TM(r4) | |
680 | mtspr SPRN_VRSAVE, r7 | |
681 | ||
682 | ld r5, VCPU_LR_TM(r4) | |
683 | lwz r6, VCPU_CR_TM(r4) | |
684 | ld r7, VCPU_CTR_TM(r4) | |
685 | ld r8, VCPU_AMR_TM(r4) | |
686 | ld r9, VCPU_TAR_TM(r4) | |
687 | mtlr r5 | |
688 | mtcr r6 | |
689 | mtctr r7 | |
690 | mtspr SPRN_AMR, r8 | |
691 | mtspr SPRN_TAR, r9 | |
692 | ||
693 | /* | |
694 | * Load up PPR and DSCR values but don't put them in the actual SPRs | |
695 | * till the last moment to avoid running with userspace PPR and DSCR for | |
696 | * too long. | |
697 | */ | |
698 | ld r29, VCPU_DSCR_TM(r4) | |
699 | ld r30, VCPU_PPR_TM(r4) | |
700 | ||
701 | std r2, PACATMSCRATCH(r13) /* Save TOC */ | |
702 | ||
703 | /* Clear the MSR RI since r1, r13 are all going to be foobar. */ | |
704 | li r5, 0 | |
705 | mtmsrd r5, 1 | |
706 | ||
707 | /* Load GPRs r0-r28 */ | |
708 | reg = 0 | |
709 | .rept 29 | |
710 | ld reg, VCPU_GPRS_TM(reg)(r31) | |
711 | reg = reg + 1 | |
712 | .endr | |
713 | ||
714 | mtspr SPRN_DSCR, r29 | |
715 | mtspr SPRN_PPR, r30 | |
716 | ||
717 | /* Load final GPRs */ | |
718 | ld 29, VCPU_GPRS_TM(29)(r31) | |
719 | ld 30, VCPU_GPRS_TM(30)(r31) | |
720 | ld 31, VCPU_GPRS_TM(31)(r31) | |
721 | ||
722 | /* TM checkpointed state is now setup. All GPRs are now volatile. */ | |
723 | TRECHKPT | |
724 | ||
725 | /* Now let's get back the state we need. */ | |
726 | HMT_MEDIUM | |
727 | GET_PACA(r13) | |
728 | ld r29, HSTATE_DSCR(r13) | |
729 | mtspr SPRN_DSCR, r29 | |
730 | ld r4, HSTATE_KVM_VCPU(r13) | |
731 | ld r1, HSTATE_HOST_R1(r13) | |
732 | ld r2, PACATMSCRATCH(r13) | |
733 | ||
734 | /* Set the MSR RI since we have our registers back. */ | |
735 | li r5, MSR_RI | |
736 | mtmsrd r5, 1 | |
737 | skip_tm: | |
738 | #endif | |
739 | ||
e0b7ec05 PM |
740 | /* Load guest PMU registers */ |
741 | /* R4 is live here (vcpu pointer) */ | |
742 | li r3, 1 | |
743 | sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */ | |
744 | mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */ | |
745 | isync | |
9bc01a9b PM |
746 | BEGIN_FTR_SECTION |
747 | ld r3, VCPU_MMCR(r4) | |
748 | andi. r5, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO | |
749 | cmpwi r5, MMCR0_PMAO | |
750 | beql kvmppc_fix_pmao | |
751 | END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG) | |
e0b7ec05 PM |
752 | lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */ |
753 | lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */ | |
754 | lwz r6, VCPU_PMC + 8(r4) | |
755 | lwz r7, VCPU_PMC + 12(r4) | |
756 | lwz r8, VCPU_PMC + 16(r4) | |
757 | lwz r9, VCPU_PMC + 20(r4) | |
758 | BEGIN_FTR_SECTION | |
759 | lwz r10, VCPU_PMC + 24(r4) | |
760 | lwz r11, VCPU_PMC + 28(r4) | |
761 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
762 | mtspr SPRN_PMC1, r3 | |
763 | mtspr SPRN_PMC2, r5 | |
764 | mtspr SPRN_PMC3, r6 | |
765 | mtspr SPRN_PMC4, r7 | |
766 | mtspr SPRN_PMC5, r8 | |
767 | mtspr SPRN_PMC6, r9 | |
768 | BEGIN_FTR_SECTION | |
769 | mtspr SPRN_PMC7, r10 | |
770 | mtspr SPRN_PMC8, r11 | |
771 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
772 | ld r3, VCPU_MMCR(r4) | |
773 | ld r5, VCPU_MMCR + 8(r4) | |
774 | ld r6, VCPU_MMCR + 16(r4) | |
775 | ld r7, VCPU_SIAR(r4) | |
776 | ld r8, VCPU_SDAR(r4) | |
777 | mtspr SPRN_MMCR1, r5 | |
778 | mtspr SPRN_MMCRA, r6 | |
779 | mtspr SPRN_SIAR, r7 | |
780 | mtspr SPRN_SDAR, r8 | |
b005255e MN |
781 | BEGIN_FTR_SECTION |
782 | ld r5, VCPU_MMCR + 24(r4) | |
783 | ld r6, VCPU_SIER(r4) | |
784 | lwz r7, VCPU_PMC + 24(r4) | |
785 | lwz r8, VCPU_PMC + 28(r4) | |
786 | ld r9, VCPU_MMCR + 32(r4) | |
787 | mtspr SPRN_MMCR2, r5 | |
788 | mtspr SPRN_SIER, r6 | |
789 | mtspr SPRN_SPMC1, r7 | |
790 | mtspr SPRN_SPMC2, r8 | |
791 | mtspr SPRN_MMCRS, r9 | |
792 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) | |
e0b7ec05 PM |
793 | mtspr SPRN_MMCR0, r3 |
794 | isync | |
795 | ||
796 | /* Load up FP, VMX and VSX registers */ | |
797 | bl kvmppc_load_fp | |
798 | ||
799 | ld r14, VCPU_GPR(R14)(r4) | |
800 | ld r15, VCPU_GPR(R15)(r4) | |
801 | ld r16, VCPU_GPR(R16)(r4) | |
802 | ld r17, VCPU_GPR(R17)(r4) | |
803 | ld r18, VCPU_GPR(R18)(r4) | |
804 | ld r19, VCPU_GPR(R19)(r4) | |
805 | ld r20, VCPU_GPR(R20)(r4) | |
806 | ld r21, VCPU_GPR(R21)(r4) | |
807 | ld r22, VCPU_GPR(R22)(r4) | |
808 | ld r23, VCPU_GPR(R23)(r4) | |
809 | ld r24, VCPU_GPR(R24)(r4) | |
810 | ld r25, VCPU_GPR(R25)(r4) | |
811 | ld r26, VCPU_GPR(R26)(r4) | |
812 | ld r27, VCPU_GPR(R27)(r4) | |
813 | ld r28, VCPU_GPR(R28)(r4) | |
814 | ld r29, VCPU_GPR(R29)(r4) | |
815 | ld r30, VCPU_GPR(R30)(r4) | |
816 | ld r31, VCPU_GPR(R31)(r4) | |
817 | ||
818 | BEGIN_FTR_SECTION | |
819 | /* Switch DSCR to guest value */ | |
820 | ld r5, VCPU_DSCR(r4) | |
821 | mtspr SPRN_DSCR, r5 | |
822 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) | |
823 | ||
b005255e MN |
824 | BEGIN_FTR_SECTION |
825 | /* Skip next section on POWER7 or PPC970 */ | |
826 | b 8f | |
827 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) | |
828 | /* Turn on TM so we can access TFHAR/TFIAR/TEXASR */ | |
829 | mfmsr r8 | |
830 | li r0, 1 | |
831 | rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG | |
832 | mtmsrd r8 | |
833 | ||
834 | /* Load up POWER8-specific registers */ | |
835 | ld r5, VCPU_IAMR(r4) | |
836 | lwz r6, VCPU_PSPB(r4) | |
837 | ld r7, VCPU_FSCR(r4) | |
838 | mtspr SPRN_IAMR, r5 | |
839 | mtspr SPRN_PSPB, r6 | |
840 | mtspr SPRN_FSCR, r7 | |
841 | ld r5, VCPU_DAWR(r4) | |
842 | ld r6, VCPU_DAWRX(r4) | |
843 | ld r7, VCPU_CIABR(r4) | |
844 | ld r8, VCPU_TAR(r4) | |
845 | mtspr SPRN_DAWR, r5 | |
846 | mtspr SPRN_DAWRX, r6 | |
847 | mtspr SPRN_CIABR, r7 | |
848 | mtspr SPRN_TAR, r8 | |
849 | ld r5, VCPU_IC(r4) | |
850 | ld r6, VCPU_VTB(r4) | |
851 | mtspr SPRN_IC, r5 | |
852 | mtspr SPRN_VTB, r6 | |
7b490411 | 853 | ld r8, VCPU_EBBHR(r4) |
b005255e MN |
854 | mtspr SPRN_EBBHR, r8 |
855 | ld r5, VCPU_EBBRR(r4) | |
856 | ld r6, VCPU_BESCR(r4) | |
857 | ld r7, VCPU_CSIGR(r4) | |
858 | ld r8, VCPU_TACR(r4) | |
859 | mtspr SPRN_EBBRR, r5 | |
860 | mtspr SPRN_BESCR, r6 | |
861 | mtspr SPRN_CSIGR, r7 | |
862 | mtspr SPRN_TACR, r8 | |
863 | ld r5, VCPU_TCSCR(r4) | |
864 | ld r6, VCPU_ACOP(r4) | |
865 | lwz r7, VCPU_GUEST_PID(r4) | |
866 | ld r8, VCPU_WORT(r4) | |
867 | mtspr SPRN_TCSCR, r5 | |
868 | mtspr SPRN_ACOP, r6 | |
869 | mtspr SPRN_PID, r7 | |
870 | mtspr SPRN_WORT, r8 | |
871 | 8: | |
872 | ||
e0b7ec05 PM |
873 | /* |
874 | * Set the decrementer to the guest decrementer. | |
875 | */ | |
876 | ld r8,VCPU_DEC_EXPIRES(r4) | |
c5fb80d3 PM |
877 | /* r8 is a host timebase value here, convert to guest TB */ |
878 | ld r5,HSTATE_KVM_VCORE(r13) | |
879 | ld r6,VCORE_TB_OFFSET(r5) | |
880 | add r8,r8,r6 | |
e0b7ec05 PM |
881 | mftb r7 |
882 | subf r3,r7,r8 | |
883 | mtspr SPRN_DEC,r3 | |
884 | stw r3,VCPU_DEC(r4) | |
885 | ||
886 | ld r5, VCPU_SPRG0(r4) | |
887 | ld r6, VCPU_SPRG1(r4) | |
888 | ld r7, VCPU_SPRG2(r4) | |
889 | ld r8, VCPU_SPRG3(r4) | |
890 | mtspr SPRN_SPRG0, r5 | |
891 | mtspr SPRN_SPRG1, r6 | |
892 | mtspr SPRN_SPRG2, r7 | |
893 | mtspr SPRN_SPRG3, r8 | |
894 | ||
895 | /* Load up DAR and DSISR */ | |
896 | ld r5, VCPU_DAR(r4) | |
897 | lwz r6, VCPU_DSISR(r4) | |
898 | mtspr SPRN_DAR, r5 | |
899 | mtspr SPRN_DSISR, r6 | |
900 | ||
901 | BEGIN_FTR_SECTION | |
902 | /* Restore AMR and UAMOR, set AMOR to all 1s */ | |
903 | ld r5,VCPU_AMR(r4) | |
904 | ld r6,VCPU_UAMOR(r4) | |
905 | li r7,-1 | |
906 | mtspr SPRN_AMR,r5 | |
907 | mtspr SPRN_UAMOR,r6 | |
908 | mtspr SPRN_AMOR,r7 | |
909 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) | |
de56a948 PM |
910 | |
911 | /* Restore state of CTRL run bit; assume 1 on entry */ | |
912 | lwz r5,VCPU_CTRL(r4) | |
913 | andi. r5,r5,1 | |
914 | bne 4f | |
915 | mfspr r6,SPRN_CTRLF | |
916 | clrrdi r6,r6,1 | |
917 | mtspr SPRN_CTRLT,r6 | |
918 | 4: | |
919 | ld r6, VCPU_CTR(r4) | |
920 | lwz r7, VCPU_XER(r4) | |
921 | ||
922 | mtctr r6 | |
923 | mtxer r7 | |
924 | ||
e3bbbbfa | 925 | kvmppc_cede_reentry: /* r4 = vcpu, r13 = paca */ |
4619ac88 PM |
926 | ld r10, VCPU_PC(r4) |
927 | ld r11, VCPU_MSR(r4) | |
de56a948 PM |
928 | ld r6, VCPU_SRR0(r4) |
929 | ld r7, VCPU_SRR1(r4) | |
e3bbbbfa PM |
930 | mtspr SPRN_SRR0, r6 |
931 | mtspr SPRN_SRR1, r7 | |
de56a948 | 932 | |
e3bbbbfa | 933 | deliver_guest_interrupt: |
4619ac88 | 934 | /* r11 = vcpu->arch.msr & ~MSR_HV */ |
de56a948 PM |
935 | rldicl r11, r11, 63 - MSR_HV_LG, 1 |
936 | rotldi r11, r11, 1 + MSR_HV_LG | |
937 | ori r11, r11, MSR_ME | |
938 | ||
19ccb76a | 939 | /* Check if we can deliver an external or decrementer interrupt now */ |
e3bbbbfa PM |
940 | ld r0, VCPU_PENDING_EXC(r4) |
941 | rldicl r0, r0, 64 - BOOK3S_IRQPRIO_EXTERNAL_LEVEL, 63 | |
942 | cmpdi cr1, r0, 0 | |
943 | andi. r8, r11, MSR_EE | |
19ccb76a | 944 | BEGIN_FTR_SECTION |
e3bbbbfa PM |
945 | mfspr r8, SPRN_LPCR |
946 | /* Insert EXTERNAL_LEVEL bit into LPCR at the MER bit position */ | |
947 | rldimi r8, r0, LPCR_MER_SH, 63 - LPCR_MER_SH | |
948 | mtspr SPRN_LPCR, r8 | |
19ccb76a PM |
949 | isync |
950 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) | |
951 | beq 5f | |
e3bbbbfa PM |
952 | li r0, BOOK3S_INTERRUPT_EXTERNAL |
953 | bne cr1, 12f | |
954 | mfspr r0, SPRN_DEC | |
955 | cmpwi r0, 0 | |
956 | li r0, BOOK3S_INTERRUPT_DECREMENTER | |
957 | bge 5f | |
19ccb76a | 958 | |
e3bbbbfa | 959 | 12: mtspr SPRN_SRR0, r10 |
19ccb76a | 960 | mr r10,r0 |
e3bbbbfa | 961 | mtspr SPRN_SRR1, r11 |
e4e38121 MN |
962 | mr r9, r4 |
963 | bl kvmppc_msr_interrupt | |
e3bbbbfa | 964 | 5: |
19ccb76a | 965 | |
27025a60 LPF |
966 | /* |
967 | * Required state: | |
968 | * R4 = vcpu | |
969 | * R10: value for HSRR0 | |
970 | * R11: value for HSRR1 | |
971 | * R13 = PACA | |
972 | */ | |
de56a948 | 973 | fast_guest_return: |
4619ac88 PM |
974 | li r0,0 |
975 | stb r0,VCPU_CEDED(r4) /* cancel cede */ | |
de56a948 PM |
976 | mtspr SPRN_HSRR0,r10 |
977 | mtspr SPRN_HSRR1,r11 | |
978 | ||
979 | /* Activate guest mode, so faults get handled by KVM */ | |
44a3add8 | 980 | li r9, KVM_GUEST_MODE_GUEST_HV |
de56a948 PM |
981 | stb r9, HSTATE_IN_GUEST(r13) |
982 | ||
983 | /* Enter guest */ | |
984 | ||
0acb9111 PM |
985 | BEGIN_FTR_SECTION |
986 | ld r5, VCPU_CFAR(r4) | |
987 | mtspr SPRN_CFAR, r5 | |
988 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
4b8473c9 PM |
989 | BEGIN_FTR_SECTION |
990 | ld r0, VCPU_PPR(r4) | |
991 | END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) | |
0acb9111 | 992 | |
de56a948 PM |
993 | ld r5, VCPU_LR(r4) |
994 | lwz r6, VCPU_CR(r4) | |
995 | mtlr r5 | |
996 | mtcr r6 | |
997 | ||
c75df6f9 MN |
998 | ld r1, VCPU_GPR(R1)(r4) |
999 | ld r2, VCPU_GPR(R2)(r4) | |
1000 | ld r3, VCPU_GPR(R3)(r4) | |
1001 | ld r5, VCPU_GPR(R5)(r4) | |
1002 | ld r6, VCPU_GPR(R6)(r4) | |
1003 | ld r7, VCPU_GPR(R7)(r4) | |
1004 | ld r8, VCPU_GPR(R8)(r4) | |
1005 | ld r9, VCPU_GPR(R9)(r4) | |
1006 | ld r10, VCPU_GPR(R10)(r4) | |
1007 | ld r11, VCPU_GPR(R11)(r4) | |
1008 | ld r12, VCPU_GPR(R12)(r4) | |
1009 | ld r13, VCPU_GPR(R13)(r4) | |
1010 | ||
4b8473c9 PM |
1011 | BEGIN_FTR_SECTION |
1012 | mtspr SPRN_PPR, r0 | |
1013 | END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) | |
1014 | ld r0, VCPU_GPR(R0)(r4) | |
c75df6f9 | 1015 | ld r4, VCPU_GPR(R4)(r4) |
de56a948 PM |
1016 | |
1017 | hrfid | |
1018 | b . | |
1019 | ||
1020 | /****************************************************************************** | |
1021 | * * | |
1022 | * Exit code * | |
1023 | * * | |
1024 | *****************************************************************************/ | |
1025 | ||
1026 | /* | |
1027 | * We come here from the first-level interrupt handlers. | |
1028 | */ | |
dd96b2c2 AK |
1029 | .globl kvmppc_interrupt_hv |
1030 | kvmppc_interrupt_hv: | |
de56a948 PM |
1031 | /* |
1032 | * Register contents: | |
1033 | * R12 = interrupt vector | |
1034 | * R13 = PACA | |
1035 | * guest CR, R12 saved in shadow VCPU SCRATCH1/0 | |
1036 | * guest R13 saved in SPRN_SCRATCH0 | |
1037 | */ | |
36e7bb38 | 1038 | std r9, HSTATE_SCRATCH2(r13) |
44a3add8 PM |
1039 | |
1040 | lbz r9, HSTATE_IN_GUEST(r13) | |
1041 | cmpwi r9, KVM_GUEST_MODE_HOST_HV | |
1042 | beq kvmppc_bad_host_intr | |
dd96b2c2 AK |
1043 | #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE |
1044 | cmpwi r9, KVM_GUEST_MODE_GUEST | |
36e7bb38 | 1045 | ld r9, HSTATE_SCRATCH2(r13) |
dd96b2c2 AK |
1046 | beq kvmppc_interrupt_pr |
1047 | #endif | |
44a3add8 PM |
1048 | /* We're now back in the host but in guest MMU context */ |
1049 | li r9, KVM_GUEST_MODE_HOST_HV | |
1050 | stb r9, HSTATE_IN_GUEST(r13) | |
1051 | ||
de56a948 PM |
1052 | ld r9, HSTATE_KVM_VCPU(r13) |
1053 | ||
1054 | /* Save registers */ | |
1055 | ||
c75df6f9 MN |
1056 | std r0, VCPU_GPR(R0)(r9) |
1057 | std r1, VCPU_GPR(R1)(r9) | |
1058 | std r2, VCPU_GPR(R2)(r9) | |
1059 | std r3, VCPU_GPR(R3)(r9) | |
1060 | std r4, VCPU_GPR(R4)(r9) | |
1061 | std r5, VCPU_GPR(R5)(r9) | |
1062 | std r6, VCPU_GPR(R6)(r9) | |
1063 | std r7, VCPU_GPR(R7)(r9) | |
1064 | std r8, VCPU_GPR(R8)(r9) | |
36e7bb38 | 1065 | ld r0, HSTATE_SCRATCH2(r13) |
c75df6f9 MN |
1066 | std r0, VCPU_GPR(R9)(r9) |
1067 | std r10, VCPU_GPR(R10)(r9) | |
1068 | std r11, VCPU_GPR(R11)(r9) | |
de56a948 PM |
1069 | ld r3, HSTATE_SCRATCH0(r13) |
1070 | lwz r4, HSTATE_SCRATCH1(r13) | |
c75df6f9 | 1071 | std r3, VCPU_GPR(R12)(r9) |
de56a948 | 1072 | stw r4, VCPU_CR(r9) |
0acb9111 PM |
1073 | BEGIN_FTR_SECTION |
1074 | ld r3, HSTATE_CFAR(r13) | |
1075 | std r3, VCPU_CFAR(r9) | |
1076 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
4b8473c9 PM |
1077 | BEGIN_FTR_SECTION |
1078 | ld r4, HSTATE_PPR(r13) | |
1079 | std r4, VCPU_PPR(r9) | |
1080 | END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) | |
de56a948 PM |
1081 | |
1082 | /* Restore R1/R2 so we can handle faults */ | |
1083 | ld r1, HSTATE_HOST_R1(r13) | |
1084 | ld r2, PACATOC(r13) | |
1085 | ||
1086 | mfspr r10, SPRN_SRR0 | |
1087 | mfspr r11, SPRN_SRR1 | |
1088 | std r10, VCPU_SRR0(r9) | |
1089 | std r11, VCPU_SRR1(r9) | |
1090 | andi. r0, r12, 2 /* need to read HSRR0/1? */ | |
1091 | beq 1f | |
1092 | mfspr r10, SPRN_HSRR0 | |
1093 | mfspr r11, SPRN_HSRR1 | |
1094 | clrrdi r12, r12, 2 | |
1095 | 1: std r10, VCPU_PC(r9) | |
1096 | std r11, VCPU_MSR(r9) | |
1097 | ||
1098 | GET_SCRATCH0(r3) | |
1099 | mflr r4 | |
c75df6f9 | 1100 | std r3, VCPU_GPR(R13)(r9) |
de56a948 PM |
1101 | std r4, VCPU_LR(r9) |
1102 | ||
de56a948 PM |
1103 | stw r12,VCPU_TRAP(r9) |
1104 | ||
697d3899 PM |
1105 | /* Save HEIR (HV emulation assist reg) in last_inst |
1106 | if this is an HEI (HV emulation interrupt, e40) */ | |
1107 | li r3,KVM_INST_FETCH_FAILED | |
1108 | BEGIN_FTR_SECTION | |
1109 | cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST | |
1110 | bne 11f | |
1111 | mfspr r3,SPRN_HEIR | |
1112 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) | |
1113 | 11: stw r3,VCPU_LAST_INST(r9) | |
1114 | ||
1115 | /* these are volatile across C function calls */ | |
1116 | mfctr r3 | |
1117 | mfxer r4 | |
1118 | std r3, VCPU_CTR(r9) | |
1119 | stw r4, VCPU_XER(r9) | |
1120 | ||
1121 | BEGIN_FTR_SECTION | |
1122 | /* If this is a page table miss then see if it's theirs or ours */ | |
1123 | cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE | |
1124 | beq kvmppc_hdsi | |
342d3db7 PM |
1125 | cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE |
1126 | beq kvmppc_hisi | |
697d3899 PM |
1127 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
1128 | ||
de56a948 PM |
1129 | /* See if this is a leftover HDEC interrupt */ |
1130 | cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER | |
1131 | bne 2f | |
1132 | mfspr r3,SPRN_HDEC | |
1133 | cmpwi r3,0 | |
1134 | bge ignore_hdec | |
1135 | 2: | |
697d3899 | 1136 | /* See if this is an hcall we can handle in real mode */ |
a8606e20 PM |
1137 | cmpwi r12,BOOK3S_INTERRUPT_SYSCALL |
1138 | beq hcall_try_real_mode | |
de56a948 | 1139 | |
54695c30 | 1140 | /* Only handle external interrupts here on arch 206 and later */ |
9e368f29 | 1141 | BEGIN_FTR_SECTION |
54695c30 BH |
1142 | b ext_interrupt_to_host |
1143 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206) | |
1144 | ||
1145 | /* External interrupt ? */ | |
1146 | cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL | |
1147 | bne+ ext_interrupt_to_host | |
1148 | ||
1149 | /* External interrupt, first check for host_ipi. If this is | |
1150 | * set, we know the host wants us out so let's do it now | |
1151 | */ | |
c934243c PM |
1152 | bl kvmppc_read_intr |
1153 | cmpdi r3, 0 | |
1154 | bgt ext_interrupt_to_host | |
54695c30 | 1155 | |
4619ac88 PM |
1156 | /* Check if any CPU is heading out to the host, if so head out too */ |
1157 | ld r5, HSTATE_KVM_VCORE(r13) | |
1158 | lwz r0, VCORE_ENTRY_EXIT(r5) | |
1159 | cmpwi r0, 0x100 | |
1160 | bge ext_interrupt_to_host | |
1161 | ||
e3bbbbfa PM |
1162 | /* Return to guest after delivering any pending interrupt */ |
1163 | mr r4, r9 | |
1164 | b deliver_guest_interrupt | |
54695c30 | 1165 | |
54695c30 | 1166 | ext_interrupt_to_host: |
de56a948 | 1167 | |
b4072df4 | 1168 | guest_exit_cont: /* r9 = vcpu, r12 = trap, r13 = paca */ |
de56a948 | 1169 | /* Save more register state */ |
de56a948 PM |
1170 | mfdar r6 |
1171 | mfdsisr r7 | |
de56a948 PM |
1172 | std r6, VCPU_DAR(r9) |
1173 | stw r7, VCPU_DSISR(r9) | |
9e368f29 | 1174 | BEGIN_FTR_SECTION |
697d3899 | 1175 | /* don't overwrite fault_dar/fault_dsisr if HDSI */ |
de56a948 PM |
1176 | cmpwi r12,BOOK3S_INTERRUPT_H_DATA_STORAGE |
1177 | beq 6f | |
9e368f29 | 1178 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
697d3899 | 1179 | std r6, VCPU_FAULT_DAR(r9) |
de56a948 PM |
1180 | stw r7, VCPU_FAULT_DSISR(r9) |
1181 | ||
b4072df4 PM |
1182 | /* See if it is a machine check */ |
1183 | cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK | |
1184 | beq machine_check_realmode | |
1185 | mc_cont: | |
1186 | ||
de56a948 | 1187 | /* Save guest CTRL register, set runlatch to 1 */ |
697d3899 | 1188 | 6: mfspr r6,SPRN_CTRLF |
de56a948 PM |
1189 | stw r6,VCPU_CTRL(r9) |
1190 | andi. r0,r6,1 | |
1191 | bne 4f | |
1192 | ori r6,r6,1 | |
1193 | mtspr SPRN_CTRLT,r6 | |
1194 | 4: | |
1195 | /* Read the guest SLB and save it away */ | |
1196 | lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */ | |
1197 | mtctr r0 | |
1198 | li r6,0 | |
1199 | addi r7,r9,VCPU_SLB | |
1200 | li r5,0 | |
1201 | 1: slbmfee r8,r6 | |
1202 | andis. r0,r8,SLB_ESID_V@h | |
1203 | beq 2f | |
1204 | add r8,r8,r6 /* put index in */ | |
1205 | slbmfev r3,r6 | |
1206 | std r8,VCPU_SLB_E(r7) | |
1207 | std r3,VCPU_SLB_V(r7) | |
1208 | addi r7,r7,VCPU_SLB_SIZE | |
1209 | addi r5,r5,1 | |
1210 | 2: addi r6,r6,1 | |
1211 | bdnz 1b | |
1212 | stw r5,VCPU_SLB_MAX(r9) | |
1213 | ||
1214 | /* | |
1215 | * Save the guest PURR/SPURR | |
1216 | */ | |
9e368f29 | 1217 | BEGIN_FTR_SECTION |
de56a948 PM |
1218 | mfspr r5,SPRN_PURR |
1219 | mfspr r6,SPRN_SPURR | |
1220 | ld r7,VCPU_PURR(r9) | |
1221 | ld r8,VCPU_SPURR(r9) | |
1222 | std r5,VCPU_PURR(r9) | |
1223 | std r6,VCPU_SPURR(r9) | |
1224 | subf r5,r7,r5 | |
1225 | subf r6,r8,r6 | |
1226 | ||
1227 | /* | |
1228 | * Restore host PURR/SPURR and add guest times | |
1229 | * so that the time in the guest gets accounted. | |
1230 | */ | |
1231 | ld r3,HSTATE_PURR(r13) | |
1232 | ld r4,HSTATE_SPURR(r13) | |
1233 | add r3,r3,r5 | |
1234 | add r4,r4,r6 | |
1235 | mtspr SPRN_PURR,r3 | |
1236 | mtspr SPRN_SPURR,r4 | |
9e368f29 | 1237 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_201) |
de56a948 | 1238 | |
e0b7ec05 PM |
1239 | /* Save DEC */ |
1240 | mfspr r5,SPRN_DEC | |
1241 | mftb r6 | |
1242 | extsw r5,r5 | |
1243 | add r5,r5,r6 | |
c5fb80d3 PM |
1244 | /* r5 is a guest timebase value here, convert to host TB */ |
1245 | ld r3,HSTATE_KVM_VCORE(r13) | |
1246 | ld r4,VCORE_TB_OFFSET(r3) | |
1247 | subf r5,r4,r5 | |
e0b7ec05 PM |
1248 | std r5,VCPU_DEC_EXPIRES(r9) |
1249 | ||
b005255e MN |
1250 | BEGIN_FTR_SECTION |
1251 | b 8f | |
1252 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) | |
b005255e MN |
1253 | /* Save POWER8-specific registers */ |
1254 | mfspr r5, SPRN_IAMR | |
1255 | mfspr r6, SPRN_PSPB | |
1256 | mfspr r7, SPRN_FSCR | |
1257 | std r5, VCPU_IAMR(r9) | |
1258 | stw r6, VCPU_PSPB(r9) | |
1259 | std r7, VCPU_FSCR(r9) | |
1260 | mfspr r5, SPRN_IC | |
1261 | mfspr r6, SPRN_VTB | |
1262 | mfspr r7, SPRN_TAR | |
1263 | std r5, VCPU_IC(r9) | |
1264 | std r6, VCPU_VTB(r9) | |
1265 | std r7, VCPU_TAR(r9) | |
7b490411 | 1266 | mfspr r8, SPRN_EBBHR |
b005255e MN |
1267 | std r8, VCPU_EBBHR(r9) |
1268 | mfspr r5, SPRN_EBBRR | |
1269 | mfspr r6, SPRN_BESCR | |
1270 | mfspr r7, SPRN_CSIGR | |
1271 | mfspr r8, SPRN_TACR | |
1272 | std r5, VCPU_EBBRR(r9) | |
1273 | std r6, VCPU_BESCR(r9) | |
1274 | std r7, VCPU_CSIGR(r9) | |
1275 | std r8, VCPU_TACR(r9) | |
1276 | mfspr r5, SPRN_TCSCR | |
1277 | mfspr r6, SPRN_ACOP | |
1278 | mfspr r7, SPRN_PID | |
1279 | mfspr r8, SPRN_WORT | |
1280 | std r5, VCPU_TCSCR(r9) | |
1281 | std r6, VCPU_ACOP(r9) | |
1282 | stw r7, VCPU_GUEST_PID(r9) | |
1283 | std r8, VCPU_WORT(r9) | |
1284 | 8: | |
1285 | ||
e0b7ec05 PM |
1286 | /* Save and reset AMR and UAMOR before turning on the MMU */ |
1287 | BEGIN_FTR_SECTION | |
1288 | mfspr r5,SPRN_AMR | |
1289 | mfspr r6,SPRN_UAMOR | |
1290 | std r5,VCPU_AMR(r9) | |
1291 | std r6,VCPU_UAMOR(r9) | |
1292 | li r6,0 | |
1293 | mtspr SPRN_AMR,r6 | |
1294 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) | |
1295 | ||
1296 | /* Switch DSCR back to host value */ | |
1297 | BEGIN_FTR_SECTION | |
1298 | mfspr r8, SPRN_DSCR | |
1299 | ld r7, HSTATE_DSCR(r13) | |
1300 | std r8, VCPU_DSCR(r9) | |
1301 | mtspr SPRN_DSCR, r7 | |
1302 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) | |
1303 | ||
1304 | /* Save non-volatile GPRs */ | |
1305 | std r14, VCPU_GPR(R14)(r9) | |
1306 | std r15, VCPU_GPR(R15)(r9) | |
1307 | std r16, VCPU_GPR(R16)(r9) | |
1308 | std r17, VCPU_GPR(R17)(r9) | |
1309 | std r18, VCPU_GPR(R18)(r9) | |
1310 | std r19, VCPU_GPR(R19)(r9) | |
1311 | std r20, VCPU_GPR(R20)(r9) | |
1312 | std r21, VCPU_GPR(R21)(r9) | |
1313 | std r22, VCPU_GPR(R22)(r9) | |
1314 | std r23, VCPU_GPR(R23)(r9) | |
1315 | std r24, VCPU_GPR(R24)(r9) | |
1316 | std r25, VCPU_GPR(R25)(r9) | |
1317 | std r26, VCPU_GPR(R26)(r9) | |
1318 | std r27, VCPU_GPR(R27)(r9) | |
1319 | std r28, VCPU_GPR(R28)(r9) | |
1320 | std r29, VCPU_GPR(R29)(r9) | |
1321 | std r30, VCPU_GPR(R30)(r9) | |
1322 | std r31, VCPU_GPR(R31)(r9) | |
1323 | ||
1324 | /* Save SPRGs */ | |
1325 | mfspr r3, SPRN_SPRG0 | |
1326 | mfspr r4, SPRN_SPRG1 | |
1327 | mfspr r5, SPRN_SPRG2 | |
1328 | mfspr r6, SPRN_SPRG3 | |
1329 | std r3, VCPU_SPRG0(r9) | |
1330 | std r4, VCPU_SPRG1(r9) | |
1331 | std r5, VCPU_SPRG2(r9) | |
1332 | std r6, VCPU_SPRG3(r9) | |
1333 | ||
1334 | /* save FP state */ | |
1335 | mr r3, r9 | |
1336 | bl kvmppc_save_fp | |
de56a948 | 1337 | |
0a8eccef PM |
1338 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1339 | BEGIN_FTR_SECTION | |
1340 | b 2f | |
1341 | END_FTR_SECTION_IFCLR(CPU_FTR_TM) | |
1342 | /* Turn on TM. */ | |
1343 | mfmsr r8 | |
1344 | li r0, 1 | |
1345 | rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG | |
1346 | mtmsrd r8 | |
1347 | ||
1348 | ld r5, VCPU_MSR(r9) | |
1349 | rldicl. r5, r5, 64 - MSR_TS_S_LG, 62 | |
1350 | beq 1f /* TM not active in guest. */ | |
1351 | ||
1352 | li r3, TM_CAUSE_KVM_RESCHED | |
1353 | ||
1354 | /* Clear the MSR RI since r1, r13 are all going to be foobar. */ | |
1355 | li r5, 0 | |
1356 | mtmsrd r5, 1 | |
1357 | ||
1358 | /* All GPRs are volatile at this point. */ | |
1359 | TRECLAIM(R3) | |
1360 | ||
1361 | /* Temporarily store r13 and r9 so we have some regs to play with */ | |
1362 | SET_SCRATCH0(r13) | |
1363 | GET_PACA(r13) | |
1364 | std r9, PACATMSCRATCH(r13) | |
1365 | ld r9, HSTATE_KVM_VCPU(r13) | |
1366 | ||
1367 | /* Get a few more GPRs free. */ | |
1368 | std r29, VCPU_GPRS_TM(29)(r9) | |
1369 | std r30, VCPU_GPRS_TM(30)(r9) | |
1370 | std r31, VCPU_GPRS_TM(31)(r9) | |
1371 | ||
1372 | /* Save away PPR and DSCR soon so don't run with user values. */ | |
1373 | mfspr r31, SPRN_PPR | |
1374 | HMT_MEDIUM | |
1375 | mfspr r30, SPRN_DSCR | |
1376 | ld r29, HSTATE_DSCR(r13) | |
1377 | mtspr SPRN_DSCR, r29 | |
1378 | ||
1379 | /* Save all but r9, r13 & r29-r31 */ | |
1380 | reg = 0 | |
1381 | .rept 29 | |
1382 | .if (reg != 9) && (reg != 13) | |
1383 | std reg, VCPU_GPRS_TM(reg)(r9) | |
1384 | .endif | |
1385 | reg = reg + 1 | |
1386 | .endr | |
1387 | /* ... now save r13 */ | |
1388 | GET_SCRATCH0(r4) | |
1389 | std r4, VCPU_GPRS_TM(13)(r9) | |
1390 | /* ... and save r9 */ | |
1391 | ld r4, PACATMSCRATCH(r13) | |
1392 | std r4, VCPU_GPRS_TM(9)(r9) | |
1393 | ||
1394 | /* Reload stack pointer and TOC. */ | |
1395 | ld r1, HSTATE_HOST_R1(r13) | |
1396 | ld r2, PACATOC(r13) | |
1397 | ||
1398 | /* Set MSR RI now we have r1 and r13 back. */ | |
1399 | li r5, MSR_RI | |
1400 | mtmsrd r5, 1 | |
1401 | ||
1402 | /* Save away checkpinted SPRs. */ | |
1403 | std r31, VCPU_PPR_TM(r9) | |
1404 | std r30, VCPU_DSCR_TM(r9) | |
1405 | mflr r5 | |
1406 | mfcr r6 | |
1407 | mfctr r7 | |
1408 | mfspr r8, SPRN_AMR | |
1409 | mfspr r10, SPRN_TAR | |
1410 | std r5, VCPU_LR_TM(r9) | |
1411 | stw r6, VCPU_CR_TM(r9) | |
1412 | std r7, VCPU_CTR_TM(r9) | |
1413 | std r8, VCPU_AMR_TM(r9) | |
1414 | std r10, VCPU_TAR_TM(r9) | |
1415 | ||
1416 | /* Restore r12 as trap number. */ | |
1417 | lwz r12, VCPU_TRAP(r9) | |
1418 | ||
1419 | /* Save FP/VSX. */ | |
1420 | addi r3, r9, VCPU_FPRS_TM | |
1421 | bl .store_fp_state | |
1422 | addi r3, r9, VCPU_VRS_TM | |
1423 | bl .store_vr_state | |
1424 | mfspr r6, SPRN_VRSAVE | |
1425 | stw r6, VCPU_VRSAVE_TM(r9) | |
1426 | 1: | |
1427 | /* | |
1428 | * We need to save these SPRs after the treclaim so that the software | |
1429 | * error code is recorded correctly in the TEXASR. Also the user may | |
1430 | * change these outside of a transaction, so they must always be | |
1431 | * context switched. | |
1432 | */ | |
1433 | mfspr r5, SPRN_TFHAR | |
1434 | mfspr r6, SPRN_TFIAR | |
1435 | mfspr r7, SPRN_TEXASR | |
1436 | std r5, VCPU_TFHAR(r9) | |
1437 | std r6, VCPU_TFIAR(r9) | |
1438 | std r7, VCPU_TEXASR(r9) | |
1439 | 2: | |
1440 | #endif | |
1441 | ||
e0b7ec05 PM |
1442 | /* Increment yield count if they have a VPA */ |
1443 | ld r8, VCPU_VPA(r9) /* do they have a VPA? */ | |
1444 | cmpdi r8, 0 | |
1445 | beq 25f | |
1446 | lwz r3, LPPACA_YIELDCOUNT(r8) | |
1447 | addi r3, r3, 1 | |
1448 | stw r3, LPPACA_YIELDCOUNT(r8) | |
1449 | li r3, 1 | |
1450 | stb r3, VCPU_VPA_DIRTY(r9) | |
1451 | 25: | |
1452 | /* Save PMU registers if requested */ | |
1453 | /* r8 and cr0.eq are live here */ | |
9bc01a9b PM |
1454 | BEGIN_FTR_SECTION |
1455 | /* | |
1456 | * POWER8 seems to have a hardware bug where setting | |
1457 | * MMCR0[PMAE] along with MMCR0[PMC1CE] and/or MMCR0[PMCjCE] | |
1458 | * when some counters are already negative doesn't seem | |
1459 | * to cause a performance monitor alert (and hence interrupt). | |
1460 | * The effect of this is that when saving the PMU state, | |
1461 | * if there is no PMU alert pending when we read MMCR0 | |
1462 | * before freezing the counters, but one becomes pending | |
1463 | * before we read the counters, we lose it. | |
1464 | * To work around this, we need a way to freeze the counters | |
1465 | * before reading MMCR0. Normally, freezing the counters | |
1466 | * is done by writing MMCR0 (to set MMCR0[FC]) which | |
1467 | * unavoidably writes MMCR0[PMA0] as well. On POWER8, | |
1468 | * we can also freeze the counters using MMCR2, by writing | |
1469 | * 1s to all the counter freeze condition bits (there are | |
1470 | * 9 bits each for 6 counters). | |
1471 | */ | |
1472 | li r3, -1 /* set all freeze bits */ | |
1473 | clrrdi r3, r3, 10 | |
1474 | mfspr r10, SPRN_MMCR2 | |
1475 | mtspr SPRN_MMCR2, r3 | |
1476 | isync | |
1477 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) | |
e0b7ec05 PM |
1478 | li r3, 1 |
1479 | sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */ | |
1480 | mfspr r4, SPRN_MMCR0 /* save MMCR0 */ | |
1481 | mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */ | |
1482 | mfspr r6, SPRN_MMCRA | |
1483 | BEGIN_FTR_SECTION | |
1484 | /* On P7, clear MMCRA in order to disable SDAR updates */ | |
1485 | li r7, 0 | |
1486 | mtspr SPRN_MMCRA, r7 | |
1487 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) | |
1488 | isync | |
1489 | beq 21f /* if no VPA, save PMU stuff anyway */ | |
1490 | lbz r7, LPPACA_PMCINUSE(r8) | |
1491 | cmpwi r7, 0 /* did they ask for PMU stuff to be saved? */ | |
1492 | bne 21f | |
1493 | std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */ | |
1494 | b 22f | |
1495 | 21: mfspr r5, SPRN_MMCR1 | |
1496 | mfspr r7, SPRN_SIAR | |
1497 | mfspr r8, SPRN_SDAR | |
1498 | std r4, VCPU_MMCR(r9) | |
1499 | std r5, VCPU_MMCR + 8(r9) | |
1500 | std r6, VCPU_MMCR + 16(r9) | |
9bc01a9b PM |
1501 | BEGIN_FTR_SECTION |
1502 | std r10, VCPU_MMCR + 24(r9) | |
1503 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) | |
e0b7ec05 PM |
1504 | std r7, VCPU_SIAR(r9) |
1505 | std r8, VCPU_SDAR(r9) | |
1506 | mfspr r3, SPRN_PMC1 | |
1507 | mfspr r4, SPRN_PMC2 | |
1508 | mfspr r5, SPRN_PMC3 | |
1509 | mfspr r6, SPRN_PMC4 | |
1510 | mfspr r7, SPRN_PMC5 | |
1511 | mfspr r8, SPRN_PMC6 | |
1512 | BEGIN_FTR_SECTION | |
1513 | mfspr r10, SPRN_PMC7 | |
1514 | mfspr r11, SPRN_PMC8 | |
1515 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
1516 | stw r3, VCPU_PMC(r9) | |
1517 | stw r4, VCPU_PMC + 4(r9) | |
1518 | stw r5, VCPU_PMC + 8(r9) | |
1519 | stw r6, VCPU_PMC + 12(r9) | |
1520 | stw r7, VCPU_PMC + 16(r9) | |
1521 | stw r8, VCPU_PMC + 20(r9) | |
1522 | BEGIN_FTR_SECTION | |
1523 | stw r10, VCPU_PMC + 24(r9) | |
1524 | stw r11, VCPU_PMC + 28(r9) | |
1525 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
b005255e | 1526 | BEGIN_FTR_SECTION |
b005255e MN |
1527 | mfspr r5, SPRN_SIER |
1528 | mfspr r6, SPRN_SPMC1 | |
1529 | mfspr r7, SPRN_SPMC2 | |
1530 | mfspr r8, SPRN_MMCRS | |
b005255e MN |
1531 | std r5, VCPU_SIER(r9) |
1532 | stw r6, VCPU_PMC + 24(r9) | |
1533 | stw r7, VCPU_PMC + 28(r9) | |
1534 | std r8, VCPU_MMCR + 32(r9) | |
1535 | lis r4, 0x8000 | |
1536 | mtspr SPRN_MMCRS, r4 | |
1537 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) | |
e0b7ec05 | 1538 | 22: |
de56a948 PM |
1539 | /* Clear out SLB */ |
1540 | li r5,0 | |
1541 | slbmte r5,r5 | |
1542 | slbia | |
1543 | ptesync | |
1544 | ||
e0b7ec05 | 1545 | hdec_soon: /* r12 = trap, r13 = paca */ |
9e368f29 PM |
1546 | BEGIN_FTR_SECTION |
1547 | b 32f | |
1548 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
1549 | /* | |
1550 | * POWER7 guest -> host partition switch code. | |
1551 | * We don't have to lock against tlbies but we do | |
1552 | * have to coordinate the hardware threads. | |
1553 | */ | |
371fefd6 PM |
1554 | /* Increment the threads-exiting-guest count in the 0xff00 |
1555 | bits of vcore->entry_exit_count */ | |
371fefd6 PM |
1556 | ld r5,HSTATE_KVM_VCORE(r13) |
1557 | addi r6,r5,VCORE_ENTRY_EXIT | |
1558 | 41: lwarx r3,0,r6 | |
1559 | addi r0,r3,0x100 | |
1560 | stwcx. r0,0,r6 | |
1561 | bne 41b | |
f019b7ad | 1562 | isync /* order stwcx. vs. reading napping_threads */ |
371fefd6 PM |
1563 | |
1564 | /* | |
1565 | * At this point we have an interrupt that we have to pass | |
1566 | * up to the kernel or qemu; we can't handle it in real mode. | |
1567 | * Thus we have to do a partition switch, so we have to | |
1568 | * collect the other threads, if we are the first thread | |
1569 | * to take an interrupt. To do this, we set the HDEC to 0, | |
1570 | * which causes an HDEC interrupt in all threads within 2ns | |
1571 | * because the HDEC register is shared between all 4 threads. | |
1572 | * However, we don't need to bother if this is an HDEC | |
1573 | * interrupt, since the other threads will already be on their | |
1574 | * way here in that case. | |
1575 | */ | |
19ccb76a PM |
1576 | cmpwi r3,0x100 /* Are we the first here? */ |
1577 | bge 43f | |
371fefd6 PM |
1578 | cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER |
1579 | beq 40f | |
371fefd6 PM |
1580 | li r0,0 |
1581 | mtspr SPRN_HDEC,r0 | |
1582 | 40: | |
19ccb76a PM |
1583 | /* |
1584 | * Send an IPI to any napping threads, since an HDEC interrupt | |
1585 | * doesn't wake CPUs up from nap. | |
1586 | */ | |
1587 | lwz r3,VCORE_NAPPING_THREADS(r5) | |
e0b7ec05 | 1588 | lbz r4,HSTATE_PTID(r13) |
19ccb76a | 1589 | li r0,1 |
2f584a14 | 1590 | sld r0,r0,r4 |
19ccb76a PM |
1591 | andc. r3,r3,r0 /* no sense IPI'ing ourselves */ |
1592 | beq 43f | |
f019b7ad PM |
1593 | /* Order entry/exit update vs. IPIs */ |
1594 | sync | |
19ccb76a PM |
1595 | mulli r4,r4,PACA_SIZE /* get paca for thread 0 */ |
1596 | subf r6,r4,r13 | |
1597 | 42: andi. r0,r3,1 | |
1598 | beq 44f | |
1599 | ld r8,HSTATE_XICS_PHYS(r6) /* get thread's XICS reg addr */ | |
1600 | li r0,IPI_PRIORITY | |
54695c30 | 1601 | li r7,XICS_MFRR |
19ccb76a PM |
1602 | stbcix r0,r7,r8 /* trigger the IPI */ |
1603 | 44: srdi. r3,r3,1 | |
1604 | addi r6,r6,PACA_SIZE | |
1605 | bne 42b | |
371fefd6 | 1606 | |
e0b7ec05 | 1607 | secondary_too_late: |
371fefd6 | 1608 | /* Secondary threads wait for primary to do partition switch */ |
e0b7ec05 PM |
1609 | 43: ld r5,HSTATE_KVM_VCORE(r13) |
1610 | ld r4,VCORE_KVM(r5) /* pointer to struct kvm */ | |
1611 | lbz r3,HSTATE_PTID(r13) | |
371fefd6 PM |
1612 | cmpwi r3,0 |
1613 | beq 15f | |
1614 | HMT_LOW | |
1615 | 13: lbz r3,VCORE_IN_GUEST(r5) | |
1616 | cmpwi r3,0 | |
1617 | bne 13b | |
1618 | HMT_MEDIUM | |
1619 | b 16f | |
1620 | ||
1621 | /* Primary thread waits for all the secondaries to exit guest */ | |
1622 | 15: lwz r3,VCORE_ENTRY_EXIT(r5) | |
1623 | srwi r0,r3,8 | |
1624 | clrldi r3,r3,56 | |
1625 | cmpw r3,r0 | |
1626 | bne 15b | |
1627 | isync | |
1628 | ||
1629 | /* Primary thread switches back to host partition */ | |
de56a948 PM |
1630 | ld r6,KVM_HOST_SDR1(r4) |
1631 | lwz r7,KVM_HOST_LPID(r4) | |
1632 | li r8,LPID_RSVD /* switch to reserved LPID */ | |
1633 | mtspr SPRN_LPID,r8 | |
1634 | ptesync | |
1635 | mtspr SPRN_SDR1,r6 /* switch to partition page table */ | |
1636 | mtspr SPRN_LPID,r7 | |
1637 | isync | |
93b0f4dc | 1638 | |
b005255e MN |
1639 | BEGIN_FTR_SECTION |
1640 | /* DPDES is shared between threads */ | |
1641 | mfspr r7, SPRN_DPDES | |
1642 | std r7, VCORE_DPDES(r5) | |
1643 | /* clear DPDES so we don't get guest doorbells in the host */ | |
1644 | li r8, 0 | |
1645 | mtspr SPRN_DPDES, r8 | |
1646 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) | |
1647 | ||
93b0f4dc PM |
1648 | /* Subtract timebase offset from timebase */ |
1649 | ld r8,VCORE_TB_OFFSET(r5) | |
1650 | cmpdi r8,0 | |
1651 | beq 17f | |
c5fb80d3 | 1652 | mftb r6 /* current guest timebase */ |
93b0f4dc PM |
1653 | subf r8,r8,r6 |
1654 | mtspr SPRN_TBU40,r8 /* update upper 40 bits */ | |
1655 | mftb r7 /* check if lower 24 bits overflowed */ | |
1656 | clrldi r6,r6,40 | |
1657 | clrldi r7,r7,40 | |
1658 | cmpld r7,r6 | |
1659 | bge 17f | |
1660 | addis r8,r8,0x100 /* if so, increment upper 40 bits */ | |
1661 | mtspr SPRN_TBU40,r8 | |
1662 | ||
388cc6e1 PM |
1663 | /* Reset PCR */ |
1664 | 17: ld r0, VCORE_PCR(r5) | |
1665 | cmpdi r0, 0 | |
1666 | beq 18f | |
1667 | li r0, 0 | |
1668 | mtspr SPRN_PCR, r0 | |
1669 | 18: | |
93b0f4dc | 1670 | /* Signal secondary CPUs to continue */ |
371fefd6 | 1671 | stb r0,VCORE_IN_GUEST(r5) |
de56a948 PM |
1672 | lis r8,0x7fff /* MAX_INT@h */ |
1673 | mtspr SPRN_HDEC,r8 | |
1674 | ||
371fefd6 | 1675 | 16: ld r8,KVM_HOST_LPCR(r4) |
de56a948 PM |
1676 | mtspr SPRN_LPCR,r8 |
1677 | isync | |
9e368f29 PM |
1678 | b 33f |
1679 | ||
1680 | /* | |
1681 | * PPC970 guest -> host partition switch code. | |
1682 | * We have to lock against concurrent tlbies, and | |
1683 | * we have to flush the whole TLB. | |
1684 | */ | |
e0b7ec05 PM |
1685 | 32: ld r5,HSTATE_KVM_VCORE(r13) |
1686 | ld r4,VCORE_KVM(r5) /* pointer to struct kvm */ | |
9e368f29 PM |
1687 | |
1688 | /* Take the guest's tlbie_lock */ | |
54bb7f4b | 1689 | #ifdef __BIG_ENDIAN__ |
9e368f29 | 1690 | lwz r8,PACA_LOCK_TOKEN(r13) |
54bb7f4b AB |
1691 | #else |
1692 | lwz r8,PACAPACAINDEX(r13) | |
1693 | #endif | |
9e368f29 PM |
1694 | addi r3,r4,KVM_TLBIE_LOCK |
1695 | 24: lwarx r0,0,r3 | |
1696 | cmpwi r0,0 | |
1697 | bne 24b | |
1698 | stwcx. r8,0,r3 | |
1699 | bne 24b | |
1700 | isync | |
1701 | ||
1702 | ld r7,KVM_HOST_LPCR(r4) /* use kvm->arch.host_lpcr for HID4 */ | |
1703 | li r0,0x18f | |
1704 | rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */ | |
1705 | or r0,r7,r0 | |
1706 | ptesync | |
1707 | sync | |
1708 | mtspr SPRN_HID4,r0 /* switch to reserved LPID */ | |
1709 | isync | |
1710 | li r0,0 | |
1711 | stw r0,0(r3) /* drop guest tlbie_lock */ | |
1712 | ||
1713 | /* invalidate the whole TLB */ | |
1714 | li r0,256 | |
1715 | mtctr r0 | |
1716 | li r6,0 | |
1717 | 25: tlbiel r6 | |
1718 | addi r6,r6,0x1000 | |
1719 | bdnz 25b | |
1720 | ptesync | |
1721 | ||
1722 | /* take native_tlbie_lock */ | |
1723 | ld r3,toc_tlbie_lock@toc(2) | |
1724 | 24: lwarx r0,0,r3 | |
1725 | cmpwi r0,0 | |
1726 | bne 24b | |
1727 | stwcx. r8,0,r3 | |
1728 | bne 24b | |
1729 | isync | |
1730 | ||
1731 | ld r6,KVM_HOST_SDR1(r4) | |
1732 | mtspr SPRN_SDR1,r6 /* switch to host page table */ | |
1733 | ||
1734 | /* Set up host HID4 value */ | |
1735 | sync | |
1736 | mtspr SPRN_HID4,r7 | |
1737 | isync | |
1738 | li r0,0 | |
1739 | stw r0,0(r3) /* drop native_tlbie_lock */ | |
1740 | ||
1741 | lis r8,0x7fff /* MAX_INT@h */ | |
1742 | mtspr SPRN_HDEC,r8 | |
1743 | ||
1744 | /* Disable HDEC interrupts */ | |
1745 | mfspr r0,SPRN_HID0 | |
1746 | li r3,0 | |
1747 | rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1 | |
1748 | sync | |
1749 | mtspr SPRN_HID0,r0 | |
1750 | mfspr r0,SPRN_HID0 | |
1751 | mfspr r0,SPRN_HID0 | |
1752 | mfspr r0,SPRN_HID0 | |
1753 | mfspr r0,SPRN_HID0 | |
1754 | mfspr r0,SPRN_HID0 | |
1755 | mfspr r0,SPRN_HID0 | |
de56a948 PM |
1756 | |
1757 | /* load host SLB entries */ | |
9e368f29 | 1758 | 33: ld r8,PACA_SLBSHADOWPTR(r13) |
de56a948 PM |
1759 | |
1760 | .rept SLB_NUM_BOLTED | |
1761 | ld r5,SLBSHADOW_SAVEAREA(r8) | |
1762 | ld r6,SLBSHADOW_SAVEAREA+8(r8) | |
1763 | andis. r7,r5,SLB_ESID_V@h | |
1764 | beq 1f | |
1765 | slbmte r6,r5 | |
1766 | 1: addi r8,r8,16 | |
1767 | .endr | |
1768 | ||
44a3add8 PM |
1769 | /* Unset guest mode */ |
1770 | li r0, KVM_GUEST_MODE_NONE | |
1771 | stb r0, HSTATE_IN_GUEST(r13) | |
1772 | ||
218309b7 PM |
1773 | ld r0, 112+PPC_LR_STKOFF(r1) |
1774 | addi r1, r1, 112 | |
1775 | mtlr r0 | |
1776 | blr | |
b4072df4 | 1777 | |
697d3899 PM |
1778 | /* |
1779 | * Check whether an HDSI is an HPTE not found fault or something else. | |
1780 | * If it is an HPTE not found fault that is due to the guest accessing | |
1781 | * a page that they have mapped but which we have paged out, then | |
1782 | * we continue on with the guest exit path. In all other cases, | |
1783 | * reflect the HDSI to the guest as a DSI. | |
1784 | */ | |
1785 | kvmppc_hdsi: | |
1786 | mfspr r4, SPRN_HDAR | |
1787 | mfspr r6, SPRN_HDSISR | |
4cf302bc PM |
1788 | /* HPTE not found fault or protection fault? */ |
1789 | andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h | |
697d3899 PM |
1790 | beq 1f /* if not, send it to the guest */ |
1791 | andi. r0, r11, MSR_DR /* data relocation enabled? */ | |
1792 | beq 3f | |
1793 | clrrdi r0, r4, 28 | |
c75df6f9 | 1794 | PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */ |
697d3899 PM |
1795 | bne 1f /* if no SLB entry found */ |
1796 | 4: std r4, VCPU_FAULT_DAR(r9) | |
1797 | stw r6, VCPU_FAULT_DSISR(r9) | |
1798 | ||
1799 | /* Search the hash table. */ | |
1800 | mr r3, r9 /* vcpu pointer */ | |
342d3db7 | 1801 | li r7, 1 /* data fault */ |
697d3899 PM |
1802 | bl .kvmppc_hpte_hv_fault |
1803 | ld r9, HSTATE_KVM_VCPU(r13) | |
1804 | ld r10, VCPU_PC(r9) | |
1805 | ld r11, VCPU_MSR(r9) | |
1806 | li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE | |
1807 | cmpdi r3, 0 /* retry the instruction */ | |
1808 | beq 6f | |
1809 | cmpdi r3, -1 /* handle in kernel mode */ | |
b4072df4 | 1810 | beq guest_exit_cont |
697d3899 PM |
1811 | cmpdi r3, -2 /* MMIO emulation; need instr word */ |
1812 | beq 2f | |
1813 | ||
1814 | /* Synthesize a DSI for the guest */ | |
1815 | ld r4, VCPU_FAULT_DAR(r9) | |
1816 | mr r6, r3 | |
1817 | 1: mtspr SPRN_DAR, r4 | |
1818 | mtspr SPRN_DSISR, r6 | |
1819 | mtspr SPRN_SRR0, r10 | |
1820 | mtspr SPRN_SRR1, r11 | |
1821 | li r10, BOOK3S_INTERRUPT_DATA_STORAGE | |
e4e38121 | 1822 | bl kvmppc_msr_interrupt |
b4072df4 | 1823 | fast_interrupt_c_return: |
697d3899 PM |
1824 | 6: ld r7, VCPU_CTR(r9) |
1825 | lwz r8, VCPU_XER(r9) | |
1826 | mtctr r7 | |
1827 | mtxer r8 | |
1828 | mr r4, r9 | |
1829 | b fast_guest_return | |
1830 | ||
1831 | 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */ | |
1832 | ld r5, KVM_VRMA_SLB_V(r5) | |
1833 | b 4b | |
1834 | ||
1835 | /* If this is for emulated MMIO, load the instruction word */ | |
1836 | 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */ | |
1837 | ||
1838 | /* Set guest mode to 'jump over instruction' so if lwz faults | |
1839 | * we'll just continue at the next IP. */ | |
1840 | li r0, KVM_GUEST_MODE_SKIP | |
1841 | stb r0, HSTATE_IN_GUEST(r13) | |
1842 | ||
1843 | /* Do the access with MSR:DR enabled */ | |
1844 | mfmsr r3 | |
1845 | ori r4, r3, MSR_DR /* Enable paging for data */ | |
1846 | mtmsrd r4 | |
1847 | lwz r8, 0(r10) | |
1848 | mtmsrd r3 | |
1849 | ||
1850 | /* Store the result */ | |
1851 | stw r8, VCPU_LAST_INST(r9) | |
1852 | ||
1853 | /* Unset guest mode. */ | |
44a3add8 | 1854 | li r0, KVM_GUEST_MODE_HOST_HV |
697d3899 | 1855 | stb r0, HSTATE_IN_GUEST(r13) |
b4072df4 | 1856 | b guest_exit_cont |
de56a948 | 1857 | |
342d3db7 PM |
1858 | /* |
1859 | * Similarly for an HISI, reflect it to the guest as an ISI unless | |
1860 | * it is an HPTE not found fault for a page that we have paged out. | |
1861 | */ | |
1862 | kvmppc_hisi: | |
1863 | andis. r0, r11, SRR1_ISI_NOPT@h | |
1864 | beq 1f | |
1865 | andi. r0, r11, MSR_IR /* instruction relocation enabled? */ | |
1866 | beq 3f | |
1867 | clrrdi r0, r10, 28 | |
c75df6f9 | 1868 | PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */ |
342d3db7 PM |
1869 | bne 1f /* if no SLB entry found */ |
1870 | 4: | |
1871 | /* Search the hash table. */ | |
1872 | mr r3, r9 /* vcpu pointer */ | |
1873 | mr r4, r10 | |
1874 | mr r6, r11 | |
1875 | li r7, 0 /* instruction fault */ | |
1876 | bl .kvmppc_hpte_hv_fault | |
1877 | ld r9, HSTATE_KVM_VCPU(r13) | |
1878 | ld r10, VCPU_PC(r9) | |
1879 | ld r11, VCPU_MSR(r9) | |
1880 | li r12, BOOK3S_INTERRUPT_H_INST_STORAGE | |
1881 | cmpdi r3, 0 /* retry the instruction */ | |
b4072df4 | 1882 | beq fast_interrupt_c_return |
342d3db7 | 1883 | cmpdi r3, -1 /* handle in kernel mode */ |
b4072df4 | 1884 | beq guest_exit_cont |
342d3db7 PM |
1885 | |
1886 | /* Synthesize an ISI for the guest */ | |
1887 | mr r11, r3 | |
1888 | 1: mtspr SPRN_SRR0, r10 | |
1889 | mtspr SPRN_SRR1, r11 | |
1890 | li r10, BOOK3S_INTERRUPT_INST_STORAGE | |
e4e38121 | 1891 | bl kvmppc_msr_interrupt |
b4072df4 | 1892 | b fast_interrupt_c_return |
342d3db7 PM |
1893 | |
1894 | 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */ | |
1895 | ld r5, KVM_VRMA_SLB_V(r6) | |
1896 | b 4b | |
1897 | ||
a8606e20 PM |
1898 | /* |
1899 | * Try to handle an hcall in real mode. | |
1900 | * Returns to the guest if we handle it, or continues on up to | |
1901 | * the kernel if we can't (i.e. if we don't have a handler for | |
1902 | * it, or if the handler returns H_TOO_HARD). | |
1903 | */ | |
1904 | .globl hcall_try_real_mode | |
1905 | hcall_try_real_mode: | |
c75df6f9 | 1906 | ld r3,VCPU_GPR(R3)(r9) |
a8606e20 | 1907 | andi. r0,r11,MSR_PR |
27025a60 LPF |
1908 | /* sc 1 from userspace - reflect to guest syscall */ |
1909 | bne sc_1_fast_return | |
a8606e20 PM |
1910 | clrrdi r3,r3,2 |
1911 | cmpldi r3,hcall_real_table_end - hcall_real_table | |
b4072df4 | 1912 | bge guest_exit_cont |
a8606e20 | 1913 | LOAD_REG_ADDR(r4, hcall_real_table) |
4baa1d87 | 1914 | lwax r3,r3,r4 |
a8606e20 | 1915 | cmpwi r3,0 |
b4072df4 | 1916 | beq guest_exit_cont |
a8606e20 PM |
1917 | add r3,r3,r4 |
1918 | mtctr r3 | |
1919 | mr r3,r9 /* get vcpu pointer */ | |
c75df6f9 | 1920 | ld r4,VCPU_GPR(R4)(r9) |
a8606e20 PM |
1921 | bctrl |
1922 | cmpdi r3,H_TOO_HARD | |
1923 | beq hcall_real_fallback | |
1924 | ld r4,HSTATE_KVM_VCPU(r13) | |
c75df6f9 | 1925 | std r3,VCPU_GPR(R3)(r4) |
a8606e20 PM |
1926 | ld r10,VCPU_PC(r4) |
1927 | ld r11,VCPU_MSR(r4) | |
1928 | b fast_guest_return | |
1929 | ||
27025a60 LPF |
1930 | sc_1_fast_return: |
1931 | mtspr SPRN_SRR0,r10 | |
1932 | mtspr SPRN_SRR1,r11 | |
1933 | li r10, BOOK3S_INTERRUPT_SYSCALL | |
e4e38121 | 1934 | bl kvmppc_msr_interrupt |
27025a60 LPF |
1935 | mr r4,r9 |
1936 | b fast_guest_return | |
1937 | ||
a8606e20 PM |
1938 | /* We've attempted a real mode hcall, but it's punted it back |
1939 | * to userspace. We need to restore some clobbered volatiles | |
1940 | * before resuming the pass-it-to-qemu path */ | |
1941 | hcall_real_fallback: | |
1942 | li r12,BOOK3S_INTERRUPT_SYSCALL | |
1943 | ld r9, HSTATE_KVM_VCPU(r13) | |
a8606e20 | 1944 | |
b4072df4 | 1945 | b guest_exit_cont |
a8606e20 PM |
1946 | |
1947 | .globl hcall_real_table | |
1948 | hcall_real_table: | |
1949 | .long 0 /* 0 - unused */ | |
1950 | .long .kvmppc_h_remove - hcall_real_table | |
1951 | .long .kvmppc_h_enter - hcall_real_table | |
1952 | .long .kvmppc_h_read - hcall_real_table | |
1953 | .long 0 /* 0x10 - H_CLEAR_MOD */ | |
1954 | .long 0 /* 0x14 - H_CLEAR_REF */ | |
1955 | .long .kvmppc_h_protect - hcall_real_table | |
69e9fbb2 | 1956 | .long .kvmppc_h_get_tce - hcall_real_table |
54738c09 | 1957 | .long .kvmppc_h_put_tce - hcall_real_table |
a8606e20 PM |
1958 | .long 0 /* 0x24 - H_SET_SPRG0 */ |
1959 | .long .kvmppc_h_set_dabr - hcall_real_table | |
1960 | .long 0 /* 0x2c */ | |
1961 | .long 0 /* 0x30 */ | |
1962 | .long 0 /* 0x34 */ | |
1963 | .long 0 /* 0x38 */ | |
1964 | .long 0 /* 0x3c */ | |
1965 | .long 0 /* 0x40 */ | |
1966 | .long 0 /* 0x44 */ | |
1967 | .long 0 /* 0x48 */ | |
1968 | .long 0 /* 0x4c */ | |
1969 | .long 0 /* 0x50 */ | |
1970 | .long 0 /* 0x54 */ | |
1971 | .long 0 /* 0x58 */ | |
1972 | .long 0 /* 0x5c */ | |
1973 | .long 0 /* 0x60 */ | |
e7d26f28 BH |
1974 | #ifdef CONFIG_KVM_XICS |
1975 | .long .kvmppc_rm_h_eoi - hcall_real_table | |
1976 | .long .kvmppc_rm_h_cppr - hcall_real_table | |
1977 | .long .kvmppc_rm_h_ipi - hcall_real_table | |
1978 | .long 0 /* 0x70 - H_IPOLL */ | |
1979 | .long .kvmppc_rm_h_xirr - hcall_real_table | |
1980 | #else | |
1981 | .long 0 /* 0x64 - H_EOI */ | |
1982 | .long 0 /* 0x68 - H_CPPR */ | |
1983 | .long 0 /* 0x6c - H_IPI */ | |
1984 | .long 0 /* 0x70 - H_IPOLL */ | |
1985 | .long 0 /* 0x74 - H_XIRR */ | |
1986 | #endif | |
a8606e20 PM |
1987 | .long 0 /* 0x78 */ |
1988 | .long 0 /* 0x7c */ | |
1989 | .long 0 /* 0x80 */ | |
1990 | .long 0 /* 0x84 */ | |
1991 | .long 0 /* 0x88 */ | |
1992 | .long 0 /* 0x8c */ | |
1993 | .long 0 /* 0x90 */ | |
1994 | .long 0 /* 0x94 */ | |
1995 | .long 0 /* 0x98 */ | |
1996 | .long 0 /* 0x9c */ | |
1997 | .long 0 /* 0xa0 */ | |
1998 | .long 0 /* 0xa4 */ | |
1999 | .long 0 /* 0xa8 */ | |
2000 | .long 0 /* 0xac */ | |
2001 | .long 0 /* 0xb0 */ | |
2002 | .long 0 /* 0xb4 */ | |
2003 | .long 0 /* 0xb8 */ | |
2004 | .long 0 /* 0xbc */ | |
2005 | .long 0 /* 0xc0 */ | |
2006 | .long 0 /* 0xc4 */ | |
2007 | .long 0 /* 0xc8 */ | |
2008 | .long 0 /* 0xcc */ | |
2009 | .long 0 /* 0xd0 */ | |
2010 | .long 0 /* 0xd4 */ | |
2011 | .long 0 /* 0xd8 */ | |
2012 | .long 0 /* 0xdc */ | |
19ccb76a | 2013 | .long .kvmppc_h_cede - hcall_real_table |
a8606e20 PM |
2014 | .long 0 /* 0xe4 */ |
2015 | .long 0 /* 0xe8 */ | |
2016 | .long 0 /* 0xec */ | |
2017 | .long 0 /* 0xf0 */ | |
2018 | .long 0 /* 0xf4 */ | |
2019 | .long 0 /* 0xf8 */ | |
2020 | .long 0 /* 0xfc */ | |
2021 | .long 0 /* 0x100 */ | |
2022 | .long 0 /* 0x104 */ | |
2023 | .long 0 /* 0x108 */ | |
2024 | .long 0 /* 0x10c */ | |
2025 | .long 0 /* 0x110 */ | |
2026 | .long 0 /* 0x114 */ | |
2027 | .long 0 /* 0x118 */ | |
2028 | .long 0 /* 0x11c */ | |
2029 | .long 0 /* 0x120 */ | |
2030 | .long .kvmppc_h_bulk_remove - hcall_real_table | |
8563bf52 PM |
2031 | .long 0 /* 0x128 */ |
2032 | .long 0 /* 0x12c */ | |
2033 | .long 0 /* 0x130 */ | |
2034 | .long .kvmppc_h_set_xdabr - hcall_real_table | |
a8606e20 PM |
2035 | hcall_real_table_end: |
2036 | ||
de56a948 PM |
2037 | ignore_hdec: |
2038 | mr r4,r9 | |
2039 | b fast_guest_return | |
2040 | ||
8563bf52 PM |
2041 | _GLOBAL(kvmppc_h_set_xdabr) |
2042 | andi. r0, r5, DABRX_USER | DABRX_KERNEL | |
2043 | beq 6f | |
2044 | li r0, DABRX_USER | DABRX_KERNEL | DABRX_BTI | |
2045 | andc. r0, r5, r0 | |
2046 | beq 3f | |
2047 | 6: li r3, H_PARAMETER | |
2048 | blr | |
2049 | ||
a8606e20 | 2050 | _GLOBAL(kvmppc_h_set_dabr) |
8563bf52 PM |
2051 | li r5, DABRX_USER | DABRX_KERNEL |
2052 | 3: | |
eee7ff9d MN |
2053 | BEGIN_FTR_SECTION |
2054 | b 2f | |
2055 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) | |
a8606e20 | 2056 | std r4,VCPU_DABR(r3) |
8563bf52 PM |
2057 | stw r5, VCPU_DABRX(r3) |
2058 | mtspr SPRN_DABRX, r5 | |
8943633c PM |
2059 | /* Work around P7 bug where DABR can get corrupted on mtspr */ |
2060 | 1: mtspr SPRN_DABR,r4 | |
2061 | mfspr r5, SPRN_DABR | |
2062 | cmpd r4, r5 | |
2063 | bne 1b | |
2064 | isync | |
a8606e20 PM |
2065 | li r3,0 |
2066 | blr | |
2067 | ||
8563bf52 PM |
2068 | /* Emulate H_SET_DABR/X on P8 for the sake of compat mode guests */ |
2069 | 2: rlwimi r5, r4, 5, DAWRX_DR | DAWRX_DW | |
2070 | rlwimi r5, r4, 1, DAWRX_WT | |
2071 | clrrdi r4, r4, 3 | |
2072 | std r4, VCPU_DAWR(r3) | |
2073 | std r5, VCPU_DAWRX(r3) | |
2074 | mtspr SPRN_DAWR, r4 | |
2075 | mtspr SPRN_DAWRX, r5 | |
2076 | li r3, 0 | |
a8606e20 PM |
2077 | blr |
2078 | ||
19ccb76a PM |
2079 | _GLOBAL(kvmppc_h_cede) |
2080 | ori r11,r11,MSR_EE | |
2081 | std r11,VCPU_MSR(r3) | |
2082 | li r0,1 | |
2083 | stb r0,VCPU_CEDED(r3) | |
2084 | sync /* order setting ceded vs. testing prodded */ | |
2085 | lbz r5,VCPU_PRODDED(r3) | |
2086 | cmpwi r5,0 | |
04f995a5 | 2087 | bne kvm_cede_prodded |
19ccb76a PM |
2088 | li r0,0 /* set trap to 0 to say hcall is handled */ |
2089 | stw r0,VCPU_TRAP(r3) | |
2090 | li r0,H_SUCCESS | |
c75df6f9 | 2091 | std r0,VCPU_GPR(R3)(r3) |
19ccb76a | 2092 | BEGIN_FTR_SECTION |
04f995a5 | 2093 | b kvm_cede_exit /* just send it up to host on 970 */ |
19ccb76a PM |
2094 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206) |
2095 | ||
2096 | /* | |
2097 | * Set our bit in the bitmask of napping threads unless all the | |
2098 | * other threads are already napping, in which case we send this | |
2099 | * up to the host. | |
2100 | */ | |
2101 | ld r5,HSTATE_KVM_VCORE(r13) | |
e0b7ec05 | 2102 | lbz r6,HSTATE_PTID(r13) |
19ccb76a PM |
2103 | lwz r8,VCORE_ENTRY_EXIT(r5) |
2104 | clrldi r8,r8,56 | |
2105 | li r0,1 | |
2106 | sld r0,r0,r6 | |
2107 | addi r6,r5,VCORE_NAPPING_THREADS | |
2108 | 31: lwarx r4,0,r6 | |
2109 | or r4,r4,r0 | |
c75df6f9 | 2110 | PPC_POPCNTW(R7,R4) |
19ccb76a | 2111 | cmpw r7,r8 |
04f995a5 | 2112 | bge kvm_cede_exit |
19ccb76a PM |
2113 | stwcx. r4,0,r6 |
2114 | bne 31b | |
f019b7ad PM |
2115 | /* order napping_threads update vs testing entry_exit_count */ |
2116 | isync | |
e0b7ec05 | 2117 | li r0,NAPPING_CEDE |
19ccb76a | 2118 | stb r0,HSTATE_NAPPING(r13) |
19ccb76a PM |
2119 | lwz r7,VCORE_ENTRY_EXIT(r5) |
2120 | cmpwi r7,0x100 | |
2121 | bge 33f /* another thread already exiting */ | |
2122 | ||
2123 | /* | |
2124 | * Although not specifically required by the architecture, POWER7 | |
2125 | * preserves the following registers in nap mode, even if an SMT mode | |
2126 | * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3, | |
2127 | * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR. | |
2128 | */ | |
2129 | /* Save non-volatile GPRs */ | |
c75df6f9 MN |
2130 | std r14, VCPU_GPR(R14)(r3) |
2131 | std r15, VCPU_GPR(R15)(r3) | |
2132 | std r16, VCPU_GPR(R16)(r3) | |
2133 | std r17, VCPU_GPR(R17)(r3) | |
2134 | std r18, VCPU_GPR(R18)(r3) | |
2135 | std r19, VCPU_GPR(R19)(r3) | |
2136 | std r20, VCPU_GPR(R20)(r3) | |
2137 | std r21, VCPU_GPR(R21)(r3) | |
2138 | std r22, VCPU_GPR(R22)(r3) | |
2139 | std r23, VCPU_GPR(R23)(r3) | |
2140 | std r24, VCPU_GPR(R24)(r3) | |
2141 | std r25, VCPU_GPR(R25)(r3) | |
2142 | std r26, VCPU_GPR(R26)(r3) | |
2143 | std r27, VCPU_GPR(R27)(r3) | |
2144 | std r28, VCPU_GPR(R28)(r3) | |
2145 | std r29, VCPU_GPR(R29)(r3) | |
2146 | std r30, VCPU_GPR(R30)(r3) | |
2147 | std r31, VCPU_GPR(R31)(r3) | |
19ccb76a PM |
2148 | |
2149 | /* save FP state */ | |
595e4f7e | 2150 | bl kvmppc_save_fp |
19ccb76a PM |
2151 | |
2152 | /* | |
aa31e843 | 2153 | * Take a nap until a decrementer or external or doobell interrupt |
582b910e PM |
2154 | * occurs, with PECE1, PECE0 and PECEDP set in LPCR. Also clear the |
2155 | * runlatch bit before napping. | |
19ccb76a | 2156 | */ |
582b910e PM |
2157 | mfspr r2, SPRN_CTRLF |
2158 | clrrdi r2, r2, 1 | |
2159 | mtspr SPRN_CTRLT, r2 | |
2160 | ||
f0888f70 PM |
2161 | li r0,1 |
2162 | stb r0,HSTATE_HWTHREAD_REQ(r13) | |
19ccb76a PM |
2163 | mfspr r5,SPRN_LPCR |
2164 | ori r5,r5,LPCR_PECE0 | LPCR_PECE1 | |
aa31e843 PM |
2165 | BEGIN_FTR_SECTION |
2166 | oris r5,r5,LPCR_PECEDP@h | |
2167 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) | |
19ccb76a PM |
2168 | mtspr SPRN_LPCR,r5 |
2169 | isync | |
2170 | li r0, 0 | |
2171 | std r0, HSTATE_SCRATCH0(r13) | |
2172 | ptesync | |
2173 | ld r0, HSTATE_SCRATCH0(r13) | |
2174 | 1: cmpd r0, r0 | |
2175 | bne 1b | |
2176 | nap | |
2177 | b . | |
2178 | ||
e3bbbbfa PM |
2179 | 33: mr r4, r3 |
2180 | li r3, 0 | |
2181 | li r12, 0 | |
2182 | b 34f | |
2183 | ||
19ccb76a | 2184 | kvm_end_cede: |
4619ac88 PM |
2185 | /* get vcpu pointer */ |
2186 | ld r4, HSTATE_KVM_VCPU(r13) | |
2187 | ||
19ccb76a PM |
2188 | /* Woken by external or decrementer interrupt */ |
2189 | ld r1, HSTATE_HOST_R1(r13) | |
19ccb76a | 2190 | |
19ccb76a PM |
2191 | /* load up FP state */ |
2192 | bl kvmppc_load_fp | |
2193 | ||
2194 | /* Load NV GPRS */ | |
c75df6f9 MN |
2195 | ld r14, VCPU_GPR(R14)(r4) |
2196 | ld r15, VCPU_GPR(R15)(r4) | |
2197 | ld r16, VCPU_GPR(R16)(r4) | |
2198 | ld r17, VCPU_GPR(R17)(r4) | |
2199 | ld r18, VCPU_GPR(R18)(r4) | |
2200 | ld r19, VCPU_GPR(R19)(r4) | |
2201 | ld r20, VCPU_GPR(R20)(r4) | |
2202 | ld r21, VCPU_GPR(R21)(r4) | |
2203 | ld r22, VCPU_GPR(R22)(r4) | |
2204 | ld r23, VCPU_GPR(R23)(r4) | |
2205 | ld r24, VCPU_GPR(R24)(r4) | |
2206 | ld r25, VCPU_GPR(R25)(r4) | |
2207 | ld r26, VCPU_GPR(R26)(r4) | |
2208 | ld r27, VCPU_GPR(R27)(r4) | |
2209 | ld r28, VCPU_GPR(R28)(r4) | |
2210 | ld r29, VCPU_GPR(R29)(r4) | |
2211 | ld r30, VCPU_GPR(R30)(r4) | |
2212 | ld r31, VCPU_GPR(R31)(r4) | |
e3bbbbfa PM |
2213 | |
2214 | /* Check the wake reason in SRR1 to see why we got here */ | |
2215 | bl kvmppc_check_wake_reason | |
19ccb76a PM |
2216 | |
2217 | /* clear our bit in vcore->napping_threads */ | |
e3bbbbfa PM |
2218 | 34: ld r5,HSTATE_KVM_VCORE(r13) |
2219 | lbz r7,HSTATE_PTID(r13) | |
19ccb76a | 2220 | li r0,1 |
e3bbbbfa | 2221 | sld r0,r0,r7 |
19ccb76a PM |
2222 | addi r6,r5,VCORE_NAPPING_THREADS |
2223 | 32: lwarx r7,0,r6 | |
2224 | andc r7,r7,r0 | |
2225 | stwcx. r7,0,r6 | |
2226 | bne 32b | |
2227 | li r0,0 | |
2228 | stb r0,HSTATE_NAPPING(r13) | |
2229 | ||
e3bbbbfa PM |
2230 | /* See if the wake reason means we need to exit */ |
2231 | stw r12, VCPU_TRAP(r4) | |
4619ac88 | 2232 | mr r9, r4 |
e3bbbbfa PM |
2233 | cmpdi r3, 0 |
2234 | bgt guest_exit_cont | |
4619ac88 | 2235 | |
19ccb76a PM |
2236 | /* see if any other thread is already exiting */ |
2237 | lwz r0,VCORE_ENTRY_EXIT(r5) | |
2238 | cmpwi r0,0x100 | |
e3bbbbfa | 2239 | bge guest_exit_cont |
19ccb76a | 2240 | |
e3bbbbfa | 2241 | b kvmppc_cede_reentry /* if not go back to guest */ |
19ccb76a PM |
2242 | |
2243 | /* cede when already previously prodded case */ | |
04f995a5 PM |
2244 | kvm_cede_prodded: |
2245 | li r0,0 | |
19ccb76a PM |
2246 | stb r0,VCPU_PRODDED(r3) |
2247 | sync /* order testing prodded vs. clearing ceded */ | |
2248 | stb r0,VCPU_CEDED(r3) | |
2249 | li r3,H_SUCCESS | |
2250 | blr | |
2251 | ||
2252 | /* we've ceded but we want to give control to the host */ | |
04f995a5 | 2253 | kvm_cede_exit: |
4619ac88 | 2254 | b hcall_real_fallback |
19ccb76a | 2255 | |
b4072df4 PM |
2256 | /* Try to handle a machine check in real mode */ |
2257 | machine_check_realmode: | |
2258 | mr r3, r9 /* get vcpu pointer */ | |
2259 | bl .kvmppc_realmode_machine_check | |
2260 | nop | |
2261 | cmpdi r3, 0 /* continue exiting from guest? */ | |
2262 | ld r9, HSTATE_KVM_VCPU(r13) | |
2263 | li r12, BOOK3S_INTERRUPT_MACHINE_CHECK | |
2264 | beq mc_cont | |
2265 | /* If not, deliver a machine check. SRR0/1 are already set */ | |
2266 | li r10, BOOK3S_INTERRUPT_MACHINE_CHECK | |
000a25dd | 2267 | ld r11, VCPU_MSR(r9) |
e4e38121 | 2268 | bl kvmppc_msr_interrupt |
b4072df4 PM |
2269 | b fast_interrupt_c_return |
2270 | ||
e3bbbbfa PM |
2271 | /* |
2272 | * Check the reason we woke from nap, and take appropriate action. | |
2273 | * Returns: | |
2274 | * 0 if nothing needs to be done | |
2275 | * 1 if something happened that needs to be handled by the host | |
2276 | * -1 if there was a guest wakeup (IPI) | |
2277 | * | |
2278 | * Also sets r12 to the interrupt vector for any interrupt that needs | |
2279 | * to be handled now by the host (0x500 for external interrupt), or zero. | |
2280 | */ | |
2281 | kvmppc_check_wake_reason: | |
2282 | mfspr r6, SPRN_SRR1 | |
aa31e843 PM |
2283 | BEGIN_FTR_SECTION |
2284 | rlwinm r6, r6, 45-31, 0xf /* extract wake reason field (P8) */ | |
2285 | FTR_SECTION_ELSE | |
2286 | rlwinm r6, r6, 45-31, 0xe /* P7 wake reason field is 3 bits */ | |
2287 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S) | |
2288 | cmpwi r6, 8 /* was it an external interrupt? */ | |
e3bbbbfa PM |
2289 | li r12, BOOK3S_INTERRUPT_EXTERNAL |
2290 | beq kvmppc_read_intr /* if so, see what it was */ | |
2291 | li r3, 0 | |
2292 | li r12, 0 | |
2293 | cmpwi r6, 6 /* was it the decrementer? */ | |
2294 | beq 0f | |
aa31e843 PM |
2295 | BEGIN_FTR_SECTION |
2296 | cmpwi r6, 5 /* privileged doorbell? */ | |
2297 | beq 0f | |
5d00f66b PM |
2298 | cmpwi r6, 3 /* hypervisor doorbell? */ |
2299 | beq 3f | |
aa31e843 | 2300 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) |
e3bbbbfa PM |
2301 | li r3, 1 /* anything else, return 1 */ |
2302 | 0: blr | |
2303 | ||
5d00f66b PM |
2304 | /* hypervisor doorbell */ |
2305 | 3: li r12, BOOK3S_INTERRUPT_H_DOORBELL | |
2306 | li r3, 1 | |
2307 | blr | |
2308 | ||
c934243c PM |
2309 | /* |
2310 | * Determine what sort of external interrupt is pending (if any). | |
2311 | * Returns: | |
2312 | * 0 if no interrupt is pending | |
2313 | * 1 if an interrupt is pending that needs to be handled by the host | |
2314 | * -1 if there was a guest wakeup IPI (which has now been cleared) | |
2315 | */ | |
2316 | kvmppc_read_intr: | |
2317 | /* see if a host IPI is pending */ | |
2318 | li r3, 1 | |
2319 | lbz r0, HSTATE_HOST_IPI(r13) | |
2320 | cmpwi r0, 0 | |
2321 | bne 1f | |
371fefd6 | 2322 | |
c934243c PM |
2323 | /* Now read the interrupt from the ICP */ |
2324 | ld r6, HSTATE_XICS_PHYS(r13) | |
19ccb76a | 2325 | li r7, XICS_XIRR |
c934243c PM |
2326 | cmpdi r6, 0 |
2327 | beq- 1f | |
2328 | lwzcix r0, r6, r7 | |
2329 | rlwinm. r3, r0, 0, 0xffffff | |
19ccb76a | 2330 | sync |
c934243c | 2331 | beq 1f /* if nothing pending in the ICP */ |
371fefd6 | 2332 | |
c934243c PM |
2333 | /* We found something in the ICP... |
2334 | * | |
2335 | * If it's not an IPI, stash it in the PACA and return to | |
2336 | * the host, we don't (yet) handle directing real external | |
2337 | * interrupts directly to the guest | |
2338 | */ | |
2339 | cmpwi r3, XICS_IPI /* if there is, is it an IPI? */ | |
c934243c | 2340 | bne 42f |
371fefd6 | 2341 | |
c934243c PM |
2342 | /* It's an IPI, clear the MFRR and EOI it */ |
2343 | li r3, 0xff | |
2344 | li r8, XICS_MFRR | |
2345 | stbcix r3, r6, r8 /* clear the IPI */ | |
2346 | stwcix r0, r6, r7 /* EOI it */ | |
2347 | sync | |
f0888f70 | 2348 | |
c934243c PM |
2349 | /* We need to re-check host IPI now in case it got set in the |
2350 | * meantime. If it's clear, we bounce the interrupt to the | |
2351 | * guest | |
2352 | */ | |
2353 | lbz r0, HSTATE_HOST_IPI(r13) | |
2354 | cmpwi r0, 0 | |
2355 | bne- 43f | |
2356 | ||
2357 | /* OK, it's an IPI for us */ | |
2358 | li r3, -1 | |
2359 | 1: blr | |
2360 | ||
2361 | 42: /* It's not an IPI and it's for the host, stash it in the PACA | |
2362 | * before exit, it will be picked up by the host ICP driver | |
2363 | */ | |
2364 | stw r0, HSTATE_SAVED_XIRR(r13) | |
e3bbbbfa | 2365 | li r3, 1 |
c934243c PM |
2366 | b 1b |
2367 | ||
2368 | 43: /* We raced with the host, we need to resend that IPI, bummer */ | |
2369 | li r0, IPI_PRIORITY | |
2370 | stbcix r0, r6, r8 /* set the IPI */ | |
2371 | sync | |
e3bbbbfa | 2372 | li r3, 1 |
c934243c | 2373 | b 1b |
371fefd6 | 2374 | |
de56a948 PM |
2375 | /* |
2376 | * Save away FP, VMX and VSX registers. | |
2377 | * r3 = vcpu pointer | |
595e4f7e PM |
2378 | * N.B. r30 and r31 are volatile across this function, |
2379 | * thus it is not callable from C. | |
a8606e20 | 2380 | */ |
595e4f7e PM |
2381 | kvmppc_save_fp: |
2382 | mflr r30 | |
2383 | mr r31,r3 | |
8943633c PM |
2384 | mfmsr r5 |
2385 | ori r8,r5,MSR_FP | |
de56a948 PM |
2386 | #ifdef CONFIG_ALTIVEC |
2387 | BEGIN_FTR_SECTION | |
2388 | oris r8,r8,MSR_VEC@h | |
2389 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
2390 | #endif | |
2391 | #ifdef CONFIG_VSX | |
2392 | BEGIN_FTR_SECTION | |
2393 | oris r8,r8,MSR_VSX@h | |
2394 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
2395 | #endif | |
2396 | mtmsrd r8 | |
2397 | isync | |
595e4f7e PM |
2398 | addi r3,r3,VCPU_FPRS |
2399 | bl .store_fp_state | |
de56a948 PM |
2400 | #ifdef CONFIG_ALTIVEC |
2401 | BEGIN_FTR_SECTION | |
595e4f7e PM |
2402 | addi r3,r31,VCPU_VRS |
2403 | bl .store_vr_state | |
de56a948 PM |
2404 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) |
2405 | #endif | |
2406 | mfspr r6,SPRN_VRSAVE | |
e724f080 | 2407 | stw r6,VCPU_VRSAVE(r31) |
595e4f7e | 2408 | mtlr r30 |
de56a948 PM |
2409 | blr |
2410 | ||
2411 | /* | |
2412 | * Load up FP, VMX and VSX registers | |
2413 | * r4 = vcpu pointer | |
595e4f7e PM |
2414 | * N.B. r30 and r31 are volatile across this function, |
2415 | * thus it is not callable from C. | |
de56a948 | 2416 | */ |
de56a948 | 2417 | kvmppc_load_fp: |
595e4f7e PM |
2418 | mflr r30 |
2419 | mr r31,r4 | |
de56a948 PM |
2420 | mfmsr r9 |
2421 | ori r8,r9,MSR_FP | |
2422 | #ifdef CONFIG_ALTIVEC | |
2423 | BEGIN_FTR_SECTION | |
2424 | oris r8,r8,MSR_VEC@h | |
2425 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
2426 | #endif | |
2427 | #ifdef CONFIG_VSX | |
2428 | BEGIN_FTR_SECTION | |
2429 | oris r8,r8,MSR_VSX@h | |
2430 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
2431 | #endif | |
2432 | mtmsrd r8 | |
2433 | isync | |
595e4f7e PM |
2434 | addi r3,r4,VCPU_FPRS |
2435 | bl .load_fp_state | |
de56a948 PM |
2436 | #ifdef CONFIG_ALTIVEC |
2437 | BEGIN_FTR_SECTION | |
595e4f7e PM |
2438 | addi r3,r31,VCPU_VRS |
2439 | bl .load_vr_state | |
de56a948 PM |
2440 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) |
2441 | #endif | |
e724f080 | 2442 | lwz r7,VCPU_VRSAVE(r31) |
de56a948 | 2443 | mtspr SPRN_VRSAVE,r7 |
595e4f7e PM |
2444 | mtlr r30 |
2445 | mr r4,r31 | |
de56a948 | 2446 | blr |
44a3add8 PM |
2447 | |
2448 | /* | |
2449 | * We come here if we get any exception or interrupt while we are | |
2450 | * executing host real mode code while in guest MMU context. | |
2451 | * For now just spin, but we should do something better. | |
2452 | */ | |
2453 | kvmppc_bad_host_intr: | |
2454 | b . | |
e4e38121 MN |
2455 | |
2456 | /* | |
2457 | * This mimics the MSR transition on IRQ delivery. The new guest MSR is taken | |
2458 | * from VCPU_INTR_MSR and is modified based on the required TM state changes. | |
2459 | * r11 has the guest MSR value (in/out) | |
2460 | * r9 has a vcpu pointer (in) | |
2461 | * r0 is used as a scratch register | |
2462 | */ | |
2463 | kvmppc_msr_interrupt: | |
2464 | rldicl r0, r11, 64 - MSR_TS_S_LG, 62 | |
2465 | cmpwi r0, 2 /* Check if we are in transactional state.. */ | |
2466 | ld r11, VCPU_INTR_MSR(r9) | |
2467 | bne 1f | |
2468 | /* ... if transactional, change to suspended */ | |
2469 | li r0, 1 | |
2470 | 1: rldimi r11, r0, MSR_TS_S_LG, 63 - MSR_TS_T_LG | |
2471 | blr | |
9bc01a9b PM |
2472 | |
2473 | /* | |
2474 | * This works around a hardware bug on POWER8E processors, where | |
2475 | * writing a 1 to the MMCR0[PMAO] bit doesn't generate a | |
2476 | * performance monitor interrupt. Instead, when we need to have | |
2477 | * an interrupt pending, we have to arrange for a counter to overflow. | |
2478 | */ | |
2479 | kvmppc_fix_pmao: | |
2480 | li r3, 0 | |
2481 | mtspr SPRN_MMCR2, r3 | |
2482 | lis r3, (MMCR0_PMXE | MMCR0_FCECE)@h | |
2483 | ori r3, r3, MMCR0_PMCjCE | MMCR0_C56RUN | |
2484 | mtspr SPRN_MMCR0, r3 | |
2485 | lis r3, 0x7fff | |
2486 | ori r3, r3, 0xffff | |
2487 | mtspr SPRN_PMC6, r3 | |
2488 | isync | |
2489 | blr |