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f05ed4d5 PM |
1 | /* |
2 | * Copyright (C) 2009. SUSE Linux Products GmbH. All rights reserved. | |
3 | * | |
4 | * Authors: | |
5 | * Alexander Graf <agraf@suse.de> | |
6 | * Kevin Wolf <mail@kevin-wolf.de> | |
7 | * Paul Mackerras <paulus@samba.org> | |
8 | * | |
9 | * Description: | |
10 | * Functions relating to running KVM on Book 3S processors where | |
11 | * we don't have access to hypervisor mode, and we run the guest | |
12 | * in problem state (user mode). | |
13 | * | |
14 | * This file is derived from arch/powerpc/kvm/44x.c, | |
15 | * by Hollis Blanchard <hollisb@us.ibm.com>. | |
16 | * | |
17 | * This program is free software; you can redistribute it and/or modify | |
18 | * it under the terms of the GNU General Public License, version 2, as | |
19 | * published by the Free Software Foundation. | |
20 | */ | |
21 | ||
22 | #include <linux/kvm_host.h> | |
93087948 | 23 | #include <linux/export.h> |
f05ed4d5 PM |
24 | #include <linux/err.h> |
25 | #include <linux/slab.h> | |
26 | ||
27 | #include <asm/reg.h> | |
28 | #include <asm/cputable.h> | |
29 | #include <asm/cacheflush.h> | |
30 | #include <asm/tlbflush.h> | |
31 | #include <asm/uaccess.h> | |
32 | #include <asm/io.h> | |
33 | #include <asm/kvm_ppc.h> | |
34 | #include <asm/kvm_book3s.h> | |
35 | #include <asm/mmu_context.h> | |
95327d08 | 36 | #include <asm/switch_to.h> |
a413f474 | 37 | #include <asm/firmware.h> |
deb26c27 | 38 | #include <asm/hvcall.h> |
f05ed4d5 PM |
39 | #include <linux/gfp.h> |
40 | #include <linux/sched.h> | |
41 | #include <linux/vmalloc.h> | |
42 | #include <linux/highmem.h> | |
43 | ||
44 | #include "trace.h" | |
45 | ||
46 | /* #define EXIT_DEBUG */ | |
47 | /* #define DEBUG_EXT */ | |
48 | ||
49 | static int kvmppc_handle_ext(struct kvm_vcpu *vcpu, unsigned int exit_nr, | |
50 | ulong msr); | |
51 | ||
52 | /* Some compatibility defines */ | |
53 | #ifdef CONFIG_PPC_BOOK3S_32 | |
54 | #define MSR_USER32 MSR_USER | |
55 | #define MSR_USER64 MSR_USER | |
56 | #define HW_PAGE_SIZE PAGE_SIZE | |
57 | #endif | |
58 | ||
59 | void kvmppc_core_vcpu_load(struct kvm_vcpu *vcpu, int cpu) | |
60 | { | |
61 | #ifdef CONFIG_PPC_BOOK3S_64 | |
468a12c2 AG |
62 | struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu); |
63 | memcpy(svcpu->slb, to_book3s(vcpu)->slb_shadow, sizeof(svcpu->slb)); | |
f05ed4d5 PM |
64 | memcpy(&get_paca()->shadow_vcpu, to_book3s(vcpu)->shadow_vcpu, |
65 | sizeof(get_paca()->shadow_vcpu)); | |
468a12c2 AG |
66 | svcpu->slb_max = to_book3s(vcpu)->slb_shadow_max; |
67 | svcpu_put(svcpu); | |
f05ed4d5 | 68 | #endif |
a47d72f3 | 69 | vcpu->cpu = smp_processor_id(); |
f05ed4d5 PM |
70 | #ifdef CONFIG_PPC_BOOK3S_32 |
71 | current->thread.kvm_shadow_vcpu = to_book3s(vcpu)->shadow_vcpu; | |
72 | #endif | |
73 | } | |
74 | ||
75 | void kvmppc_core_vcpu_put(struct kvm_vcpu *vcpu) | |
76 | { | |
77 | #ifdef CONFIG_PPC_BOOK3S_64 | |
468a12c2 AG |
78 | struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu); |
79 | memcpy(to_book3s(vcpu)->slb_shadow, svcpu->slb, sizeof(svcpu->slb)); | |
f05ed4d5 PM |
80 | memcpy(to_book3s(vcpu)->shadow_vcpu, &get_paca()->shadow_vcpu, |
81 | sizeof(get_paca()->shadow_vcpu)); | |
468a12c2 AG |
82 | to_book3s(vcpu)->slb_shadow_max = svcpu->slb_max; |
83 | svcpu_put(svcpu); | |
f05ed4d5 PM |
84 | #endif |
85 | ||
28c483b6 | 86 | kvmppc_giveup_ext(vcpu, MSR_FP | MSR_VEC | MSR_VSX); |
a47d72f3 | 87 | vcpu->cpu = -1; |
f05ed4d5 PM |
88 | } |
89 | ||
7c973a2e | 90 | int kvmppc_core_check_requests(struct kvm_vcpu *vcpu) |
03d25c5b | 91 | { |
7c973a2e AG |
92 | int r = 1; /* Indicate we want to get back into the guest */ |
93 | ||
9b0cb3c8 AG |
94 | /* We misuse TLB_FLUSH to indicate that we want to clear |
95 | all shadow cache entries */ | |
96 | if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) | |
97 | kvmppc_mmu_pte_flush(vcpu, 0, 0); | |
7c973a2e AG |
98 | |
99 | return r; | |
03d25c5b AG |
100 | } |
101 | ||
9b0cb3c8 AG |
102 | /************* MMU Notifiers *************/ |
103 | ||
104 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva) | |
105 | { | |
106 | trace_kvm_unmap_hva(hva); | |
107 | ||
108 | /* | |
109 | * Flush all shadow tlb entries everywhere. This is slow, but | |
110 | * we are 100% sure that we catch the to be unmapped page | |
111 | */ | |
112 | kvm_flush_remote_tlbs(kvm); | |
113 | ||
114 | return 0; | |
115 | } | |
116 | ||
117 | int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end) | |
118 | { | |
119 | /* kvm_unmap_hva flushes everything anyways */ | |
120 | kvm_unmap_hva(kvm, start); | |
121 | ||
122 | return 0; | |
123 | } | |
124 | ||
125 | int kvm_age_hva(struct kvm *kvm, unsigned long hva) | |
126 | { | |
127 | /* XXX could be more clever ;) */ | |
128 | return 0; | |
129 | } | |
130 | ||
131 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva) | |
132 | { | |
133 | /* XXX could be more clever ;) */ | |
134 | return 0; | |
135 | } | |
136 | ||
137 | void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte) | |
138 | { | |
139 | /* The page will get remapped properly on its next fault */ | |
140 | kvm_unmap_hva(kvm, hva); | |
141 | } | |
142 | ||
143 | /*****************************************/ | |
144 | ||
f05ed4d5 PM |
145 | static void kvmppc_recalc_shadow_msr(struct kvm_vcpu *vcpu) |
146 | { | |
147 | ulong smsr = vcpu->arch.shared->msr; | |
148 | ||
149 | /* Guest MSR values */ | |
3a2e7b0d | 150 | smsr &= MSR_FE0 | MSR_FE1 | MSR_SF | MSR_SE | MSR_BE; |
f05ed4d5 PM |
151 | /* Process MSR values */ |
152 | smsr |= MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_PR | MSR_EE; | |
153 | /* External providers the guest reserved */ | |
154 | smsr |= (vcpu->arch.shared->msr & vcpu->arch.guest_owned_ext); | |
155 | /* 64-bit Process MSR values */ | |
156 | #ifdef CONFIG_PPC_BOOK3S_64 | |
157 | smsr |= MSR_ISF | MSR_HV; | |
158 | #endif | |
159 | vcpu->arch.shadow_msr = smsr; | |
160 | } | |
161 | ||
162 | void kvmppc_set_msr(struct kvm_vcpu *vcpu, u64 msr) | |
163 | { | |
164 | ulong old_msr = vcpu->arch.shared->msr; | |
165 | ||
166 | #ifdef EXIT_DEBUG | |
167 | printk(KERN_INFO "KVM: Set MSR to 0x%llx\n", msr); | |
168 | #endif | |
169 | ||
170 | msr &= to_book3s(vcpu)->msr_mask; | |
171 | vcpu->arch.shared->msr = msr; | |
172 | kvmppc_recalc_shadow_msr(vcpu); | |
173 | ||
174 | if (msr & MSR_POW) { | |
175 | if (!vcpu->arch.pending_exceptions) { | |
176 | kvm_vcpu_block(vcpu); | |
966cd0f3 | 177 | clear_bit(KVM_REQ_UNHALT, &vcpu->requests); |
f05ed4d5 PM |
178 | vcpu->stat.halt_wakeup++; |
179 | ||
180 | /* Unset POW bit after we woke up */ | |
181 | msr &= ~MSR_POW; | |
182 | vcpu->arch.shared->msr = msr; | |
183 | } | |
184 | } | |
185 | ||
186 | if ((vcpu->arch.shared->msr & (MSR_PR|MSR_IR|MSR_DR)) != | |
187 | (old_msr & (MSR_PR|MSR_IR|MSR_DR))) { | |
188 | kvmppc_mmu_flush_segments(vcpu); | |
189 | kvmppc_mmu_map_segment(vcpu, kvmppc_get_pc(vcpu)); | |
190 | ||
191 | /* Preload magic page segment when in kernel mode */ | |
192 | if (!(msr & MSR_PR) && vcpu->arch.magic_page_pa) { | |
193 | struct kvm_vcpu_arch *a = &vcpu->arch; | |
194 | ||
195 | if (msr & MSR_DR) | |
196 | kvmppc_mmu_map_segment(vcpu, a->magic_page_ea); | |
197 | else | |
198 | kvmppc_mmu_map_segment(vcpu, a->magic_page_pa); | |
199 | } | |
200 | } | |
201 | ||
bbcc9c06 BH |
202 | /* |
203 | * When switching from 32 to 64-bit, we may have a stale 32-bit | |
204 | * magic page around, we need to flush it. Typically 32-bit magic | |
205 | * page will be instanciated when calling into RTAS. Note: We | |
206 | * assume that such transition only happens while in kernel mode, | |
207 | * ie, we never transition from user 32-bit to kernel 64-bit with | |
208 | * a 32-bit magic page around. | |
209 | */ | |
210 | if (vcpu->arch.magic_page_pa && | |
211 | !(old_msr & MSR_PR) && !(old_msr & MSR_SF) && (msr & MSR_SF)) { | |
212 | /* going from RTAS to normal kernel code */ | |
213 | kvmppc_mmu_pte_flush(vcpu, (uint32_t)vcpu->arch.magic_page_pa, | |
214 | ~0xFFFUL); | |
215 | } | |
216 | ||
f05ed4d5 PM |
217 | /* Preload FPU if it's enabled */ |
218 | if (vcpu->arch.shared->msr & MSR_FP) | |
219 | kvmppc_handle_ext(vcpu, BOOK3S_INTERRUPT_FP_UNAVAIL, MSR_FP); | |
220 | } | |
221 | ||
222 | void kvmppc_set_pvr(struct kvm_vcpu *vcpu, u32 pvr) | |
223 | { | |
224 | u32 host_pvr; | |
225 | ||
226 | vcpu->arch.hflags &= ~BOOK3S_HFLAG_SLB; | |
227 | vcpu->arch.pvr = pvr; | |
228 | #ifdef CONFIG_PPC_BOOK3S_64 | |
229 | if ((pvr >= 0x330000) && (pvr < 0x70330000)) { | |
230 | kvmppc_mmu_book3s_64_init(vcpu); | |
1022fc3d AG |
231 | if (!to_book3s(vcpu)->hior_explicit) |
232 | to_book3s(vcpu)->hior = 0xfff00000; | |
f05ed4d5 | 233 | to_book3s(vcpu)->msr_mask = 0xffffffffffffffffULL; |
af8f38b3 | 234 | vcpu->arch.cpu_type = KVM_CPU_3S_64; |
f05ed4d5 PM |
235 | } else |
236 | #endif | |
237 | { | |
238 | kvmppc_mmu_book3s_32_init(vcpu); | |
1022fc3d AG |
239 | if (!to_book3s(vcpu)->hior_explicit) |
240 | to_book3s(vcpu)->hior = 0; | |
f05ed4d5 | 241 | to_book3s(vcpu)->msr_mask = 0xffffffffULL; |
af8f38b3 | 242 | vcpu->arch.cpu_type = KVM_CPU_3S_32; |
f05ed4d5 PM |
243 | } |
244 | ||
af8f38b3 AG |
245 | kvmppc_sanity_check(vcpu); |
246 | ||
f05ed4d5 PM |
247 | /* If we are in hypervisor level on 970, we can tell the CPU to |
248 | * treat DCBZ as 32 bytes store */ | |
249 | vcpu->arch.hflags &= ~BOOK3S_HFLAG_DCBZ32; | |
250 | if (vcpu->arch.mmu.is_dcbz32(vcpu) && (mfmsr() & MSR_HV) && | |
251 | !strcmp(cur_cpu_spec->platform, "ppc970")) | |
252 | vcpu->arch.hflags |= BOOK3S_HFLAG_DCBZ32; | |
253 | ||
254 | /* Cell performs badly if MSR_FEx are set. So let's hope nobody | |
255 | really needs them in a VM on Cell and force disable them. */ | |
256 | if (!strcmp(cur_cpu_spec->platform, "ppc-cell-be")) | |
257 | to_book3s(vcpu)->msr_mask &= ~(MSR_FE0 | MSR_FE1); | |
258 | ||
259 | #ifdef CONFIG_PPC_BOOK3S_32 | |
260 | /* 32 bit Book3S always has 32 byte dcbz */ | |
261 | vcpu->arch.hflags |= BOOK3S_HFLAG_DCBZ32; | |
262 | #endif | |
263 | ||
264 | /* On some CPUs we can execute paired single operations natively */ | |
265 | asm ( "mfpvr %0" : "=r"(host_pvr)); | |
266 | switch (host_pvr) { | |
267 | case 0x00080200: /* lonestar 2.0 */ | |
268 | case 0x00088202: /* lonestar 2.2 */ | |
269 | case 0x70000100: /* gekko 1.0 */ | |
270 | case 0x00080100: /* gekko 2.0 */ | |
271 | case 0x00083203: /* gekko 2.3a */ | |
272 | case 0x00083213: /* gekko 2.3b */ | |
273 | case 0x00083204: /* gekko 2.4 */ | |
274 | case 0x00083214: /* gekko 2.4e (8SE) - retail HW2 */ | |
275 | case 0x00087200: /* broadway */ | |
276 | vcpu->arch.hflags |= BOOK3S_HFLAG_NATIVE_PS; | |
277 | /* Enable HID2.PSE - in case we need it later */ | |
278 | mtspr(SPRN_HID2_GEKKO, mfspr(SPRN_HID2_GEKKO) | (1 << 29)); | |
279 | } | |
280 | } | |
281 | ||
282 | /* Book3s_32 CPUs always have 32 bytes cache line size, which Linux assumes. To | |
283 | * make Book3s_32 Linux work on Book3s_64, we have to make sure we trap dcbz to | |
284 | * emulate 32 bytes dcbz length. | |
285 | * | |
286 | * The Book3s_64 inventors also realized this case and implemented a special bit | |
287 | * in the HID5 register, which is a hypervisor ressource. Thus we can't use it. | |
288 | * | |
289 | * My approach here is to patch the dcbz instruction on executing pages. | |
290 | */ | |
291 | static void kvmppc_patch_dcbz(struct kvm_vcpu *vcpu, struct kvmppc_pte *pte) | |
292 | { | |
293 | struct page *hpage; | |
294 | u64 hpage_offset; | |
295 | u32 *page; | |
296 | int i; | |
297 | ||
298 | hpage = gfn_to_page(vcpu->kvm, pte->raddr >> PAGE_SHIFT); | |
32cad84f | 299 | if (is_error_page(hpage)) |
f05ed4d5 | 300 | return; |
f05ed4d5 PM |
301 | |
302 | hpage_offset = pte->raddr & ~PAGE_MASK; | |
303 | hpage_offset &= ~0xFFFULL; | |
304 | hpage_offset /= 4; | |
305 | ||
306 | get_page(hpage); | |
2480b208 | 307 | page = kmap_atomic(hpage); |
f05ed4d5 PM |
308 | |
309 | /* patch dcbz into reserved instruction, so we trap */ | |
310 | for (i=hpage_offset; i < hpage_offset + (HW_PAGE_SIZE / 4); i++) | |
311 | if ((page[i] & 0xff0007ff) == INS_DCBZ) | |
312 | page[i] &= 0xfffffff7; | |
313 | ||
2480b208 | 314 | kunmap_atomic(page); |
f05ed4d5 PM |
315 | put_page(hpage); |
316 | } | |
317 | ||
318 | static int kvmppc_visible_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
319 | { | |
320 | ulong mp_pa = vcpu->arch.magic_page_pa; | |
321 | ||
bbcc9c06 BH |
322 | if (!(vcpu->arch.shared->msr & MSR_SF)) |
323 | mp_pa = (uint32_t)mp_pa; | |
324 | ||
f05ed4d5 PM |
325 | if (unlikely(mp_pa) && |
326 | unlikely((mp_pa & KVM_PAM) >> PAGE_SHIFT == gfn)) { | |
327 | return 1; | |
328 | } | |
329 | ||
330 | return kvm_is_visible_gfn(vcpu->kvm, gfn); | |
331 | } | |
332 | ||
333 | int kvmppc_handle_pagefault(struct kvm_run *run, struct kvm_vcpu *vcpu, | |
334 | ulong eaddr, int vec) | |
335 | { | |
336 | bool data = (vec == BOOK3S_INTERRUPT_DATA_STORAGE); | |
337 | int r = RESUME_GUEST; | |
338 | int relocated; | |
339 | int page_found = 0; | |
340 | struct kvmppc_pte pte; | |
341 | bool is_mmio = false; | |
342 | bool dr = (vcpu->arch.shared->msr & MSR_DR) ? true : false; | |
343 | bool ir = (vcpu->arch.shared->msr & MSR_IR) ? true : false; | |
344 | u64 vsid; | |
345 | ||
346 | relocated = data ? dr : ir; | |
347 | ||
348 | /* Resolve real address if translation turned on */ | |
349 | if (relocated) { | |
350 | page_found = vcpu->arch.mmu.xlate(vcpu, eaddr, &pte, data); | |
351 | } else { | |
352 | pte.may_execute = true; | |
353 | pte.may_read = true; | |
354 | pte.may_write = true; | |
355 | pte.raddr = eaddr & KVM_PAM; | |
356 | pte.eaddr = eaddr; | |
357 | pte.vpage = eaddr >> 12; | |
358 | } | |
359 | ||
360 | switch (vcpu->arch.shared->msr & (MSR_DR|MSR_IR)) { | |
361 | case 0: | |
362 | pte.vpage |= ((u64)VSID_REAL << (SID_SHIFT - 12)); | |
363 | break; | |
364 | case MSR_DR: | |
365 | case MSR_IR: | |
366 | vcpu->arch.mmu.esid_to_vsid(vcpu, eaddr >> SID_SHIFT, &vsid); | |
367 | ||
368 | if ((vcpu->arch.shared->msr & (MSR_DR|MSR_IR)) == MSR_DR) | |
369 | pte.vpage |= ((u64)VSID_REAL_DR << (SID_SHIFT - 12)); | |
370 | else | |
371 | pte.vpage |= ((u64)VSID_REAL_IR << (SID_SHIFT - 12)); | |
372 | pte.vpage |= vsid; | |
373 | ||
374 | if (vsid == -1) | |
375 | page_found = -EINVAL; | |
376 | break; | |
377 | } | |
378 | ||
379 | if (vcpu->arch.mmu.is_dcbz32(vcpu) && | |
380 | (!(vcpu->arch.hflags & BOOK3S_HFLAG_DCBZ32))) { | |
381 | /* | |
382 | * If we do the dcbz hack, we have to NX on every execution, | |
383 | * so we can patch the executing code. This renders our guest | |
384 | * NX-less. | |
385 | */ | |
386 | pte.may_execute = !data; | |
387 | } | |
388 | ||
389 | if (page_found == -ENOENT) { | |
390 | /* Page not found in guest PTE entries */ | |
468a12c2 | 391 | struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu); |
f05ed4d5 | 392 | vcpu->arch.shared->dar = kvmppc_get_fault_dar(vcpu); |
468a12c2 | 393 | vcpu->arch.shared->dsisr = svcpu->fault_dsisr; |
f05ed4d5 | 394 | vcpu->arch.shared->msr |= |
468a12c2 AG |
395 | (svcpu->shadow_srr1 & 0x00000000f8000000ULL); |
396 | svcpu_put(svcpu); | |
f05ed4d5 PM |
397 | kvmppc_book3s_queue_irqprio(vcpu, vec); |
398 | } else if (page_found == -EPERM) { | |
399 | /* Storage protection */ | |
468a12c2 | 400 | struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu); |
f05ed4d5 | 401 | vcpu->arch.shared->dar = kvmppc_get_fault_dar(vcpu); |
468a12c2 | 402 | vcpu->arch.shared->dsisr = svcpu->fault_dsisr & ~DSISR_NOHPTE; |
f05ed4d5 PM |
403 | vcpu->arch.shared->dsisr |= DSISR_PROTFAULT; |
404 | vcpu->arch.shared->msr |= | |
468a12c2 AG |
405 | svcpu->shadow_srr1 & 0x00000000f8000000ULL; |
406 | svcpu_put(svcpu); | |
f05ed4d5 PM |
407 | kvmppc_book3s_queue_irqprio(vcpu, vec); |
408 | } else if (page_found == -EINVAL) { | |
409 | /* Page not found in guest SLB */ | |
410 | vcpu->arch.shared->dar = kvmppc_get_fault_dar(vcpu); | |
411 | kvmppc_book3s_queue_irqprio(vcpu, vec + 0x80); | |
412 | } else if (!is_mmio && | |
413 | kvmppc_visible_gfn(vcpu, pte.raddr >> PAGE_SHIFT)) { | |
414 | /* The guest's PTE is not mapped yet. Map on the host */ | |
415 | kvmppc_mmu_map_page(vcpu, &pte); | |
416 | if (data) | |
417 | vcpu->stat.sp_storage++; | |
418 | else if (vcpu->arch.mmu.is_dcbz32(vcpu) && | |
419 | (!(vcpu->arch.hflags & BOOK3S_HFLAG_DCBZ32))) | |
420 | kvmppc_patch_dcbz(vcpu, &pte); | |
421 | } else { | |
422 | /* MMIO */ | |
423 | vcpu->stat.mmio_exits++; | |
424 | vcpu->arch.paddr_accessed = pte.raddr; | |
6020c0f6 | 425 | vcpu->arch.vaddr_accessed = pte.eaddr; |
f05ed4d5 PM |
426 | r = kvmppc_emulate_mmio(run, vcpu); |
427 | if ( r == RESUME_HOST_NV ) | |
428 | r = RESUME_HOST; | |
429 | } | |
430 | ||
431 | return r; | |
432 | } | |
433 | ||
434 | static inline int get_fpr_index(int i) | |
435 | { | |
28c483b6 | 436 | return i * TS_FPRWIDTH; |
f05ed4d5 PM |
437 | } |
438 | ||
439 | /* Give up external provider (FPU, Altivec, VSX) */ | |
440 | void kvmppc_giveup_ext(struct kvm_vcpu *vcpu, ulong msr) | |
441 | { | |
442 | struct thread_struct *t = ¤t->thread; | |
443 | u64 *vcpu_fpr = vcpu->arch.fpr; | |
444 | #ifdef CONFIG_VSX | |
445 | u64 *vcpu_vsx = vcpu->arch.vsr; | |
446 | #endif | |
447 | u64 *thread_fpr = (u64*)t->fpr; | |
448 | int i; | |
449 | ||
28c483b6 PM |
450 | /* |
451 | * VSX instructions can access FP and vector registers, so if | |
452 | * we are giving up VSX, make sure we give up FP and VMX as well. | |
453 | */ | |
454 | if (msr & MSR_VSX) | |
455 | msr |= MSR_FP | MSR_VEC; | |
456 | ||
457 | msr &= vcpu->arch.guest_owned_ext; | |
458 | if (!msr) | |
f05ed4d5 PM |
459 | return; |
460 | ||
461 | #ifdef DEBUG_EXT | |
462 | printk(KERN_INFO "Giving up ext 0x%lx\n", msr); | |
463 | #endif | |
464 | ||
28c483b6 PM |
465 | if (msr & MSR_FP) { |
466 | /* | |
467 | * Note that on CPUs with VSX, giveup_fpu stores | |
468 | * both the traditional FP registers and the added VSX | |
469 | * registers into thread.fpr[]. | |
470 | */ | |
f05ed4d5 PM |
471 | giveup_fpu(current); |
472 | for (i = 0; i < ARRAY_SIZE(vcpu->arch.fpr); i++) | |
473 | vcpu_fpr[i] = thread_fpr[get_fpr_index(i)]; | |
474 | ||
475 | vcpu->arch.fpscr = t->fpscr.val; | |
28c483b6 PM |
476 | |
477 | #ifdef CONFIG_VSX | |
478 | if (cpu_has_feature(CPU_FTR_VSX)) | |
479 | for (i = 0; i < ARRAY_SIZE(vcpu->arch.vsr) / 2; i++) | |
480 | vcpu_vsx[i] = thread_fpr[get_fpr_index(i) + 1]; | |
481 | #endif | |
482 | } | |
483 | ||
f05ed4d5 | 484 | #ifdef CONFIG_ALTIVEC |
28c483b6 | 485 | if (msr & MSR_VEC) { |
f05ed4d5 PM |
486 | giveup_altivec(current); |
487 | memcpy(vcpu->arch.vr, t->vr, sizeof(vcpu->arch.vr)); | |
488 | vcpu->arch.vscr = t->vscr; | |
f05ed4d5 | 489 | } |
28c483b6 | 490 | #endif |
f05ed4d5 | 491 | |
28c483b6 | 492 | vcpu->arch.guest_owned_ext &= ~(msr | MSR_VSX); |
f05ed4d5 PM |
493 | kvmppc_recalc_shadow_msr(vcpu); |
494 | } | |
495 | ||
496 | static int kvmppc_read_inst(struct kvm_vcpu *vcpu) | |
497 | { | |
498 | ulong srr0 = kvmppc_get_pc(vcpu); | |
499 | u32 last_inst = kvmppc_get_last_inst(vcpu); | |
500 | int ret; | |
501 | ||
502 | ret = kvmppc_ld(vcpu, &srr0, sizeof(u32), &last_inst, false); | |
503 | if (ret == -ENOENT) { | |
504 | ulong msr = vcpu->arch.shared->msr; | |
505 | ||
506 | msr = kvmppc_set_field(msr, 33, 33, 1); | |
507 | msr = kvmppc_set_field(msr, 34, 36, 0); | |
508 | vcpu->arch.shared->msr = kvmppc_set_field(msr, 42, 47, 0); | |
509 | kvmppc_book3s_queue_irqprio(vcpu, BOOK3S_INTERRUPT_INST_STORAGE); | |
510 | return EMULATE_AGAIN; | |
511 | } | |
512 | ||
513 | return EMULATE_DONE; | |
514 | } | |
515 | ||
516 | static int kvmppc_check_ext(struct kvm_vcpu *vcpu, unsigned int exit_nr) | |
517 | { | |
518 | ||
519 | /* Need to do paired single emulation? */ | |
520 | if (!(vcpu->arch.hflags & BOOK3S_HFLAG_PAIRED_SINGLE)) | |
521 | return EMULATE_DONE; | |
522 | ||
523 | /* Read out the instruction */ | |
524 | if (kvmppc_read_inst(vcpu) == EMULATE_DONE) | |
525 | /* Need to emulate */ | |
526 | return EMULATE_FAIL; | |
527 | ||
528 | return EMULATE_AGAIN; | |
529 | } | |
530 | ||
531 | /* Handle external providers (FPU, Altivec, VSX) */ | |
532 | static int kvmppc_handle_ext(struct kvm_vcpu *vcpu, unsigned int exit_nr, | |
533 | ulong msr) | |
534 | { | |
535 | struct thread_struct *t = ¤t->thread; | |
536 | u64 *vcpu_fpr = vcpu->arch.fpr; | |
537 | #ifdef CONFIG_VSX | |
538 | u64 *vcpu_vsx = vcpu->arch.vsr; | |
539 | #endif | |
540 | u64 *thread_fpr = (u64*)t->fpr; | |
541 | int i; | |
542 | ||
543 | /* When we have paired singles, we emulate in software */ | |
544 | if (vcpu->arch.hflags & BOOK3S_HFLAG_PAIRED_SINGLE) | |
545 | return RESUME_GUEST; | |
546 | ||
547 | if (!(vcpu->arch.shared->msr & msr)) { | |
548 | kvmppc_book3s_queue_irqprio(vcpu, exit_nr); | |
549 | return RESUME_GUEST; | |
550 | } | |
551 | ||
28c483b6 PM |
552 | if (msr == MSR_VSX) { |
553 | /* No VSX? Give an illegal instruction interrupt */ | |
554 | #ifdef CONFIG_VSX | |
555 | if (!cpu_has_feature(CPU_FTR_VSX)) | |
556 | #endif | |
557 | { | |
558 | kvmppc_core_queue_program(vcpu, SRR1_PROGILL); | |
559 | return RESUME_GUEST; | |
560 | } | |
561 | ||
562 | /* | |
563 | * We have to load up all the FP and VMX registers before | |
564 | * we can let the guest use VSX instructions. | |
565 | */ | |
566 | msr = MSR_FP | MSR_VEC | MSR_VSX; | |
f05ed4d5 PM |
567 | } |
568 | ||
28c483b6 PM |
569 | /* See if we already own all the ext(s) needed */ |
570 | msr &= ~vcpu->arch.guest_owned_ext; | |
571 | if (!msr) | |
572 | return RESUME_GUEST; | |
573 | ||
f05ed4d5 PM |
574 | #ifdef DEBUG_EXT |
575 | printk(KERN_INFO "Loading up ext 0x%lx\n", msr); | |
576 | #endif | |
577 | ||
578 | current->thread.regs->msr |= msr; | |
579 | ||
28c483b6 | 580 | if (msr & MSR_FP) { |
f05ed4d5 PM |
581 | for (i = 0; i < ARRAY_SIZE(vcpu->arch.fpr); i++) |
582 | thread_fpr[get_fpr_index(i)] = vcpu_fpr[i]; | |
28c483b6 PM |
583 | #ifdef CONFIG_VSX |
584 | for (i = 0; i < ARRAY_SIZE(vcpu->arch.vsr) / 2; i++) | |
585 | thread_fpr[get_fpr_index(i) + 1] = vcpu_vsx[i]; | |
586 | #endif | |
f05ed4d5 PM |
587 | t->fpscr.val = vcpu->arch.fpscr; |
588 | t->fpexc_mode = 0; | |
589 | kvmppc_load_up_fpu(); | |
28c483b6 PM |
590 | } |
591 | ||
592 | if (msr & MSR_VEC) { | |
f05ed4d5 PM |
593 | #ifdef CONFIG_ALTIVEC |
594 | memcpy(t->vr, vcpu->arch.vr, sizeof(vcpu->arch.vr)); | |
595 | t->vscr = vcpu->arch.vscr; | |
596 | t->vrsave = -1; | |
597 | kvmppc_load_up_altivec(); | |
598 | #endif | |
f05ed4d5 PM |
599 | } |
600 | ||
601 | vcpu->arch.guest_owned_ext |= msr; | |
f05ed4d5 PM |
602 | kvmppc_recalc_shadow_msr(vcpu); |
603 | ||
604 | return RESUME_GUEST; | |
605 | } | |
606 | ||
607 | int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu, | |
608 | unsigned int exit_nr) | |
609 | { | |
610 | int r = RESUME_HOST; | |
7ee78855 | 611 | int s; |
f05ed4d5 PM |
612 | |
613 | vcpu->stat.sum_exits++; | |
614 | ||
615 | run->exit_reason = KVM_EXIT_UNKNOWN; | |
616 | run->ready_for_interrupt_injection = 1; | |
617 | ||
bd2be683 | 618 | /* We get here with MSR.EE=1 */ |
3b1d9d7d | 619 | |
97c95059 | 620 | trace_kvm_exit(exit_nr, vcpu); |
706fb730 | 621 | kvm_guest_exit(); |
c63ddcb4 | 622 | |
f05ed4d5 PM |
623 | switch (exit_nr) { |
624 | case BOOK3S_INTERRUPT_INST_STORAGE: | |
468a12c2 AG |
625 | { |
626 | struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu); | |
627 | ulong shadow_srr1 = svcpu->shadow_srr1; | |
f05ed4d5 PM |
628 | vcpu->stat.pf_instruc++; |
629 | ||
630 | #ifdef CONFIG_PPC_BOOK3S_32 | |
631 | /* We set segments as unused segments when invalidating them. So | |
632 | * treat the respective fault as segment fault. */ | |
468a12c2 | 633 | if (svcpu->sr[kvmppc_get_pc(vcpu) >> SID_SHIFT] == SR_INVALID) { |
f05ed4d5 PM |
634 | kvmppc_mmu_map_segment(vcpu, kvmppc_get_pc(vcpu)); |
635 | r = RESUME_GUEST; | |
468a12c2 | 636 | svcpu_put(svcpu); |
f05ed4d5 PM |
637 | break; |
638 | } | |
639 | #endif | |
468a12c2 | 640 | svcpu_put(svcpu); |
f05ed4d5 PM |
641 | |
642 | /* only care about PTEG not found errors, but leave NX alone */ | |
468a12c2 | 643 | if (shadow_srr1 & 0x40000000) { |
f05ed4d5 PM |
644 | r = kvmppc_handle_pagefault(run, vcpu, kvmppc_get_pc(vcpu), exit_nr); |
645 | vcpu->stat.sp_instruc++; | |
646 | } else if (vcpu->arch.mmu.is_dcbz32(vcpu) && | |
647 | (!(vcpu->arch.hflags & BOOK3S_HFLAG_DCBZ32))) { | |
648 | /* | |
649 | * XXX If we do the dcbz hack we use the NX bit to flush&patch the page, | |
650 | * so we can't use the NX bit inside the guest. Let's cross our fingers, | |
651 | * that no guest that needs the dcbz hack does NX. | |
652 | */ | |
653 | kvmppc_mmu_pte_flush(vcpu, kvmppc_get_pc(vcpu), ~0xFFFUL); | |
654 | r = RESUME_GUEST; | |
655 | } else { | |
468a12c2 | 656 | vcpu->arch.shared->msr |= shadow_srr1 & 0x58000000; |
f05ed4d5 PM |
657 | kvmppc_book3s_queue_irqprio(vcpu, exit_nr); |
658 | r = RESUME_GUEST; | |
659 | } | |
660 | break; | |
468a12c2 | 661 | } |
f05ed4d5 PM |
662 | case BOOK3S_INTERRUPT_DATA_STORAGE: |
663 | { | |
664 | ulong dar = kvmppc_get_fault_dar(vcpu); | |
468a12c2 AG |
665 | struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu); |
666 | u32 fault_dsisr = svcpu->fault_dsisr; | |
f05ed4d5 PM |
667 | vcpu->stat.pf_storage++; |
668 | ||
669 | #ifdef CONFIG_PPC_BOOK3S_32 | |
670 | /* We set segments as unused segments when invalidating them. So | |
671 | * treat the respective fault as segment fault. */ | |
468a12c2 | 672 | if ((svcpu->sr[dar >> SID_SHIFT]) == SR_INVALID) { |
f05ed4d5 PM |
673 | kvmppc_mmu_map_segment(vcpu, dar); |
674 | r = RESUME_GUEST; | |
468a12c2 | 675 | svcpu_put(svcpu); |
f05ed4d5 PM |
676 | break; |
677 | } | |
678 | #endif | |
468a12c2 | 679 | svcpu_put(svcpu); |
f05ed4d5 PM |
680 | |
681 | /* The only case we need to handle is missing shadow PTEs */ | |
468a12c2 | 682 | if (fault_dsisr & DSISR_NOHPTE) { |
f05ed4d5 PM |
683 | r = kvmppc_handle_pagefault(run, vcpu, dar, exit_nr); |
684 | } else { | |
685 | vcpu->arch.shared->dar = dar; | |
468a12c2 | 686 | vcpu->arch.shared->dsisr = fault_dsisr; |
f05ed4d5 PM |
687 | kvmppc_book3s_queue_irqprio(vcpu, exit_nr); |
688 | r = RESUME_GUEST; | |
689 | } | |
690 | break; | |
691 | } | |
692 | case BOOK3S_INTERRUPT_DATA_SEGMENT: | |
693 | if (kvmppc_mmu_map_segment(vcpu, kvmppc_get_fault_dar(vcpu)) < 0) { | |
694 | vcpu->arch.shared->dar = kvmppc_get_fault_dar(vcpu); | |
695 | kvmppc_book3s_queue_irqprio(vcpu, | |
696 | BOOK3S_INTERRUPT_DATA_SEGMENT); | |
697 | } | |
698 | r = RESUME_GUEST; | |
699 | break; | |
700 | case BOOK3S_INTERRUPT_INST_SEGMENT: | |
701 | if (kvmppc_mmu_map_segment(vcpu, kvmppc_get_pc(vcpu)) < 0) { | |
702 | kvmppc_book3s_queue_irqprio(vcpu, | |
703 | BOOK3S_INTERRUPT_INST_SEGMENT); | |
704 | } | |
705 | r = RESUME_GUEST; | |
706 | break; | |
707 | /* We're good on these - the host merely wanted to get our attention */ | |
708 | case BOOK3S_INTERRUPT_DECREMENTER: | |
4f225ae0 | 709 | case BOOK3S_INTERRUPT_HV_DECREMENTER: |
f05ed4d5 PM |
710 | vcpu->stat.dec_exits++; |
711 | r = RESUME_GUEST; | |
712 | break; | |
713 | case BOOK3S_INTERRUPT_EXTERNAL: | |
4f225ae0 AG |
714 | case BOOK3S_INTERRUPT_EXTERNAL_LEVEL: |
715 | case BOOK3S_INTERRUPT_EXTERNAL_HV: | |
f05ed4d5 PM |
716 | vcpu->stat.ext_intr_exits++; |
717 | r = RESUME_GUEST; | |
718 | break; | |
719 | case BOOK3S_INTERRUPT_PERFMON: | |
720 | r = RESUME_GUEST; | |
721 | break; | |
722 | case BOOK3S_INTERRUPT_PROGRAM: | |
4f225ae0 | 723 | case BOOK3S_INTERRUPT_H_EMUL_ASSIST: |
f05ed4d5 PM |
724 | { |
725 | enum emulation_result er; | |
468a12c2 | 726 | struct kvmppc_book3s_shadow_vcpu *svcpu; |
f05ed4d5 PM |
727 | ulong flags; |
728 | ||
729 | program_interrupt: | |
468a12c2 AG |
730 | svcpu = svcpu_get(vcpu); |
731 | flags = svcpu->shadow_srr1 & 0x1f0000ull; | |
732 | svcpu_put(svcpu); | |
f05ed4d5 PM |
733 | |
734 | if (vcpu->arch.shared->msr & MSR_PR) { | |
735 | #ifdef EXIT_DEBUG | |
736 | printk(KERN_INFO "Userspace triggered 0x700 exception at 0x%lx (0x%x)\n", kvmppc_get_pc(vcpu), kvmppc_get_last_inst(vcpu)); | |
737 | #endif | |
738 | if ((kvmppc_get_last_inst(vcpu) & 0xff0007ff) != | |
739 | (INS_DCBZ & 0xfffffff7)) { | |
740 | kvmppc_core_queue_program(vcpu, flags); | |
741 | r = RESUME_GUEST; | |
742 | break; | |
743 | } | |
744 | } | |
745 | ||
746 | vcpu->stat.emulated_inst_exits++; | |
747 | er = kvmppc_emulate_instruction(run, vcpu); | |
748 | switch (er) { | |
749 | case EMULATE_DONE: | |
750 | r = RESUME_GUEST_NV; | |
751 | break; | |
752 | case EMULATE_AGAIN: | |
753 | r = RESUME_GUEST; | |
754 | break; | |
755 | case EMULATE_FAIL: | |
756 | printk(KERN_CRIT "%s: emulation at %lx failed (%08x)\n", | |
757 | __func__, kvmppc_get_pc(vcpu), kvmppc_get_last_inst(vcpu)); | |
758 | kvmppc_core_queue_program(vcpu, flags); | |
759 | r = RESUME_GUEST; | |
760 | break; | |
761 | case EMULATE_DO_MMIO: | |
762 | run->exit_reason = KVM_EXIT_MMIO; | |
763 | r = RESUME_HOST_NV; | |
764 | break; | |
c402a3f4 | 765 | case EMULATE_EXIT_USER: |
50c7bb80 AG |
766 | r = RESUME_HOST_NV; |
767 | break; | |
f05ed4d5 PM |
768 | default: |
769 | BUG(); | |
770 | } | |
771 | break; | |
772 | } | |
773 | case BOOK3S_INTERRUPT_SYSCALL: | |
a668f2bd AG |
774 | if (vcpu->arch.papr_enabled && |
775 | (kvmppc_get_last_inst(vcpu) == 0x44000022) && | |
776 | !(vcpu->arch.shared->msr & MSR_PR)) { | |
777 | /* SC 1 papr hypercalls */ | |
778 | ulong cmd = kvmppc_get_gpr(vcpu, 3); | |
779 | int i; | |
780 | ||
96f38d72 | 781 | #ifdef CONFIG_KVM_BOOK3S_64_PR |
a668f2bd AG |
782 | if (kvmppc_h_pr(vcpu, cmd) == EMULATE_DONE) { |
783 | r = RESUME_GUEST; | |
784 | break; | |
785 | } | |
96f38d72 | 786 | #endif |
a668f2bd AG |
787 | |
788 | run->papr_hcall.nr = cmd; | |
789 | for (i = 0; i < 9; ++i) { | |
790 | ulong gpr = kvmppc_get_gpr(vcpu, 4 + i); | |
791 | run->papr_hcall.args[i] = gpr; | |
792 | } | |
793 | run->exit_reason = KVM_EXIT_PAPR_HCALL; | |
794 | vcpu->arch.hcall_needed = 1; | |
795 | r = RESUME_HOST; | |
796 | } else if (vcpu->arch.osi_enabled && | |
f05ed4d5 PM |
797 | (((u32)kvmppc_get_gpr(vcpu, 3)) == OSI_SC_MAGIC_R3) && |
798 | (((u32)kvmppc_get_gpr(vcpu, 4)) == OSI_SC_MAGIC_R4)) { | |
799 | /* MOL hypercalls */ | |
800 | u64 *gprs = run->osi.gprs; | |
801 | int i; | |
802 | ||
803 | run->exit_reason = KVM_EXIT_OSI; | |
804 | for (i = 0; i < 32; i++) | |
805 | gprs[i] = kvmppc_get_gpr(vcpu, i); | |
806 | vcpu->arch.osi_needed = 1; | |
807 | r = RESUME_HOST_NV; | |
808 | } else if (!(vcpu->arch.shared->msr & MSR_PR) && | |
809 | (((u32)kvmppc_get_gpr(vcpu, 0)) == KVM_SC_MAGIC_R0)) { | |
810 | /* KVM PV hypercalls */ | |
811 | kvmppc_set_gpr(vcpu, 3, kvmppc_kvm_pv(vcpu)); | |
812 | r = RESUME_GUEST; | |
813 | } else { | |
814 | /* Guest syscalls */ | |
815 | vcpu->stat.syscall_exits++; | |
816 | kvmppc_book3s_queue_irqprio(vcpu, exit_nr); | |
817 | r = RESUME_GUEST; | |
818 | } | |
819 | break; | |
820 | case BOOK3S_INTERRUPT_FP_UNAVAIL: | |
821 | case BOOK3S_INTERRUPT_ALTIVEC: | |
822 | case BOOK3S_INTERRUPT_VSX: | |
823 | { | |
824 | int ext_msr = 0; | |
825 | ||
826 | switch (exit_nr) { | |
827 | case BOOK3S_INTERRUPT_FP_UNAVAIL: ext_msr = MSR_FP; break; | |
828 | case BOOK3S_INTERRUPT_ALTIVEC: ext_msr = MSR_VEC; break; | |
829 | case BOOK3S_INTERRUPT_VSX: ext_msr = MSR_VSX; break; | |
830 | } | |
831 | ||
832 | switch (kvmppc_check_ext(vcpu, exit_nr)) { | |
833 | case EMULATE_DONE: | |
834 | /* everything ok - let's enable the ext */ | |
835 | r = kvmppc_handle_ext(vcpu, exit_nr, ext_msr); | |
836 | break; | |
837 | case EMULATE_FAIL: | |
838 | /* we need to emulate this instruction */ | |
839 | goto program_interrupt; | |
840 | break; | |
841 | default: | |
842 | /* nothing to worry about - go again */ | |
843 | break; | |
844 | } | |
845 | break; | |
846 | } | |
847 | case BOOK3S_INTERRUPT_ALIGNMENT: | |
848 | if (kvmppc_read_inst(vcpu) == EMULATE_DONE) { | |
849 | vcpu->arch.shared->dsisr = kvmppc_alignment_dsisr(vcpu, | |
850 | kvmppc_get_last_inst(vcpu)); | |
851 | vcpu->arch.shared->dar = kvmppc_alignment_dar(vcpu, | |
852 | kvmppc_get_last_inst(vcpu)); | |
853 | kvmppc_book3s_queue_irqprio(vcpu, exit_nr); | |
854 | } | |
855 | r = RESUME_GUEST; | |
856 | break; | |
857 | case BOOK3S_INTERRUPT_MACHINE_CHECK: | |
858 | case BOOK3S_INTERRUPT_TRACE: | |
859 | kvmppc_book3s_queue_irqprio(vcpu, exit_nr); | |
860 | r = RESUME_GUEST; | |
861 | break; | |
862 | default: | |
468a12c2 AG |
863 | { |
864 | struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu); | |
865 | ulong shadow_srr1 = svcpu->shadow_srr1; | |
866 | svcpu_put(svcpu); | |
f05ed4d5 PM |
867 | /* Ugh - bork here! What did we get? */ |
868 | printk(KERN_EMERG "exit_nr=0x%x | pc=0x%lx | msr=0x%lx\n", | |
468a12c2 | 869 | exit_nr, kvmppc_get_pc(vcpu), shadow_srr1); |
f05ed4d5 PM |
870 | r = RESUME_HOST; |
871 | BUG(); | |
872 | break; | |
873 | } | |
468a12c2 | 874 | } |
f05ed4d5 PM |
875 | |
876 | if (!(r & RESUME_HOST)) { | |
877 | /* To avoid clobbering exit_reason, only check for signals if | |
878 | * we aren't already exiting to userspace for some other | |
879 | * reason. */ | |
e371f713 AG |
880 | |
881 | /* | |
882 | * Interrupts could be timers for the guest which we have to | |
883 | * inject again, so let's postpone them until we're in the guest | |
884 | * and if we really did time things so badly, then we just exit | |
885 | * again due to a host external interrupt. | |
886 | */ | |
bd2be683 | 887 | local_irq_disable(); |
7ee78855 AG |
888 | s = kvmppc_prepare_to_enter(vcpu); |
889 | if (s <= 0) { | |
bd2be683 | 890 | local_irq_enable(); |
7ee78855 | 891 | r = s; |
24afa37b | 892 | } else { |
bd2be683 | 893 | kvmppc_lazy_ee_enable(); |
f05ed4d5 PM |
894 | } |
895 | } | |
896 | ||
897 | trace_kvm_book3s_reenter(r, vcpu); | |
898 | ||
899 | return r; | |
900 | } | |
901 | ||
902 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, | |
903 | struct kvm_sregs *sregs) | |
904 | { | |
905 | struct kvmppc_vcpu_book3s *vcpu3s = to_book3s(vcpu); | |
906 | int i; | |
907 | ||
908 | sregs->pvr = vcpu->arch.pvr; | |
909 | ||
910 | sregs->u.s.sdr1 = to_book3s(vcpu)->sdr1; | |
911 | if (vcpu->arch.hflags & BOOK3S_HFLAG_SLB) { | |
912 | for (i = 0; i < 64; i++) { | |
913 | sregs->u.s.ppc64.slb[i].slbe = vcpu->arch.slb[i].orige | i; | |
914 | sregs->u.s.ppc64.slb[i].slbv = vcpu->arch.slb[i].origv; | |
915 | } | |
916 | } else { | |
917 | for (i = 0; i < 16; i++) | |
918 | sregs->u.s.ppc32.sr[i] = vcpu->arch.shared->sr[i]; | |
919 | ||
920 | for (i = 0; i < 8; i++) { | |
921 | sregs->u.s.ppc32.ibat[i] = vcpu3s->ibat[i].raw; | |
922 | sregs->u.s.ppc32.dbat[i] = vcpu3s->dbat[i].raw; | |
923 | } | |
924 | } | |
925 | ||
926 | return 0; | |
927 | } | |
928 | ||
929 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, | |
930 | struct kvm_sregs *sregs) | |
931 | { | |
932 | struct kvmppc_vcpu_book3s *vcpu3s = to_book3s(vcpu); | |
933 | int i; | |
934 | ||
935 | kvmppc_set_pvr(vcpu, sregs->pvr); | |
936 | ||
937 | vcpu3s->sdr1 = sregs->u.s.sdr1; | |
938 | if (vcpu->arch.hflags & BOOK3S_HFLAG_SLB) { | |
939 | for (i = 0; i < 64; i++) { | |
940 | vcpu->arch.mmu.slbmte(vcpu, sregs->u.s.ppc64.slb[i].slbv, | |
941 | sregs->u.s.ppc64.slb[i].slbe); | |
942 | } | |
943 | } else { | |
944 | for (i = 0; i < 16; i++) { | |
945 | vcpu->arch.mmu.mtsrin(vcpu, i, sregs->u.s.ppc32.sr[i]); | |
946 | } | |
947 | for (i = 0; i < 8; i++) { | |
948 | kvmppc_set_bat(vcpu, &(vcpu3s->ibat[i]), false, | |
949 | (u32)sregs->u.s.ppc32.ibat[i]); | |
950 | kvmppc_set_bat(vcpu, &(vcpu3s->ibat[i]), true, | |
951 | (u32)(sregs->u.s.ppc32.ibat[i] >> 32)); | |
952 | kvmppc_set_bat(vcpu, &(vcpu3s->dbat[i]), false, | |
953 | (u32)sregs->u.s.ppc32.dbat[i]); | |
954 | kvmppc_set_bat(vcpu, &(vcpu3s->dbat[i]), true, | |
955 | (u32)(sregs->u.s.ppc32.dbat[i] >> 32)); | |
956 | } | |
957 | } | |
958 | ||
959 | /* Flush the MMU after messing with the segments */ | |
960 | kvmppc_mmu_pte_flush(vcpu, 0, 0); | |
961 | ||
962 | return 0; | |
963 | } | |
964 | ||
a136a8bd | 965 | int kvmppc_get_one_reg(struct kvm_vcpu *vcpu, u64 id, union kvmppc_one_reg *val) |
31f3438e | 966 | { |
a136a8bd | 967 | int r = 0; |
31f3438e | 968 | |
a136a8bd | 969 | switch (id) { |
31f3438e | 970 | case KVM_REG_PPC_HIOR: |
a136a8bd | 971 | *val = get_reg_val(id, to_book3s(vcpu)->hior); |
31f3438e | 972 | break; |
a8bd19ef PM |
973 | #ifdef CONFIG_VSX |
974 | case KVM_REG_PPC_VSR0 ... KVM_REG_PPC_VSR31: { | |
975 | long int i = id - KVM_REG_PPC_VSR0; | |
976 | ||
977 | if (!cpu_has_feature(CPU_FTR_VSX)) { | |
978 | r = -ENXIO; | |
979 | break; | |
980 | } | |
981 | val->vsxval[0] = vcpu->arch.fpr[i]; | |
982 | val->vsxval[1] = vcpu->arch.vsr[i]; | |
983 | break; | |
984 | } | |
985 | #endif /* CONFIG_VSX */ | |
31f3438e | 986 | default: |
a136a8bd | 987 | r = -EINVAL; |
31f3438e PM |
988 | break; |
989 | } | |
990 | ||
991 | return r; | |
992 | } | |
993 | ||
a136a8bd | 994 | int kvmppc_set_one_reg(struct kvm_vcpu *vcpu, u64 id, union kvmppc_one_reg *val) |
31f3438e | 995 | { |
a136a8bd | 996 | int r = 0; |
31f3438e | 997 | |
a136a8bd | 998 | switch (id) { |
31f3438e | 999 | case KVM_REG_PPC_HIOR: |
a136a8bd PM |
1000 | to_book3s(vcpu)->hior = set_reg_val(id, *val); |
1001 | to_book3s(vcpu)->hior_explicit = true; | |
31f3438e | 1002 | break; |
a8bd19ef PM |
1003 | #ifdef CONFIG_VSX |
1004 | case KVM_REG_PPC_VSR0 ... KVM_REG_PPC_VSR31: { | |
1005 | long int i = id - KVM_REG_PPC_VSR0; | |
1006 | ||
1007 | if (!cpu_has_feature(CPU_FTR_VSX)) { | |
1008 | r = -ENXIO; | |
1009 | break; | |
1010 | } | |
1011 | vcpu->arch.fpr[i] = val->vsxval[0]; | |
1012 | vcpu->arch.vsr[i] = val->vsxval[1]; | |
1013 | break; | |
1014 | } | |
1015 | #endif /* CONFIG_VSX */ | |
31f3438e | 1016 | default: |
a136a8bd | 1017 | r = -EINVAL; |
31f3438e PM |
1018 | break; |
1019 | } | |
1020 | ||
1021 | return r; | |
1022 | } | |
1023 | ||
f05ed4d5 PM |
1024 | int kvmppc_core_check_processor_compat(void) |
1025 | { | |
1026 | return 0; | |
1027 | } | |
1028 | ||
1029 | struct kvm_vcpu *kvmppc_core_vcpu_create(struct kvm *kvm, unsigned int id) | |
1030 | { | |
1031 | struct kvmppc_vcpu_book3s *vcpu_book3s; | |
1032 | struct kvm_vcpu *vcpu; | |
1033 | int err = -ENOMEM; | |
1034 | unsigned long p; | |
1035 | ||
1036 | vcpu_book3s = vzalloc(sizeof(struct kvmppc_vcpu_book3s)); | |
1037 | if (!vcpu_book3s) | |
1038 | goto out; | |
1039 | ||
1040 | vcpu_book3s->shadow_vcpu = (struct kvmppc_book3s_shadow_vcpu *) | |
1041 | kzalloc(sizeof(*vcpu_book3s->shadow_vcpu), GFP_KERNEL); | |
1042 | if (!vcpu_book3s->shadow_vcpu) | |
1043 | goto free_vcpu; | |
1044 | ||
1045 | vcpu = &vcpu_book3s->vcpu; | |
1046 | err = kvm_vcpu_init(vcpu, kvm, id); | |
1047 | if (err) | |
1048 | goto free_shadow_vcpu; | |
1049 | ||
1050 | p = __get_free_page(GFP_KERNEL|__GFP_ZERO); | |
1051 | /* the real shared page fills the last 4k of our page */ | |
1052 | vcpu->arch.shared = (void*)(p + PAGE_SIZE - 4096); | |
1053 | if (!p) | |
1054 | goto uninit_vcpu; | |
1055 | ||
f05ed4d5 PM |
1056 | #ifdef CONFIG_PPC_BOOK3S_64 |
1057 | /* default to book3s_64 (970fx) */ | |
1058 | vcpu->arch.pvr = 0x3C0301; | |
1059 | #else | |
1060 | /* default to book3s_32 (750) */ | |
1061 | vcpu->arch.pvr = 0x84202; | |
1062 | #endif | |
1063 | kvmppc_set_pvr(vcpu, vcpu->arch.pvr); | |
1064 | vcpu->arch.slb_nr = 64; | |
1065 | ||
f05ed4d5 PM |
1066 | vcpu->arch.shadow_msr = MSR_USER64; |
1067 | ||
1068 | err = kvmppc_mmu_init(vcpu); | |
1069 | if (err < 0) | |
1070 | goto uninit_vcpu; | |
1071 | ||
1072 | return vcpu; | |
1073 | ||
1074 | uninit_vcpu: | |
1075 | kvm_vcpu_uninit(vcpu); | |
1076 | free_shadow_vcpu: | |
1077 | kfree(vcpu_book3s->shadow_vcpu); | |
1078 | free_vcpu: | |
1079 | vfree(vcpu_book3s); | |
1080 | out: | |
1081 | return ERR_PTR(err); | |
1082 | } | |
1083 | ||
1084 | void kvmppc_core_vcpu_free(struct kvm_vcpu *vcpu) | |
1085 | { | |
1086 | struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu); | |
1087 | ||
1088 | free_page((unsigned long)vcpu->arch.shared & PAGE_MASK); | |
1089 | kvm_vcpu_uninit(vcpu); | |
1090 | kfree(vcpu_book3s->shadow_vcpu); | |
1091 | vfree(vcpu_book3s); | |
1092 | } | |
1093 | ||
df6909e5 | 1094 | int kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu) |
f05ed4d5 PM |
1095 | { |
1096 | int ret; | |
1097 | double fpr[32][TS_FPRWIDTH]; | |
1098 | unsigned int fpscr; | |
1099 | int fpexc_mode; | |
1100 | #ifdef CONFIG_ALTIVEC | |
1101 | vector128 vr[32]; | |
1102 | vector128 vscr; | |
1103 | unsigned long uninitialized_var(vrsave); | |
1104 | int used_vr; | |
1105 | #endif | |
1106 | #ifdef CONFIG_VSX | |
1107 | int used_vsr; | |
1108 | #endif | |
1109 | ulong ext_msr; | |
1110 | ||
af8f38b3 AG |
1111 | /* Check if we can run the vcpu at all */ |
1112 | if (!vcpu->arch.sane) { | |
1113 | kvm_run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
7d82714d AG |
1114 | ret = -EINVAL; |
1115 | goto out; | |
af8f38b3 AG |
1116 | } |
1117 | ||
e371f713 AG |
1118 | /* |
1119 | * Interrupts could be timers for the guest which we have to inject | |
1120 | * again, so let's postpone them until we're in the guest and if we | |
1121 | * really did time things so badly, then we just exit again due to | |
1122 | * a host external interrupt. | |
1123 | */ | |
bd2be683 | 1124 | local_irq_disable(); |
7ee78855 AG |
1125 | ret = kvmppc_prepare_to_enter(vcpu); |
1126 | if (ret <= 0) { | |
bd2be683 | 1127 | local_irq_enable(); |
7d82714d | 1128 | goto out; |
f05ed4d5 PM |
1129 | } |
1130 | ||
1131 | /* Save FPU state in stack */ | |
1132 | if (current->thread.regs->msr & MSR_FP) | |
1133 | giveup_fpu(current); | |
1134 | memcpy(fpr, current->thread.fpr, sizeof(current->thread.fpr)); | |
1135 | fpscr = current->thread.fpscr.val; | |
1136 | fpexc_mode = current->thread.fpexc_mode; | |
1137 | ||
1138 | #ifdef CONFIG_ALTIVEC | |
1139 | /* Save Altivec state in stack */ | |
1140 | used_vr = current->thread.used_vr; | |
1141 | if (used_vr) { | |
1142 | if (current->thread.regs->msr & MSR_VEC) | |
1143 | giveup_altivec(current); | |
1144 | memcpy(vr, current->thread.vr, sizeof(current->thread.vr)); | |
1145 | vscr = current->thread.vscr; | |
1146 | vrsave = current->thread.vrsave; | |
1147 | } | |
1148 | #endif | |
1149 | ||
1150 | #ifdef CONFIG_VSX | |
1151 | /* Save VSX state in stack */ | |
1152 | used_vsr = current->thread.used_vsr; | |
1153 | if (used_vsr && (current->thread.regs->msr & MSR_VSX)) | |
28c483b6 | 1154 | __giveup_vsx(current); |
f05ed4d5 PM |
1155 | #endif |
1156 | ||
1157 | /* Remember the MSR with disabled extensions */ | |
1158 | ext_msr = current->thread.regs->msr; | |
1159 | ||
f05ed4d5 PM |
1160 | /* Preload FPU if it's enabled */ |
1161 | if (vcpu->arch.shared->msr & MSR_FP) | |
1162 | kvmppc_handle_ext(vcpu, BOOK3S_INTERRUPT_FP_UNAVAIL, MSR_FP); | |
1163 | ||
bd2be683 | 1164 | kvmppc_lazy_ee_enable(); |
df6909e5 PM |
1165 | |
1166 | ret = __kvmppc_vcpu_run(kvm_run, vcpu); | |
1167 | ||
24afa37b AG |
1168 | /* No need for kvm_guest_exit. It's done in handle_exit. |
1169 | We also get here with interrupts enabled. */ | |
f05ed4d5 | 1170 | |
f05ed4d5 | 1171 | /* Make sure we save the guest FPU/Altivec/VSX state */ |
28c483b6 PM |
1172 | kvmppc_giveup_ext(vcpu, MSR_FP | MSR_VEC | MSR_VSX); |
1173 | ||
1174 | current->thread.regs->msr = ext_msr; | |
f05ed4d5 | 1175 | |
28c483b6 | 1176 | /* Restore FPU/VSX state from stack */ |
f05ed4d5 PM |
1177 | memcpy(current->thread.fpr, fpr, sizeof(current->thread.fpr)); |
1178 | current->thread.fpscr.val = fpscr; | |
1179 | current->thread.fpexc_mode = fpexc_mode; | |
1180 | ||
1181 | #ifdef CONFIG_ALTIVEC | |
1182 | /* Restore Altivec state from stack */ | |
1183 | if (used_vr && current->thread.used_vr) { | |
1184 | memcpy(current->thread.vr, vr, sizeof(current->thread.vr)); | |
1185 | current->thread.vscr = vscr; | |
1186 | current->thread.vrsave = vrsave; | |
1187 | } | |
1188 | current->thread.used_vr = used_vr; | |
1189 | #endif | |
1190 | ||
1191 | #ifdef CONFIG_VSX | |
1192 | current->thread.used_vsr = used_vsr; | |
1193 | #endif | |
1194 | ||
7d82714d | 1195 | out: |
0652eaae | 1196 | vcpu->mode = OUTSIDE_GUEST_MODE; |
f05ed4d5 PM |
1197 | return ret; |
1198 | } | |
1199 | ||
82ed3616 PM |
1200 | /* |
1201 | * Get (and clear) the dirty memory log for a memory slot. | |
1202 | */ | |
1203 | int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, | |
1204 | struct kvm_dirty_log *log) | |
1205 | { | |
1206 | struct kvm_memory_slot *memslot; | |
1207 | struct kvm_vcpu *vcpu; | |
1208 | ulong ga, ga_end; | |
1209 | int is_dirty = 0; | |
1210 | int r; | |
1211 | unsigned long n; | |
1212 | ||
1213 | mutex_lock(&kvm->slots_lock); | |
1214 | ||
1215 | r = kvm_get_dirty_log(kvm, log, &is_dirty); | |
1216 | if (r) | |
1217 | goto out; | |
1218 | ||
1219 | /* If nothing is dirty, don't bother messing with page tables. */ | |
1220 | if (is_dirty) { | |
1221 | memslot = id_to_memslot(kvm->memslots, log->slot); | |
1222 | ||
1223 | ga = memslot->base_gfn << PAGE_SHIFT; | |
1224 | ga_end = ga + (memslot->npages << PAGE_SHIFT); | |
1225 | ||
1226 | kvm_for_each_vcpu(n, vcpu, kvm) | |
1227 | kvmppc_mmu_pte_pflush(vcpu, ga, ga_end); | |
1228 | ||
1229 | n = kvm_dirty_bitmap_bytes(memslot); | |
1230 | memset(memslot->dirty_bitmap, 0, n); | |
1231 | } | |
1232 | ||
1233 | r = 0; | |
1234 | out: | |
1235 | mutex_unlock(&kvm->slots_lock); | |
1236 | return r; | |
1237 | } | |
1238 | ||
5b74716e BH |
1239 | #ifdef CONFIG_PPC64 |
1240 | int kvm_vm_ioctl_get_smmu_info(struct kvm *kvm, struct kvm_ppc_smmu_info *info) | |
1241 | { | |
1242 | /* No flags */ | |
1243 | info->flags = 0; | |
1244 | ||
1245 | /* SLB is always 64 entries */ | |
1246 | info->slb_size = 64; | |
1247 | ||
1248 | /* Standard 4k base page size segment */ | |
1249 | info->sps[0].page_shift = 12; | |
1250 | info->sps[0].slb_enc = 0; | |
1251 | info->sps[0].enc[0].page_shift = 12; | |
1252 | info->sps[0].enc[0].pte_enc = 0; | |
1253 | ||
1254 | /* Standard 16M large page size segment */ | |
1255 | info->sps[1].page_shift = 24; | |
1256 | info->sps[1].slb_enc = SLB_VSID_L; | |
1257 | info->sps[1].enc[0].page_shift = 24; | |
1258 | info->sps[1].enc[0].pte_enc = 0; | |
1259 | ||
1260 | return 0; | |
1261 | } | |
1262 | #endif /* CONFIG_PPC64 */ | |
1263 | ||
a66b48c3 PM |
1264 | void kvmppc_core_free_memslot(struct kvm_memory_slot *free, |
1265 | struct kvm_memory_slot *dont) | |
1266 | { | |
1267 | } | |
1268 | ||
1269 | int kvmppc_core_create_memslot(struct kvm_memory_slot *slot, | |
1270 | unsigned long npages) | |
1271 | { | |
1272 | return 0; | |
1273 | } | |
1274 | ||
f9e0554d | 1275 | int kvmppc_core_prepare_memory_region(struct kvm *kvm, |
a66b48c3 | 1276 | struct kvm_memory_slot *memslot, |
f9e0554d PM |
1277 | struct kvm_userspace_memory_region *mem) |
1278 | { | |
1279 | return 0; | |
1280 | } | |
1281 | ||
1282 | void kvmppc_core_commit_memory_region(struct kvm *kvm, | |
dfe49dbd | 1283 | struct kvm_userspace_memory_region *mem, |
8482644a | 1284 | const struct kvm_memory_slot *old) |
dfe49dbd PM |
1285 | { |
1286 | } | |
1287 | ||
1288 | void kvmppc_core_flush_memslot(struct kvm *kvm, struct kvm_memory_slot *memslot) | |
f9e0554d PM |
1289 | { |
1290 | } | |
1291 | ||
a413f474 IM |
1292 | static unsigned int kvm_global_user_count = 0; |
1293 | static DEFINE_SPINLOCK(kvm_global_user_count_lock); | |
1294 | ||
f9e0554d PM |
1295 | int kvmppc_core_init_vm(struct kvm *kvm) |
1296 | { | |
f31e65e1 BH |
1297 | #ifdef CONFIG_PPC64 |
1298 | INIT_LIST_HEAD(&kvm->arch.spapr_tce_tables); | |
1299 | #endif | |
1300 | ||
a413f474 IM |
1301 | if (firmware_has_feature(FW_FEATURE_SET_MODE)) { |
1302 | spin_lock(&kvm_global_user_count_lock); | |
1303 | if (++kvm_global_user_count == 1) | |
1304 | pSeries_disable_reloc_on_exc(); | |
1305 | spin_unlock(&kvm_global_user_count_lock); | |
1306 | } | |
f9e0554d PM |
1307 | return 0; |
1308 | } | |
1309 | ||
1310 | void kvmppc_core_destroy_vm(struct kvm *kvm) | |
1311 | { | |
f31e65e1 BH |
1312 | #ifdef CONFIG_PPC64 |
1313 | WARN_ON(!list_empty(&kvm->arch.spapr_tce_tables)); | |
1314 | #endif | |
a413f474 IM |
1315 | |
1316 | if (firmware_has_feature(FW_FEATURE_SET_MODE)) { | |
1317 | spin_lock(&kvm_global_user_count_lock); | |
1318 | BUG_ON(kvm_global_user_count == 0); | |
1319 | if (--kvm_global_user_count == 0) | |
1320 | pSeries_enable_reloc_on_exc(); | |
1321 | spin_unlock(&kvm_global_user_count_lock); | |
1322 | } | |
f9e0554d PM |
1323 | } |
1324 | ||
f05ed4d5 PM |
1325 | static int kvmppc_book3s_init(void) |
1326 | { | |
1327 | int r; | |
1328 | ||
1329 | r = kvm_init(NULL, sizeof(struct kvmppc_vcpu_book3s), 0, | |
1330 | THIS_MODULE); | |
1331 | ||
1332 | if (r) | |
1333 | return r; | |
1334 | ||
1335 | r = kvmppc_mmu_hpte_sysinit(); | |
1336 | ||
1337 | return r; | |
1338 | } | |
1339 | ||
1340 | static void kvmppc_book3s_exit(void) | |
1341 | { | |
1342 | kvmppc_mmu_hpte_sysexit(); | |
1343 | kvm_exit(); | |
1344 | } | |
1345 | ||
1346 | module_init(kvmppc_book3s_init); | |
1347 | module_exit(kvmppc_book3s_exit); |