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KVM: PPC: BookE: Implement EPR exit
[mirror_ubuntu-bionic-kernel.git] / arch / powerpc / kvm / booke.c
CommitLineData
bbf45ba5
HB		 1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
14 *
15 * Copyright IBM Corp. 2007
4cd35f67 16 * Copyright 2010-2011 Freescale Semiconductor, Inc.
bbf45ba5
HB		 17 *
18 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
19 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
d30f6e48
SW		 20 * Scott Wood <scottwood@freescale.com>
21 * Varun Sethi <varun.sethi@freescale.com>
bbf45ba5
HB		 22 */
23
24#include <linux/errno.h>
25#include <linux/err.h>
26#include <linux/kvm_host.h>
5a0e3ad6 27#include <linux/gfp.h>
bbf45ba5
HB		 28#include <linux/module.h>
29#include <linux/vmalloc.h>
30#include <linux/fs.h>
7924bd41 31
bbf45ba5
HB		 32#include <asm/cputable.h>
33#include <asm/uaccess.h>
34#include <asm/kvm_ppc.h>
d9fbd03d 35#include <asm/cacheflush.h>
d30f6e48
SW		 36#include <asm/dbell.h>
37#include <asm/hw_irq.h>
38#include <asm/irq.h>
b50df19c 39#include <asm/time.h>
bbf45ba5 40
d30f6e48 41#include "timing.h"
75f74f0d 42#include "booke.h"
97c95059 43#include "trace.h"
bbf45ba5 44
d9fbd03d
HB		 45unsigned long kvmppc_booke_handlers;
46
bbf45ba5
HB		 47#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
48#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
49
50struct kvm_stats_debugfs_item debugfs_entries[] = {
bbf45ba5
HB		 51 { "mmio", VCPU_STAT(mmio_exits) },
52 { "dcr", VCPU_STAT(dcr_exits) },
53 { "sig", VCPU_STAT(signal_exits) },
bbf45ba5
HB		 54 { "itlb_r", VCPU_STAT(itlb_real_miss_exits) },
55 { "itlb_v", VCPU_STAT(itlb_virt_miss_exits) },
56 { "dtlb_r", VCPU_STAT(dtlb_real_miss_exits) },
57 { "dtlb_v", VCPU_STAT(dtlb_virt_miss_exits) },
58 { "sysc", VCPU_STAT(syscall_exits) },
59 { "isi", VCPU_STAT(isi_exits) },
60 { "dsi", VCPU_STAT(dsi_exits) },
61 { "inst_emu", VCPU_STAT(emulated_inst_exits) },
62 { "dec", VCPU_STAT(dec_exits) },
63 { "ext_intr", VCPU_STAT(ext_intr_exits) },
45c5eb67 64 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
d30f6e48
SW		 65 { "doorbell", VCPU_STAT(dbell_exits) },
66 { "guest doorbell", VCPU_STAT(gdbell_exits) },
cf1c5ca4 67 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
bbf45ba5
HB		 68 { NULL }
69};
70
bbf45ba5
HB		 71/* TODO: use vcpu_printf() */
72void kvmppc_dump_vcpu(struct kvm_vcpu *vcpu)
73{
74 int i;
75
666e7252 76 printk("pc: %08lx msr: %08llx\n", vcpu->arch.pc, vcpu->arch.shared->msr);
5cf8ca22 77 printk("lr: %08lx ctr: %08lx\n", vcpu->arch.lr, vcpu->arch.ctr);
de7906c3
AG		 78 printk("srr0: %08llx srr1: %08llx\n", vcpu->arch.shared->srr0,
79 vcpu->arch.shared->srr1);
bbf45ba5
HB		 80
81 printk("exceptions: %08lx\n", vcpu->arch.pending_exceptions);
82
83 for (i = 0; i < 32; i += 4) {
5cf8ca22 84 printk("gpr%02d: %08lx %08lx %08lx %08lx\n", i,
8e5b26b5
AG		 85 kvmppc_get_gpr(vcpu, i),
86 kvmppc_get_gpr(vcpu, i+1),
87 kvmppc_get_gpr(vcpu, i+2),
88 kvmppc_get_gpr(vcpu, i+3));
bbf45ba5
HB		 89 }
90}
91
4cd35f67
SW		 92#ifdef CONFIG_SPE
93void kvmppc_vcpu_disable_spe(struct kvm_vcpu *vcpu)
94{
95 preempt_disable();
96 enable_kernel_spe();
97 kvmppc_save_guest_spe(vcpu);
98 vcpu->arch.shadow_msr &= ~MSR_SPE;
99 preempt_enable();
100}
101
102static void kvmppc_vcpu_enable_spe(struct kvm_vcpu *vcpu)
103{
104 preempt_disable();
105 enable_kernel_spe();
106 kvmppc_load_guest_spe(vcpu);
107 vcpu->arch.shadow_msr |= MSR_SPE;
108 preempt_enable();
109}
110
111static void kvmppc_vcpu_sync_spe(struct kvm_vcpu *vcpu)
112{
113 if (vcpu->arch.shared->msr & MSR_SPE) {
114 if (!(vcpu->arch.shadow_msr & MSR_SPE))
115 kvmppc_vcpu_enable_spe(vcpu);
116 } else if (vcpu->arch.shadow_msr & MSR_SPE) {
117 kvmppc_vcpu_disable_spe(vcpu);
118 }
119}
120#else
121static void kvmppc_vcpu_sync_spe(struct kvm_vcpu *vcpu)
122{
123}
124#endif
125
7a08c274
AG		 126static void kvmppc_vcpu_sync_fpu(struct kvm_vcpu *vcpu)
127{
128#if defined(CONFIG_PPC_FPU) && !defined(CONFIG_KVM_BOOKE_HV)
129 /* We always treat the FP bit as enabled from the host
130 perspective, so only need to adjust the shadow MSR */
131 vcpu->arch.shadow_msr &= ~MSR_FP;
132 vcpu->arch.shadow_msr |= vcpu->arch.shared->msr & MSR_FP;
133#endif
134}
135
dd9ebf1f
LY		 136/*
137 * Helper function for "full" MSR writes. No need to call this if only
138 * EE/CE/ME/DE/RI are changing.
139 */
4cd35f67
SW		 140void kvmppc_set_msr(struct kvm_vcpu *vcpu, u32 new_msr)
141{
dd9ebf1f 142 u32 old_msr = vcpu->arch.shared->msr;
4cd35f67 143
d30f6e48
SW		 144#ifdef CONFIG_KVM_BOOKE_HV
145 new_msr |= MSR_GS;
146#endif
147
4cd35f67
SW		 148 vcpu->arch.shared->msr = new_msr;
149
dd9ebf1f 150 kvmppc_mmu_msr_notify(vcpu, old_msr);
4cd35f67 151 kvmppc_vcpu_sync_spe(vcpu);
7a08c274 152 kvmppc_vcpu_sync_fpu(vcpu);
4cd35f67
SW		 153}
154
d4cf3892
HB		 155static void kvmppc_booke_queue_irqprio(struct kvm_vcpu *vcpu,
156 unsigned int priority)
9dd921cf 157{
6346046c 158 trace_kvm_booke_queue_irqprio(vcpu, priority);
9dd921cf
HB		 159 set_bit(priority, &vcpu->arch.pending_exceptions);
160}
161
daf5e271
LY		 162static void kvmppc_core_queue_dtlb_miss(struct kvm_vcpu *vcpu,
163 ulong dear_flags, ulong esr_flags)
9dd921cf 164{
daf5e271
LY		 165 vcpu->arch.queued_dear = dear_flags;
166 vcpu->arch.queued_esr = esr_flags;
167 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DTLB_MISS);
168}
169
170static void kvmppc_core_queue_data_storage(struct kvm_vcpu *vcpu,
171 ulong dear_flags, ulong esr_flags)
172{
173 vcpu->arch.queued_dear = dear_flags;
174 vcpu->arch.queued_esr = esr_flags;
175 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DATA_STORAGE);
176}
177
178static void kvmppc_core_queue_inst_storage(struct kvm_vcpu *vcpu,
179 ulong esr_flags)
180{
181 vcpu->arch.queued_esr = esr_flags;
182 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_INST_STORAGE);
183}
184
185void kvmppc_core_queue_program(struct kvm_vcpu *vcpu, ulong esr_flags)
186{
187 vcpu->arch.queued_esr = esr_flags;
d4cf3892 188 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_PROGRAM);
9dd921cf
HB		 189}
190
191void kvmppc_core_queue_dec(struct kvm_vcpu *vcpu)
192{
d4cf3892 193 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DECREMENTER);
9dd921cf
HB		 194}
195
196int kvmppc_core_pending_dec(struct kvm_vcpu *vcpu)
197{
d4cf3892 198 return test_bit(BOOKE_IRQPRIO_DECREMENTER, &vcpu->arch.pending_exceptions);
9dd921cf
HB		 199}
200
7706664d
AG		 201void kvmppc_core_dequeue_dec(struct kvm_vcpu *vcpu)
202{
203 clear_bit(BOOKE_IRQPRIO_DECREMENTER, &vcpu->arch.pending_exceptions);
204}
205
9dd921cf
HB		 206void kvmppc_core_queue_external(struct kvm_vcpu *vcpu,
207 struct kvm_interrupt *irq)
208{
c5335f17
AG		 209 unsigned int prio = BOOKE_IRQPRIO_EXTERNAL;
210
211 if (irq->irq == KVM_INTERRUPT_SET_LEVEL)
212 prio = BOOKE_IRQPRIO_EXTERNAL_LEVEL;
213
214 kvmppc_booke_queue_irqprio(vcpu, prio);
9dd921cf
HB		 215}
216
4496f974
AG		 217void kvmppc_core_dequeue_external(struct kvm_vcpu *vcpu,
218 struct kvm_interrupt *irq)
219{
220 clear_bit(BOOKE_IRQPRIO_EXTERNAL, &vcpu->arch.pending_exceptions);
c5335f17 221 clear_bit(BOOKE_IRQPRIO_EXTERNAL_LEVEL, &vcpu->arch.pending_exceptions);
4496f974
AG		 222}
223
f61c94bb
BB		 224static void kvmppc_core_queue_watchdog(struct kvm_vcpu *vcpu)
225{
226 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_WATCHDOG);
227}
228
229static void kvmppc_core_dequeue_watchdog(struct kvm_vcpu *vcpu)
230{
231 clear_bit(BOOKE_IRQPRIO_WATCHDOG, &vcpu->arch.pending_exceptions);
232}
233
d30f6e48
SW		 234static void set_guest_srr(struct kvm_vcpu *vcpu, unsigned long srr0, u32 srr1)
235{
236#ifdef CONFIG_KVM_BOOKE_HV
237 mtspr(SPRN_GSRR0, srr0);
238 mtspr(SPRN_GSRR1, srr1);
239#else
240 vcpu->arch.shared->srr0 = srr0;
241 vcpu->arch.shared->srr1 = srr1;
242#endif
243}
244
245static void set_guest_csrr(struct kvm_vcpu *vcpu, unsigned long srr0, u32 srr1)
246{
247 vcpu->arch.csrr0 = srr0;
248 vcpu->arch.csrr1 = srr1;
249}
250
251static void set_guest_dsrr(struct kvm_vcpu *vcpu, unsigned long srr0, u32 srr1)
252{
253 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC)) {
254 vcpu->arch.dsrr0 = srr0;
255 vcpu->arch.dsrr1 = srr1;
256 } else {
257 set_guest_csrr(vcpu, srr0, srr1);
258 }
259}
260
261static void set_guest_mcsrr(struct kvm_vcpu *vcpu, unsigned long srr0, u32 srr1)
262{
263 vcpu->arch.mcsrr0 = srr0;
264 vcpu->arch.mcsrr1 = srr1;
265}
266
267static unsigned long get_guest_dear(struct kvm_vcpu *vcpu)
268{
269#ifdef CONFIG_KVM_BOOKE_HV
270 return mfspr(SPRN_GDEAR);
271#else
272 return vcpu->arch.shared->dar;
273#endif
274}
275
276static void set_guest_dear(struct kvm_vcpu *vcpu, unsigned long dear)
277{
278#ifdef CONFIG_KVM_BOOKE_HV
279 mtspr(SPRN_GDEAR, dear);
280#else
281 vcpu->arch.shared->dar = dear;
282#endif
283}
284
285static unsigned long get_guest_esr(struct kvm_vcpu *vcpu)
286{
287#ifdef CONFIG_KVM_BOOKE_HV
288 return mfspr(SPRN_GESR);
289#else
290 return vcpu->arch.shared->esr;
291#endif
292}
293
294static void set_guest_esr(struct kvm_vcpu *vcpu, u32 esr)
295{
296#ifdef CONFIG_KVM_BOOKE_HV
297 mtspr(SPRN_GESR, esr);
298#else
299 vcpu->arch.shared->esr = esr;
300#endif
301}
302
d4cf3892
HB		 303/* Deliver the interrupt of the corresponding priority, if possible. */
304static int kvmppc_booke_irqprio_deliver(struct kvm_vcpu *vcpu,
305 unsigned int priority)
bbf45ba5 306{
d4cf3892 307 int allowed = 0;
79300f8c 308 ulong msr_mask = 0;
1c810636 309 bool update_esr = false, update_dear = false, update_epr = false;
5c6cedf4
AG		 310 ulong crit_raw = vcpu->arch.shared->critical;
311 ulong crit_r1 = kvmppc_get_gpr(vcpu, 1);
312 bool crit;
c5335f17 313 bool keep_irq = false;
d30f6e48 314 enum int_class int_class;
95e90b43 315 ulong new_msr = vcpu->arch.shared->msr;
5c6cedf4
AG		 316
317 /* Truncate crit indicators in 32 bit mode */
318 if (!(vcpu->arch.shared->msr & MSR_SF)) {
319 crit_raw &= 0xffffffff;
320 crit_r1 &= 0xffffffff;
321 }
322
323 /* Critical section when crit == r1 */
324 crit = (crit_raw == crit_r1);
325 /* ... and we're in supervisor mode */
326 crit = crit && !(vcpu->arch.shared->msr & MSR_PR);
d4cf3892 327
c5335f17
AG		 328 if (priority == BOOKE_IRQPRIO_EXTERNAL_LEVEL) {
329 priority = BOOKE_IRQPRIO_EXTERNAL;
330 keep_irq = true;
331 }
332
1c810636
AG		 333 if ((priority == BOOKE_IRQPRIO_EXTERNAL) && vcpu->arch.epr_enabled)
334 update_epr = true;
335
d4cf3892 336 switch (priority) {
d4cf3892 337 case BOOKE_IRQPRIO_DTLB_MISS:
d4cf3892 338 case BOOKE_IRQPRIO_DATA_STORAGE:
daf5e271
LY		 339 update_dear = true;
340 /* fall through */
d4cf3892 341 case BOOKE_IRQPRIO_INST_STORAGE:
daf5e271
LY		 342 case BOOKE_IRQPRIO_PROGRAM:
343 update_esr = true;
344 /* fall through */
345 case BOOKE_IRQPRIO_ITLB_MISS:
346 case BOOKE_IRQPRIO_SYSCALL:
d4cf3892 347 case BOOKE_IRQPRIO_FP_UNAVAIL:
bb3a8a17
HB		 348 case BOOKE_IRQPRIO_SPE_UNAVAIL:
349 case BOOKE_IRQPRIO_SPE_FP_DATA:
350 case BOOKE_IRQPRIO_SPE_FP_ROUND:
d4cf3892
HB		 351 case BOOKE_IRQPRIO_AP_UNAVAIL:
352 case BOOKE_IRQPRIO_ALIGNMENT:
353 allowed = 1;
79300f8c 354 msr_mask = MSR_CE | MSR_ME | MSR_DE;
d30f6e48 355 int_class = INT_CLASS_NONCRIT;
bbf45ba5 356 break;
f61c94bb 357 case BOOKE_IRQPRIO_WATCHDOG:
d4cf3892 358 case BOOKE_IRQPRIO_CRITICAL:
4ab96919 359 case BOOKE_IRQPRIO_DBELL_CRIT:
666e7252 360 allowed = vcpu->arch.shared->msr & MSR_CE;
d30f6e48 361 allowed = allowed && !crit;
79300f8c 362 msr_mask = MSR_ME;
d30f6e48 363 int_class = INT_CLASS_CRIT;
bbf45ba5 364 break;
d4cf3892 365 case BOOKE_IRQPRIO_MACHINE_CHECK:
666e7252 366 allowed = vcpu->arch.shared->msr & MSR_ME;
d30f6e48 367 allowed = allowed && !crit;
d30f6e48 368 int_class = INT_CLASS_MC;
bbf45ba5 369 break;
d4cf3892
HB		 370 case BOOKE_IRQPRIO_DECREMENTER:
371 case BOOKE_IRQPRIO_FIT:
dfd4d47e
SW		 372 keep_irq = true;
373 /* fall through */
374 case BOOKE_IRQPRIO_EXTERNAL:
4ab96919 375 case BOOKE_IRQPRIO_DBELL:
666e7252 376 allowed = vcpu->arch.shared->msr & MSR_EE;
5c6cedf4 377 allowed = allowed && !crit;
79300f8c 378 msr_mask = MSR_CE | MSR_ME | MSR_DE;
d30f6e48 379 int_class = INT_CLASS_NONCRIT;
bbf45ba5 380 break;
d4cf3892 381 case BOOKE_IRQPRIO_DEBUG:
666e7252 382 allowed = vcpu->arch.shared->msr & MSR_DE;
d30f6e48 383 allowed = allowed && !crit;
79300f8c 384 msr_mask = MSR_ME;
d30f6e48 385 int_class = INT_CLASS_CRIT;
bbf45ba5 386 break;
bbf45ba5
HB		 387 }
388
d4cf3892 389 if (allowed) {
d30f6e48
SW		 390 switch (int_class) {
391 case INT_CLASS_NONCRIT:
392 set_guest_srr(vcpu, vcpu->arch.pc,
393 vcpu->arch.shared->msr);
394 break;
395 case INT_CLASS_CRIT:
396 set_guest_csrr(vcpu, vcpu->arch.pc,
397 vcpu->arch.shared->msr);
398 break;
399 case INT_CLASS_DBG:
400 set_guest_dsrr(vcpu, vcpu->arch.pc,
401 vcpu->arch.shared->msr);
402 break;
403 case INT_CLASS_MC:
404 set_guest_mcsrr(vcpu, vcpu->arch.pc,
405 vcpu->arch.shared->msr);
406 break;
407 }
408
d4cf3892 409 vcpu->arch.pc = vcpu->arch.ivpr | vcpu->arch.ivor[priority];
daf5e271 410 if (update_esr == true)
d30f6e48 411 set_guest_esr(vcpu, vcpu->arch.queued_esr);
daf5e271 412 if (update_dear == true)
d30f6e48 413 set_guest_dear(vcpu, vcpu->arch.queued_dear);
1c810636
AG		 414 if (update_epr == true)
415 kvm_make_request(KVM_REQ_EPR_EXIT, vcpu);
95e90b43
MC		 416
417 new_msr &= msr_mask;
418#if defined(CONFIG_64BIT)
419 if (vcpu->arch.epcr & SPRN_EPCR_ICM)
420 new_msr |= MSR_CM;
421#endif
422 kvmppc_set_msr(vcpu, new_msr);
bbf45ba5 423
c5335f17
AG		 424 if (!keep_irq)
425 clear_bit(priority, &vcpu->arch.pending_exceptions);
bbf45ba5
HB		 426 }
427
d30f6e48
SW		 428#ifdef CONFIG_KVM_BOOKE_HV
429 /*
430 * If an interrupt is pending but masked, raise a guest doorbell
431 * so that we are notified when the guest enables the relevant
432 * MSR bit.
433 */
434 if (vcpu->arch.pending_exceptions & BOOKE_IRQMASK_EE)
435 kvmppc_set_pending_interrupt(vcpu, INT_CLASS_NONCRIT);
436 if (vcpu->arch.pending_exceptions & BOOKE_IRQMASK_CE)
437 kvmppc_set_pending_interrupt(vcpu, INT_CLASS_CRIT);
438 if (vcpu->arch.pending_exceptions & BOOKE_IRQPRIO_MACHINE_CHECK)
439 kvmppc_set_pending_interrupt(vcpu, INT_CLASS_MC);
440#endif
441
d4cf3892 442 return allowed;
bbf45ba5
HB		 443}
444
f61c94bb
BB		 445/*
446 * Return the number of jiffies until the next timeout. If the timeout is
447 * longer than the NEXT_TIMER_MAX_DELTA, then return NEXT_TIMER_MAX_DELTA
448 * because the larger value can break the timer APIs.
449 */
450static unsigned long watchdog_next_timeout(struct kvm_vcpu *vcpu)
451{
452 u64 tb, wdt_tb, wdt_ticks = 0;
453 u64 nr_jiffies = 0;
454 u32 period = TCR_GET_WP(vcpu->arch.tcr);
455
456 wdt_tb = 1ULL << (63 - period);
457 tb = get_tb();
458 /*
459 * The watchdog timeout will hapeen when TB bit corresponding
460 * to watchdog will toggle from 0 to 1.
461 */
462 if (tb & wdt_tb)
463 wdt_ticks = wdt_tb;
464
465 wdt_ticks += wdt_tb - (tb & (wdt_tb - 1));
466
467 /* Convert timebase ticks to jiffies */
468 nr_jiffies = wdt_ticks;
469
470 if (do_div(nr_jiffies, tb_ticks_per_jiffy))
471 nr_jiffies++;
472
473 return min_t(unsigned long long, nr_jiffies, NEXT_TIMER_MAX_DELTA);
474}
475
476static void arm_next_watchdog(struct kvm_vcpu *vcpu)
477{
478 unsigned long nr_jiffies;
479 unsigned long flags;
480
481 /*
482 * If TSR_ENW and TSR_WIS are not set then no need to exit to
483 * userspace, so clear the KVM_REQ_WATCHDOG request.
484 */
485 if ((vcpu->arch.tsr & (TSR_ENW | TSR_WIS)) != (TSR_ENW | TSR_WIS))
486 clear_bit(KVM_REQ_WATCHDOG, &vcpu->requests);
487
488 spin_lock_irqsave(&vcpu->arch.wdt_lock, flags);
489 nr_jiffies = watchdog_next_timeout(vcpu);
490 /*
491 * If the number of jiffies of watchdog timer >= NEXT_TIMER_MAX_DELTA
492 * then do not run the watchdog timer as this can break timer APIs.
493 */
494 if (nr_jiffies < NEXT_TIMER_MAX_DELTA)
495 mod_timer(&vcpu->arch.wdt_timer, jiffies + nr_jiffies);
496 else
497 del_timer(&vcpu->arch.wdt_timer);
498 spin_unlock_irqrestore(&vcpu->arch.wdt_lock, flags);
499}
500
501void kvmppc_watchdog_func(unsigned long data)
502{
503 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
504 u32 tsr, new_tsr;
505 int final;
506
507 do {
508 new_tsr = tsr = vcpu->arch.tsr;
509 final = 0;
510
511 /* Time out event */
512 if (tsr & TSR_ENW) {
513 if (tsr & TSR_WIS)
514 final = 1;
515 else
516 new_tsr = tsr | TSR_WIS;
517 } else {
518 new_tsr = tsr | TSR_ENW;
519 }
520 } while (cmpxchg(&vcpu->arch.tsr, tsr, new_tsr) != tsr);
521
522 if (new_tsr & TSR_WIS) {
523 smp_wmb();
524 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
525 kvm_vcpu_kick(vcpu);
526 }
527
528 /*
529 * If this is final watchdog expiry and some action is required
530 * then exit to userspace.
531 */
532 if (final && (vcpu->arch.tcr & TCR_WRC_MASK) &&
533 vcpu->arch.watchdog_enabled) {
534 smp_wmb();
535 kvm_make_request(KVM_REQ_WATCHDOG, vcpu);
536 kvm_vcpu_kick(vcpu);
537 }
538
539 /*
540 * Stop running the watchdog timer after final expiration to
541 * prevent the host from being flooded with timers if the
542 * guest sets a short period.
543 * Timers will resume when TSR/TCR is updated next time.
544 */
545 if (!final)
546 arm_next_watchdog(vcpu);
547}
548
dfd4d47e
SW		 549static void update_timer_ints(struct kvm_vcpu *vcpu)
550{
551 if ((vcpu->arch.tcr & TCR_DIE) && (vcpu->arch.tsr & TSR_DIS))
552 kvmppc_core_queue_dec(vcpu);
553 else
554 kvmppc_core_dequeue_dec(vcpu);
f61c94bb
BB		 555
556 if ((vcpu->arch.tcr & TCR_WIE) && (vcpu->arch.tsr & TSR_WIS))
557 kvmppc_core_queue_watchdog(vcpu);
558 else
559 kvmppc_core_dequeue_watchdog(vcpu);
dfd4d47e
SW		 560}
561
c59a6a3e 562static void kvmppc_core_check_exceptions(struct kvm_vcpu *vcpu)
bbf45ba5
HB		 563{
564 unsigned long *pending = &vcpu->arch.pending_exceptions;
bbf45ba5
HB		 565 unsigned int priority;
566
9ab80843 567 priority = __ffs(*pending);
8b3a00fc 568 while (priority < BOOKE_IRQPRIO_MAX) {
d4cf3892 569 if (kvmppc_booke_irqprio_deliver(vcpu, priority))
bbf45ba5 570 break;
bbf45ba5
HB		 571
572 priority = find_next_bit(pending,
573 BITS_PER_BYTE * sizeof(*pending),
574 priority + 1);
575 }
90bba358
AG		 576
577 /* Tell the guest about our interrupt status */
29ac26ef 578 vcpu->arch.shared->int_pending = !!*pending;
bbf45ba5
HB		 579}
580
c59a6a3e 581/* Check pending exceptions and deliver one, if possible. */
a8e4ef84 582int kvmppc_core_prepare_to_enter(struct kvm_vcpu *vcpu)
c59a6a3e 583{
a8e4ef84 584 int r = 0;
c59a6a3e
SW		 585 WARN_ON_ONCE(!irqs_disabled());
586
587 kvmppc_core_check_exceptions(vcpu);
588
b8c649a9
AG		 589 if (vcpu->requests) {
590 /* Exception delivery raised request; start over */
591 return 1;
592 }
593
c59a6a3e
SW		 594 if (vcpu->arch.shared->msr & MSR_WE) {
595 local_irq_enable();
596 kvm_vcpu_block(vcpu);
966cd0f3 597 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
c59a6a3e
SW		 598 local_irq_disable();
599
600 kvmppc_set_exit_type(vcpu, EMULATED_MTMSRWE_EXITS);
a8e4ef84 601 r = 1;
c59a6a3e 602 };
a8e4ef84
AG		 603
604 return r;
605}
606
7c973a2e 607int kvmppc_core_check_requests(struct kvm_vcpu *vcpu)
4ffc6356 608{
7c973a2e
AG		 609 int r = 1; /* Indicate we want to get back into the guest */
610
2d8185d4
AG		 611 if (kvm_check_request(KVM_REQ_PENDING_TIMER, vcpu))
612 update_timer_ints(vcpu);
862d31f7 613#if defined(CONFIG_KVM_E500V2) || defined(CONFIG_KVM_E500MC)
2d8185d4
AG		 614 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
615 kvmppc_core_flush_tlb(vcpu);
862d31f7 616#endif
7c973a2e 617
f61c94bb
BB		 618 if (kvm_check_request(KVM_REQ_WATCHDOG, vcpu)) {
619 vcpu->run->exit_reason = KVM_EXIT_WATCHDOG;
620 r = 0;
621 }
622
1c810636
AG		 623 if (kvm_check_request(KVM_REQ_EPR_EXIT, vcpu)) {
624 vcpu->run->epr.epr = 0;
625 vcpu->arch.epr_needed = true;
626 vcpu->run->exit_reason = KVM_EXIT_EPR;
627 r = 0;
628 }
629
7c973a2e 630 return r;
4ffc6356
AG		 631}
632
df6909e5
PM		 633int kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
634{
7ee78855 635 int ret, s;
8fae845f
SW		 636#ifdef CONFIG_PPC_FPU
637 unsigned int fpscr;
638 int fpexc_mode;
639 u64 fpr[32];
640#endif
df6909e5 641
af8f38b3
AG		 642 if (!vcpu->arch.sane) {
643 kvm_run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
644 return -EINVAL;
645 }
646
df6909e5 647 local_irq_disable();
7ee78855
AG		 648 s = kvmppc_prepare_to_enter(vcpu);
649 if (s <= 0) {
24afa37b 650 local_irq_enable();
7ee78855 651 ret = s;
1d1ef222
SW		 652 goto out;
653 }
bd2be683 654 kvmppc_lazy_ee_enable();
1d1ef222 655
df6909e5 656 kvm_guest_enter();
8fae845f
SW		 657
658#ifdef CONFIG_PPC_FPU
659 /* Save userspace FPU state in stack */
660 enable_kernel_fp();
661 memcpy(fpr, current->thread.fpr, sizeof(current->thread.fpr));
662 fpscr = current->thread.fpscr.val;
663 fpexc_mode = current->thread.fpexc_mode;
664
665 /* Restore guest FPU state to thread */
666 memcpy(current->thread.fpr, vcpu->arch.fpr, sizeof(vcpu->arch.fpr));
667 current->thread.fpscr.val = vcpu->arch.fpscr;
668
669 /*
670 * Since we can't trap on MSR_FP in GS-mode, we consider the guest
671 * as always using the FPU. Kernel usage of FP (via
672 * enable_kernel_fp()) in this thread must not occur while
673 * vcpu->fpu_active is set.
674 */
675 vcpu->fpu_active = 1;
676
677 kvmppc_load_guest_fp(vcpu);
678#endif
679
df6909e5 680 ret = __kvmppc_vcpu_run(kvm_run, vcpu);
8fae845f 681
24afa37b
AG		 682 /* No need for kvm_guest_exit. It's done in handle_exit.
683 We also get here with interrupts enabled. */
684
8fae845f
SW		 685#ifdef CONFIG_PPC_FPU
686 kvmppc_save_guest_fp(vcpu);
687
688 vcpu->fpu_active = 0;
689
690 /* Save guest FPU state from thread */
691 memcpy(vcpu->arch.fpr, current->thread.fpr, sizeof(vcpu->arch.fpr));
692 vcpu->arch.fpscr = current->thread.fpscr.val;
693
694 /* Restore userspace FPU state from stack */
695 memcpy(current->thread.fpr, fpr, sizeof(current->thread.fpr));
696 current->thread.fpscr.val = fpscr;
697 current->thread.fpexc_mode = fpexc_mode;
698#endif
699
1d1ef222 700out:
d69c6436 701 vcpu->mode = OUTSIDE_GUEST_MODE;
df6909e5
PM		 702 return ret;
703}
704
d30f6e48
SW		 705static int emulation_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
706{
707 enum emulation_result er;
708
709 er = kvmppc_emulate_instruction(run, vcpu);
710 switch (er) {
711 case EMULATE_DONE:
712 /* don't overwrite subtypes, just account kvm_stats */
713 kvmppc_account_exit_stat(vcpu, EMULATED_INST_EXITS);
714 /* Future optimization: only reload non-volatiles if
715 * they were actually modified by emulation. */
716 return RESUME_GUEST_NV;
717
718 case EMULATE_DO_DCR:
719 run->exit_reason = KVM_EXIT_DCR;
720 return RESUME_HOST;
721
722 case EMULATE_FAIL:
d30f6e48
SW		 723 printk(KERN_CRIT "%s: emulation at %lx failed (%08x)\n",
724 __func__, vcpu->arch.pc, vcpu->arch.last_inst);
725 /* For debugging, encode the failing instruction and
726 * report it to userspace. */
727 run->hw.hardware_exit_reason = ~0ULL << 32;
728 run->hw.hardware_exit_reason |= vcpu->arch.last_inst;
d1ff5499 729 kvmppc_core_queue_program(vcpu, ESR_PIL);
d30f6e48
SW		 730 return RESUME_HOST;
731
732 default:
733 BUG();
734 }
735}
736
4e642ccb 737static void kvmppc_fill_pt_regs(struct pt_regs *regs)
bbf45ba5 738{
4e642ccb 739 ulong r1, ip, msr, lr;
bbf45ba5 740
4e642ccb
AG		 741 asm("mr %0, 1" : "=r"(r1));
742 asm("mflr %0" : "=r"(lr));
743 asm("mfmsr %0" : "=r"(msr));
744 asm("bl 1f; 1: mflr %0" : "=r"(ip));
745
746 memset(regs, 0, sizeof(*regs));
747 regs->gpr[1] = r1;
748 regs->nip = ip;
749 regs->msr = msr;
750 regs->link = lr;
751}
752
6328e593
BB		 753/*
754 * For interrupts needed to be handled by host interrupt handlers,
755 * corresponding host handler are called from here in similar way
756 * (but not exact) as they are called from low level handler
757 * (such as from arch/powerpc/kernel/head_fsl_booke.S).
758 */
4e642ccb
AG		 759static void kvmppc_restart_interrupt(struct kvm_vcpu *vcpu,
760 unsigned int exit_nr)
761{
762 struct pt_regs regs;
73e75b41 763
d30f6e48
SW		 764 switch (exit_nr) {
765 case BOOKE_INTERRUPT_EXTERNAL:
4e642ccb
AG		 766 kvmppc_fill_pt_regs(&regs);
767 do_IRQ(&regs);
d30f6e48 768 break;
d30f6e48 769 case BOOKE_INTERRUPT_DECREMENTER:
4e642ccb
AG		 770 kvmppc_fill_pt_regs(&regs);
771 timer_interrupt(&regs);
d30f6e48 772 break;
d30f6e48
SW		 773#if defined(CONFIG_PPC_FSL_BOOK3E) || defined(CONFIG_PPC_BOOK3E_64)
774 case BOOKE_INTERRUPT_DOORBELL:
4e642ccb
AG		 775 kvmppc_fill_pt_regs(&regs);
776 doorbell_exception(&regs);
d30f6e48
SW		 777 break;
778#endif
779 case BOOKE_INTERRUPT_MACHINE_CHECK:
780 /* FIXME */
781 break;
7cc1e8ee
AG		 782 case BOOKE_INTERRUPT_PERFORMANCE_MONITOR:
783 kvmppc_fill_pt_regs(&regs);
784 performance_monitor_exception(&regs);
785 break;
6328e593
BB		 786 case BOOKE_INTERRUPT_WATCHDOG:
787 kvmppc_fill_pt_regs(&regs);
788#ifdef CONFIG_BOOKE_WDT
789 WatchdogException(&regs);
790#else
791 unknown_exception(&regs);
792#endif
793 break;
794 case BOOKE_INTERRUPT_CRITICAL:
795 unknown_exception(&regs);
796 break;
d30f6e48 797 }
4e642ccb
AG		 798}
799
800/**
801 * kvmppc_handle_exit
802 *
803 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
804 */
805int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
806 unsigned int exit_nr)
807{
808 int r = RESUME_HOST;
7ee78855 809 int s;
4e642ccb
AG		 810
811 /* update before a new last_exit_type is rewritten */
812 kvmppc_update_timing_stats(vcpu);
813
814 /* restart interrupts if they were meant for the host */
815 kvmppc_restart_interrupt(vcpu, exit_nr);
d30f6e48 816
bbf45ba5
HB		 817 local_irq_enable();
818
97c95059 819 trace_kvm_exit(exit_nr, vcpu);
706fb730 820 kvm_guest_exit();
97c95059 821
bbf45ba5
HB		 822 run->exit_reason = KVM_EXIT_UNKNOWN;
823 run->ready_for_interrupt_injection = 1;
824
825 switch (exit_nr) {
826 case BOOKE_INTERRUPT_MACHINE_CHECK:
c35c9d84
AG		 827 printk("MACHINE CHECK: %lx\n", mfspr(SPRN_MCSR));
828 kvmppc_dump_vcpu(vcpu);
829 /* For debugging, send invalid exit reason to user space */
830 run->hw.hardware_exit_reason = ~1ULL << 32;
831 run->hw.hardware_exit_reason |= mfspr(SPRN_MCSR);
832 r = RESUME_HOST;
bbf45ba5
HB		 833 break;
834
835 case BOOKE_INTERRUPT_EXTERNAL:
7b701591 836 kvmppc_account_exit(vcpu, EXT_INTR_EXITS);
1b6766c7
HB		 837 r = RESUME_GUEST;
838 break;
839
bbf45ba5 840 case BOOKE_INTERRUPT_DECREMENTER:
7b701591 841 kvmppc_account_exit(vcpu, DEC_EXITS);
bbf45ba5
HB		 842 r = RESUME_GUEST;
843 break;
844
6328e593
BB		 845 case BOOKE_INTERRUPT_WATCHDOG:
846 r = RESUME_GUEST;
847 break;
848
d30f6e48
SW		 849 case BOOKE_INTERRUPT_DOORBELL:
850 kvmppc_account_exit(vcpu, DBELL_EXITS);
d30f6e48
SW		 851 r = RESUME_GUEST;
852 break;
853
854 case BOOKE_INTERRUPT_GUEST_DBELL_CRIT:
855 kvmppc_account_exit(vcpu, GDBELL_EXITS);
856
857 /*
858 * We are here because there is a pending guest interrupt
859 * which could not be delivered as MSR_CE or MSR_ME was not
860 * set. Once we break from here we will retry delivery.
861 */
862 r = RESUME_GUEST;
863 break;
864
865 case BOOKE_INTERRUPT_GUEST_DBELL:
866 kvmppc_account_exit(vcpu, GDBELL_EXITS);
867
868 /*
869 * We are here because there is a pending guest interrupt
870 * which could not be delivered as MSR_EE was not set. Once
871 * we break from here we will retry delivery.
872 */
873 r = RESUME_GUEST;
874 break;
875
95f2e921
AG		 876 case BOOKE_INTERRUPT_PERFORMANCE_MONITOR:
877 r = RESUME_GUEST;
878 break;
879
d30f6e48
SW		 880 case BOOKE_INTERRUPT_HV_PRIV:
881 r = emulation_exit(run, vcpu);
882 break;
883
bbf45ba5 884 case BOOKE_INTERRUPT_PROGRAM:
d30f6e48 885 if (vcpu->arch.shared->msr & (MSR_PR | MSR_GS)) {
0268597c
AG		 886 /*
887 * Program traps generated by user-level software must
888 * be handled by the guest kernel.
889 *
890 * In GS mode, hypervisor privileged instructions trap
891 * on BOOKE_INTERRUPT_HV_PRIV, not here, so these are
892 * actual program interrupts, handled by the guest.
893 */
daf5e271 894 kvmppc_core_queue_program(vcpu, vcpu->arch.fault_esr);
bbf45ba5 895 r = RESUME_GUEST;
7b701591 896 kvmppc_account_exit(vcpu, USR_PR_INST);
bbf45ba5
HB		 897 break;
898 }
899
d30f6e48 900 r = emulation_exit(run, vcpu);
bbf45ba5
HB		 901 break;
902
de368dce 903 case BOOKE_INTERRUPT_FP_UNAVAIL:
d4cf3892 904 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_FP_UNAVAIL);
7b701591 905 kvmppc_account_exit(vcpu, FP_UNAVAIL);
de368dce
CE		 906 r = RESUME_GUEST;
907 break;
908
4cd35f67
SW		 909#ifdef CONFIG_SPE
910 case BOOKE_INTERRUPT_SPE_UNAVAIL: {
911 if (vcpu->arch.shared->msr & MSR_SPE)
912 kvmppc_vcpu_enable_spe(vcpu);
913 else
914 kvmppc_booke_queue_irqprio(vcpu,
915 BOOKE_IRQPRIO_SPE_UNAVAIL);
bb3a8a17
HB		 916 r = RESUME_GUEST;
917 break;
4cd35f67 918 }
bb3a8a17
HB		 919
920 case BOOKE_INTERRUPT_SPE_FP_DATA:
921 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_SPE_FP_DATA);
922 r = RESUME_GUEST;
923 break;
924
925 case BOOKE_INTERRUPT_SPE_FP_ROUND:
926 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_SPE_FP_ROUND);
927 r = RESUME_GUEST;
928 break;
4cd35f67
SW		 929#else
930 case BOOKE_INTERRUPT_SPE_UNAVAIL:
931 /*
932 * Guest wants SPE, but host kernel doesn't support it. Send
933 * an "unimplemented operation" program check to the guest.
934 */
935 kvmppc_core_queue_program(vcpu, ESR_PUO | ESR_SPV);
936 r = RESUME_GUEST;
937 break;
938
939 /*
940 * These really should never happen without CONFIG_SPE,
941 * as we should never enable the real MSR[SPE] in the guest.
942 */
943 case BOOKE_INTERRUPT_SPE_FP_DATA:
944 case BOOKE_INTERRUPT_SPE_FP_ROUND:
945 printk(KERN_CRIT "%s: unexpected SPE interrupt %u at %08lx\n",
946 __func__, exit_nr, vcpu->arch.pc);
947 run->hw.hardware_exit_reason = exit_nr;
948 r = RESUME_HOST;
949 break;
950#endif
bb3a8a17 951
bbf45ba5 952 case BOOKE_INTERRUPT_DATA_STORAGE:
daf5e271
LY		 953 kvmppc_core_queue_data_storage(vcpu, vcpu->arch.fault_dear,
954 vcpu->arch.fault_esr);
7b701591 955 kvmppc_account_exit(vcpu, DSI_EXITS);
bbf45ba5
HB		 956 r = RESUME_GUEST;
957 break;
958
959 case BOOKE_INTERRUPT_INST_STORAGE:
daf5e271 960 kvmppc_core_queue_inst_storage(vcpu, vcpu->arch.fault_esr);
7b701591 961 kvmppc_account_exit(vcpu, ISI_EXITS);
bbf45ba5
HB		 962 r = RESUME_GUEST;
963 break;
964
d30f6e48
SW		 965#ifdef CONFIG_KVM_BOOKE_HV
966 case BOOKE_INTERRUPT_HV_SYSCALL:
967 if (!(vcpu->arch.shared->msr & MSR_PR)) {
968 kvmppc_set_gpr(vcpu, 3, kvmppc_kvm_pv(vcpu));
969 } else {
970 /*
971 * hcall from guest userspace -- send privileged
972 * instruction program check.
973 */
974 kvmppc_core_queue_program(vcpu, ESR_PPR);
975 }
976
977 r = RESUME_GUEST;
978 break;
979#else
bbf45ba5 980 case BOOKE_INTERRUPT_SYSCALL:
2a342ed5
AG		 981 if (!(vcpu->arch.shared->msr & MSR_PR) &&
982 (((u32)kvmppc_get_gpr(vcpu, 0)) == KVM_SC_MAGIC_R0)) {
983 /* KVM PV hypercalls */
984 kvmppc_set_gpr(vcpu, 3, kvmppc_kvm_pv(vcpu));
985 r = RESUME_GUEST;
986 } else {
987 /* Guest syscalls */
988 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_SYSCALL);
989 }
7b701591 990 kvmppc_account_exit(vcpu, SYSCALL_EXITS);
bbf45ba5
HB		 991 r = RESUME_GUEST;
992 break;
d30f6e48 993#endif
bbf45ba5
HB		 994
995 case BOOKE_INTERRUPT_DTLB_MISS: {
bbf45ba5 996 unsigned long eaddr = vcpu->arch.fault_dear;
7924bd41 997 int gtlb_index;
475e7cdd 998 gpa_t gpaddr;
bbf45ba5
HB		 999 gfn_t gfn;
1000
bf7ca4bd 1001#ifdef CONFIG_KVM_E500V2
a4cd8b23
SW		 1002 if (!(vcpu->arch.shared->msr & MSR_PR) &&
1003 (eaddr & PAGE_MASK) == vcpu->arch.magic_page_ea) {
1004 kvmppc_map_magic(vcpu);
1005 kvmppc_account_exit(vcpu, DTLB_VIRT_MISS_EXITS);
1006 r = RESUME_GUEST;
1007
1008 break;
1009 }
1010#endif
1011
bbf45ba5 1012 /* Check the guest TLB. */
fa86b8dd 1013 gtlb_index = kvmppc_mmu_dtlb_index(vcpu, eaddr);
7924bd41 1014 if (gtlb_index < 0) {
bbf45ba5 1015 /* The guest didn't have a mapping for it. */
daf5e271
LY		 1016 kvmppc_core_queue_dtlb_miss(vcpu,
1017 vcpu->arch.fault_dear,
1018 vcpu->arch.fault_esr);
b52a638c 1019 kvmppc_mmu_dtlb_miss(vcpu);
7b701591 1020 kvmppc_account_exit(vcpu, DTLB_REAL_MISS_EXITS);
bbf45ba5
HB		 1021 r = RESUME_GUEST;
1022 break;
1023 }
1024
be8d1cae 1025 gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr);
475e7cdd 1026 gfn = gpaddr >> PAGE_SHIFT;
bbf45ba5
HB		 1027
1028 if (kvm_is_visible_gfn(vcpu->kvm, gfn)) {
1029 /* The guest TLB had a mapping, but the shadow TLB
1030 * didn't, and it is RAM. This could be because:
1031 * a) the entry is mapping the host kernel, or
1032 * b) the guest used a large mapping which we're faking
1033 * Either way, we need to satisfy the fault without
1034 * invoking the guest. */
58a96214 1035 kvmppc_mmu_map(vcpu, eaddr, gpaddr, gtlb_index);
7b701591 1036 kvmppc_account_exit(vcpu, DTLB_VIRT_MISS_EXITS);
bbf45ba5
HB		 1037 r = RESUME_GUEST;
1038 } else {
1039 /* Guest has mapped and accessed a page which is not
1040 * actually RAM. */
475e7cdd 1041 vcpu->arch.paddr_accessed = gpaddr;
6020c0f6 1042 vcpu->arch.vaddr_accessed = eaddr;
bbf45ba5 1043 r = kvmppc_emulate_mmio(run, vcpu);
7b701591 1044 kvmppc_account_exit(vcpu, MMIO_EXITS);
bbf45ba5
HB		 1045 }
1046
1047 break;
1048 }
1049
1050 case BOOKE_INTERRUPT_ITLB_MISS: {
bbf45ba5 1051 unsigned long eaddr = vcpu->arch.pc;
89168618 1052 gpa_t gpaddr;
bbf45ba5 1053 gfn_t gfn;
7924bd41 1054 int gtlb_index;
bbf45ba5
HB		 1055
1056 r = RESUME_GUEST;
1057
1058 /* Check the guest TLB. */
fa86b8dd 1059 gtlb_index = kvmppc_mmu_itlb_index(vcpu, eaddr);
7924bd41 1060 if (gtlb_index < 0) {
bbf45ba5 1061 /* The guest didn't have a mapping for it. */
d4cf3892 1062 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_ITLB_MISS);
b52a638c 1063 kvmppc_mmu_itlb_miss(vcpu);
7b701591 1064 kvmppc_account_exit(vcpu, ITLB_REAL_MISS_EXITS);
bbf45ba5
HB		 1065 break;
1066 }
1067
7b701591 1068 kvmppc_account_exit(vcpu, ITLB_VIRT_MISS_EXITS);
bbf45ba5 1069
be8d1cae 1070 gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr);
89168618 1071 gfn = gpaddr >> PAGE_SHIFT;
bbf45ba5
HB		 1072
1073 if (kvm_is_visible_gfn(vcpu->kvm, gfn)) {
1074 /* The guest TLB had a mapping, but the shadow TLB
1075 * didn't. This could be because:
1076 * a) the entry is mapping the host kernel, or
1077 * b) the guest used a large mapping which we're faking
1078 * Either way, we need to satisfy the fault without
1079 * invoking the guest. */
58a96214 1080 kvmppc_mmu_map(vcpu, eaddr, gpaddr, gtlb_index);
bbf45ba5
HB		 1081 } else {
1082 /* Guest mapped and leaped at non-RAM! */
d4cf3892 1083 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_MACHINE_CHECK);
bbf45ba5
HB		 1084 }
1085
1086 break;
1087 }
1088
6a0ab738
HB		 1089 case BOOKE_INTERRUPT_DEBUG: {
1090 u32 dbsr;
1091
1092 vcpu->arch.pc = mfspr(SPRN_CSRR0);
1093
1094 /* clear IAC events in DBSR register */
1095 dbsr = mfspr(SPRN_DBSR);
1096 dbsr &= DBSR_IAC1 | DBSR_IAC2 | DBSR_IAC3 | DBSR_IAC4;
1097 mtspr(SPRN_DBSR, dbsr);
1098
1099 run->exit_reason = KVM_EXIT_DEBUG;
7b701591 1100 kvmppc_account_exit(vcpu, DEBUG_EXITS);
6a0ab738
HB		 1101 r = RESUME_HOST;
1102 break;
1103 }
1104
bbf45ba5
HB		 1105 default:
1106 printk(KERN_EMERG "exit_nr %d\n", exit_nr);
1107 BUG();
1108 }
1109
a8e4ef84
AG		 1110 /*
1111 * To avoid clobbering exit_reason, only check for signals if we
1112 * aren't already exiting to userspace for some other reason.
1113 */
03660ba2
AG		 1114 if (!(r & RESUME_HOST)) {
1115 local_irq_disable();
7ee78855
AG		 1116 s = kvmppc_prepare_to_enter(vcpu);
1117 if (s <= 0) {
24afa37b 1118 local_irq_enable();
7ee78855 1119 r = (s << 2) | RESUME_HOST | (r & RESUME_FLAG_NV);
24afa37b 1120 } else {
bd2be683 1121 kvmppc_lazy_ee_enable();
03660ba2 1122 }
bbf45ba5
HB		 1123 }
1124
1125 return r;
1126}
1127
1128/* Initial guest state: 16MB mapping 0 -> 0, PC = 0, MSR = 0, R1 = 16MB */
1129int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
1130{
082decf2 1131 int i;
af8f38b3 1132 int r;
082decf2 1133
bbf45ba5 1134 vcpu->arch.pc = 0;
b5904972 1135 vcpu->arch.shared->pir = vcpu->vcpu_id;
8e5b26b5 1136 kvmppc_set_gpr(vcpu, 1, (16<<20) - 8); /* -8 for the callee-save LR slot */
d30f6e48 1137 kvmppc_set_msr(vcpu, 0);
bbf45ba5 1138
d30f6e48
SW		 1139#ifndef CONFIG_KVM_BOOKE_HV
1140 vcpu->arch.shadow_msr = MSR_USER | MSR_DE | MSR_IS | MSR_DS;
49dd2c49 1141 vcpu->arch.shadow_pid = 1;
d30f6e48
SW		 1142 vcpu->arch.shared->msr = 0;
1143#endif
49dd2c49 1144
082decf2
HB		 1145 /* Eye-catching numbers so we know if the guest takes an interrupt
1146 * before it's programmed its own IVPR/IVORs. */
bbf45ba5 1147 vcpu->arch.ivpr = 0x55550000;
082decf2
HB		 1148 for (i = 0; i < BOOKE_IRQPRIO_MAX; i++)
1149 vcpu->arch.ivor[i] = 0x7700 | i * 4;
bbf45ba5 1150
73e75b41
HB		 1151 kvmppc_init_timing_stats(vcpu);
1152
af8f38b3
AG		 1153 r = kvmppc_core_vcpu_setup(vcpu);
1154 kvmppc_sanity_check(vcpu);
1155 return r;
bbf45ba5
HB		 1156}
1157
f61c94bb
BB		 1158int kvmppc_subarch_vcpu_init(struct kvm_vcpu *vcpu)
1159{
1160 /* setup watchdog timer once */
1161 spin_lock_init(&vcpu->arch.wdt_lock);
1162 setup_timer(&vcpu->arch.wdt_timer, kvmppc_watchdog_func,
1163 (unsigned long)vcpu);
1164
1165 return 0;
1166}
1167
1168void kvmppc_subarch_vcpu_uninit(struct kvm_vcpu *vcpu)
1169{
1170 del_timer_sync(&vcpu->arch.wdt_timer);
1171}
1172
bbf45ba5
HB		 1173int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1174{
1175 int i;
1176
1177 regs->pc = vcpu->arch.pc;
992b5b29 1178 regs->cr = kvmppc_get_cr(vcpu);
bbf45ba5
HB		 1179 regs->ctr = vcpu->arch.ctr;
1180 regs->lr = vcpu->arch.lr;
992b5b29 1181 regs->xer = kvmppc_get_xer(vcpu);
666e7252 1182 regs->msr = vcpu->arch.shared->msr;
de7906c3
AG		 1183 regs->srr0 = vcpu->arch.shared->srr0;
1184 regs->srr1 = vcpu->arch.shared->srr1;
bbf45ba5 1185 regs->pid = vcpu->arch.pid;
a73a9599
AG		 1186 regs->sprg0 = vcpu->arch.shared->sprg0;
1187 regs->sprg1 = vcpu->arch.shared->sprg1;
1188 regs->sprg2 = vcpu->arch.shared->sprg2;
1189 regs->sprg3 = vcpu->arch.shared->sprg3;
b5904972
SW		 1190 regs->sprg4 = vcpu->arch.shared->sprg4;
1191 regs->sprg5 = vcpu->arch.shared->sprg5;
1192 regs->sprg6 = vcpu->arch.shared->sprg6;
1193 regs->sprg7 = vcpu->arch.shared->sprg7;
bbf45ba5
HB		 1194
1195 for (i = 0; i < ARRAY_SIZE(regs->gpr); i++)
8e5b26b5 1196 regs->gpr[i] = kvmppc_get_gpr(vcpu, i);
bbf45ba5
HB		 1197
1198 return 0;
1199}
1200
1201int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1202{
1203 int i;
1204
1205 vcpu->arch.pc = regs->pc;
992b5b29 1206 kvmppc_set_cr(vcpu, regs->cr);
bbf45ba5
HB		 1207 vcpu->arch.ctr = regs->ctr;
1208 vcpu->arch.lr = regs->lr;
992b5b29 1209 kvmppc_set_xer(vcpu, regs->xer);
b8fd68ac 1210 kvmppc_set_msr(vcpu, regs->msr);
de7906c3
AG		 1211 vcpu->arch.shared->srr0 = regs->srr0;
1212 vcpu->arch.shared->srr1 = regs->srr1;
5ce941ee 1213 kvmppc_set_pid(vcpu, regs->pid);
a73a9599
AG		 1214 vcpu->arch.shared->sprg0 = regs->sprg0;
1215 vcpu->arch.shared->sprg1 = regs->sprg1;
1216 vcpu->arch.shared->sprg2 = regs->sprg2;
1217 vcpu->arch.shared->sprg3 = regs->sprg3;
b5904972
SW		 1218 vcpu->arch.shared->sprg4 = regs->sprg4;
1219 vcpu->arch.shared->sprg5 = regs->sprg5;
1220 vcpu->arch.shared->sprg6 = regs->sprg6;
1221 vcpu->arch.shared->sprg7 = regs->sprg7;
bbf45ba5 1222
8e5b26b5
AG		 1223 for (i = 0; i < ARRAY_SIZE(regs->gpr); i++)
1224 kvmppc_set_gpr(vcpu, i, regs->gpr[i]);
bbf45ba5
HB		 1225
1226 return 0;
1227}
1228
5ce941ee
SW		 1229static void get_sregs_base(struct kvm_vcpu *vcpu,
1230 struct kvm_sregs *sregs)
1231{
1232 u64 tb = get_tb();
1233
1234 sregs->u.e.features |= KVM_SREGS_E_BASE;
1235
1236 sregs->u.e.csrr0 = vcpu->arch.csrr0;
1237 sregs->u.e.csrr1 = vcpu->arch.csrr1;
1238 sregs->u.e.mcsr = vcpu->arch.mcsr;
d30f6e48
SW		 1239 sregs->u.e.esr = get_guest_esr(vcpu);
1240 sregs->u.e.dear = get_guest_dear(vcpu);
5ce941ee
SW		 1241 sregs->u.e.tsr = vcpu->arch.tsr;
1242 sregs->u.e.tcr = vcpu->arch.tcr;
1243 sregs->u.e.dec = kvmppc_get_dec(vcpu, tb);
1244 sregs->u.e.tb = tb;
1245 sregs->u.e.vrsave = vcpu->arch.vrsave;
1246}
1247
1248static int set_sregs_base(struct kvm_vcpu *vcpu,
1249 struct kvm_sregs *sregs)
1250{
1251 if (!(sregs->u.e.features & KVM_SREGS_E_BASE))
1252 return 0;
1253
1254 vcpu->arch.csrr0 = sregs->u.e.csrr0;
1255 vcpu->arch.csrr1 = sregs->u.e.csrr1;
1256 vcpu->arch.mcsr = sregs->u.e.mcsr;
d30f6e48
SW		 1257 set_guest_esr(vcpu, sregs->u.e.esr);
1258 set_guest_dear(vcpu, sregs->u.e.dear);
5ce941ee 1259 vcpu->arch.vrsave = sregs->u.e.vrsave;
dfd4d47e 1260 kvmppc_set_tcr(vcpu, sregs->u.e.tcr);
5ce941ee 1261
dfd4d47e 1262 if (sregs->u.e.update_special & KVM_SREGS_E_UPDATE_DEC) {
5ce941ee 1263 vcpu->arch.dec = sregs->u.e.dec;
dfd4d47e
SW		 1264 kvmppc_emulate_dec(vcpu);
1265 }
5ce941ee
SW		 1266
1267 if (sregs->u.e.update_special & KVM_SREGS_E_UPDATE_TSR) {
f61c94bb
BB		 1268 u32 old_tsr = vcpu->arch.tsr;
1269
dfd4d47e 1270 vcpu->arch.tsr = sregs->u.e.tsr;
f61c94bb
BB		 1271
1272 if ((old_tsr ^ vcpu->arch.tsr) & (TSR_ENW | TSR_WIS))
1273 arm_next_watchdog(vcpu);
1274
dfd4d47e 1275 update_timer_ints(vcpu);
5ce941ee
SW		 1276 }
1277
1278 return 0;
1279}
1280
1281static void get_sregs_arch206(struct kvm_vcpu *vcpu,
1282 struct kvm_sregs *sregs)
1283{
1284 sregs->u.e.features |= KVM_SREGS_E_ARCH206;
1285
841741f2 1286 sregs->u.e.pir = vcpu->vcpu_id;
5ce941ee
SW		 1287 sregs->u.e.mcsrr0 = vcpu->arch.mcsrr0;
1288 sregs->u.e.mcsrr1 = vcpu->arch.mcsrr1;
1289 sregs->u.e.decar = vcpu->arch.decar;
1290 sregs->u.e.ivpr = vcpu->arch.ivpr;
1291}
1292
1293static int set_sregs_arch206(struct kvm_vcpu *vcpu,
1294 struct kvm_sregs *sregs)
1295{
1296 if (!(sregs->u.e.features & KVM_SREGS_E_ARCH206))
1297 return 0;
1298
841741f2 1299 if (sregs->u.e.pir != vcpu->vcpu_id)
5ce941ee
SW		 1300 return -EINVAL;
1301
1302 vcpu->arch.mcsrr0 = sregs->u.e.mcsrr0;
1303 vcpu->arch.mcsrr1 = sregs->u.e.mcsrr1;
1304 vcpu->arch.decar = sregs->u.e.decar;
1305 vcpu->arch.ivpr = sregs->u.e.ivpr;
1306
1307 return 0;
1308}
1309
1310void kvmppc_get_sregs_ivor(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
1311{
1312 sregs->u.e.features |= KVM_SREGS_E_IVOR;
1313
1314 sregs->u.e.ivor_low[0] = vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL];
1315 sregs->u.e.ivor_low[1] = vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK];
1316 sregs->u.e.ivor_low[2] = vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE];
1317 sregs->u.e.ivor_low[3] = vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE];
1318 sregs->u.e.ivor_low[4] = vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL];
1319 sregs->u.e.ivor_low[5] = vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT];
1320 sregs->u.e.ivor_low[6] = vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM];
1321 sregs->u.e.ivor_low[7] = vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL];
1322 sregs->u.e.ivor_low[8] = vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL];
1323 sregs->u.e.ivor_low[9] = vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL];
1324 sregs->u.e.ivor_low[10] = vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER];
1325 sregs->u.e.ivor_low[11] = vcpu->arch.ivor[BOOKE_IRQPRIO_FIT];
1326 sregs->u.e.ivor_low[12] = vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG];
1327 sregs->u.e.ivor_low[13] = vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS];
1328 sregs->u.e.ivor_low[14] = vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS];
1329 sregs->u.e.ivor_low[15] = vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG];
1330}
1331
1332int kvmppc_set_sregs_ivor(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
1333{
1334 if (!(sregs->u.e.features & KVM_SREGS_E_IVOR))
1335 return 0;
1336
1337 vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL] = sregs->u.e.ivor_low[0];
1338 vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK] = sregs->u.e.ivor_low[1];
1339 vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE] = sregs->u.e.ivor_low[2];
1340 vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE] = sregs->u.e.ivor_low[3];
1341 vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL] = sregs->u.e.ivor_low[4];
1342 vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT] = sregs->u.e.ivor_low[5];
1343 vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM] = sregs->u.e.ivor_low[6];
1344 vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL] = sregs->u.e.ivor_low[7];
1345 vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL] = sregs->u.e.ivor_low[8];
1346 vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL] = sregs->u.e.ivor_low[9];
1347 vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER] = sregs->u.e.ivor_low[10];
1348 vcpu->arch.ivor[BOOKE_IRQPRIO_FIT] = sregs->u.e.ivor_low[11];
1349 vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG] = sregs->u.e.ivor_low[12];
1350 vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS] = sregs->u.e.ivor_low[13];
1351 vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS] = sregs->u.e.ivor_low[14];
1352 vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG] = sregs->u.e.ivor_low[15];
1353
1354 return 0;
1355}
1356
bbf45ba5
HB		 1357int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
1358 struct kvm_sregs *sregs)
1359{
5ce941ee
SW		 1360 sregs->pvr = vcpu->arch.pvr;
1361
1362 get_sregs_base(vcpu, sregs);
1363 get_sregs_arch206(vcpu, sregs);
1364 kvmppc_core_get_sregs(vcpu, sregs);
1365 return 0;
bbf45ba5
HB		 1366}
1367
1368int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
1369 struct kvm_sregs *sregs)
1370{
5ce941ee
SW		 1371 int ret;
1372
1373 if (vcpu->arch.pvr != sregs->pvr)
1374 return -EINVAL;
1375
1376 ret = set_sregs_base(vcpu, sregs);
1377 if (ret < 0)
1378 return ret;
1379
1380 ret = set_sregs_arch206(vcpu, sregs);
1381 if (ret < 0)
1382 return ret;
1383
1384 return kvmppc_core_set_sregs(vcpu, sregs);
bbf45ba5
HB		 1385}
1386
31f3438e
PM		 1387int kvm_vcpu_ioctl_get_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
1388{
6df8d3fc
BB		 1389 int r = -EINVAL;
1390
1391 switch (reg->id) {
1392 case KVM_REG_PPC_IAC1:
1393 case KVM_REG_PPC_IAC2:
1394 case KVM_REG_PPC_IAC3:
1395 case KVM_REG_PPC_IAC4: {
1396 int iac = reg->id - KVM_REG_PPC_IAC1;
1397 r = copy_to_user((u64 __user *)(long)reg->addr,
1398 &vcpu->arch.dbg_reg.iac[iac], sizeof(u64));
1399 break;
1400 }
1401 case KVM_REG_PPC_DAC1:
1402 case KVM_REG_PPC_DAC2: {
1403 int dac = reg->id - KVM_REG_PPC_DAC1;
1404 r = copy_to_user((u64 __user *)(long)reg->addr,
1405 &vcpu->arch.dbg_reg.dac[dac], sizeof(u64));
1406 break;
1407 }
352df1de
MC		 1408#if defined(CONFIG_64BIT)
1409 case KVM_REG_PPC_EPCR:
1410 r = put_user(vcpu->arch.epcr, (u32 __user *)(long)reg->addr);
1411 break;
1412#endif
6df8d3fc
BB		 1413 default:
1414 break;
1415 }
1416 return r;
31f3438e
PM		 1417}
1418
1419int kvm_vcpu_ioctl_set_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
1420{
6df8d3fc
BB		 1421 int r = -EINVAL;
1422
1423 switch (reg->id) {
1424 case KVM_REG_PPC_IAC1:
1425 case KVM_REG_PPC_IAC2:
1426 case KVM_REG_PPC_IAC3:
1427 case KVM_REG_PPC_IAC4: {
1428 int iac = reg->id - KVM_REG_PPC_IAC1;
1429 r = copy_from_user(&vcpu->arch.dbg_reg.iac[iac],
1430 (u64 __user *)(long)reg->addr, sizeof(u64));
1431 break;
1432 }
1433 case KVM_REG_PPC_DAC1:
1434 case KVM_REG_PPC_DAC2: {
1435 int dac = reg->id - KVM_REG_PPC_DAC1;
1436 r = copy_from_user(&vcpu->arch.dbg_reg.dac[dac],
1437 (u64 __user *)(long)reg->addr, sizeof(u64));
1438 break;
1439 }
352df1de
MC		 1440#if defined(CONFIG_64BIT)
1441 case KVM_REG_PPC_EPCR: {
1442 u32 new_epcr;
1443 r = get_user(new_epcr, (u32 __user *)(long)reg->addr);
1444 if (r == 0)
1445 kvmppc_set_epcr(vcpu, new_epcr);
1446 break;
1447 }
1448#endif
6df8d3fc
BB		 1449 default:
1450 break;
1451 }
1452 return r;
31f3438e
PM		 1453}
1454
bbf45ba5
HB		 1455int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1456{
1457 return -ENOTSUPP;
1458}
1459
1460int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1461{
1462 return -ENOTSUPP;
1463}
1464
bbf45ba5
HB		 1465int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1466 struct kvm_translation *tr)
1467{
98001d8d
AK		 1468 int r;
1469
98001d8d 1470 r = kvmppc_core_vcpu_translate(vcpu, tr);
98001d8d 1471 return r;
bbf45ba5 1472}
d9fbd03d 1473
4e755758
AG		 1474int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
1475{
1476 return -ENOTSUPP;
1477}
1478
a66b48c3
PM		 1479void kvmppc_core_free_memslot(struct kvm_memory_slot *free,
1480 struct kvm_memory_slot *dont)
1481{
1482}
1483
1484int kvmppc_core_create_memslot(struct kvm_memory_slot *slot,
1485 unsigned long npages)
1486{
1487 return 0;
1488}
1489
f9e0554d 1490int kvmppc_core_prepare_memory_region(struct kvm *kvm,
a66b48c3 1491 struct kvm_memory_slot *memslot,
f9e0554d
PM		 1492 struct kvm_userspace_memory_region *mem)
1493{
1494 return 0;
1495}
1496
1497void kvmppc_core_commit_memory_region(struct kvm *kvm,
dfe49dbd
PM		 1498 struct kvm_userspace_memory_region *mem,
1499 struct kvm_memory_slot old)
1500{
1501}
1502
1503void kvmppc_core_flush_memslot(struct kvm *kvm, struct kvm_memory_slot *memslot)
f9e0554d
PM		 1504{
1505}
1506
38f98824
MC		 1507void kvmppc_set_epcr(struct kvm_vcpu *vcpu, u32 new_epcr)
1508{
1509#if defined(CONFIG_64BIT)
1510 vcpu->arch.epcr = new_epcr;
1511#ifdef CONFIG_KVM_BOOKE_HV
1512 vcpu->arch.shadow_epcr &= ~SPRN_EPCR_GICM;
1513 if (vcpu->arch.epcr & SPRN_EPCR_ICM)
1514 vcpu->arch.shadow_epcr |= SPRN_EPCR_GICM;
1515#endif
1516#endif
1517}
1518
dfd4d47e
SW		 1519void kvmppc_set_tcr(struct kvm_vcpu *vcpu, u32 new_tcr)
1520{
1521 vcpu->arch.tcr = new_tcr;
f61c94bb 1522 arm_next_watchdog(vcpu);
dfd4d47e
SW		 1523 update_timer_ints(vcpu);
1524}
1525
1526void kvmppc_set_tsr_bits(struct kvm_vcpu *vcpu, u32 tsr_bits)
1527{
1528 set_bits(tsr_bits, &vcpu->arch.tsr);
1529 smp_wmb();
1530 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1531 kvm_vcpu_kick(vcpu);
1532}
1533
1534void kvmppc_clr_tsr_bits(struct kvm_vcpu *vcpu, u32 tsr_bits)
1535{
1536 clear_bits(tsr_bits, &vcpu->arch.tsr);
f61c94bb
BB		 1537
1538 /*
1539 * We may have stopped the watchdog due to
1540 * being stuck on final expiration.
1541 */
1542 if (tsr_bits & (TSR_ENW | TSR_WIS))
1543 arm_next_watchdog(vcpu);
1544
dfd4d47e
SW		 1545 update_timer_ints(vcpu);
1546}
1547
1548void kvmppc_decrementer_func(unsigned long data)
1549{
1550 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
1551
21bd000a
BB		 1552 if (vcpu->arch.tcr & TCR_ARE) {
1553 vcpu->arch.dec = vcpu->arch.decar;
1554 kvmppc_emulate_dec(vcpu);
1555 }
1556
dfd4d47e
SW		 1557 kvmppc_set_tsr_bits(vcpu, TSR_DIS);
1558}
1559
94fa9d99
SW		 1560void kvmppc_booke_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1561{
a47d72f3 1562 vcpu->cpu = smp_processor_id();
d30f6e48 1563 current->thread.kvm_vcpu = vcpu;
94fa9d99
SW		 1564}
1565
1566void kvmppc_booke_vcpu_put(struct kvm_vcpu *vcpu)
1567{
d30f6e48 1568 current->thread.kvm_vcpu = NULL;
a47d72f3 1569 vcpu->cpu = -1;
94fa9d99
SW		 1570}
1571
2986b8c7 1572int __init kvmppc_booke_init(void)
d9fbd03d 1573{
d30f6e48 1574#ifndef CONFIG_KVM_BOOKE_HV
d9fbd03d
HB		 1575 unsigned long ivor[16];
1576 unsigned long max_ivor = 0;
1577 int i;
1578
1579 /* We install our own exception handlers by hijacking IVPR. IVPR must
1580 * be 16-bit aligned, so we need a 64KB allocation. */
1581 kvmppc_booke_handlers = __get_free_pages(GFP_KERNEL | __GFP_ZERO,
1582 VCPU_SIZE_ORDER);
1583 if (!kvmppc_booke_handlers)
1584 return -ENOMEM;
1585
1586 /* XXX make sure our handlers are smaller than Linux's */
1587
1588 /* Copy our interrupt handlers to match host IVORs. That way we don't
1589 * have to swap the IVORs on every guest/host transition. */
1590 ivor[0] = mfspr(SPRN_IVOR0);
1591 ivor[1] = mfspr(SPRN_IVOR1);
1592 ivor[2] = mfspr(SPRN_IVOR2);
1593 ivor[3] = mfspr(SPRN_IVOR3);
1594 ivor[4] = mfspr(SPRN_IVOR4);
1595 ivor[5] = mfspr(SPRN_IVOR5);
1596 ivor[6] = mfspr(SPRN_IVOR6);
1597 ivor[7] = mfspr(SPRN_IVOR7);
1598 ivor[8] = mfspr(SPRN_IVOR8);
1599 ivor[9] = mfspr(SPRN_IVOR9);
1600 ivor[10] = mfspr(SPRN_IVOR10);
1601 ivor[11] = mfspr(SPRN_IVOR11);
1602 ivor[12] = mfspr(SPRN_IVOR12);
1603 ivor[13] = mfspr(SPRN_IVOR13);
1604 ivor[14] = mfspr(SPRN_IVOR14);
1605 ivor[15] = mfspr(SPRN_IVOR15);
1606
1607 for (i = 0; i < 16; i++) {
1608 if (ivor[i] > max_ivor)
1609 max_ivor = ivor[i];
1610
1611 memcpy((void *)kvmppc_booke_handlers + ivor[i],
1612 kvmppc_handlers_start + i * kvmppc_handler_len,
1613 kvmppc_handler_len);
1614 }
1615 flush_icache_range(kvmppc_booke_handlers,
1616 kvmppc_booke_handlers + max_ivor + kvmppc_handler_len);
d30f6e48 1617#endif /* !BOOKE_HV */
db93f574 1618 return 0;
d9fbd03d
HB		 1619}
1620
db93f574 1621void __exit kvmppc_booke_exit(void)
d9fbd03d
HB		 1622{
1623 free_pages(kvmppc_booke_handlers, VCPU_SIZE_ORDER);
1624 kvm_exit();
1625}
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