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bbf45ba5 HB |
1 | /* |
2 | * This program is free software; you can redistribute it and/or modify | |
3 | * it under the terms of the GNU General Public License, version 2, as | |
4 | * published by the Free Software Foundation. | |
5 | * | |
6 | * This program is distributed in the hope that it will be useful, | |
7 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
8 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
9 | * GNU General Public License for more details. | |
10 | * | |
11 | * You should have received a copy of the GNU General Public License | |
12 | * along with this program; if not, write to the Free Software | |
13 | * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. | |
14 | * | |
15 | * Copyright IBM Corp. 2007 | |
4cd35f67 | 16 | * Copyright 2010-2011 Freescale Semiconductor, Inc. |
bbf45ba5 HB |
17 | * |
18 | * Authors: Hollis Blanchard <hollisb@us.ibm.com> | |
19 | * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com> | |
d30f6e48 SW |
20 | * Scott Wood <scottwood@freescale.com> |
21 | * Varun Sethi <varun.sethi@freescale.com> | |
bbf45ba5 HB |
22 | */ |
23 | ||
24 | #include <linux/errno.h> | |
25 | #include <linux/err.h> | |
26 | #include <linux/kvm_host.h> | |
5a0e3ad6 | 27 | #include <linux/gfp.h> |
bbf45ba5 HB |
28 | #include <linux/module.h> |
29 | #include <linux/vmalloc.h> | |
30 | #include <linux/fs.h> | |
7924bd41 | 31 | |
bbf45ba5 HB |
32 | #include <asm/cputable.h> |
33 | #include <asm/uaccess.h> | |
34 | #include <asm/kvm_ppc.h> | |
d9fbd03d | 35 | #include <asm/cacheflush.h> |
d30f6e48 SW |
36 | #include <asm/dbell.h> |
37 | #include <asm/hw_irq.h> | |
38 | #include <asm/irq.h> | |
b50df19c | 39 | #include <asm/time.h> |
bbf45ba5 | 40 | |
d30f6e48 | 41 | #include "timing.h" |
75f74f0d | 42 | #include "booke.h" |
dba291f2 AK |
43 | |
44 | #define CREATE_TRACE_POINTS | |
45 | #include "trace_booke.h" | |
bbf45ba5 | 46 | |
d9fbd03d HB |
47 | unsigned long kvmppc_booke_handlers; |
48 | ||
bbf45ba5 HB |
49 | #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM |
50 | #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU | |
51 | ||
52 | struct kvm_stats_debugfs_item debugfs_entries[] = { | |
bbf45ba5 HB |
53 | { "mmio", VCPU_STAT(mmio_exits) }, |
54 | { "dcr", VCPU_STAT(dcr_exits) }, | |
55 | { "sig", VCPU_STAT(signal_exits) }, | |
bbf45ba5 HB |
56 | { "itlb_r", VCPU_STAT(itlb_real_miss_exits) }, |
57 | { "itlb_v", VCPU_STAT(itlb_virt_miss_exits) }, | |
58 | { "dtlb_r", VCPU_STAT(dtlb_real_miss_exits) }, | |
59 | { "dtlb_v", VCPU_STAT(dtlb_virt_miss_exits) }, | |
60 | { "sysc", VCPU_STAT(syscall_exits) }, | |
61 | { "isi", VCPU_STAT(isi_exits) }, | |
62 | { "dsi", VCPU_STAT(dsi_exits) }, | |
63 | { "inst_emu", VCPU_STAT(emulated_inst_exits) }, | |
64 | { "dec", VCPU_STAT(dec_exits) }, | |
65 | { "ext_intr", VCPU_STAT(ext_intr_exits) }, | |
45c5eb67 | 66 | { "halt_wakeup", VCPU_STAT(halt_wakeup) }, |
d30f6e48 SW |
67 | { "doorbell", VCPU_STAT(dbell_exits) }, |
68 | { "guest doorbell", VCPU_STAT(gdbell_exits) }, | |
cf1c5ca4 | 69 | { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, |
bbf45ba5 HB |
70 | { NULL } |
71 | }; | |
72 | ||
bbf45ba5 HB |
73 | /* TODO: use vcpu_printf() */ |
74 | void kvmppc_dump_vcpu(struct kvm_vcpu *vcpu) | |
75 | { | |
76 | int i; | |
77 | ||
666e7252 | 78 | printk("pc: %08lx msr: %08llx\n", vcpu->arch.pc, vcpu->arch.shared->msr); |
5cf8ca22 | 79 | printk("lr: %08lx ctr: %08lx\n", vcpu->arch.lr, vcpu->arch.ctr); |
de7906c3 AG |
80 | printk("srr0: %08llx srr1: %08llx\n", vcpu->arch.shared->srr0, |
81 | vcpu->arch.shared->srr1); | |
bbf45ba5 HB |
82 | |
83 | printk("exceptions: %08lx\n", vcpu->arch.pending_exceptions); | |
84 | ||
85 | for (i = 0; i < 32; i += 4) { | |
5cf8ca22 | 86 | printk("gpr%02d: %08lx %08lx %08lx %08lx\n", i, |
8e5b26b5 AG |
87 | kvmppc_get_gpr(vcpu, i), |
88 | kvmppc_get_gpr(vcpu, i+1), | |
89 | kvmppc_get_gpr(vcpu, i+2), | |
90 | kvmppc_get_gpr(vcpu, i+3)); | |
bbf45ba5 HB |
91 | } |
92 | } | |
93 | ||
4cd35f67 SW |
94 | #ifdef CONFIG_SPE |
95 | void kvmppc_vcpu_disable_spe(struct kvm_vcpu *vcpu) | |
96 | { | |
97 | preempt_disable(); | |
98 | enable_kernel_spe(); | |
99 | kvmppc_save_guest_spe(vcpu); | |
100 | vcpu->arch.shadow_msr &= ~MSR_SPE; | |
101 | preempt_enable(); | |
102 | } | |
103 | ||
104 | static void kvmppc_vcpu_enable_spe(struct kvm_vcpu *vcpu) | |
105 | { | |
106 | preempt_disable(); | |
107 | enable_kernel_spe(); | |
108 | kvmppc_load_guest_spe(vcpu); | |
109 | vcpu->arch.shadow_msr |= MSR_SPE; | |
110 | preempt_enable(); | |
111 | } | |
112 | ||
113 | static void kvmppc_vcpu_sync_spe(struct kvm_vcpu *vcpu) | |
114 | { | |
115 | if (vcpu->arch.shared->msr & MSR_SPE) { | |
116 | if (!(vcpu->arch.shadow_msr & MSR_SPE)) | |
117 | kvmppc_vcpu_enable_spe(vcpu); | |
118 | } else if (vcpu->arch.shadow_msr & MSR_SPE) { | |
119 | kvmppc_vcpu_disable_spe(vcpu); | |
120 | } | |
121 | } | |
122 | #else | |
123 | static void kvmppc_vcpu_sync_spe(struct kvm_vcpu *vcpu) | |
124 | { | |
125 | } | |
126 | #endif | |
127 | ||
7a08c274 AG |
128 | static void kvmppc_vcpu_sync_fpu(struct kvm_vcpu *vcpu) |
129 | { | |
130 | #if defined(CONFIG_PPC_FPU) && !defined(CONFIG_KVM_BOOKE_HV) | |
131 | /* We always treat the FP bit as enabled from the host | |
132 | perspective, so only need to adjust the shadow MSR */ | |
133 | vcpu->arch.shadow_msr &= ~MSR_FP; | |
134 | vcpu->arch.shadow_msr |= vcpu->arch.shared->msr & MSR_FP; | |
135 | #endif | |
136 | } | |
137 | ||
ce11e48b BB |
138 | static void kvmppc_vcpu_sync_debug(struct kvm_vcpu *vcpu) |
139 | { | |
140 | /* Synchronize guest's desire to get debug interrupts into shadow MSR */ | |
141 | #ifndef CONFIG_KVM_BOOKE_HV | |
142 | vcpu->arch.shadow_msr &= ~MSR_DE; | |
143 | vcpu->arch.shadow_msr |= vcpu->arch.shared->msr & MSR_DE; | |
144 | #endif | |
145 | ||
146 | /* Force enable debug interrupts when user space wants to debug */ | |
147 | if (vcpu->guest_debug) { | |
148 | #ifdef CONFIG_KVM_BOOKE_HV | |
149 | /* | |
150 | * Since there is no shadow MSR, sync MSR_DE into the guest | |
151 | * visible MSR. | |
152 | */ | |
153 | vcpu->arch.shared->msr |= MSR_DE; | |
154 | #else | |
155 | vcpu->arch.shadow_msr |= MSR_DE; | |
156 | vcpu->arch.shared->msr &= ~MSR_DE; | |
157 | #endif | |
158 | } | |
159 | } | |
160 | ||
dd9ebf1f LY |
161 | /* |
162 | * Helper function for "full" MSR writes. No need to call this if only | |
163 | * EE/CE/ME/DE/RI are changing. | |
164 | */ | |
4cd35f67 SW |
165 | void kvmppc_set_msr(struct kvm_vcpu *vcpu, u32 new_msr) |
166 | { | |
dd9ebf1f | 167 | u32 old_msr = vcpu->arch.shared->msr; |
4cd35f67 | 168 | |
d30f6e48 SW |
169 | #ifdef CONFIG_KVM_BOOKE_HV |
170 | new_msr |= MSR_GS; | |
171 | #endif | |
172 | ||
4cd35f67 SW |
173 | vcpu->arch.shared->msr = new_msr; |
174 | ||
dd9ebf1f | 175 | kvmppc_mmu_msr_notify(vcpu, old_msr); |
4cd35f67 | 176 | kvmppc_vcpu_sync_spe(vcpu); |
7a08c274 | 177 | kvmppc_vcpu_sync_fpu(vcpu); |
ce11e48b | 178 | kvmppc_vcpu_sync_debug(vcpu); |
4cd35f67 SW |
179 | } |
180 | ||
d4cf3892 HB |
181 | static void kvmppc_booke_queue_irqprio(struct kvm_vcpu *vcpu, |
182 | unsigned int priority) | |
9dd921cf | 183 | { |
6346046c | 184 | trace_kvm_booke_queue_irqprio(vcpu, priority); |
9dd921cf HB |
185 | set_bit(priority, &vcpu->arch.pending_exceptions); |
186 | } | |
187 | ||
daf5e271 LY |
188 | static void kvmppc_core_queue_dtlb_miss(struct kvm_vcpu *vcpu, |
189 | ulong dear_flags, ulong esr_flags) | |
9dd921cf | 190 | { |
daf5e271 LY |
191 | vcpu->arch.queued_dear = dear_flags; |
192 | vcpu->arch.queued_esr = esr_flags; | |
193 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DTLB_MISS); | |
194 | } | |
195 | ||
196 | static void kvmppc_core_queue_data_storage(struct kvm_vcpu *vcpu, | |
197 | ulong dear_flags, ulong esr_flags) | |
198 | { | |
199 | vcpu->arch.queued_dear = dear_flags; | |
200 | vcpu->arch.queued_esr = esr_flags; | |
201 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DATA_STORAGE); | |
202 | } | |
203 | ||
204 | static void kvmppc_core_queue_inst_storage(struct kvm_vcpu *vcpu, | |
205 | ulong esr_flags) | |
206 | { | |
207 | vcpu->arch.queued_esr = esr_flags; | |
208 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_INST_STORAGE); | |
209 | } | |
210 | ||
011da899 AG |
211 | static void kvmppc_core_queue_alignment(struct kvm_vcpu *vcpu, ulong dear_flags, |
212 | ulong esr_flags) | |
213 | { | |
214 | vcpu->arch.queued_dear = dear_flags; | |
215 | vcpu->arch.queued_esr = esr_flags; | |
216 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_ALIGNMENT); | |
217 | } | |
218 | ||
daf5e271 LY |
219 | void kvmppc_core_queue_program(struct kvm_vcpu *vcpu, ulong esr_flags) |
220 | { | |
221 | vcpu->arch.queued_esr = esr_flags; | |
d4cf3892 | 222 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_PROGRAM); |
9dd921cf HB |
223 | } |
224 | ||
225 | void kvmppc_core_queue_dec(struct kvm_vcpu *vcpu) | |
226 | { | |
d4cf3892 | 227 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DECREMENTER); |
9dd921cf HB |
228 | } |
229 | ||
230 | int kvmppc_core_pending_dec(struct kvm_vcpu *vcpu) | |
231 | { | |
d4cf3892 | 232 | return test_bit(BOOKE_IRQPRIO_DECREMENTER, &vcpu->arch.pending_exceptions); |
9dd921cf HB |
233 | } |
234 | ||
7706664d AG |
235 | void kvmppc_core_dequeue_dec(struct kvm_vcpu *vcpu) |
236 | { | |
237 | clear_bit(BOOKE_IRQPRIO_DECREMENTER, &vcpu->arch.pending_exceptions); | |
238 | } | |
239 | ||
9dd921cf HB |
240 | void kvmppc_core_queue_external(struct kvm_vcpu *vcpu, |
241 | struct kvm_interrupt *irq) | |
242 | { | |
c5335f17 AG |
243 | unsigned int prio = BOOKE_IRQPRIO_EXTERNAL; |
244 | ||
245 | if (irq->irq == KVM_INTERRUPT_SET_LEVEL) | |
246 | prio = BOOKE_IRQPRIO_EXTERNAL_LEVEL; | |
247 | ||
248 | kvmppc_booke_queue_irqprio(vcpu, prio); | |
9dd921cf HB |
249 | } |
250 | ||
4fe27d2a | 251 | void kvmppc_core_dequeue_external(struct kvm_vcpu *vcpu) |
4496f974 AG |
252 | { |
253 | clear_bit(BOOKE_IRQPRIO_EXTERNAL, &vcpu->arch.pending_exceptions); | |
c5335f17 | 254 | clear_bit(BOOKE_IRQPRIO_EXTERNAL_LEVEL, &vcpu->arch.pending_exceptions); |
4496f974 AG |
255 | } |
256 | ||
f61c94bb BB |
257 | static void kvmppc_core_queue_watchdog(struct kvm_vcpu *vcpu) |
258 | { | |
259 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_WATCHDOG); | |
260 | } | |
261 | ||
262 | static void kvmppc_core_dequeue_watchdog(struct kvm_vcpu *vcpu) | |
263 | { | |
264 | clear_bit(BOOKE_IRQPRIO_WATCHDOG, &vcpu->arch.pending_exceptions); | |
265 | } | |
266 | ||
d30f6e48 SW |
267 | static void set_guest_srr(struct kvm_vcpu *vcpu, unsigned long srr0, u32 srr1) |
268 | { | |
31579eea BB |
269 | kvmppc_set_srr0(vcpu, srr0); |
270 | kvmppc_set_srr1(vcpu, srr1); | |
d30f6e48 SW |
271 | } |
272 | ||
273 | static void set_guest_csrr(struct kvm_vcpu *vcpu, unsigned long srr0, u32 srr1) | |
274 | { | |
275 | vcpu->arch.csrr0 = srr0; | |
276 | vcpu->arch.csrr1 = srr1; | |
277 | } | |
278 | ||
279 | static void set_guest_dsrr(struct kvm_vcpu *vcpu, unsigned long srr0, u32 srr1) | |
280 | { | |
281 | if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC)) { | |
282 | vcpu->arch.dsrr0 = srr0; | |
283 | vcpu->arch.dsrr1 = srr1; | |
284 | } else { | |
285 | set_guest_csrr(vcpu, srr0, srr1); | |
286 | } | |
287 | } | |
288 | ||
289 | static void set_guest_mcsrr(struct kvm_vcpu *vcpu, unsigned long srr0, u32 srr1) | |
290 | { | |
291 | vcpu->arch.mcsrr0 = srr0; | |
292 | vcpu->arch.mcsrr1 = srr1; | |
293 | } | |
294 | ||
295 | static unsigned long get_guest_dear(struct kvm_vcpu *vcpu) | |
296 | { | |
297 | #ifdef CONFIG_KVM_BOOKE_HV | |
298 | return mfspr(SPRN_GDEAR); | |
299 | #else | |
300 | return vcpu->arch.shared->dar; | |
301 | #endif | |
302 | } | |
303 | ||
304 | static void set_guest_dear(struct kvm_vcpu *vcpu, unsigned long dear) | |
305 | { | |
306 | #ifdef CONFIG_KVM_BOOKE_HV | |
307 | mtspr(SPRN_GDEAR, dear); | |
308 | #else | |
309 | vcpu->arch.shared->dar = dear; | |
310 | #endif | |
311 | } | |
312 | ||
313 | static unsigned long get_guest_esr(struct kvm_vcpu *vcpu) | |
314 | { | |
315 | #ifdef CONFIG_KVM_BOOKE_HV | |
316 | return mfspr(SPRN_GESR); | |
317 | #else | |
318 | return vcpu->arch.shared->esr; | |
319 | #endif | |
320 | } | |
321 | ||
322 | static void set_guest_esr(struct kvm_vcpu *vcpu, u32 esr) | |
323 | { | |
324 | #ifdef CONFIG_KVM_BOOKE_HV | |
325 | mtspr(SPRN_GESR, esr); | |
326 | #else | |
327 | vcpu->arch.shared->esr = esr; | |
328 | #endif | |
329 | } | |
330 | ||
324b3e63 AG |
331 | static unsigned long get_guest_epr(struct kvm_vcpu *vcpu) |
332 | { | |
333 | #ifdef CONFIG_KVM_BOOKE_HV | |
334 | return mfspr(SPRN_GEPR); | |
335 | #else | |
336 | return vcpu->arch.epr; | |
337 | #endif | |
338 | } | |
339 | ||
d4cf3892 HB |
340 | /* Deliver the interrupt of the corresponding priority, if possible. */ |
341 | static int kvmppc_booke_irqprio_deliver(struct kvm_vcpu *vcpu, | |
342 | unsigned int priority) | |
bbf45ba5 | 343 | { |
d4cf3892 | 344 | int allowed = 0; |
79300f8c | 345 | ulong msr_mask = 0; |
1c810636 | 346 | bool update_esr = false, update_dear = false, update_epr = false; |
5c6cedf4 AG |
347 | ulong crit_raw = vcpu->arch.shared->critical; |
348 | ulong crit_r1 = kvmppc_get_gpr(vcpu, 1); | |
349 | bool crit; | |
c5335f17 | 350 | bool keep_irq = false; |
d30f6e48 | 351 | enum int_class int_class; |
95e90b43 | 352 | ulong new_msr = vcpu->arch.shared->msr; |
5c6cedf4 AG |
353 | |
354 | /* Truncate crit indicators in 32 bit mode */ | |
355 | if (!(vcpu->arch.shared->msr & MSR_SF)) { | |
356 | crit_raw &= 0xffffffff; | |
357 | crit_r1 &= 0xffffffff; | |
358 | } | |
359 | ||
360 | /* Critical section when crit == r1 */ | |
361 | crit = (crit_raw == crit_r1); | |
362 | /* ... and we're in supervisor mode */ | |
363 | crit = crit && !(vcpu->arch.shared->msr & MSR_PR); | |
d4cf3892 | 364 | |
c5335f17 AG |
365 | if (priority == BOOKE_IRQPRIO_EXTERNAL_LEVEL) { |
366 | priority = BOOKE_IRQPRIO_EXTERNAL; | |
367 | keep_irq = true; | |
368 | } | |
369 | ||
5df554ad | 370 | if ((priority == BOOKE_IRQPRIO_EXTERNAL) && vcpu->arch.epr_flags) |
1c810636 AG |
371 | update_epr = true; |
372 | ||
d4cf3892 | 373 | switch (priority) { |
d4cf3892 | 374 | case BOOKE_IRQPRIO_DTLB_MISS: |
d4cf3892 | 375 | case BOOKE_IRQPRIO_DATA_STORAGE: |
011da899 | 376 | case BOOKE_IRQPRIO_ALIGNMENT: |
daf5e271 LY |
377 | update_dear = true; |
378 | /* fall through */ | |
d4cf3892 | 379 | case BOOKE_IRQPRIO_INST_STORAGE: |
daf5e271 LY |
380 | case BOOKE_IRQPRIO_PROGRAM: |
381 | update_esr = true; | |
382 | /* fall through */ | |
383 | case BOOKE_IRQPRIO_ITLB_MISS: | |
384 | case BOOKE_IRQPRIO_SYSCALL: | |
d4cf3892 | 385 | case BOOKE_IRQPRIO_FP_UNAVAIL: |
bb3a8a17 HB |
386 | case BOOKE_IRQPRIO_SPE_UNAVAIL: |
387 | case BOOKE_IRQPRIO_SPE_FP_DATA: | |
388 | case BOOKE_IRQPRIO_SPE_FP_ROUND: | |
d4cf3892 | 389 | case BOOKE_IRQPRIO_AP_UNAVAIL: |
d4cf3892 | 390 | allowed = 1; |
79300f8c | 391 | msr_mask = MSR_CE | MSR_ME | MSR_DE; |
d30f6e48 | 392 | int_class = INT_CLASS_NONCRIT; |
bbf45ba5 | 393 | break; |
f61c94bb | 394 | case BOOKE_IRQPRIO_WATCHDOG: |
d4cf3892 | 395 | case BOOKE_IRQPRIO_CRITICAL: |
4ab96919 | 396 | case BOOKE_IRQPRIO_DBELL_CRIT: |
666e7252 | 397 | allowed = vcpu->arch.shared->msr & MSR_CE; |
d30f6e48 | 398 | allowed = allowed && !crit; |
79300f8c | 399 | msr_mask = MSR_ME; |
d30f6e48 | 400 | int_class = INT_CLASS_CRIT; |
bbf45ba5 | 401 | break; |
d4cf3892 | 402 | case BOOKE_IRQPRIO_MACHINE_CHECK: |
666e7252 | 403 | allowed = vcpu->arch.shared->msr & MSR_ME; |
d30f6e48 | 404 | allowed = allowed && !crit; |
d30f6e48 | 405 | int_class = INT_CLASS_MC; |
bbf45ba5 | 406 | break; |
d4cf3892 HB |
407 | case BOOKE_IRQPRIO_DECREMENTER: |
408 | case BOOKE_IRQPRIO_FIT: | |
dfd4d47e SW |
409 | keep_irq = true; |
410 | /* fall through */ | |
411 | case BOOKE_IRQPRIO_EXTERNAL: | |
4ab96919 | 412 | case BOOKE_IRQPRIO_DBELL: |
666e7252 | 413 | allowed = vcpu->arch.shared->msr & MSR_EE; |
5c6cedf4 | 414 | allowed = allowed && !crit; |
79300f8c | 415 | msr_mask = MSR_CE | MSR_ME | MSR_DE; |
d30f6e48 | 416 | int_class = INT_CLASS_NONCRIT; |
bbf45ba5 | 417 | break; |
d4cf3892 | 418 | case BOOKE_IRQPRIO_DEBUG: |
666e7252 | 419 | allowed = vcpu->arch.shared->msr & MSR_DE; |
d30f6e48 | 420 | allowed = allowed && !crit; |
79300f8c | 421 | msr_mask = MSR_ME; |
d30f6e48 | 422 | int_class = INT_CLASS_CRIT; |
bbf45ba5 | 423 | break; |
bbf45ba5 HB |
424 | } |
425 | ||
d4cf3892 | 426 | if (allowed) { |
d30f6e48 SW |
427 | switch (int_class) { |
428 | case INT_CLASS_NONCRIT: | |
429 | set_guest_srr(vcpu, vcpu->arch.pc, | |
430 | vcpu->arch.shared->msr); | |
431 | break; | |
432 | case INT_CLASS_CRIT: | |
433 | set_guest_csrr(vcpu, vcpu->arch.pc, | |
434 | vcpu->arch.shared->msr); | |
435 | break; | |
436 | case INT_CLASS_DBG: | |
437 | set_guest_dsrr(vcpu, vcpu->arch.pc, | |
438 | vcpu->arch.shared->msr); | |
439 | break; | |
440 | case INT_CLASS_MC: | |
441 | set_guest_mcsrr(vcpu, vcpu->arch.pc, | |
442 | vcpu->arch.shared->msr); | |
443 | break; | |
444 | } | |
445 | ||
d4cf3892 | 446 | vcpu->arch.pc = vcpu->arch.ivpr | vcpu->arch.ivor[priority]; |
daf5e271 | 447 | if (update_esr == true) |
d30f6e48 | 448 | set_guest_esr(vcpu, vcpu->arch.queued_esr); |
daf5e271 | 449 | if (update_dear == true) |
d30f6e48 | 450 | set_guest_dear(vcpu, vcpu->arch.queued_dear); |
5df554ad SW |
451 | if (update_epr == true) { |
452 | if (vcpu->arch.epr_flags & KVMPPC_EPR_USER) | |
453 | kvm_make_request(KVM_REQ_EPR_EXIT, vcpu); | |
eb1e4f43 SW |
454 | else if (vcpu->arch.epr_flags & KVMPPC_EPR_KERNEL) { |
455 | BUG_ON(vcpu->arch.irq_type != KVMPPC_IRQ_MPIC); | |
456 | kvmppc_mpic_set_epr(vcpu); | |
457 | } | |
5df554ad | 458 | } |
95e90b43 MC |
459 | |
460 | new_msr &= msr_mask; | |
461 | #if defined(CONFIG_64BIT) | |
462 | if (vcpu->arch.epcr & SPRN_EPCR_ICM) | |
463 | new_msr |= MSR_CM; | |
464 | #endif | |
465 | kvmppc_set_msr(vcpu, new_msr); | |
bbf45ba5 | 466 | |
c5335f17 AG |
467 | if (!keep_irq) |
468 | clear_bit(priority, &vcpu->arch.pending_exceptions); | |
bbf45ba5 HB |
469 | } |
470 | ||
d30f6e48 SW |
471 | #ifdef CONFIG_KVM_BOOKE_HV |
472 | /* | |
473 | * If an interrupt is pending but masked, raise a guest doorbell | |
474 | * so that we are notified when the guest enables the relevant | |
475 | * MSR bit. | |
476 | */ | |
477 | if (vcpu->arch.pending_exceptions & BOOKE_IRQMASK_EE) | |
478 | kvmppc_set_pending_interrupt(vcpu, INT_CLASS_NONCRIT); | |
479 | if (vcpu->arch.pending_exceptions & BOOKE_IRQMASK_CE) | |
480 | kvmppc_set_pending_interrupt(vcpu, INT_CLASS_CRIT); | |
481 | if (vcpu->arch.pending_exceptions & BOOKE_IRQPRIO_MACHINE_CHECK) | |
482 | kvmppc_set_pending_interrupt(vcpu, INT_CLASS_MC); | |
483 | #endif | |
484 | ||
d4cf3892 | 485 | return allowed; |
bbf45ba5 HB |
486 | } |
487 | ||
f61c94bb BB |
488 | /* |
489 | * Return the number of jiffies until the next timeout. If the timeout is | |
490 | * longer than the NEXT_TIMER_MAX_DELTA, then return NEXT_TIMER_MAX_DELTA | |
491 | * because the larger value can break the timer APIs. | |
492 | */ | |
493 | static unsigned long watchdog_next_timeout(struct kvm_vcpu *vcpu) | |
494 | { | |
495 | u64 tb, wdt_tb, wdt_ticks = 0; | |
496 | u64 nr_jiffies = 0; | |
497 | u32 period = TCR_GET_WP(vcpu->arch.tcr); | |
498 | ||
499 | wdt_tb = 1ULL << (63 - period); | |
500 | tb = get_tb(); | |
501 | /* | |
502 | * The watchdog timeout will hapeen when TB bit corresponding | |
503 | * to watchdog will toggle from 0 to 1. | |
504 | */ | |
505 | if (tb & wdt_tb) | |
506 | wdt_ticks = wdt_tb; | |
507 | ||
508 | wdt_ticks += wdt_tb - (tb & (wdt_tb - 1)); | |
509 | ||
510 | /* Convert timebase ticks to jiffies */ | |
511 | nr_jiffies = wdt_ticks; | |
512 | ||
513 | if (do_div(nr_jiffies, tb_ticks_per_jiffy)) | |
514 | nr_jiffies++; | |
515 | ||
516 | return min_t(unsigned long long, nr_jiffies, NEXT_TIMER_MAX_DELTA); | |
517 | } | |
518 | ||
519 | static void arm_next_watchdog(struct kvm_vcpu *vcpu) | |
520 | { | |
521 | unsigned long nr_jiffies; | |
522 | unsigned long flags; | |
523 | ||
524 | /* | |
525 | * If TSR_ENW and TSR_WIS are not set then no need to exit to | |
526 | * userspace, so clear the KVM_REQ_WATCHDOG request. | |
527 | */ | |
528 | if ((vcpu->arch.tsr & (TSR_ENW | TSR_WIS)) != (TSR_ENW | TSR_WIS)) | |
529 | clear_bit(KVM_REQ_WATCHDOG, &vcpu->requests); | |
530 | ||
531 | spin_lock_irqsave(&vcpu->arch.wdt_lock, flags); | |
532 | nr_jiffies = watchdog_next_timeout(vcpu); | |
533 | /* | |
534 | * If the number of jiffies of watchdog timer >= NEXT_TIMER_MAX_DELTA | |
535 | * then do not run the watchdog timer as this can break timer APIs. | |
536 | */ | |
537 | if (nr_jiffies < NEXT_TIMER_MAX_DELTA) | |
538 | mod_timer(&vcpu->arch.wdt_timer, jiffies + nr_jiffies); | |
539 | else | |
540 | del_timer(&vcpu->arch.wdt_timer); | |
541 | spin_unlock_irqrestore(&vcpu->arch.wdt_lock, flags); | |
542 | } | |
543 | ||
544 | void kvmppc_watchdog_func(unsigned long data) | |
545 | { | |
546 | struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data; | |
547 | u32 tsr, new_tsr; | |
548 | int final; | |
549 | ||
550 | do { | |
551 | new_tsr = tsr = vcpu->arch.tsr; | |
552 | final = 0; | |
553 | ||
554 | /* Time out event */ | |
555 | if (tsr & TSR_ENW) { | |
556 | if (tsr & TSR_WIS) | |
557 | final = 1; | |
558 | else | |
559 | new_tsr = tsr | TSR_WIS; | |
560 | } else { | |
561 | new_tsr = tsr | TSR_ENW; | |
562 | } | |
563 | } while (cmpxchg(&vcpu->arch.tsr, tsr, new_tsr) != tsr); | |
564 | ||
565 | if (new_tsr & TSR_WIS) { | |
566 | smp_wmb(); | |
567 | kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); | |
568 | kvm_vcpu_kick(vcpu); | |
569 | } | |
570 | ||
571 | /* | |
572 | * If this is final watchdog expiry and some action is required | |
573 | * then exit to userspace. | |
574 | */ | |
575 | if (final && (vcpu->arch.tcr & TCR_WRC_MASK) && | |
576 | vcpu->arch.watchdog_enabled) { | |
577 | smp_wmb(); | |
578 | kvm_make_request(KVM_REQ_WATCHDOG, vcpu); | |
579 | kvm_vcpu_kick(vcpu); | |
580 | } | |
581 | ||
582 | /* | |
583 | * Stop running the watchdog timer after final expiration to | |
584 | * prevent the host from being flooded with timers if the | |
585 | * guest sets a short period. | |
586 | * Timers will resume when TSR/TCR is updated next time. | |
587 | */ | |
588 | if (!final) | |
589 | arm_next_watchdog(vcpu); | |
590 | } | |
591 | ||
dfd4d47e SW |
592 | static void update_timer_ints(struct kvm_vcpu *vcpu) |
593 | { | |
594 | if ((vcpu->arch.tcr & TCR_DIE) && (vcpu->arch.tsr & TSR_DIS)) | |
595 | kvmppc_core_queue_dec(vcpu); | |
596 | else | |
597 | kvmppc_core_dequeue_dec(vcpu); | |
f61c94bb BB |
598 | |
599 | if ((vcpu->arch.tcr & TCR_WIE) && (vcpu->arch.tsr & TSR_WIS)) | |
600 | kvmppc_core_queue_watchdog(vcpu); | |
601 | else | |
602 | kvmppc_core_dequeue_watchdog(vcpu); | |
dfd4d47e SW |
603 | } |
604 | ||
c59a6a3e | 605 | static void kvmppc_core_check_exceptions(struct kvm_vcpu *vcpu) |
bbf45ba5 HB |
606 | { |
607 | unsigned long *pending = &vcpu->arch.pending_exceptions; | |
bbf45ba5 HB |
608 | unsigned int priority; |
609 | ||
9ab80843 | 610 | priority = __ffs(*pending); |
8b3a00fc | 611 | while (priority < BOOKE_IRQPRIO_MAX) { |
d4cf3892 | 612 | if (kvmppc_booke_irqprio_deliver(vcpu, priority)) |
bbf45ba5 | 613 | break; |
bbf45ba5 HB |
614 | |
615 | priority = find_next_bit(pending, | |
616 | BITS_PER_BYTE * sizeof(*pending), | |
617 | priority + 1); | |
618 | } | |
90bba358 AG |
619 | |
620 | /* Tell the guest about our interrupt status */ | |
29ac26ef | 621 | vcpu->arch.shared->int_pending = !!*pending; |
bbf45ba5 HB |
622 | } |
623 | ||
c59a6a3e | 624 | /* Check pending exceptions and deliver one, if possible. */ |
a8e4ef84 | 625 | int kvmppc_core_prepare_to_enter(struct kvm_vcpu *vcpu) |
c59a6a3e | 626 | { |
a8e4ef84 | 627 | int r = 0; |
c59a6a3e SW |
628 | WARN_ON_ONCE(!irqs_disabled()); |
629 | ||
630 | kvmppc_core_check_exceptions(vcpu); | |
631 | ||
b8c649a9 AG |
632 | if (vcpu->requests) { |
633 | /* Exception delivery raised request; start over */ | |
634 | return 1; | |
635 | } | |
636 | ||
c59a6a3e SW |
637 | if (vcpu->arch.shared->msr & MSR_WE) { |
638 | local_irq_enable(); | |
639 | kvm_vcpu_block(vcpu); | |
966cd0f3 | 640 | clear_bit(KVM_REQ_UNHALT, &vcpu->requests); |
6c85f52b | 641 | hard_irq_disable(); |
c59a6a3e SW |
642 | |
643 | kvmppc_set_exit_type(vcpu, EMULATED_MTMSRWE_EXITS); | |
a8e4ef84 | 644 | r = 1; |
c59a6a3e | 645 | }; |
a8e4ef84 AG |
646 | |
647 | return r; | |
648 | } | |
649 | ||
7c973a2e | 650 | int kvmppc_core_check_requests(struct kvm_vcpu *vcpu) |
4ffc6356 | 651 | { |
7c973a2e AG |
652 | int r = 1; /* Indicate we want to get back into the guest */ |
653 | ||
2d8185d4 AG |
654 | if (kvm_check_request(KVM_REQ_PENDING_TIMER, vcpu)) |
655 | update_timer_ints(vcpu); | |
862d31f7 | 656 | #if defined(CONFIG_KVM_E500V2) || defined(CONFIG_KVM_E500MC) |
2d8185d4 AG |
657 | if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) |
658 | kvmppc_core_flush_tlb(vcpu); | |
862d31f7 | 659 | #endif |
7c973a2e | 660 | |
f61c94bb BB |
661 | if (kvm_check_request(KVM_REQ_WATCHDOG, vcpu)) { |
662 | vcpu->run->exit_reason = KVM_EXIT_WATCHDOG; | |
663 | r = 0; | |
664 | } | |
665 | ||
1c810636 AG |
666 | if (kvm_check_request(KVM_REQ_EPR_EXIT, vcpu)) { |
667 | vcpu->run->epr.epr = 0; | |
668 | vcpu->arch.epr_needed = true; | |
669 | vcpu->run->exit_reason = KVM_EXIT_EPR; | |
670 | r = 0; | |
671 | } | |
672 | ||
7c973a2e | 673 | return r; |
4ffc6356 AG |
674 | } |
675 | ||
df6909e5 PM |
676 | int kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu) |
677 | { | |
7ee78855 | 678 | int ret, s; |
f5f97210 | 679 | struct debug_reg debug; |
df6909e5 | 680 | |
af8f38b3 AG |
681 | if (!vcpu->arch.sane) { |
682 | kvm_run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
683 | return -EINVAL; | |
684 | } | |
685 | ||
7ee78855 AG |
686 | s = kvmppc_prepare_to_enter(vcpu); |
687 | if (s <= 0) { | |
7ee78855 | 688 | ret = s; |
1d1ef222 SW |
689 | goto out; |
690 | } | |
6c85f52b | 691 | /* interrupts now hard-disabled */ |
1d1ef222 | 692 | |
8fae845f SW |
693 | #ifdef CONFIG_PPC_FPU |
694 | /* Save userspace FPU state in stack */ | |
695 | enable_kernel_fp(); | |
8fae845f SW |
696 | |
697 | /* | |
698 | * Since we can't trap on MSR_FP in GS-mode, we consider the guest | |
699 | * as always using the FPU. Kernel usage of FP (via | |
700 | * enable_kernel_fp()) in this thread must not occur while | |
701 | * vcpu->fpu_active is set. | |
702 | */ | |
703 | vcpu->fpu_active = 1; | |
704 | ||
705 | kvmppc_load_guest_fp(vcpu); | |
706 | #endif | |
707 | ||
ce11e48b | 708 | /* Switch to guest debug context */ |
f5f97210 SW |
709 | debug = vcpu->arch.shadow_dbg_reg; |
710 | switch_booke_debug_regs(&debug); | |
711 | debug = current->thread.debug; | |
ce11e48b BB |
712 | current->thread.debug = vcpu->arch.shadow_dbg_reg; |
713 | ||
08c9a188 | 714 | vcpu->arch.pgdir = current->mm->pgd; |
5f1c248f | 715 | kvmppc_fix_ee_before_entry(); |
f8941fbe | 716 | |
df6909e5 | 717 | ret = __kvmppc_vcpu_run(kvm_run, vcpu); |
8fae845f | 718 | |
24afa37b AG |
719 | /* No need for kvm_guest_exit. It's done in handle_exit. |
720 | We also get here with interrupts enabled. */ | |
721 | ||
ce11e48b | 722 | /* Switch back to user space debug context */ |
f5f97210 SW |
723 | switch_booke_debug_regs(&debug); |
724 | current->thread.debug = debug; | |
ce11e48b | 725 | |
8fae845f SW |
726 | #ifdef CONFIG_PPC_FPU |
727 | kvmppc_save_guest_fp(vcpu); | |
728 | ||
729 | vcpu->fpu_active = 0; | |
8fae845f SW |
730 | #endif |
731 | ||
1d1ef222 | 732 | out: |
d69c6436 | 733 | vcpu->mode = OUTSIDE_GUEST_MODE; |
df6909e5 PM |
734 | return ret; |
735 | } | |
736 | ||
d30f6e48 SW |
737 | static int emulation_exit(struct kvm_run *run, struct kvm_vcpu *vcpu) |
738 | { | |
739 | enum emulation_result er; | |
740 | ||
741 | er = kvmppc_emulate_instruction(run, vcpu); | |
742 | switch (er) { | |
743 | case EMULATE_DONE: | |
744 | /* don't overwrite subtypes, just account kvm_stats */ | |
745 | kvmppc_account_exit_stat(vcpu, EMULATED_INST_EXITS); | |
746 | /* Future optimization: only reload non-volatiles if | |
747 | * they were actually modified by emulation. */ | |
748 | return RESUME_GUEST_NV; | |
749 | ||
750 | case EMULATE_DO_DCR: | |
751 | run->exit_reason = KVM_EXIT_DCR; | |
752 | return RESUME_HOST; | |
753 | ||
754 | case EMULATE_FAIL: | |
d30f6e48 SW |
755 | printk(KERN_CRIT "%s: emulation at %lx failed (%08x)\n", |
756 | __func__, vcpu->arch.pc, vcpu->arch.last_inst); | |
757 | /* For debugging, encode the failing instruction and | |
758 | * report it to userspace. */ | |
759 | run->hw.hardware_exit_reason = ~0ULL << 32; | |
760 | run->hw.hardware_exit_reason |= vcpu->arch.last_inst; | |
d1ff5499 | 761 | kvmppc_core_queue_program(vcpu, ESR_PIL); |
d30f6e48 SW |
762 | return RESUME_HOST; |
763 | ||
9b4f5308 BB |
764 | case EMULATE_EXIT_USER: |
765 | return RESUME_HOST; | |
766 | ||
d30f6e48 SW |
767 | default: |
768 | BUG(); | |
769 | } | |
770 | } | |
771 | ||
ce11e48b BB |
772 | static int kvmppc_handle_debug(struct kvm_run *run, struct kvm_vcpu *vcpu) |
773 | { | |
774 | struct debug_reg *dbg_reg = &(vcpu->arch.shadow_dbg_reg); | |
775 | u32 dbsr = vcpu->arch.dbsr; | |
776 | ||
777 | run->debug.arch.status = 0; | |
778 | run->debug.arch.address = vcpu->arch.pc; | |
779 | ||
780 | if (dbsr & (DBSR_IAC1 | DBSR_IAC2 | DBSR_IAC3 | DBSR_IAC4)) { | |
781 | run->debug.arch.status |= KVMPPC_DEBUG_BREAKPOINT; | |
782 | } else { | |
783 | if (dbsr & (DBSR_DAC1W | DBSR_DAC2W)) | |
784 | run->debug.arch.status |= KVMPPC_DEBUG_WATCH_WRITE; | |
785 | else if (dbsr & (DBSR_DAC1R | DBSR_DAC2R)) | |
786 | run->debug.arch.status |= KVMPPC_DEBUG_WATCH_READ; | |
787 | if (dbsr & (DBSR_DAC1R | DBSR_DAC1W)) | |
788 | run->debug.arch.address = dbg_reg->dac1; | |
789 | else if (dbsr & (DBSR_DAC2R | DBSR_DAC2W)) | |
790 | run->debug.arch.address = dbg_reg->dac2; | |
791 | } | |
792 | ||
793 | return RESUME_HOST; | |
794 | } | |
795 | ||
4e642ccb | 796 | static void kvmppc_fill_pt_regs(struct pt_regs *regs) |
bbf45ba5 | 797 | { |
4e642ccb | 798 | ulong r1, ip, msr, lr; |
bbf45ba5 | 799 | |
4e642ccb AG |
800 | asm("mr %0, 1" : "=r"(r1)); |
801 | asm("mflr %0" : "=r"(lr)); | |
802 | asm("mfmsr %0" : "=r"(msr)); | |
803 | asm("bl 1f; 1: mflr %0" : "=r"(ip)); | |
804 | ||
805 | memset(regs, 0, sizeof(*regs)); | |
806 | regs->gpr[1] = r1; | |
807 | regs->nip = ip; | |
808 | regs->msr = msr; | |
809 | regs->link = lr; | |
810 | } | |
811 | ||
6328e593 BB |
812 | /* |
813 | * For interrupts needed to be handled by host interrupt handlers, | |
814 | * corresponding host handler are called from here in similar way | |
815 | * (but not exact) as they are called from low level handler | |
816 | * (such as from arch/powerpc/kernel/head_fsl_booke.S). | |
817 | */ | |
4e642ccb AG |
818 | static void kvmppc_restart_interrupt(struct kvm_vcpu *vcpu, |
819 | unsigned int exit_nr) | |
820 | { | |
821 | struct pt_regs regs; | |
73e75b41 | 822 | |
d30f6e48 SW |
823 | switch (exit_nr) { |
824 | case BOOKE_INTERRUPT_EXTERNAL: | |
4e642ccb AG |
825 | kvmppc_fill_pt_regs(®s); |
826 | do_IRQ(®s); | |
d30f6e48 | 827 | break; |
d30f6e48 | 828 | case BOOKE_INTERRUPT_DECREMENTER: |
4e642ccb AG |
829 | kvmppc_fill_pt_regs(®s); |
830 | timer_interrupt(®s); | |
d30f6e48 | 831 | break; |
5f17ce8b | 832 | #if defined(CONFIG_PPC_DOORBELL) |
d30f6e48 | 833 | case BOOKE_INTERRUPT_DOORBELL: |
4e642ccb AG |
834 | kvmppc_fill_pt_regs(®s); |
835 | doorbell_exception(®s); | |
d30f6e48 SW |
836 | break; |
837 | #endif | |
838 | case BOOKE_INTERRUPT_MACHINE_CHECK: | |
839 | /* FIXME */ | |
840 | break; | |
7cc1e8ee AG |
841 | case BOOKE_INTERRUPT_PERFORMANCE_MONITOR: |
842 | kvmppc_fill_pt_regs(®s); | |
843 | performance_monitor_exception(®s); | |
844 | break; | |
6328e593 BB |
845 | case BOOKE_INTERRUPT_WATCHDOG: |
846 | kvmppc_fill_pt_regs(®s); | |
847 | #ifdef CONFIG_BOOKE_WDT | |
848 | WatchdogException(®s); | |
849 | #else | |
850 | unknown_exception(®s); | |
851 | #endif | |
852 | break; | |
853 | case BOOKE_INTERRUPT_CRITICAL: | |
854 | unknown_exception(®s); | |
855 | break; | |
ce11e48b BB |
856 | case BOOKE_INTERRUPT_DEBUG: |
857 | /* Save DBSR before preemption is enabled */ | |
858 | vcpu->arch.dbsr = mfspr(SPRN_DBSR); | |
859 | kvmppc_clear_dbsr(); | |
860 | break; | |
d30f6e48 | 861 | } |
4e642ccb AG |
862 | } |
863 | ||
864 | /** | |
865 | * kvmppc_handle_exit | |
866 | * | |
867 | * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV) | |
868 | */ | |
869 | int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu, | |
870 | unsigned int exit_nr) | |
871 | { | |
872 | int r = RESUME_HOST; | |
7ee78855 | 873 | int s; |
f1e89028 | 874 | int idx; |
4e642ccb AG |
875 | |
876 | /* update before a new last_exit_type is rewritten */ | |
877 | kvmppc_update_timing_stats(vcpu); | |
878 | ||
879 | /* restart interrupts if they were meant for the host */ | |
880 | kvmppc_restart_interrupt(vcpu, exit_nr); | |
d30f6e48 | 881 | |
bbf45ba5 HB |
882 | local_irq_enable(); |
883 | ||
97c95059 | 884 | trace_kvm_exit(exit_nr, vcpu); |
706fb730 | 885 | kvm_guest_exit(); |
97c95059 | 886 | |
bbf45ba5 HB |
887 | run->exit_reason = KVM_EXIT_UNKNOWN; |
888 | run->ready_for_interrupt_injection = 1; | |
889 | ||
890 | switch (exit_nr) { | |
891 | case BOOKE_INTERRUPT_MACHINE_CHECK: | |
c35c9d84 AG |
892 | printk("MACHINE CHECK: %lx\n", mfspr(SPRN_MCSR)); |
893 | kvmppc_dump_vcpu(vcpu); | |
894 | /* For debugging, send invalid exit reason to user space */ | |
895 | run->hw.hardware_exit_reason = ~1ULL << 32; | |
896 | run->hw.hardware_exit_reason |= mfspr(SPRN_MCSR); | |
897 | r = RESUME_HOST; | |
bbf45ba5 HB |
898 | break; |
899 | ||
900 | case BOOKE_INTERRUPT_EXTERNAL: | |
7b701591 | 901 | kvmppc_account_exit(vcpu, EXT_INTR_EXITS); |
1b6766c7 HB |
902 | r = RESUME_GUEST; |
903 | break; | |
904 | ||
bbf45ba5 | 905 | case BOOKE_INTERRUPT_DECREMENTER: |
7b701591 | 906 | kvmppc_account_exit(vcpu, DEC_EXITS); |
bbf45ba5 HB |
907 | r = RESUME_GUEST; |
908 | break; | |
909 | ||
6328e593 BB |
910 | case BOOKE_INTERRUPT_WATCHDOG: |
911 | r = RESUME_GUEST; | |
912 | break; | |
913 | ||
d30f6e48 SW |
914 | case BOOKE_INTERRUPT_DOORBELL: |
915 | kvmppc_account_exit(vcpu, DBELL_EXITS); | |
d30f6e48 SW |
916 | r = RESUME_GUEST; |
917 | break; | |
918 | ||
919 | case BOOKE_INTERRUPT_GUEST_DBELL_CRIT: | |
920 | kvmppc_account_exit(vcpu, GDBELL_EXITS); | |
921 | ||
922 | /* | |
923 | * We are here because there is a pending guest interrupt | |
924 | * which could not be delivered as MSR_CE or MSR_ME was not | |
925 | * set. Once we break from here we will retry delivery. | |
926 | */ | |
927 | r = RESUME_GUEST; | |
928 | break; | |
929 | ||
930 | case BOOKE_INTERRUPT_GUEST_DBELL: | |
931 | kvmppc_account_exit(vcpu, GDBELL_EXITS); | |
932 | ||
933 | /* | |
934 | * We are here because there is a pending guest interrupt | |
935 | * which could not be delivered as MSR_EE was not set. Once | |
936 | * we break from here we will retry delivery. | |
937 | */ | |
938 | r = RESUME_GUEST; | |
939 | break; | |
940 | ||
95f2e921 AG |
941 | case BOOKE_INTERRUPT_PERFORMANCE_MONITOR: |
942 | r = RESUME_GUEST; | |
943 | break; | |
944 | ||
d30f6e48 SW |
945 | case BOOKE_INTERRUPT_HV_PRIV: |
946 | r = emulation_exit(run, vcpu); | |
947 | break; | |
948 | ||
bbf45ba5 | 949 | case BOOKE_INTERRUPT_PROGRAM: |
d30f6e48 | 950 | if (vcpu->arch.shared->msr & (MSR_PR | MSR_GS)) { |
0268597c AG |
951 | /* |
952 | * Program traps generated by user-level software must | |
953 | * be handled by the guest kernel. | |
954 | * | |
955 | * In GS mode, hypervisor privileged instructions trap | |
956 | * on BOOKE_INTERRUPT_HV_PRIV, not here, so these are | |
957 | * actual program interrupts, handled by the guest. | |
958 | */ | |
daf5e271 | 959 | kvmppc_core_queue_program(vcpu, vcpu->arch.fault_esr); |
bbf45ba5 | 960 | r = RESUME_GUEST; |
7b701591 | 961 | kvmppc_account_exit(vcpu, USR_PR_INST); |
bbf45ba5 HB |
962 | break; |
963 | } | |
964 | ||
d30f6e48 | 965 | r = emulation_exit(run, vcpu); |
bbf45ba5 HB |
966 | break; |
967 | ||
de368dce | 968 | case BOOKE_INTERRUPT_FP_UNAVAIL: |
d4cf3892 | 969 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_FP_UNAVAIL); |
7b701591 | 970 | kvmppc_account_exit(vcpu, FP_UNAVAIL); |
de368dce CE |
971 | r = RESUME_GUEST; |
972 | break; | |
973 | ||
4cd35f67 SW |
974 | #ifdef CONFIG_SPE |
975 | case BOOKE_INTERRUPT_SPE_UNAVAIL: { | |
976 | if (vcpu->arch.shared->msr & MSR_SPE) | |
977 | kvmppc_vcpu_enable_spe(vcpu); | |
978 | else | |
979 | kvmppc_booke_queue_irqprio(vcpu, | |
980 | BOOKE_IRQPRIO_SPE_UNAVAIL); | |
bb3a8a17 HB |
981 | r = RESUME_GUEST; |
982 | break; | |
4cd35f67 | 983 | } |
bb3a8a17 HB |
984 | |
985 | case BOOKE_INTERRUPT_SPE_FP_DATA: | |
986 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_SPE_FP_DATA); | |
987 | r = RESUME_GUEST; | |
988 | break; | |
989 | ||
990 | case BOOKE_INTERRUPT_SPE_FP_ROUND: | |
991 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_SPE_FP_ROUND); | |
992 | r = RESUME_GUEST; | |
993 | break; | |
4cd35f67 SW |
994 | #else |
995 | case BOOKE_INTERRUPT_SPE_UNAVAIL: | |
996 | /* | |
997 | * Guest wants SPE, but host kernel doesn't support it. Send | |
998 | * an "unimplemented operation" program check to the guest. | |
999 | */ | |
1000 | kvmppc_core_queue_program(vcpu, ESR_PUO | ESR_SPV); | |
1001 | r = RESUME_GUEST; | |
1002 | break; | |
1003 | ||
1004 | /* | |
1005 | * These really should never happen without CONFIG_SPE, | |
1006 | * as we should never enable the real MSR[SPE] in the guest. | |
1007 | */ | |
1008 | case BOOKE_INTERRUPT_SPE_FP_DATA: | |
1009 | case BOOKE_INTERRUPT_SPE_FP_ROUND: | |
1010 | printk(KERN_CRIT "%s: unexpected SPE interrupt %u at %08lx\n", | |
1011 | __func__, exit_nr, vcpu->arch.pc); | |
1012 | run->hw.hardware_exit_reason = exit_nr; | |
1013 | r = RESUME_HOST; | |
1014 | break; | |
1015 | #endif | |
bb3a8a17 | 1016 | |
bbf45ba5 | 1017 | case BOOKE_INTERRUPT_DATA_STORAGE: |
daf5e271 LY |
1018 | kvmppc_core_queue_data_storage(vcpu, vcpu->arch.fault_dear, |
1019 | vcpu->arch.fault_esr); | |
7b701591 | 1020 | kvmppc_account_exit(vcpu, DSI_EXITS); |
bbf45ba5 HB |
1021 | r = RESUME_GUEST; |
1022 | break; | |
1023 | ||
1024 | case BOOKE_INTERRUPT_INST_STORAGE: | |
daf5e271 | 1025 | kvmppc_core_queue_inst_storage(vcpu, vcpu->arch.fault_esr); |
7b701591 | 1026 | kvmppc_account_exit(vcpu, ISI_EXITS); |
bbf45ba5 HB |
1027 | r = RESUME_GUEST; |
1028 | break; | |
1029 | ||
011da899 AG |
1030 | case BOOKE_INTERRUPT_ALIGNMENT: |
1031 | kvmppc_core_queue_alignment(vcpu, vcpu->arch.fault_dear, | |
1032 | vcpu->arch.fault_esr); | |
1033 | r = RESUME_GUEST; | |
1034 | break; | |
1035 | ||
d30f6e48 SW |
1036 | #ifdef CONFIG_KVM_BOOKE_HV |
1037 | case BOOKE_INTERRUPT_HV_SYSCALL: | |
1038 | if (!(vcpu->arch.shared->msr & MSR_PR)) { | |
1039 | kvmppc_set_gpr(vcpu, 3, kvmppc_kvm_pv(vcpu)); | |
1040 | } else { | |
1041 | /* | |
1042 | * hcall from guest userspace -- send privileged | |
1043 | * instruction program check. | |
1044 | */ | |
1045 | kvmppc_core_queue_program(vcpu, ESR_PPR); | |
1046 | } | |
1047 | ||
1048 | r = RESUME_GUEST; | |
1049 | break; | |
1050 | #else | |
bbf45ba5 | 1051 | case BOOKE_INTERRUPT_SYSCALL: |
2a342ed5 AG |
1052 | if (!(vcpu->arch.shared->msr & MSR_PR) && |
1053 | (((u32)kvmppc_get_gpr(vcpu, 0)) == KVM_SC_MAGIC_R0)) { | |
1054 | /* KVM PV hypercalls */ | |
1055 | kvmppc_set_gpr(vcpu, 3, kvmppc_kvm_pv(vcpu)); | |
1056 | r = RESUME_GUEST; | |
1057 | } else { | |
1058 | /* Guest syscalls */ | |
1059 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_SYSCALL); | |
1060 | } | |
7b701591 | 1061 | kvmppc_account_exit(vcpu, SYSCALL_EXITS); |
bbf45ba5 HB |
1062 | r = RESUME_GUEST; |
1063 | break; | |
d30f6e48 | 1064 | #endif |
bbf45ba5 HB |
1065 | |
1066 | case BOOKE_INTERRUPT_DTLB_MISS: { | |
bbf45ba5 | 1067 | unsigned long eaddr = vcpu->arch.fault_dear; |
7924bd41 | 1068 | int gtlb_index; |
475e7cdd | 1069 | gpa_t gpaddr; |
bbf45ba5 HB |
1070 | gfn_t gfn; |
1071 | ||
bf7ca4bd | 1072 | #ifdef CONFIG_KVM_E500V2 |
a4cd8b23 SW |
1073 | if (!(vcpu->arch.shared->msr & MSR_PR) && |
1074 | (eaddr & PAGE_MASK) == vcpu->arch.magic_page_ea) { | |
1075 | kvmppc_map_magic(vcpu); | |
1076 | kvmppc_account_exit(vcpu, DTLB_VIRT_MISS_EXITS); | |
1077 | r = RESUME_GUEST; | |
1078 | ||
1079 | break; | |
1080 | } | |
1081 | #endif | |
1082 | ||
bbf45ba5 | 1083 | /* Check the guest TLB. */ |
fa86b8dd | 1084 | gtlb_index = kvmppc_mmu_dtlb_index(vcpu, eaddr); |
7924bd41 | 1085 | if (gtlb_index < 0) { |
bbf45ba5 | 1086 | /* The guest didn't have a mapping for it. */ |
daf5e271 LY |
1087 | kvmppc_core_queue_dtlb_miss(vcpu, |
1088 | vcpu->arch.fault_dear, | |
1089 | vcpu->arch.fault_esr); | |
b52a638c | 1090 | kvmppc_mmu_dtlb_miss(vcpu); |
7b701591 | 1091 | kvmppc_account_exit(vcpu, DTLB_REAL_MISS_EXITS); |
bbf45ba5 HB |
1092 | r = RESUME_GUEST; |
1093 | break; | |
1094 | } | |
1095 | ||
f1e89028 SW |
1096 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
1097 | ||
be8d1cae | 1098 | gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr); |
475e7cdd | 1099 | gfn = gpaddr >> PAGE_SHIFT; |
bbf45ba5 HB |
1100 | |
1101 | if (kvm_is_visible_gfn(vcpu->kvm, gfn)) { | |
1102 | /* The guest TLB had a mapping, but the shadow TLB | |
1103 | * didn't, and it is RAM. This could be because: | |
1104 | * a) the entry is mapping the host kernel, or | |
1105 | * b) the guest used a large mapping which we're faking | |
1106 | * Either way, we need to satisfy the fault without | |
1107 | * invoking the guest. */ | |
58a96214 | 1108 | kvmppc_mmu_map(vcpu, eaddr, gpaddr, gtlb_index); |
7b701591 | 1109 | kvmppc_account_exit(vcpu, DTLB_VIRT_MISS_EXITS); |
bbf45ba5 HB |
1110 | r = RESUME_GUEST; |
1111 | } else { | |
1112 | /* Guest has mapped and accessed a page which is not | |
1113 | * actually RAM. */ | |
475e7cdd | 1114 | vcpu->arch.paddr_accessed = gpaddr; |
6020c0f6 | 1115 | vcpu->arch.vaddr_accessed = eaddr; |
bbf45ba5 | 1116 | r = kvmppc_emulate_mmio(run, vcpu); |
7b701591 | 1117 | kvmppc_account_exit(vcpu, MMIO_EXITS); |
bbf45ba5 HB |
1118 | } |
1119 | ||
f1e89028 | 1120 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
bbf45ba5 HB |
1121 | break; |
1122 | } | |
1123 | ||
1124 | case BOOKE_INTERRUPT_ITLB_MISS: { | |
bbf45ba5 | 1125 | unsigned long eaddr = vcpu->arch.pc; |
89168618 | 1126 | gpa_t gpaddr; |
bbf45ba5 | 1127 | gfn_t gfn; |
7924bd41 | 1128 | int gtlb_index; |
bbf45ba5 HB |
1129 | |
1130 | r = RESUME_GUEST; | |
1131 | ||
1132 | /* Check the guest TLB. */ | |
fa86b8dd | 1133 | gtlb_index = kvmppc_mmu_itlb_index(vcpu, eaddr); |
7924bd41 | 1134 | if (gtlb_index < 0) { |
bbf45ba5 | 1135 | /* The guest didn't have a mapping for it. */ |
d4cf3892 | 1136 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_ITLB_MISS); |
b52a638c | 1137 | kvmppc_mmu_itlb_miss(vcpu); |
7b701591 | 1138 | kvmppc_account_exit(vcpu, ITLB_REAL_MISS_EXITS); |
bbf45ba5 HB |
1139 | break; |
1140 | } | |
1141 | ||
7b701591 | 1142 | kvmppc_account_exit(vcpu, ITLB_VIRT_MISS_EXITS); |
bbf45ba5 | 1143 | |
f1e89028 SW |
1144 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
1145 | ||
be8d1cae | 1146 | gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr); |
89168618 | 1147 | gfn = gpaddr >> PAGE_SHIFT; |
bbf45ba5 HB |
1148 | |
1149 | if (kvm_is_visible_gfn(vcpu->kvm, gfn)) { | |
1150 | /* The guest TLB had a mapping, but the shadow TLB | |
1151 | * didn't. This could be because: | |
1152 | * a) the entry is mapping the host kernel, or | |
1153 | * b) the guest used a large mapping which we're faking | |
1154 | * Either way, we need to satisfy the fault without | |
1155 | * invoking the guest. */ | |
58a96214 | 1156 | kvmppc_mmu_map(vcpu, eaddr, gpaddr, gtlb_index); |
bbf45ba5 HB |
1157 | } else { |
1158 | /* Guest mapped and leaped at non-RAM! */ | |
d4cf3892 | 1159 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_MACHINE_CHECK); |
bbf45ba5 HB |
1160 | } |
1161 | ||
f1e89028 | 1162 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
bbf45ba5 HB |
1163 | break; |
1164 | } | |
1165 | ||
6a0ab738 | 1166 | case BOOKE_INTERRUPT_DEBUG: { |
ce11e48b BB |
1167 | r = kvmppc_handle_debug(run, vcpu); |
1168 | if (r == RESUME_HOST) | |
1169 | run->exit_reason = KVM_EXIT_DEBUG; | |
7b701591 | 1170 | kvmppc_account_exit(vcpu, DEBUG_EXITS); |
6a0ab738 HB |
1171 | break; |
1172 | } | |
1173 | ||
bbf45ba5 HB |
1174 | default: |
1175 | printk(KERN_EMERG "exit_nr %d\n", exit_nr); | |
1176 | BUG(); | |
1177 | } | |
1178 | ||
a8e4ef84 AG |
1179 | /* |
1180 | * To avoid clobbering exit_reason, only check for signals if we | |
1181 | * aren't already exiting to userspace for some other reason. | |
1182 | */ | |
03660ba2 | 1183 | if (!(r & RESUME_HOST)) { |
7ee78855 | 1184 | s = kvmppc_prepare_to_enter(vcpu); |
6c85f52b | 1185 | if (s <= 0) |
7ee78855 | 1186 | r = (s << 2) | RESUME_HOST | (r & RESUME_FLAG_NV); |
6c85f52b SW |
1187 | else { |
1188 | /* interrupts now hard-disabled */ | |
5f1c248f | 1189 | kvmppc_fix_ee_before_entry(); |
03660ba2 | 1190 | } |
bbf45ba5 HB |
1191 | } |
1192 | ||
1193 | return r; | |
1194 | } | |
1195 | ||
d26f22c9 BB |
1196 | static void kvmppc_set_tsr(struct kvm_vcpu *vcpu, u32 new_tsr) |
1197 | { | |
1198 | u32 old_tsr = vcpu->arch.tsr; | |
1199 | ||
1200 | vcpu->arch.tsr = new_tsr; | |
1201 | ||
1202 | if ((old_tsr ^ vcpu->arch.tsr) & (TSR_ENW | TSR_WIS)) | |
1203 | arm_next_watchdog(vcpu); | |
1204 | ||
1205 | update_timer_ints(vcpu); | |
1206 | } | |
1207 | ||
bbf45ba5 HB |
1208 | /* Initial guest state: 16MB mapping 0 -> 0, PC = 0, MSR = 0, R1 = 16MB */ |
1209 | int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) | |
1210 | { | |
082decf2 | 1211 | int i; |
af8f38b3 | 1212 | int r; |
082decf2 | 1213 | |
bbf45ba5 | 1214 | vcpu->arch.pc = 0; |
b5904972 | 1215 | vcpu->arch.shared->pir = vcpu->vcpu_id; |
8e5b26b5 | 1216 | kvmppc_set_gpr(vcpu, 1, (16<<20) - 8); /* -8 for the callee-save LR slot */ |
d30f6e48 | 1217 | kvmppc_set_msr(vcpu, 0); |
bbf45ba5 | 1218 | |
d30f6e48 | 1219 | #ifndef CONFIG_KVM_BOOKE_HV |
ce11e48b | 1220 | vcpu->arch.shadow_msr = MSR_USER | MSR_IS | MSR_DS; |
49dd2c49 | 1221 | vcpu->arch.shadow_pid = 1; |
d30f6e48 SW |
1222 | vcpu->arch.shared->msr = 0; |
1223 | #endif | |
49dd2c49 | 1224 | |
082decf2 HB |
1225 | /* Eye-catching numbers so we know if the guest takes an interrupt |
1226 | * before it's programmed its own IVPR/IVORs. */ | |
bbf45ba5 | 1227 | vcpu->arch.ivpr = 0x55550000; |
082decf2 HB |
1228 | for (i = 0; i < BOOKE_IRQPRIO_MAX; i++) |
1229 | vcpu->arch.ivor[i] = 0x7700 | i * 4; | |
bbf45ba5 | 1230 | |
73e75b41 HB |
1231 | kvmppc_init_timing_stats(vcpu); |
1232 | ||
af8f38b3 AG |
1233 | r = kvmppc_core_vcpu_setup(vcpu); |
1234 | kvmppc_sanity_check(vcpu); | |
1235 | return r; | |
bbf45ba5 HB |
1236 | } |
1237 | ||
f61c94bb BB |
1238 | int kvmppc_subarch_vcpu_init(struct kvm_vcpu *vcpu) |
1239 | { | |
1240 | /* setup watchdog timer once */ | |
1241 | spin_lock_init(&vcpu->arch.wdt_lock); | |
1242 | setup_timer(&vcpu->arch.wdt_timer, kvmppc_watchdog_func, | |
1243 | (unsigned long)vcpu); | |
1244 | ||
1245 | return 0; | |
1246 | } | |
1247 | ||
1248 | void kvmppc_subarch_vcpu_uninit(struct kvm_vcpu *vcpu) | |
1249 | { | |
1250 | del_timer_sync(&vcpu->arch.wdt_timer); | |
1251 | } | |
1252 | ||
bbf45ba5 HB |
1253 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
1254 | { | |
1255 | int i; | |
1256 | ||
1257 | regs->pc = vcpu->arch.pc; | |
992b5b29 | 1258 | regs->cr = kvmppc_get_cr(vcpu); |
bbf45ba5 HB |
1259 | regs->ctr = vcpu->arch.ctr; |
1260 | regs->lr = vcpu->arch.lr; | |
992b5b29 | 1261 | regs->xer = kvmppc_get_xer(vcpu); |
666e7252 | 1262 | regs->msr = vcpu->arch.shared->msr; |
31579eea BB |
1263 | regs->srr0 = kvmppc_get_srr0(vcpu); |
1264 | regs->srr1 = kvmppc_get_srr1(vcpu); | |
bbf45ba5 | 1265 | regs->pid = vcpu->arch.pid; |
a73a9599 AG |
1266 | regs->sprg0 = vcpu->arch.shared->sprg0; |
1267 | regs->sprg1 = vcpu->arch.shared->sprg1; | |
1268 | regs->sprg2 = vcpu->arch.shared->sprg2; | |
1269 | regs->sprg3 = vcpu->arch.shared->sprg3; | |
b5904972 SW |
1270 | regs->sprg4 = vcpu->arch.shared->sprg4; |
1271 | regs->sprg5 = vcpu->arch.shared->sprg5; | |
1272 | regs->sprg6 = vcpu->arch.shared->sprg6; | |
1273 | regs->sprg7 = vcpu->arch.shared->sprg7; | |
bbf45ba5 HB |
1274 | |
1275 | for (i = 0; i < ARRAY_SIZE(regs->gpr); i++) | |
8e5b26b5 | 1276 | regs->gpr[i] = kvmppc_get_gpr(vcpu, i); |
bbf45ba5 HB |
1277 | |
1278 | return 0; | |
1279 | } | |
1280 | ||
1281 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
1282 | { | |
1283 | int i; | |
1284 | ||
1285 | vcpu->arch.pc = regs->pc; | |
992b5b29 | 1286 | kvmppc_set_cr(vcpu, regs->cr); |
bbf45ba5 HB |
1287 | vcpu->arch.ctr = regs->ctr; |
1288 | vcpu->arch.lr = regs->lr; | |
992b5b29 | 1289 | kvmppc_set_xer(vcpu, regs->xer); |
b8fd68ac | 1290 | kvmppc_set_msr(vcpu, regs->msr); |
31579eea BB |
1291 | kvmppc_set_srr0(vcpu, regs->srr0); |
1292 | kvmppc_set_srr1(vcpu, regs->srr1); | |
5ce941ee | 1293 | kvmppc_set_pid(vcpu, regs->pid); |
a73a9599 AG |
1294 | vcpu->arch.shared->sprg0 = regs->sprg0; |
1295 | vcpu->arch.shared->sprg1 = regs->sprg1; | |
1296 | vcpu->arch.shared->sprg2 = regs->sprg2; | |
1297 | vcpu->arch.shared->sprg3 = regs->sprg3; | |
b5904972 SW |
1298 | vcpu->arch.shared->sprg4 = regs->sprg4; |
1299 | vcpu->arch.shared->sprg5 = regs->sprg5; | |
1300 | vcpu->arch.shared->sprg6 = regs->sprg6; | |
1301 | vcpu->arch.shared->sprg7 = regs->sprg7; | |
bbf45ba5 | 1302 | |
8e5b26b5 AG |
1303 | for (i = 0; i < ARRAY_SIZE(regs->gpr); i++) |
1304 | kvmppc_set_gpr(vcpu, i, regs->gpr[i]); | |
bbf45ba5 HB |
1305 | |
1306 | return 0; | |
1307 | } | |
1308 | ||
5ce941ee SW |
1309 | static void get_sregs_base(struct kvm_vcpu *vcpu, |
1310 | struct kvm_sregs *sregs) | |
1311 | { | |
1312 | u64 tb = get_tb(); | |
1313 | ||
1314 | sregs->u.e.features |= KVM_SREGS_E_BASE; | |
1315 | ||
1316 | sregs->u.e.csrr0 = vcpu->arch.csrr0; | |
1317 | sregs->u.e.csrr1 = vcpu->arch.csrr1; | |
1318 | sregs->u.e.mcsr = vcpu->arch.mcsr; | |
d30f6e48 SW |
1319 | sregs->u.e.esr = get_guest_esr(vcpu); |
1320 | sregs->u.e.dear = get_guest_dear(vcpu); | |
5ce941ee SW |
1321 | sregs->u.e.tsr = vcpu->arch.tsr; |
1322 | sregs->u.e.tcr = vcpu->arch.tcr; | |
1323 | sregs->u.e.dec = kvmppc_get_dec(vcpu, tb); | |
1324 | sregs->u.e.tb = tb; | |
1325 | sregs->u.e.vrsave = vcpu->arch.vrsave; | |
1326 | } | |
1327 | ||
1328 | static int set_sregs_base(struct kvm_vcpu *vcpu, | |
1329 | struct kvm_sregs *sregs) | |
1330 | { | |
1331 | if (!(sregs->u.e.features & KVM_SREGS_E_BASE)) | |
1332 | return 0; | |
1333 | ||
1334 | vcpu->arch.csrr0 = sregs->u.e.csrr0; | |
1335 | vcpu->arch.csrr1 = sregs->u.e.csrr1; | |
1336 | vcpu->arch.mcsr = sregs->u.e.mcsr; | |
d30f6e48 SW |
1337 | set_guest_esr(vcpu, sregs->u.e.esr); |
1338 | set_guest_dear(vcpu, sregs->u.e.dear); | |
5ce941ee | 1339 | vcpu->arch.vrsave = sregs->u.e.vrsave; |
dfd4d47e | 1340 | kvmppc_set_tcr(vcpu, sregs->u.e.tcr); |
5ce941ee | 1341 | |
dfd4d47e | 1342 | if (sregs->u.e.update_special & KVM_SREGS_E_UPDATE_DEC) { |
5ce941ee | 1343 | vcpu->arch.dec = sregs->u.e.dec; |
dfd4d47e SW |
1344 | kvmppc_emulate_dec(vcpu); |
1345 | } | |
5ce941ee | 1346 | |
d26f22c9 BB |
1347 | if (sregs->u.e.update_special & KVM_SREGS_E_UPDATE_TSR) |
1348 | kvmppc_set_tsr(vcpu, sregs->u.e.tsr); | |
5ce941ee SW |
1349 | |
1350 | return 0; | |
1351 | } | |
1352 | ||
1353 | static void get_sregs_arch206(struct kvm_vcpu *vcpu, | |
1354 | struct kvm_sregs *sregs) | |
1355 | { | |
1356 | sregs->u.e.features |= KVM_SREGS_E_ARCH206; | |
1357 | ||
841741f2 | 1358 | sregs->u.e.pir = vcpu->vcpu_id; |
5ce941ee SW |
1359 | sregs->u.e.mcsrr0 = vcpu->arch.mcsrr0; |
1360 | sregs->u.e.mcsrr1 = vcpu->arch.mcsrr1; | |
1361 | sregs->u.e.decar = vcpu->arch.decar; | |
1362 | sregs->u.e.ivpr = vcpu->arch.ivpr; | |
1363 | } | |
1364 | ||
1365 | static int set_sregs_arch206(struct kvm_vcpu *vcpu, | |
1366 | struct kvm_sregs *sregs) | |
1367 | { | |
1368 | if (!(sregs->u.e.features & KVM_SREGS_E_ARCH206)) | |
1369 | return 0; | |
1370 | ||
841741f2 | 1371 | if (sregs->u.e.pir != vcpu->vcpu_id) |
5ce941ee SW |
1372 | return -EINVAL; |
1373 | ||
1374 | vcpu->arch.mcsrr0 = sregs->u.e.mcsrr0; | |
1375 | vcpu->arch.mcsrr1 = sregs->u.e.mcsrr1; | |
1376 | vcpu->arch.decar = sregs->u.e.decar; | |
1377 | vcpu->arch.ivpr = sregs->u.e.ivpr; | |
1378 | ||
1379 | return 0; | |
1380 | } | |
1381 | ||
3a167bea | 1382 | int kvmppc_get_sregs_ivor(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
5ce941ee SW |
1383 | { |
1384 | sregs->u.e.features |= KVM_SREGS_E_IVOR; | |
1385 | ||
1386 | sregs->u.e.ivor_low[0] = vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL]; | |
1387 | sregs->u.e.ivor_low[1] = vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK]; | |
1388 | sregs->u.e.ivor_low[2] = vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE]; | |
1389 | sregs->u.e.ivor_low[3] = vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE]; | |
1390 | sregs->u.e.ivor_low[4] = vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL]; | |
1391 | sregs->u.e.ivor_low[5] = vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT]; | |
1392 | sregs->u.e.ivor_low[6] = vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM]; | |
1393 | sregs->u.e.ivor_low[7] = vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL]; | |
1394 | sregs->u.e.ivor_low[8] = vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL]; | |
1395 | sregs->u.e.ivor_low[9] = vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL]; | |
1396 | sregs->u.e.ivor_low[10] = vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER]; | |
1397 | sregs->u.e.ivor_low[11] = vcpu->arch.ivor[BOOKE_IRQPRIO_FIT]; | |
1398 | sregs->u.e.ivor_low[12] = vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG]; | |
1399 | sregs->u.e.ivor_low[13] = vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS]; | |
1400 | sregs->u.e.ivor_low[14] = vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS]; | |
1401 | sregs->u.e.ivor_low[15] = vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG]; | |
3a167bea | 1402 | return 0; |
5ce941ee SW |
1403 | } |
1404 | ||
1405 | int kvmppc_set_sregs_ivor(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) | |
1406 | { | |
1407 | if (!(sregs->u.e.features & KVM_SREGS_E_IVOR)) | |
1408 | return 0; | |
1409 | ||
1410 | vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL] = sregs->u.e.ivor_low[0]; | |
1411 | vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK] = sregs->u.e.ivor_low[1]; | |
1412 | vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE] = sregs->u.e.ivor_low[2]; | |
1413 | vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE] = sregs->u.e.ivor_low[3]; | |
1414 | vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL] = sregs->u.e.ivor_low[4]; | |
1415 | vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT] = sregs->u.e.ivor_low[5]; | |
1416 | vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM] = sregs->u.e.ivor_low[6]; | |
1417 | vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL] = sregs->u.e.ivor_low[7]; | |
1418 | vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL] = sregs->u.e.ivor_low[8]; | |
1419 | vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL] = sregs->u.e.ivor_low[9]; | |
1420 | vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER] = sregs->u.e.ivor_low[10]; | |
1421 | vcpu->arch.ivor[BOOKE_IRQPRIO_FIT] = sregs->u.e.ivor_low[11]; | |
1422 | vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG] = sregs->u.e.ivor_low[12]; | |
1423 | vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS] = sregs->u.e.ivor_low[13]; | |
1424 | vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS] = sregs->u.e.ivor_low[14]; | |
1425 | vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG] = sregs->u.e.ivor_low[15]; | |
1426 | ||
1427 | return 0; | |
1428 | } | |
1429 | ||
bbf45ba5 HB |
1430 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, |
1431 | struct kvm_sregs *sregs) | |
1432 | { | |
5ce941ee SW |
1433 | sregs->pvr = vcpu->arch.pvr; |
1434 | ||
1435 | get_sregs_base(vcpu, sregs); | |
1436 | get_sregs_arch206(vcpu, sregs); | |
cbbc58d4 | 1437 | return vcpu->kvm->arch.kvm_ops->get_sregs(vcpu, sregs); |
bbf45ba5 HB |
1438 | } |
1439 | ||
1440 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, | |
1441 | struct kvm_sregs *sregs) | |
1442 | { | |
5ce941ee SW |
1443 | int ret; |
1444 | ||
1445 | if (vcpu->arch.pvr != sregs->pvr) | |
1446 | return -EINVAL; | |
1447 | ||
1448 | ret = set_sregs_base(vcpu, sregs); | |
1449 | if (ret < 0) | |
1450 | return ret; | |
1451 | ||
1452 | ret = set_sregs_arch206(vcpu, sregs); | |
1453 | if (ret < 0) | |
1454 | return ret; | |
1455 | ||
cbbc58d4 | 1456 | return vcpu->kvm->arch.kvm_ops->set_sregs(vcpu, sregs); |
bbf45ba5 HB |
1457 | } |
1458 | ||
31f3438e PM |
1459 | int kvm_vcpu_ioctl_get_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg) |
1460 | { | |
35b299e2 MC |
1461 | int r = 0; |
1462 | union kvmppc_one_reg val; | |
1463 | int size; | |
35b299e2 MC |
1464 | |
1465 | size = one_reg_size(reg->id); | |
1466 | if (size > sizeof(val)) | |
1467 | return -EINVAL; | |
6df8d3fc BB |
1468 | |
1469 | switch (reg->id) { | |
1470 | case KVM_REG_PPC_IAC1: | |
547465ef BB |
1471 | val = get_reg_val(reg->id, vcpu->arch.dbg_reg.iac1); |
1472 | break; | |
6df8d3fc | 1473 | case KVM_REG_PPC_IAC2: |
547465ef BB |
1474 | val = get_reg_val(reg->id, vcpu->arch.dbg_reg.iac2); |
1475 | break; | |
1476 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 | |
6df8d3fc | 1477 | case KVM_REG_PPC_IAC3: |
547465ef BB |
1478 | val = get_reg_val(reg->id, vcpu->arch.dbg_reg.iac3); |
1479 | break; | |
35b299e2 | 1480 | case KVM_REG_PPC_IAC4: |
547465ef | 1481 | val = get_reg_val(reg->id, vcpu->arch.dbg_reg.iac4); |
6df8d3fc | 1482 | break; |
547465ef | 1483 | #endif |
6df8d3fc | 1484 | case KVM_REG_PPC_DAC1: |
547465ef BB |
1485 | val = get_reg_val(reg->id, vcpu->arch.dbg_reg.dac1); |
1486 | break; | |
35b299e2 | 1487 | case KVM_REG_PPC_DAC2: |
547465ef | 1488 | val = get_reg_val(reg->id, vcpu->arch.dbg_reg.dac2); |
6df8d3fc | 1489 | break; |
324b3e63 AG |
1490 | case KVM_REG_PPC_EPR: { |
1491 | u32 epr = get_guest_epr(vcpu); | |
35b299e2 | 1492 | val = get_reg_val(reg->id, epr); |
324b3e63 AG |
1493 | break; |
1494 | } | |
352df1de MC |
1495 | #if defined(CONFIG_64BIT) |
1496 | case KVM_REG_PPC_EPCR: | |
35b299e2 | 1497 | val = get_reg_val(reg->id, vcpu->arch.epcr); |
352df1de MC |
1498 | break; |
1499 | #endif | |
78accda4 | 1500 | case KVM_REG_PPC_TCR: |
35b299e2 | 1501 | val = get_reg_val(reg->id, vcpu->arch.tcr); |
78accda4 BB |
1502 | break; |
1503 | case KVM_REG_PPC_TSR: | |
35b299e2 | 1504 | val = get_reg_val(reg->id, vcpu->arch.tsr); |
78accda4 | 1505 | break; |
35b299e2 | 1506 | case KVM_REG_PPC_DEBUG_INST: |
b12c7841 | 1507 | val = get_reg_val(reg->id, KVMPPC_INST_EHPRIV_DEBUG); |
8c32a2ea | 1508 | break; |
8b75cbbe PM |
1509 | case KVM_REG_PPC_VRSAVE: |
1510 | val = get_reg_val(reg->id, vcpu->arch.vrsave); | |
8c32a2ea | 1511 | break; |
6df8d3fc | 1512 | default: |
cbbc58d4 | 1513 | r = vcpu->kvm->arch.kvm_ops->get_one_reg(vcpu, reg->id, &val); |
6df8d3fc BB |
1514 | break; |
1515 | } | |
35b299e2 MC |
1516 | |
1517 | if (r) | |
1518 | return r; | |
1519 | ||
1520 | if (copy_to_user((char __user *)(unsigned long)reg->addr, &val, size)) | |
1521 | r = -EFAULT; | |
1522 | ||
6df8d3fc | 1523 | return r; |
31f3438e PM |
1524 | } |
1525 | ||
1526 | int kvm_vcpu_ioctl_set_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg) | |
1527 | { | |
35b299e2 MC |
1528 | int r = 0; |
1529 | union kvmppc_one_reg val; | |
1530 | int size; | |
35b299e2 MC |
1531 | |
1532 | size = one_reg_size(reg->id); | |
1533 | if (size > sizeof(val)) | |
1534 | return -EINVAL; | |
1535 | ||
1536 | if (copy_from_user(&val, (char __user *)(unsigned long)reg->addr, size)) | |
1537 | return -EFAULT; | |
6df8d3fc BB |
1538 | |
1539 | switch (reg->id) { | |
1540 | case KVM_REG_PPC_IAC1: | |
547465ef BB |
1541 | vcpu->arch.dbg_reg.iac1 = set_reg_val(reg->id, val); |
1542 | break; | |
6df8d3fc | 1543 | case KVM_REG_PPC_IAC2: |
547465ef BB |
1544 | vcpu->arch.dbg_reg.iac2 = set_reg_val(reg->id, val); |
1545 | break; | |
1546 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 | |
6df8d3fc | 1547 | case KVM_REG_PPC_IAC3: |
547465ef BB |
1548 | vcpu->arch.dbg_reg.iac3 = set_reg_val(reg->id, val); |
1549 | break; | |
35b299e2 | 1550 | case KVM_REG_PPC_IAC4: |
547465ef | 1551 | vcpu->arch.dbg_reg.iac4 = set_reg_val(reg->id, val); |
6df8d3fc | 1552 | break; |
547465ef | 1553 | #endif |
6df8d3fc | 1554 | case KVM_REG_PPC_DAC1: |
547465ef BB |
1555 | vcpu->arch.dbg_reg.dac1 = set_reg_val(reg->id, val); |
1556 | break; | |
35b299e2 | 1557 | case KVM_REG_PPC_DAC2: |
547465ef | 1558 | vcpu->arch.dbg_reg.dac2 = set_reg_val(reg->id, val); |
6df8d3fc | 1559 | break; |
324b3e63 | 1560 | case KVM_REG_PPC_EPR: { |
35b299e2 MC |
1561 | u32 new_epr = set_reg_val(reg->id, val); |
1562 | kvmppc_set_epr(vcpu, new_epr); | |
324b3e63 AG |
1563 | break; |
1564 | } | |
352df1de MC |
1565 | #if defined(CONFIG_64BIT) |
1566 | case KVM_REG_PPC_EPCR: { | |
35b299e2 MC |
1567 | u32 new_epcr = set_reg_val(reg->id, val); |
1568 | kvmppc_set_epcr(vcpu, new_epcr); | |
352df1de MC |
1569 | break; |
1570 | } | |
1571 | #endif | |
78accda4 | 1572 | case KVM_REG_PPC_OR_TSR: { |
35b299e2 | 1573 | u32 tsr_bits = set_reg_val(reg->id, val); |
78accda4 BB |
1574 | kvmppc_set_tsr_bits(vcpu, tsr_bits); |
1575 | break; | |
1576 | } | |
1577 | case KVM_REG_PPC_CLEAR_TSR: { | |
35b299e2 | 1578 | u32 tsr_bits = set_reg_val(reg->id, val); |
78accda4 BB |
1579 | kvmppc_clr_tsr_bits(vcpu, tsr_bits); |
1580 | break; | |
1581 | } | |
1582 | case KVM_REG_PPC_TSR: { | |
35b299e2 | 1583 | u32 tsr = set_reg_val(reg->id, val); |
78accda4 BB |
1584 | kvmppc_set_tsr(vcpu, tsr); |
1585 | break; | |
1586 | } | |
1587 | case KVM_REG_PPC_TCR: { | |
35b299e2 | 1588 | u32 tcr = set_reg_val(reg->id, val); |
78accda4 BB |
1589 | kvmppc_set_tcr(vcpu, tcr); |
1590 | break; | |
1591 | } | |
8b75cbbe PM |
1592 | case KVM_REG_PPC_VRSAVE: |
1593 | vcpu->arch.vrsave = set_reg_val(reg->id, val); | |
1594 | break; | |
6df8d3fc | 1595 | default: |
cbbc58d4 | 1596 | r = vcpu->kvm->arch.kvm_ops->set_one_reg(vcpu, reg->id, &val); |
6df8d3fc BB |
1597 | break; |
1598 | } | |
35b299e2 | 1599 | |
6df8d3fc | 1600 | return r; |
31f3438e PM |
1601 | } |
1602 | ||
bbf45ba5 HB |
1603 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) |
1604 | { | |
1605 | return -ENOTSUPP; | |
1606 | } | |
1607 | ||
1608 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
1609 | { | |
1610 | return -ENOTSUPP; | |
1611 | } | |
1612 | ||
bbf45ba5 HB |
1613 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, |
1614 | struct kvm_translation *tr) | |
1615 | { | |
98001d8d AK |
1616 | int r; |
1617 | ||
98001d8d | 1618 | r = kvmppc_core_vcpu_translate(vcpu, tr); |
98001d8d | 1619 | return r; |
bbf45ba5 | 1620 | } |
d9fbd03d | 1621 | |
4e755758 AG |
1622 | int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) |
1623 | { | |
1624 | return -ENOTSUPP; | |
1625 | } | |
1626 | ||
5587027c | 1627 | void kvmppc_core_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, |
a66b48c3 PM |
1628 | struct kvm_memory_slot *dont) |
1629 | { | |
1630 | } | |
1631 | ||
5587027c | 1632 | int kvmppc_core_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, |
a66b48c3 PM |
1633 | unsigned long npages) |
1634 | { | |
1635 | return 0; | |
1636 | } | |
1637 | ||
f9e0554d | 1638 | int kvmppc_core_prepare_memory_region(struct kvm *kvm, |
a66b48c3 | 1639 | struct kvm_memory_slot *memslot, |
f9e0554d PM |
1640 | struct kvm_userspace_memory_region *mem) |
1641 | { | |
1642 | return 0; | |
1643 | } | |
1644 | ||
1645 | void kvmppc_core_commit_memory_region(struct kvm *kvm, | |
dfe49dbd | 1646 | struct kvm_userspace_memory_region *mem, |
8482644a | 1647 | const struct kvm_memory_slot *old) |
dfe49dbd PM |
1648 | { |
1649 | } | |
1650 | ||
1651 | void kvmppc_core_flush_memslot(struct kvm *kvm, struct kvm_memory_slot *memslot) | |
f9e0554d PM |
1652 | { |
1653 | } | |
1654 | ||
38f98824 MC |
1655 | void kvmppc_set_epcr(struct kvm_vcpu *vcpu, u32 new_epcr) |
1656 | { | |
1657 | #if defined(CONFIG_64BIT) | |
1658 | vcpu->arch.epcr = new_epcr; | |
1659 | #ifdef CONFIG_KVM_BOOKE_HV | |
1660 | vcpu->arch.shadow_epcr &= ~SPRN_EPCR_GICM; | |
1661 | if (vcpu->arch.epcr & SPRN_EPCR_ICM) | |
1662 | vcpu->arch.shadow_epcr |= SPRN_EPCR_GICM; | |
1663 | #endif | |
1664 | #endif | |
1665 | } | |
1666 | ||
dfd4d47e SW |
1667 | void kvmppc_set_tcr(struct kvm_vcpu *vcpu, u32 new_tcr) |
1668 | { | |
1669 | vcpu->arch.tcr = new_tcr; | |
f61c94bb | 1670 | arm_next_watchdog(vcpu); |
dfd4d47e SW |
1671 | update_timer_ints(vcpu); |
1672 | } | |
1673 | ||
1674 | void kvmppc_set_tsr_bits(struct kvm_vcpu *vcpu, u32 tsr_bits) | |
1675 | { | |
1676 | set_bits(tsr_bits, &vcpu->arch.tsr); | |
1677 | smp_wmb(); | |
1678 | kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); | |
1679 | kvm_vcpu_kick(vcpu); | |
1680 | } | |
1681 | ||
1682 | void kvmppc_clr_tsr_bits(struct kvm_vcpu *vcpu, u32 tsr_bits) | |
1683 | { | |
1684 | clear_bits(tsr_bits, &vcpu->arch.tsr); | |
f61c94bb BB |
1685 | |
1686 | /* | |
1687 | * We may have stopped the watchdog due to | |
1688 | * being stuck on final expiration. | |
1689 | */ | |
1690 | if (tsr_bits & (TSR_ENW | TSR_WIS)) | |
1691 | arm_next_watchdog(vcpu); | |
1692 | ||
dfd4d47e SW |
1693 | update_timer_ints(vcpu); |
1694 | } | |
1695 | ||
1696 | void kvmppc_decrementer_func(unsigned long data) | |
1697 | { | |
1698 | struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data; | |
1699 | ||
21bd000a BB |
1700 | if (vcpu->arch.tcr & TCR_ARE) { |
1701 | vcpu->arch.dec = vcpu->arch.decar; | |
1702 | kvmppc_emulate_dec(vcpu); | |
1703 | } | |
1704 | ||
dfd4d47e SW |
1705 | kvmppc_set_tsr_bits(vcpu, TSR_DIS); |
1706 | } | |
1707 | ||
ce11e48b BB |
1708 | static int kvmppc_booke_add_breakpoint(struct debug_reg *dbg_reg, |
1709 | uint64_t addr, int index) | |
1710 | { | |
1711 | switch (index) { | |
1712 | case 0: | |
1713 | dbg_reg->dbcr0 |= DBCR0_IAC1; | |
1714 | dbg_reg->iac1 = addr; | |
1715 | break; | |
1716 | case 1: | |
1717 | dbg_reg->dbcr0 |= DBCR0_IAC2; | |
1718 | dbg_reg->iac2 = addr; | |
1719 | break; | |
1720 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 | |
1721 | case 2: | |
1722 | dbg_reg->dbcr0 |= DBCR0_IAC3; | |
1723 | dbg_reg->iac3 = addr; | |
1724 | break; | |
1725 | case 3: | |
1726 | dbg_reg->dbcr0 |= DBCR0_IAC4; | |
1727 | dbg_reg->iac4 = addr; | |
1728 | break; | |
1729 | #endif | |
1730 | default: | |
1731 | return -EINVAL; | |
1732 | } | |
1733 | ||
1734 | dbg_reg->dbcr0 |= DBCR0_IDM; | |
1735 | return 0; | |
1736 | } | |
1737 | ||
1738 | static int kvmppc_booke_add_watchpoint(struct debug_reg *dbg_reg, uint64_t addr, | |
1739 | int type, int index) | |
1740 | { | |
1741 | switch (index) { | |
1742 | case 0: | |
1743 | if (type & KVMPPC_DEBUG_WATCH_READ) | |
1744 | dbg_reg->dbcr0 |= DBCR0_DAC1R; | |
1745 | if (type & KVMPPC_DEBUG_WATCH_WRITE) | |
1746 | dbg_reg->dbcr0 |= DBCR0_DAC1W; | |
1747 | dbg_reg->dac1 = addr; | |
1748 | break; | |
1749 | case 1: | |
1750 | if (type & KVMPPC_DEBUG_WATCH_READ) | |
1751 | dbg_reg->dbcr0 |= DBCR0_DAC2R; | |
1752 | if (type & KVMPPC_DEBUG_WATCH_WRITE) | |
1753 | dbg_reg->dbcr0 |= DBCR0_DAC2W; | |
1754 | dbg_reg->dac2 = addr; | |
1755 | break; | |
1756 | default: | |
1757 | return -EINVAL; | |
1758 | } | |
1759 | ||
1760 | dbg_reg->dbcr0 |= DBCR0_IDM; | |
1761 | return 0; | |
1762 | } | |
1763 | void kvm_guest_protect_msr(struct kvm_vcpu *vcpu, ulong prot_bitmap, bool set) | |
1764 | { | |
1765 | /* XXX: Add similar MSR protection for BookE-PR */ | |
1766 | #ifdef CONFIG_KVM_BOOKE_HV | |
1767 | BUG_ON(prot_bitmap & ~(MSRP_UCLEP | MSRP_DEP | MSRP_PMMP)); | |
1768 | if (set) { | |
1769 | if (prot_bitmap & MSR_UCLE) | |
1770 | vcpu->arch.shadow_msrp |= MSRP_UCLEP; | |
1771 | if (prot_bitmap & MSR_DE) | |
1772 | vcpu->arch.shadow_msrp |= MSRP_DEP; | |
1773 | if (prot_bitmap & MSR_PMM) | |
1774 | vcpu->arch.shadow_msrp |= MSRP_PMMP; | |
1775 | } else { | |
1776 | if (prot_bitmap & MSR_UCLE) | |
1777 | vcpu->arch.shadow_msrp &= ~MSRP_UCLEP; | |
1778 | if (prot_bitmap & MSR_DE) | |
1779 | vcpu->arch.shadow_msrp &= ~MSRP_DEP; | |
1780 | if (prot_bitmap & MSR_PMM) | |
1781 | vcpu->arch.shadow_msrp &= ~MSRP_PMMP; | |
1782 | } | |
1783 | #endif | |
1784 | } | |
1785 | ||
1786 | int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, | |
1787 | struct kvm_guest_debug *dbg) | |
1788 | { | |
1789 | struct debug_reg *dbg_reg; | |
1790 | int n, b = 0, w = 0; | |
1791 | ||
1792 | if (!(dbg->control & KVM_GUESTDBG_ENABLE)) { | |
1793 | vcpu->arch.shadow_dbg_reg.dbcr0 = 0; | |
1794 | vcpu->guest_debug = 0; | |
1795 | kvm_guest_protect_msr(vcpu, MSR_DE, false); | |
1796 | return 0; | |
1797 | } | |
1798 | ||
1799 | kvm_guest_protect_msr(vcpu, MSR_DE, true); | |
1800 | vcpu->guest_debug = dbg->control; | |
1801 | vcpu->arch.shadow_dbg_reg.dbcr0 = 0; | |
1802 | /* Set DBCR0_EDM in guest visible DBCR0 register. */ | |
1803 | vcpu->arch.dbg_reg.dbcr0 = DBCR0_EDM; | |
1804 | ||
1805 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | |
1806 | vcpu->arch.shadow_dbg_reg.dbcr0 |= DBCR0_IDM | DBCR0_IC; | |
1807 | ||
1808 | /* Code below handles only HW breakpoints */ | |
1809 | dbg_reg = &(vcpu->arch.shadow_dbg_reg); | |
1810 | ||
1811 | #ifdef CONFIG_KVM_BOOKE_HV | |
1812 | /* | |
1813 | * On BookE-HV (e500mc) the guest is always executed with MSR.GS=1 | |
1814 | * DBCR1 and DBCR2 are set to trigger debug events when MSR.PR is 0 | |
1815 | */ | |
1816 | dbg_reg->dbcr1 = 0; | |
1817 | dbg_reg->dbcr2 = 0; | |
1818 | #else | |
1819 | /* | |
1820 | * On BookE-PR (e500v2) the guest is always executed with MSR.PR=1 | |
1821 | * We set DBCR1 and DBCR2 to only trigger debug events when MSR.PR | |
1822 | * is set. | |
1823 | */ | |
1824 | dbg_reg->dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | DBCR1_IAC3US | | |
1825 | DBCR1_IAC4US; | |
1826 | dbg_reg->dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US; | |
1827 | #endif | |
1828 | ||
1829 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) | |
1830 | return 0; | |
1831 | ||
1832 | for (n = 0; n < (KVMPPC_BOOKE_IAC_NUM + KVMPPC_BOOKE_DAC_NUM); n++) { | |
1833 | uint64_t addr = dbg->arch.bp[n].addr; | |
1834 | uint32_t type = dbg->arch.bp[n].type; | |
1835 | ||
1836 | if (type == KVMPPC_DEBUG_NONE) | |
1837 | continue; | |
1838 | ||
1839 | if (type & !(KVMPPC_DEBUG_WATCH_READ | | |
1840 | KVMPPC_DEBUG_WATCH_WRITE | | |
1841 | KVMPPC_DEBUG_BREAKPOINT)) | |
1842 | return -EINVAL; | |
1843 | ||
1844 | if (type & KVMPPC_DEBUG_BREAKPOINT) { | |
1845 | /* Setting H/W breakpoint */ | |
1846 | if (kvmppc_booke_add_breakpoint(dbg_reg, addr, b++)) | |
1847 | return -EINVAL; | |
1848 | } else { | |
1849 | /* Setting H/W watchpoint */ | |
1850 | if (kvmppc_booke_add_watchpoint(dbg_reg, addr, | |
1851 | type, w++)) | |
1852 | return -EINVAL; | |
1853 | } | |
1854 | } | |
1855 | ||
1856 | return 0; | |
1857 | } | |
1858 | ||
94fa9d99 SW |
1859 | void kvmppc_booke_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
1860 | { | |
a47d72f3 | 1861 | vcpu->cpu = smp_processor_id(); |
d30f6e48 | 1862 | current->thread.kvm_vcpu = vcpu; |
94fa9d99 SW |
1863 | } |
1864 | ||
1865 | void kvmppc_booke_vcpu_put(struct kvm_vcpu *vcpu) | |
1866 | { | |
d30f6e48 | 1867 | current->thread.kvm_vcpu = NULL; |
a47d72f3 | 1868 | vcpu->cpu = -1; |
ce11e48b BB |
1869 | |
1870 | /* Clear pending debug event in DBSR */ | |
1871 | kvmppc_clear_dbsr(); | |
94fa9d99 SW |
1872 | } |
1873 | ||
3a167bea AK |
1874 | void kvmppc_mmu_destroy(struct kvm_vcpu *vcpu) |
1875 | { | |
cbbc58d4 | 1876 | vcpu->kvm->arch.kvm_ops->mmu_destroy(vcpu); |
3a167bea AK |
1877 | } |
1878 | ||
1879 | int kvmppc_core_init_vm(struct kvm *kvm) | |
1880 | { | |
cbbc58d4 | 1881 | return kvm->arch.kvm_ops->init_vm(kvm); |
3a167bea AK |
1882 | } |
1883 | ||
1884 | struct kvm_vcpu *kvmppc_core_vcpu_create(struct kvm *kvm, unsigned int id) | |
1885 | { | |
cbbc58d4 | 1886 | return kvm->arch.kvm_ops->vcpu_create(kvm, id); |
3a167bea AK |
1887 | } |
1888 | ||
1889 | void kvmppc_core_vcpu_free(struct kvm_vcpu *vcpu) | |
1890 | { | |
cbbc58d4 | 1891 | vcpu->kvm->arch.kvm_ops->vcpu_free(vcpu); |
3a167bea AK |
1892 | } |
1893 | ||
1894 | void kvmppc_core_destroy_vm(struct kvm *kvm) | |
1895 | { | |
cbbc58d4 | 1896 | kvm->arch.kvm_ops->destroy_vm(kvm); |
3a167bea AK |
1897 | } |
1898 | ||
1899 | void kvmppc_core_vcpu_load(struct kvm_vcpu *vcpu, int cpu) | |
1900 | { | |
cbbc58d4 | 1901 | vcpu->kvm->arch.kvm_ops->vcpu_load(vcpu, cpu); |
3a167bea AK |
1902 | } |
1903 | ||
1904 | void kvmppc_core_vcpu_put(struct kvm_vcpu *vcpu) | |
1905 | { | |
cbbc58d4 | 1906 | vcpu->kvm->arch.kvm_ops->vcpu_put(vcpu); |
94fa9d99 SW |
1907 | } |
1908 | ||
2986b8c7 | 1909 | int __init kvmppc_booke_init(void) |
d9fbd03d | 1910 | { |
d30f6e48 | 1911 | #ifndef CONFIG_KVM_BOOKE_HV |
d9fbd03d | 1912 | unsigned long ivor[16]; |
1d542d9c | 1913 | unsigned long *handler = kvmppc_booke_handler_addr; |
d9fbd03d | 1914 | unsigned long max_ivor = 0; |
1d542d9c | 1915 | unsigned long handler_len; |
d9fbd03d HB |
1916 | int i; |
1917 | ||
1918 | /* We install our own exception handlers by hijacking IVPR. IVPR must | |
1919 | * be 16-bit aligned, so we need a 64KB allocation. */ | |
1920 | kvmppc_booke_handlers = __get_free_pages(GFP_KERNEL | __GFP_ZERO, | |
1921 | VCPU_SIZE_ORDER); | |
1922 | if (!kvmppc_booke_handlers) | |
1923 | return -ENOMEM; | |
1924 | ||
1925 | /* XXX make sure our handlers are smaller than Linux's */ | |
1926 | ||
1927 | /* Copy our interrupt handlers to match host IVORs. That way we don't | |
1928 | * have to swap the IVORs on every guest/host transition. */ | |
1929 | ivor[0] = mfspr(SPRN_IVOR0); | |
1930 | ivor[1] = mfspr(SPRN_IVOR1); | |
1931 | ivor[2] = mfspr(SPRN_IVOR2); | |
1932 | ivor[3] = mfspr(SPRN_IVOR3); | |
1933 | ivor[4] = mfspr(SPRN_IVOR4); | |
1934 | ivor[5] = mfspr(SPRN_IVOR5); | |
1935 | ivor[6] = mfspr(SPRN_IVOR6); | |
1936 | ivor[7] = mfspr(SPRN_IVOR7); | |
1937 | ivor[8] = mfspr(SPRN_IVOR8); | |
1938 | ivor[9] = mfspr(SPRN_IVOR9); | |
1939 | ivor[10] = mfspr(SPRN_IVOR10); | |
1940 | ivor[11] = mfspr(SPRN_IVOR11); | |
1941 | ivor[12] = mfspr(SPRN_IVOR12); | |
1942 | ivor[13] = mfspr(SPRN_IVOR13); | |
1943 | ivor[14] = mfspr(SPRN_IVOR14); | |
1944 | ivor[15] = mfspr(SPRN_IVOR15); | |
1945 | ||
1946 | for (i = 0; i < 16; i++) { | |
1947 | if (ivor[i] > max_ivor) | |
1d542d9c | 1948 | max_ivor = i; |
d9fbd03d | 1949 | |
1d542d9c | 1950 | handler_len = handler[i + 1] - handler[i]; |
d9fbd03d | 1951 | memcpy((void *)kvmppc_booke_handlers + ivor[i], |
1d542d9c | 1952 | (void *)handler[i], handler_len); |
d9fbd03d | 1953 | } |
1d542d9c BB |
1954 | |
1955 | handler_len = handler[max_ivor + 1] - handler[max_ivor]; | |
1956 | flush_icache_range(kvmppc_booke_handlers, kvmppc_booke_handlers + | |
1957 | ivor[max_ivor] + handler_len); | |
d30f6e48 | 1958 | #endif /* !BOOKE_HV */ |
db93f574 | 1959 | return 0; |
d9fbd03d HB |
1960 | } |
1961 | ||
db93f574 | 1962 | void __exit kvmppc_booke_exit(void) |
d9fbd03d HB |
1963 | { |
1964 | free_pages(kvmppc_booke_handlers, VCPU_SIZE_ORDER); | |
1965 | kvm_exit(); | |
1966 | } |