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KVM: PPC: BOOKE: Allow guest to change MSR_DE
[mirror_ubuntu-bionic-kernel.git] / arch / powerpc / kvm / booke.c
CommitLineData
bbf45ba5
HB		 1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
14 *
15 * Copyright IBM Corp. 2007
4cd35f67 16 * Copyright 2010-2011 Freescale Semiconductor, Inc.
bbf45ba5
HB		 17 *
18 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
19 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
d30f6e48
SW		 20 * Scott Wood <scottwood@freescale.com>
21 * Varun Sethi <varun.sethi@freescale.com>
bbf45ba5
HB		 22 */
23
24#include <linux/errno.h>
25#include <linux/err.h>
26#include <linux/kvm_host.h>
5a0e3ad6 27#include <linux/gfp.h>
bbf45ba5
HB		 28#include <linux/module.h>
29#include <linux/vmalloc.h>
30#include <linux/fs.h>
7924bd41 31
bbf45ba5
HB		 32#include <asm/cputable.h>
33#include <asm/uaccess.h>
34#include <asm/kvm_ppc.h>
d9fbd03d 35#include <asm/cacheflush.h>
d30f6e48
SW		 36#include <asm/dbell.h>
37#include <asm/hw_irq.h>
38#include <asm/irq.h>
b50df19c 39#include <asm/time.h>
bbf45ba5 40
d30f6e48 41#include "timing.h"
75f74f0d 42#include "booke.h"
dba291f2
AK		 43
44#define CREATE_TRACE_POINTS
45#include "trace_booke.h"
bbf45ba5 46
d9fbd03d
HB		 47unsigned long kvmppc_booke_handlers;
48
bbf45ba5
HB		 49#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
50#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
51
52struct kvm_stats_debugfs_item debugfs_entries[] = {
bbf45ba5 53 { "mmio", VCPU_STAT(mmio_exits) },
bbf45ba5 54 { "sig", VCPU_STAT(signal_exits) },
bbf45ba5
HB		 55 { "itlb_r", VCPU_STAT(itlb_real_miss_exits) },
56 { "itlb_v", VCPU_STAT(itlb_virt_miss_exits) },
57 { "dtlb_r", VCPU_STAT(dtlb_real_miss_exits) },
58 { "dtlb_v", VCPU_STAT(dtlb_virt_miss_exits) },
59 { "sysc", VCPU_STAT(syscall_exits) },
60 { "isi", VCPU_STAT(isi_exits) },
61 { "dsi", VCPU_STAT(dsi_exits) },
62 { "inst_emu", VCPU_STAT(emulated_inst_exits) },
63 { "dec", VCPU_STAT(dec_exits) },
64 { "ext_intr", VCPU_STAT(ext_intr_exits) },
45c5eb67 65 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
d30f6e48
SW		 66 { "doorbell", VCPU_STAT(dbell_exits) },
67 { "guest doorbell", VCPU_STAT(gdbell_exits) },
cf1c5ca4 68 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
bbf45ba5
HB		 69 { NULL }
70};
71
bbf45ba5
HB		 72/* TODO: use vcpu_printf() */
73void kvmppc_dump_vcpu(struct kvm_vcpu *vcpu)
74{
75 int i;
76
666e7252 77 printk("pc: %08lx msr: %08llx\n", vcpu->arch.pc, vcpu->arch.shared->msr);
5cf8ca22 78 printk("lr: %08lx ctr: %08lx\n", vcpu->arch.lr, vcpu->arch.ctr);
de7906c3
AG		 79 printk("srr0: %08llx srr1: %08llx\n", vcpu->arch.shared->srr0,
80 vcpu->arch.shared->srr1);
bbf45ba5
HB		 81
82 printk("exceptions: %08lx\n", vcpu->arch.pending_exceptions);
83
84 for (i = 0; i < 32; i += 4) {
5cf8ca22 85 printk("gpr%02d: %08lx %08lx %08lx %08lx\n", i,
8e5b26b5
AG		 86 kvmppc_get_gpr(vcpu, i),
87 kvmppc_get_gpr(vcpu, i+1),
88 kvmppc_get_gpr(vcpu, i+2),
89 kvmppc_get_gpr(vcpu, i+3));
bbf45ba5
HB		 90 }
91}
92
4cd35f67
SW		 93#ifdef CONFIG_SPE
94void kvmppc_vcpu_disable_spe(struct kvm_vcpu *vcpu)
95{
96 preempt_disable();
97 enable_kernel_spe();
98 kvmppc_save_guest_spe(vcpu);
99 vcpu->arch.shadow_msr &= ~MSR_SPE;
100 preempt_enable();
101}
102
103static void kvmppc_vcpu_enable_spe(struct kvm_vcpu *vcpu)
104{
105 preempt_disable();
106 enable_kernel_spe();
107 kvmppc_load_guest_spe(vcpu);
108 vcpu->arch.shadow_msr |= MSR_SPE;
109 preempt_enable();
110}
111
112static void kvmppc_vcpu_sync_spe(struct kvm_vcpu *vcpu)
113{
114 if (vcpu->arch.shared->msr & MSR_SPE) {
115 if (!(vcpu->arch.shadow_msr & MSR_SPE))
116 kvmppc_vcpu_enable_spe(vcpu);
117 } else if (vcpu->arch.shadow_msr & MSR_SPE) {
118 kvmppc_vcpu_disable_spe(vcpu);
119 }
120}
121#else
122static void kvmppc_vcpu_sync_spe(struct kvm_vcpu *vcpu)
123{
124}
125#endif
126
7a08c274
AG		 127static void kvmppc_vcpu_sync_fpu(struct kvm_vcpu *vcpu)
128{
129#if defined(CONFIG_PPC_FPU) && !defined(CONFIG_KVM_BOOKE_HV)
130 /* We always treat the FP bit as enabled from the host
131 perspective, so only need to adjust the shadow MSR */
132 vcpu->arch.shadow_msr &= ~MSR_FP;
133 vcpu->arch.shadow_msr |= vcpu->arch.shared->msr & MSR_FP;
134#endif
135}
136
ce11e48b
BB		 137static void kvmppc_vcpu_sync_debug(struct kvm_vcpu *vcpu)
138{
139 /* Synchronize guest's desire to get debug interrupts into shadow MSR */
140#ifndef CONFIG_KVM_BOOKE_HV
141 vcpu->arch.shadow_msr &= ~MSR_DE;
142 vcpu->arch.shadow_msr |= vcpu->arch.shared->msr & MSR_DE;
143#endif
144
145 /* Force enable debug interrupts when user space wants to debug */
146 if (vcpu->guest_debug) {
147#ifdef CONFIG_KVM_BOOKE_HV
148 /*
149 * Since there is no shadow MSR, sync MSR_DE into the guest
150 * visible MSR.
151 */
152 vcpu->arch.shared->msr |= MSR_DE;
153#else
154 vcpu->arch.shadow_msr |= MSR_DE;
155 vcpu->arch.shared->msr &= ~MSR_DE;
156#endif
157 }
158}
159
dd9ebf1f
LY		 160/*
161 * Helper function for "full" MSR writes. No need to call this if only
162 * EE/CE/ME/DE/RI are changing.
163 */
4cd35f67
SW		 164void kvmppc_set_msr(struct kvm_vcpu *vcpu, u32 new_msr)
165{
dd9ebf1f 166 u32 old_msr = vcpu->arch.shared->msr;
4cd35f67 167
d30f6e48
SW		 168#ifdef CONFIG_KVM_BOOKE_HV
169 new_msr |= MSR_GS;
170#endif
171
4cd35f67
SW		 172 vcpu->arch.shared->msr = new_msr;
173
dd9ebf1f 174 kvmppc_mmu_msr_notify(vcpu, old_msr);
4cd35f67 175 kvmppc_vcpu_sync_spe(vcpu);
7a08c274 176 kvmppc_vcpu_sync_fpu(vcpu);
ce11e48b 177 kvmppc_vcpu_sync_debug(vcpu);
4cd35f67
SW		 178}
179
d4cf3892
HB		 180static void kvmppc_booke_queue_irqprio(struct kvm_vcpu *vcpu,
181 unsigned int priority)
9dd921cf 182{
6346046c 183 trace_kvm_booke_queue_irqprio(vcpu, priority);
9dd921cf
HB		 184 set_bit(priority, &vcpu->arch.pending_exceptions);
185}
186
8de12015
AG		 187void kvmppc_core_queue_dtlb_miss(struct kvm_vcpu *vcpu,
188 ulong dear_flags, ulong esr_flags)
9dd921cf 189{
daf5e271
LY		 190 vcpu->arch.queued_dear = dear_flags;
191 vcpu->arch.queued_esr = esr_flags;
192 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DTLB_MISS);
193}
194
8de12015
AG		 195void kvmppc_core_queue_data_storage(struct kvm_vcpu *vcpu,
196 ulong dear_flags, ulong esr_flags)
daf5e271
LY		 197{
198 vcpu->arch.queued_dear = dear_flags;
199 vcpu->arch.queued_esr = esr_flags;
200 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DATA_STORAGE);
201}
202
8de12015
AG		 203void kvmppc_core_queue_itlb_miss(struct kvm_vcpu *vcpu)
204{
205 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_ITLB_MISS);
206}
207
208void kvmppc_core_queue_inst_storage(struct kvm_vcpu *vcpu, ulong esr_flags)
daf5e271
LY		 209{
210 vcpu->arch.queued_esr = esr_flags;
211 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_INST_STORAGE);
212}
213
011da899
AG		 214static void kvmppc_core_queue_alignment(struct kvm_vcpu *vcpu, ulong dear_flags,
215 ulong esr_flags)
216{
217 vcpu->arch.queued_dear = dear_flags;
218 vcpu->arch.queued_esr = esr_flags;
219 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_ALIGNMENT);
220}
221
daf5e271
LY		 222void kvmppc_core_queue_program(struct kvm_vcpu *vcpu, ulong esr_flags)
223{
224 vcpu->arch.queued_esr = esr_flags;
d4cf3892 225 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_PROGRAM);
9dd921cf
HB		 226}
227
228void kvmppc_core_queue_dec(struct kvm_vcpu *vcpu)
229{
d4cf3892 230 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DECREMENTER);
9dd921cf
HB		 231}
232
233int kvmppc_core_pending_dec(struct kvm_vcpu *vcpu)
234{
d4cf3892 235 return test_bit(BOOKE_IRQPRIO_DECREMENTER, &vcpu->arch.pending_exceptions);
9dd921cf
HB		 236}
237
7706664d
AG		 238void kvmppc_core_dequeue_dec(struct kvm_vcpu *vcpu)
239{
240 clear_bit(BOOKE_IRQPRIO_DECREMENTER, &vcpu->arch.pending_exceptions);
241}
242
9dd921cf
HB		 243void kvmppc_core_queue_external(struct kvm_vcpu *vcpu,
244 struct kvm_interrupt *irq)
245{
c5335f17
AG		 246 unsigned int prio = BOOKE_IRQPRIO_EXTERNAL;
247
248 if (irq->irq == KVM_INTERRUPT_SET_LEVEL)
249 prio = BOOKE_IRQPRIO_EXTERNAL_LEVEL;
250
251 kvmppc_booke_queue_irqprio(vcpu, prio);
9dd921cf
HB		 252}
253
4fe27d2a 254void kvmppc_core_dequeue_external(struct kvm_vcpu *vcpu)
4496f974
AG		 255{
256 clear_bit(BOOKE_IRQPRIO_EXTERNAL, &vcpu->arch.pending_exceptions);
c5335f17 257 clear_bit(BOOKE_IRQPRIO_EXTERNAL_LEVEL, &vcpu->arch.pending_exceptions);
4496f974
AG		 258}
259
f61c94bb
BB		 260static void kvmppc_core_queue_watchdog(struct kvm_vcpu *vcpu)
261{
262 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_WATCHDOG);
263}
264
265static void kvmppc_core_dequeue_watchdog(struct kvm_vcpu *vcpu)
266{
267 clear_bit(BOOKE_IRQPRIO_WATCHDOG, &vcpu->arch.pending_exceptions);
268}
269
d30f6e48
SW		 270static void set_guest_srr(struct kvm_vcpu *vcpu, unsigned long srr0, u32 srr1)
271{
31579eea
BB		 272 kvmppc_set_srr0(vcpu, srr0);
273 kvmppc_set_srr1(vcpu, srr1);
d30f6e48
SW		 274}
275
276static void set_guest_csrr(struct kvm_vcpu *vcpu, unsigned long srr0, u32 srr1)
277{
278 vcpu->arch.csrr0 = srr0;
279 vcpu->arch.csrr1 = srr1;
280}
281
282static void set_guest_dsrr(struct kvm_vcpu *vcpu, unsigned long srr0, u32 srr1)
283{
284 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC)) {
285 vcpu->arch.dsrr0 = srr0;
286 vcpu->arch.dsrr1 = srr1;
287 } else {
288 set_guest_csrr(vcpu, srr0, srr1);
289 }
290}
291
292static void set_guest_mcsrr(struct kvm_vcpu *vcpu, unsigned long srr0, u32 srr1)
293{
294 vcpu->arch.mcsrr0 = srr0;
295 vcpu->arch.mcsrr1 = srr1;
296}
297
d4cf3892
HB		 298/* Deliver the interrupt of the corresponding priority, if possible. */
299static int kvmppc_booke_irqprio_deliver(struct kvm_vcpu *vcpu,
300 unsigned int priority)
bbf45ba5 301{
d4cf3892 302 int allowed = 0;
79300f8c 303 ulong msr_mask = 0;
1c810636 304 bool update_esr = false, update_dear = false, update_epr = false;
5c6cedf4
AG		 305 ulong crit_raw = vcpu->arch.shared->critical;
306 ulong crit_r1 = kvmppc_get_gpr(vcpu, 1);
307 bool crit;
c5335f17 308 bool keep_irq = false;
d30f6e48 309 enum int_class int_class;
95e90b43 310 ulong new_msr = vcpu->arch.shared->msr;
5c6cedf4
AG		 311
312 /* Truncate crit indicators in 32 bit mode */
313 if (!(vcpu->arch.shared->msr & MSR_SF)) {
314 crit_raw &= 0xffffffff;
315 crit_r1 &= 0xffffffff;
316 }
317
318 /* Critical section when crit == r1 */
319 crit = (crit_raw == crit_r1);
320 /* ... and we're in supervisor mode */
321 crit = crit && !(vcpu->arch.shared->msr & MSR_PR);
d4cf3892 322
c5335f17
AG		 323 if (priority == BOOKE_IRQPRIO_EXTERNAL_LEVEL) {
324 priority = BOOKE_IRQPRIO_EXTERNAL;
325 keep_irq = true;
326 }
327
5df554ad 328 if ((priority == BOOKE_IRQPRIO_EXTERNAL) && vcpu->arch.epr_flags)
1c810636
AG		 329 update_epr = true;
330
d4cf3892 331 switch (priority) {
d4cf3892 332 case BOOKE_IRQPRIO_DTLB_MISS:
d4cf3892 333 case BOOKE_IRQPRIO_DATA_STORAGE:
011da899 334 case BOOKE_IRQPRIO_ALIGNMENT:
daf5e271
LY		 335 update_dear = true;
336 /* fall through */
d4cf3892 337 case BOOKE_IRQPRIO_INST_STORAGE:
daf5e271
LY		 338 case BOOKE_IRQPRIO_PROGRAM:
339 update_esr = true;
340 /* fall through */
341 case BOOKE_IRQPRIO_ITLB_MISS:
342 case BOOKE_IRQPRIO_SYSCALL:
d4cf3892 343 case BOOKE_IRQPRIO_FP_UNAVAIL:
bb3a8a17
HB		 344 case BOOKE_IRQPRIO_SPE_UNAVAIL:
345 case BOOKE_IRQPRIO_SPE_FP_DATA:
346 case BOOKE_IRQPRIO_SPE_FP_ROUND:
d4cf3892 347 case BOOKE_IRQPRIO_AP_UNAVAIL:
d4cf3892 348 allowed = 1;
79300f8c 349 msr_mask = MSR_CE | MSR_ME | MSR_DE;
d30f6e48 350 int_class = INT_CLASS_NONCRIT;
bbf45ba5 351 break;
f61c94bb 352 case BOOKE_IRQPRIO_WATCHDOG:
d4cf3892 353 case BOOKE_IRQPRIO_CRITICAL:
4ab96919 354 case BOOKE_IRQPRIO_DBELL_CRIT:
666e7252 355 allowed = vcpu->arch.shared->msr & MSR_CE;
d30f6e48 356 allowed = allowed && !crit;
79300f8c 357 msr_mask = MSR_ME;
d30f6e48 358 int_class = INT_CLASS_CRIT;
bbf45ba5 359 break;
d4cf3892 360 case BOOKE_IRQPRIO_MACHINE_CHECK:
666e7252 361 allowed = vcpu->arch.shared->msr & MSR_ME;
d30f6e48 362 allowed = allowed && !crit;
d30f6e48 363 int_class = INT_CLASS_MC;
bbf45ba5 364 break;
d4cf3892
HB		 365 case BOOKE_IRQPRIO_DECREMENTER:
366 case BOOKE_IRQPRIO_FIT:
dfd4d47e
SW		 367 keep_irq = true;
368 /* fall through */
369 case BOOKE_IRQPRIO_EXTERNAL:
4ab96919 370 case BOOKE_IRQPRIO_DBELL:
666e7252 371 allowed = vcpu->arch.shared->msr & MSR_EE;
5c6cedf4 372 allowed = allowed && !crit;
79300f8c 373 msr_mask = MSR_CE | MSR_ME | MSR_DE;
d30f6e48 374 int_class = INT_CLASS_NONCRIT;
bbf45ba5 375 break;
d4cf3892 376 case BOOKE_IRQPRIO_DEBUG:
666e7252 377 allowed = vcpu->arch.shared->msr & MSR_DE;
d30f6e48 378 allowed = allowed && !crit;
79300f8c 379 msr_mask = MSR_ME;
9fee7563
BB		 380 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC))
381 int_class = INT_CLASS_DBG;
382 else
383 int_class = INT_CLASS_CRIT;
384
bbf45ba5 385 break;
bbf45ba5
HB		 386 }
387
d4cf3892 388 if (allowed) {
d30f6e48
SW		 389 switch (int_class) {
390 case INT_CLASS_NONCRIT:
391 set_guest_srr(vcpu, vcpu->arch.pc,
392 vcpu->arch.shared->msr);
393 break;
394 case INT_CLASS_CRIT:
395 set_guest_csrr(vcpu, vcpu->arch.pc,
396 vcpu->arch.shared->msr);
397 break;
398 case INT_CLASS_DBG:
399 set_guest_dsrr(vcpu, vcpu->arch.pc,
400 vcpu->arch.shared->msr);
401 break;
402 case INT_CLASS_MC:
403 set_guest_mcsrr(vcpu, vcpu->arch.pc,
404 vcpu->arch.shared->msr);
405 break;
406 }
407
d4cf3892 408 vcpu->arch.pc = vcpu->arch.ivpr | vcpu->arch.ivor[priority];
daf5e271 409 if (update_esr == true)
dc168549 410 kvmppc_set_esr(vcpu, vcpu->arch.queued_esr);
daf5e271 411 if (update_dear == true)
a5414d4b 412 kvmppc_set_dar(vcpu, vcpu->arch.queued_dear);
5df554ad
SW		 413 if (update_epr == true) {
414 if (vcpu->arch.epr_flags & KVMPPC_EPR_USER)
415 kvm_make_request(KVM_REQ_EPR_EXIT, vcpu);
eb1e4f43
SW		 416 else if (vcpu->arch.epr_flags & KVMPPC_EPR_KERNEL) {
417 BUG_ON(vcpu->arch.irq_type != KVMPPC_IRQ_MPIC);
418 kvmppc_mpic_set_epr(vcpu);
419 }
5df554ad 420 }
95e90b43
MC		 421
422 new_msr &= msr_mask;
423#if defined(CONFIG_64BIT)
424 if (vcpu->arch.epcr & SPRN_EPCR_ICM)
425 new_msr |= MSR_CM;
426#endif
427 kvmppc_set_msr(vcpu, new_msr);
bbf45ba5 428
c5335f17
AG		 429 if (!keep_irq)
430 clear_bit(priority, &vcpu->arch.pending_exceptions);
bbf45ba5
HB		 431 }
432
d30f6e48
SW		 433#ifdef CONFIG_KVM_BOOKE_HV
434 /*
435 * If an interrupt is pending but masked, raise a guest doorbell
436 * so that we are notified when the guest enables the relevant
437 * MSR bit.
438 */
439 if (vcpu->arch.pending_exceptions & BOOKE_IRQMASK_EE)
440 kvmppc_set_pending_interrupt(vcpu, INT_CLASS_NONCRIT);
441 if (vcpu->arch.pending_exceptions & BOOKE_IRQMASK_CE)
442 kvmppc_set_pending_interrupt(vcpu, INT_CLASS_CRIT);
443 if (vcpu->arch.pending_exceptions & BOOKE_IRQPRIO_MACHINE_CHECK)
444 kvmppc_set_pending_interrupt(vcpu, INT_CLASS_MC);
445#endif
446
d4cf3892 447 return allowed;
bbf45ba5
HB		 448}
449
f61c94bb
BB		 450/*
451 * Return the number of jiffies until the next timeout. If the timeout is
452 * longer than the NEXT_TIMER_MAX_DELTA, then return NEXT_TIMER_MAX_DELTA
453 * because the larger value can break the timer APIs.
454 */
455static unsigned long watchdog_next_timeout(struct kvm_vcpu *vcpu)
456{
457 u64 tb, wdt_tb, wdt_ticks = 0;
458 u64 nr_jiffies = 0;
459 u32 period = TCR_GET_WP(vcpu->arch.tcr);
460
461 wdt_tb = 1ULL << (63 - period);
462 tb = get_tb();
463 /*
464 * The watchdog timeout will hapeen when TB bit corresponding
465 * to watchdog will toggle from 0 to 1.
466 */
467 if (tb & wdt_tb)
468 wdt_ticks = wdt_tb;
469
470 wdt_ticks += wdt_tb - (tb & (wdt_tb - 1));
471
472 /* Convert timebase ticks to jiffies */
473 nr_jiffies = wdt_ticks;
474
475 if (do_div(nr_jiffies, tb_ticks_per_jiffy))
476 nr_jiffies++;
477
478 return min_t(unsigned long long, nr_jiffies, NEXT_TIMER_MAX_DELTA);
479}
480
481static void arm_next_watchdog(struct kvm_vcpu *vcpu)
482{
483 unsigned long nr_jiffies;
484 unsigned long flags;
485
486 /*
487 * If TSR_ENW and TSR_WIS are not set then no need to exit to
488 * userspace, so clear the KVM_REQ_WATCHDOG request.
489 */
490 if ((vcpu->arch.tsr & (TSR_ENW | TSR_WIS)) != (TSR_ENW | TSR_WIS))
491 clear_bit(KVM_REQ_WATCHDOG, &vcpu->requests);
492
493 spin_lock_irqsave(&vcpu->arch.wdt_lock, flags);
494 nr_jiffies = watchdog_next_timeout(vcpu);
495 /*
496 * If the number of jiffies of watchdog timer >= NEXT_TIMER_MAX_DELTA
497 * then do not run the watchdog timer as this can break timer APIs.
498 */
499 if (nr_jiffies < NEXT_TIMER_MAX_DELTA)
500 mod_timer(&vcpu->arch.wdt_timer, jiffies + nr_jiffies);
501 else
502 del_timer(&vcpu->arch.wdt_timer);
503 spin_unlock_irqrestore(&vcpu->arch.wdt_lock, flags);
504}
505
506void kvmppc_watchdog_func(unsigned long data)
507{
508 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
509 u32 tsr, new_tsr;
510 int final;
511
512 do {
513 new_tsr = tsr = vcpu->arch.tsr;
514 final = 0;
515
516 /* Time out event */
517 if (tsr & TSR_ENW) {
518 if (tsr & TSR_WIS)
519 final = 1;
520 else
521 new_tsr = tsr | TSR_WIS;
522 } else {
523 new_tsr = tsr | TSR_ENW;
524 }
525 } while (cmpxchg(&vcpu->arch.tsr, tsr, new_tsr) != tsr);
526
527 if (new_tsr & TSR_WIS) {
528 smp_wmb();
529 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
530 kvm_vcpu_kick(vcpu);
531 }
532
533 /*
534 * If this is final watchdog expiry and some action is required
535 * then exit to userspace.
536 */
537 if (final && (vcpu->arch.tcr & TCR_WRC_MASK) &&
538 vcpu->arch.watchdog_enabled) {
539 smp_wmb();
540 kvm_make_request(KVM_REQ_WATCHDOG, vcpu);
541 kvm_vcpu_kick(vcpu);
542 }
543
544 /*
545 * Stop running the watchdog timer after final expiration to
546 * prevent the host from being flooded with timers if the
547 * guest sets a short period.
548 * Timers will resume when TSR/TCR is updated next time.
549 */
550 if (!final)
551 arm_next_watchdog(vcpu);
552}
553
dfd4d47e
SW		 554static void update_timer_ints(struct kvm_vcpu *vcpu)
555{
556 if ((vcpu->arch.tcr & TCR_DIE) && (vcpu->arch.tsr & TSR_DIS))
557 kvmppc_core_queue_dec(vcpu);
558 else
559 kvmppc_core_dequeue_dec(vcpu);
f61c94bb
BB		 560
561 if ((vcpu->arch.tcr & TCR_WIE) && (vcpu->arch.tsr & TSR_WIS))
562 kvmppc_core_queue_watchdog(vcpu);
563 else
564 kvmppc_core_dequeue_watchdog(vcpu);
dfd4d47e
SW		 565}
566
c59a6a3e 567static void kvmppc_core_check_exceptions(struct kvm_vcpu *vcpu)
bbf45ba5
HB		 568{
569 unsigned long *pending = &vcpu->arch.pending_exceptions;
bbf45ba5
HB		 570 unsigned int priority;
571
9ab80843 572 priority = __ffs(*pending);
8b3a00fc 573 while (priority < BOOKE_IRQPRIO_MAX) {
d4cf3892 574 if (kvmppc_booke_irqprio_deliver(vcpu, priority))
bbf45ba5 575 break;
bbf45ba5
HB		 576
577 priority = find_next_bit(pending,
578 BITS_PER_BYTE * sizeof(*pending),
579 priority + 1);
580 }
90bba358
AG		 581
582 /* Tell the guest about our interrupt status */
29ac26ef 583 vcpu->arch.shared->int_pending = !!*pending;
bbf45ba5
HB		 584}
585
c59a6a3e 586/* Check pending exceptions and deliver one, if possible. */
a8e4ef84 587int kvmppc_core_prepare_to_enter(struct kvm_vcpu *vcpu)
c59a6a3e 588{
a8e4ef84 589 int r = 0;
c59a6a3e
SW		 590 WARN_ON_ONCE(!irqs_disabled());
591
592 kvmppc_core_check_exceptions(vcpu);
593
b8c649a9
AG		 594 if (vcpu->requests) {
595 /* Exception delivery raised request; start over */
596 return 1;
597 }
598
c59a6a3e
SW		 599 if (vcpu->arch.shared->msr & MSR_WE) {
600 local_irq_enable();
601 kvm_vcpu_block(vcpu);
966cd0f3 602 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
6c85f52b 603 hard_irq_disable();
c59a6a3e
SW		 604
605 kvmppc_set_exit_type(vcpu, EMULATED_MTMSRWE_EXITS);
a8e4ef84 606 r = 1;
c59a6a3e 607 };
a8e4ef84
AG		 608
609 return r;
610}
611
7c973a2e 612int kvmppc_core_check_requests(struct kvm_vcpu *vcpu)
4ffc6356 613{
7c973a2e
AG		 614 int r = 1; /* Indicate we want to get back into the guest */
615
2d8185d4
AG		 616 if (kvm_check_request(KVM_REQ_PENDING_TIMER, vcpu))
617 update_timer_ints(vcpu);
862d31f7 618#if defined(CONFIG_KVM_E500V2) || defined(CONFIG_KVM_E500MC)
2d8185d4
AG		 619 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
620 kvmppc_core_flush_tlb(vcpu);
862d31f7 621#endif
7c973a2e 622
f61c94bb
BB		 623 if (kvm_check_request(KVM_REQ_WATCHDOG, vcpu)) {
624 vcpu->run->exit_reason = KVM_EXIT_WATCHDOG;
625 r = 0;
626 }
627
1c810636
AG		 628 if (kvm_check_request(KVM_REQ_EPR_EXIT, vcpu)) {
629 vcpu->run->epr.epr = 0;
630 vcpu->arch.epr_needed = true;
631 vcpu->run->exit_reason = KVM_EXIT_EPR;
632 r = 0;
633 }
634
7c973a2e 635 return r;
4ffc6356
AG		 636}
637
df6909e5
PM		 638int kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
639{
7ee78855 640 int ret, s;
f5f97210 641 struct debug_reg debug;
df6909e5 642
af8f38b3
AG		 643 if (!vcpu->arch.sane) {
644 kvm_run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
645 return -EINVAL;
646 }
647
7ee78855
AG		 648 s = kvmppc_prepare_to_enter(vcpu);
649 if (s <= 0) {
7ee78855 650 ret = s;
1d1ef222
SW		 651 goto out;
652 }
6c85f52b 653 /* interrupts now hard-disabled */
1d1ef222 654
8fae845f
SW		 655#ifdef CONFIG_PPC_FPU
656 /* Save userspace FPU state in stack */
657 enable_kernel_fp();
8fae845f
SW		 658
659 /*
660 * Since we can't trap on MSR_FP in GS-mode, we consider the guest
661 * as always using the FPU. Kernel usage of FP (via
662 * enable_kernel_fp()) in this thread must not occur while
663 * vcpu->fpu_active is set.
664 */
665 vcpu->fpu_active = 1;
666
667 kvmppc_load_guest_fp(vcpu);
668#endif
669
ce11e48b 670 /* Switch to guest debug context */
f5f97210
SW		 671 debug = vcpu->arch.shadow_dbg_reg;
672 switch_booke_debug_regs(&debug);
673 debug = current->thread.debug;
ce11e48b
BB		 674 current->thread.debug = vcpu->arch.shadow_dbg_reg;
675
08c9a188 676 vcpu->arch.pgdir = current->mm->pgd;
5f1c248f 677 kvmppc_fix_ee_before_entry();
f8941fbe 678
df6909e5 679 ret = __kvmppc_vcpu_run(kvm_run, vcpu);
8fae845f 680
24afa37b
AG		 681 /* No need for kvm_guest_exit. It's done in handle_exit.
682 We also get here with interrupts enabled. */
683
ce11e48b 684 /* Switch back to user space debug context */
f5f97210
SW		 685 switch_booke_debug_regs(&debug);
686 current->thread.debug = debug;
ce11e48b 687
8fae845f
SW		 688#ifdef CONFIG_PPC_FPU
689 kvmppc_save_guest_fp(vcpu);
690
691 vcpu->fpu_active = 0;
8fae845f
SW		 692#endif
693
1d1ef222 694out:
d69c6436 695 vcpu->mode = OUTSIDE_GUEST_MODE;
df6909e5
PM		 696 return ret;
697}
698
d30f6e48
SW		 699static int emulation_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
700{
701 enum emulation_result er;
702
703 er = kvmppc_emulate_instruction(run, vcpu);
704 switch (er) {
705 case EMULATE_DONE:
706 /* don't overwrite subtypes, just account kvm_stats */
707 kvmppc_account_exit_stat(vcpu, EMULATED_INST_EXITS);
708 /* Future optimization: only reload non-volatiles if
709 * they were actually modified by emulation. */
710 return RESUME_GUEST_NV;
711
51f04726
MC		 712 case EMULATE_AGAIN:
713 return RESUME_GUEST;
714
d30f6e48 715 case EMULATE_FAIL:
d30f6e48
SW		 716 printk(KERN_CRIT "%s: emulation at %lx failed (%08x)\n",
717 __func__, vcpu->arch.pc, vcpu->arch.last_inst);
718 /* For debugging, encode the failing instruction and
719 * report it to userspace. */
720 run->hw.hardware_exit_reason = ~0ULL << 32;
721 run->hw.hardware_exit_reason |= vcpu->arch.last_inst;
d1ff5499 722 kvmppc_core_queue_program(vcpu, ESR_PIL);
d30f6e48
SW		 723 return RESUME_HOST;
724
9b4f5308
BB		 725 case EMULATE_EXIT_USER:
726 return RESUME_HOST;
727
d30f6e48
SW		 728 default:
729 BUG();
730 }
731}
732
ce11e48b
BB		 733static int kvmppc_handle_debug(struct kvm_run *run, struct kvm_vcpu *vcpu)
734{
735 struct debug_reg *dbg_reg = &(vcpu->arch.shadow_dbg_reg);
736 u32 dbsr = vcpu->arch.dbsr;
737
738 run->debug.arch.status = 0;
739 run->debug.arch.address = vcpu->arch.pc;
740
741 if (dbsr & (DBSR_IAC1 | DBSR_IAC2 | DBSR_IAC3 | DBSR_IAC4)) {
742 run->debug.arch.status |= KVMPPC_DEBUG_BREAKPOINT;
743 } else {
744 if (dbsr & (DBSR_DAC1W | DBSR_DAC2W))
745 run->debug.arch.status |= KVMPPC_DEBUG_WATCH_WRITE;
746 else if (dbsr & (DBSR_DAC1R | DBSR_DAC2R))
747 run->debug.arch.status |= KVMPPC_DEBUG_WATCH_READ;
748 if (dbsr & (DBSR_DAC1R | DBSR_DAC1W))
749 run->debug.arch.address = dbg_reg->dac1;
750 else if (dbsr & (DBSR_DAC2R | DBSR_DAC2W))
751 run->debug.arch.address = dbg_reg->dac2;
752 }
753
754 return RESUME_HOST;
755}
756
4e642ccb 757static void kvmppc_fill_pt_regs(struct pt_regs *regs)
bbf45ba5 758{
4e642ccb 759 ulong r1, ip, msr, lr;
bbf45ba5 760
4e642ccb
AG		 761 asm("mr %0, 1" : "=r"(r1));
762 asm("mflr %0" : "=r"(lr));
763 asm("mfmsr %0" : "=r"(msr));
764 asm("bl 1f; 1: mflr %0" : "=r"(ip));
765
766 memset(regs, 0, sizeof(*regs));
767 regs->gpr[1] = r1;
768 regs->nip = ip;
769 regs->msr = msr;
770 regs->link = lr;
771}
772
6328e593
BB		 773/*
774 * For interrupts needed to be handled by host interrupt handlers,
775 * corresponding host handler are called from here in similar way
776 * (but not exact) as they are called from low level handler
777 * (such as from arch/powerpc/kernel/head_fsl_booke.S).
778 */
4e642ccb
AG		 779static void kvmppc_restart_interrupt(struct kvm_vcpu *vcpu,
780 unsigned int exit_nr)
781{
782 struct pt_regs regs;
73e75b41 783
d30f6e48
SW		 784 switch (exit_nr) {
785 case BOOKE_INTERRUPT_EXTERNAL:
4e642ccb
AG		 786 kvmppc_fill_pt_regs(&regs);
787 do_IRQ(&regs);
d30f6e48 788 break;
d30f6e48 789 case BOOKE_INTERRUPT_DECREMENTER:
4e642ccb
AG		 790 kvmppc_fill_pt_regs(&regs);
791 timer_interrupt(&regs);
d30f6e48 792 break;
5f17ce8b 793#if defined(CONFIG_PPC_DOORBELL)
d30f6e48 794 case BOOKE_INTERRUPT_DOORBELL:
4e642ccb
AG		 795 kvmppc_fill_pt_regs(&regs);
796 doorbell_exception(&regs);
d30f6e48
SW		 797 break;
798#endif
799 case BOOKE_INTERRUPT_MACHINE_CHECK:
800 /* FIXME */
801 break;
7cc1e8ee
AG		 802 case BOOKE_INTERRUPT_PERFORMANCE_MONITOR:
803 kvmppc_fill_pt_regs(&regs);
804 performance_monitor_exception(&regs);
805 break;
6328e593
BB		 806 case BOOKE_INTERRUPT_WATCHDOG:
807 kvmppc_fill_pt_regs(&regs);
808#ifdef CONFIG_BOOKE_WDT
809 WatchdogException(&regs);
810#else
811 unknown_exception(&regs);
812#endif
813 break;
814 case BOOKE_INTERRUPT_CRITICAL:
815 unknown_exception(&regs);
816 break;
ce11e48b
BB		 817 case BOOKE_INTERRUPT_DEBUG:
818 /* Save DBSR before preemption is enabled */
819 vcpu->arch.dbsr = mfspr(SPRN_DBSR);
820 kvmppc_clear_dbsr();
821 break;
d30f6e48 822 }
4e642ccb
AG		 823}
824
f5250471
MC		 825static int kvmppc_resume_inst_load(struct kvm_run *run, struct kvm_vcpu *vcpu,
826 enum emulation_result emulated, u32 last_inst)
827{
828 switch (emulated) {
829 case EMULATE_AGAIN:
830 return RESUME_GUEST;
831
832 case EMULATE_FAIL:
833 pr_debug("%s: load instruction from guest address %lx failed\n",
834 __func__, vcpu->arch.pc);
835 /* For debugging, encode the failing instruction and
836 * report it to userspace. */
837 run->hw.hardware_exit_reason = ~0ULL << 32;
838 run->hw.hardware_exit_reason |= last_inst;
839 kvmppc_core_queue_program(vcpu, ESR_PIL);
840 return RESUME_HOST;
841
842 default:
843 BUG();
844 }
845}
846
4e642ccb
AG		 847/**
848 * kvmppc_handle_exit
849 *
850 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
851 */
852int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
853 unsigned int exit_nr)
854{
855 int r = RESUME_HOST;
7ee78855 856 int s;
f1e89028 857 int idx;
f5250471
MC		 858 u32 last_inst = KVM_INST_FETCH_FAILED;
859 enum emulation_result emulated = EMULATE_DONE;
4e642ccb
AG		 860
861 /* update before a new last_exit_type is rewritten */
862 kvmppc_update_timing_stats(vcpu);
863
864 /* restart interrupts if they were meant for the host */
865 kvmppc_restart_interrupt(vcpu, exit_nr);
d30f6e48 866
f5250471
MC		 867 /*
868 * get last instruction before beeing preempted
869 * TODO: for e6500 check also BOOKE_INTERRUPT_LRAT_ERROR & ESR_DATA
870 */
871 switch (exit_nr) {
872 case BOOKE_INTERRUPT_DATA_STORAGE:
873 case BOOKE_INTERRUPT_DTLB_MISS:
874 case BOOKE_INTERRUPT_HV_PRIV:
875 emulated = kvmppc_get_last_inst(vcpu, false, &last_inst);
876 break;
877 default:
878 break;
879 }
880
bbf45ba5
HB		 881 local_irq_enable();
882
97c95059 883 trace_kvm_exit(exit_nr, vcpu);
706fb730 884 kvm_guest_exit();
97c95059 885
bbf45ba5
HB		 886 run->exit_reason = KVM_EXIT_UNKNOWN;
887 run->ready_for_interrupt_injection = 1;
888
f5250471
MC		 889 if (emulated != EMULATE_DONE) {
890 r = kvmppc_resume_inst_load(run, vcpu, emulated, last_inst);
891 goto out;
892 }
893
bbf45ba5
HB		 894 switch (exit_nr) {
895 case BOOKE_INTERRUPT_MACHINE_CHECK:
c35c9d84
AG		 896 printk("MACHINE CHECK: %lx\n", mfspr(SPRN_MCSR));
897 kvmppc_dump_vcpu(vcpu);
898 /* For debugging, send invalid exit reason to user space */
899 run->hw.hardware_exit_reason = ~1ULL << 32;
900 run->hw.hardware_exit_reason |= mfspr(SPRN_MCSR);
901 r = RESUME_HOST;
bbf45ba5
HB		 902 break;
903
904 case BOOKE_INTERRUPT_EXTERNAL:
7b701591 905 kvmppc_account_exit(vcpu, EXT_INTR_EXITS);
1b6766c7
HB		 906 r = RESUME_GUEST;
907 break;
908
bbf45ba5 909 case BOOKE_INTERRUPT_DECREMENTER:
7b701591 910 kvmppc_account_exit(vcpu, DEC_EXITS);
bbf45ba5
HB		 911 r = RESUME_GUEST;
912 break;
913
6328e593
BB		 914 case BOOKE_INTERRUPT_WATCHDOG:
915 r = RESUME_GUEST;
916 break;
917
d30f6e48
SW		 918 case BOOKE_INTERRUPT_DOORBELL:
919 kvmppc_account_exit(vcpu, DBELL_EXITS);
d30f6e48
SW		 920 r = RESUME_GUEST;
921 break;
922
923 case BOOKE_INTERRUPT_GUEST_DBELL_CRIT:
924 kvmppc_account_exit(vcpu, GDBELL_EXITS);
925
926 /*
927 * We are here because there is a pending guest interrupt
928 * which could not be delivered as MSR_CE or MSR_ME was not
929 * set. Once we break from here we will retry delivery.
930 */
931 r = RESUME_GUEST;
932 break;
933
934 case BOOKE_INTERRUPT_GUEST_DBELL:
935 kvmppc_account_exit(vcpu, GDBELL_EXITS);
936
937 /*
938 * We are here because there is a pending guest interrupt
939 * which could not be delivered as MSR_EE was not set. Once
940 * we break from here we will retry delivery.
941 */
942 r = RESUME_GUEST;
943 break;
944
95f2e921
AG		 945 case BOOKE_INTERRUPT_PERFORMANCE_MONITOR:
946 r = RESUME_GUEST;
947 break;
948
d30f6e48
SW		 949 case BOOKE_INTERRUPT_HV_PRIV:
950 r = emulation_exit(run, vcpu);
951 break;
952
bbf45ba5 953 case BOOKE_INTERRUPT_PROGRAM:
d30f6e48 954 if (vcpu->arch.shared->msr & (MSR_PR | MSR_GS)) {
0268597c
AG		 955 /*
956 * Program traps generated by user-level software must
957 * be handled by the guest kernel.
958 *
959 * In GS mode, hypervisor privileged instructions trap
960 * on BOOKE_INTERRUPT_HV_PRIV, not here, so these are
961 * actual program interrupts, handled by the guest.
962 */
daf5e271 963 kvmppc_core_queue_program(vcpu, vcpu->arch.fault_esr);
bbf45ba5 964 r = RESUME_GUEST;
7b701591 965 kvmppc_account_exit(vcpu, USR_PR_INST);
bbf45ba5
HB		 966 break;
967 }
968
d30f6e48 969 r = emulation_exit(run, vcpu);
bbf45ba5
HB		 970 break;
971
de368dce 972 case BOOKE_INTERRUPT_FP_UNAVAIL:
d4cf3892 973 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_FP_UNAVAIL);
7b701591 974 kvmppc_account_exit(vcpu, FP_UNAVAIL);
de368dce
CE		 975 r = RESUME_GUEST;
976 break;
977
4cd35f67
SW		 978#ifdef CONFIG_SPE
979 case BOOKE_INTERRUPT_SPE_UNAVAIL: {
980 if (vcpu->arch.shared->msr & MSR_SPE)
981 kvmppc_vcpu_enable_spe(vcpu);
982 else
983 kvmppc_booke_queue_irqprio(vcpu,
984 BOOKE_IRQPRIO_SPE_UNAVAIL);
bb3a8a17
HB		 985 r = RESUME_GUEST;
986 break;
4cd35f67 987 }
bb3a8a17
HB		 988
989 case BOOKE_INTERRUPT_SPE_FP_DATA:
990 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_SPE_FP_DATA);
991 r = RESUME_GUEST;
992 break;
993
994 case BOOKE_INTERRUPT_SPE_FP_ROUND:
995 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_SPE_FP_ROUND);
996 r = RESUME_GUEST;
997 break;
4cd35f67
SW		 998#else
999 case BOOKE_INTERRUPT_SPE_UNAVAIL:
1000 /*
1001 * Guest wants SPE, but host kernel doesn't support it. Send
1002 * an "unimplemented operation" program check to the guest.
1003 */
1004 kvmppc_core_queue_program(vcpu, ESR_PUO | ESR_SPV);
1005 r = RESUME_GUEST;
1006 break;
1007
1008 /*
1009 * These really should never happen without CONFIG_SPE,
1010 * as we should never enable the real MSR[SPE] in the guest.
1011 */
1012 case BOOKE_INTERRUPT_SPE_FP_DATA:
1013 case BOOKE_INTERRUPT_SPE_FP_ROUND:
1014 printk(KERN_CRIT "%s: unexpected SPE interrupt %u at %08lx\n",
1015 __func__, exit_nr, vcpu->arch.pc);
1016 run->hw.hardware_exit_reason = exit_nr;
1017 r = RESUME_HOST;
1018 break;
1019#endif
bb3a8a17 1020
bbf45ba5 1021 case BOOKE_INTERRUPT_DATA_STORAGE:
daf5e271
LY		 1022 kvmppc_core_queue_data_storage(vcpu, vcpu->arch.fault_dear,
1023 vcpu->arch.fault_esr);
7b701591 1024 kvmppc_account_exit(vcpu, DSI_EXITS);
bbf45ba5
HB		 1025 r = RESUME_GUEST;
1026 break;
1027
1028 case BOOKE_INTERRUPT_INST_STORAGE:
daf5e271 1029 kvmppc_core_queue_inst_storage(vcpu, vcpu->arch.fault_esr);
7b701591 1030 kvmppc_account_exit(vcpu, ISI_EXITS);
bbf45ba5
HB		 1031 r = RESUME_GUEST;
1032 break;
1033
011da899
AG		 1034 case BOOKE_INTERRUPT_ALIGNMENT:
1035 kvmppc_core_queue_alignment(vcpu, vcpu->arch.fault_dear,
1036 vcpu->arch.fault_esr);
1037 r = RESUME_GUEST;
1038 break;
1039
d30f6e48
SW		 1040#ifdef CONFIG_KVM_BOOKE_HV
1041 case BOOKE_INTERRUPT_HV_SYSCALL:
1042 if (!(vcpu->arch.shared->msr & MSR_PR)) {
1043 kvmppc_set_gpr(vcpu, 3, kvmppc_kvm_pv(vcpu));
1044 } else {
1045 /*
1046 * hcall from guest userspace -- send privileged
1047 * instruction program check.
1048 */
1049 kvmppc_core_queue_program(vcpu, ESR_PPR);
1050 }
1051
1052 r = RESUME_GUEST;
1053 break;
1054#else
bbf45ba5 1055 case BOOKE_INTERRUPT_SYSCALL:
2a342ed5
AG		 1056 if (!(vcpu->arch.shared->msr & MSR_PR) &&
1057 (((u32)kvmppc_get_gpr(vcpu, 0)) == KVM_SC_MAGIC_R0)) {
1058 /* KVM PV hypercalls */
1059 kvmppc_set_gpr(vcpu, 3, kvmppc_kvm_pv(vcpu));
1060 r = RESUME_GUEST;
1061 } else {
1062 /* Guest syscalls */
1063 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_SYSCALL);
1064 }
7b701591 1065 kvmppc_account_exit(vcpu, SYSCALL_EXITS);
bbf45ba5
HB		 1066 r = RESUME_GUEST;
1067 break;
d30f6e48 1068#endif
bbf45ba5
HB		 1069
1070 case BOOKE_INTERRUPT_DTLB_MISS: {
bbf45ba5 1071 unsigned long eaddr = vcpu->arch.fault_dear;
7924bd41 1072 int gtlb_index;
475e7cdd 1073 gpa_t gpaddr;
bbf45ba5
HB		 1074 gfn_t gfn;
1075
bf7ca4bd 1076#ifdef CONFIG_KVM_E500V2
a4cd8b23
SW		 1077 if (!(vcpu->arch.shared->msr & MSR_PR) &&
1078 (eaddr & PAGE_MASK) == vcpu->arch.magic_page_ea) {
1079 kvmppc_map_magic(vcpu);
1080 kvmppc_account_exit(vcpu, DTLB_VIRT_MISS_EXITS);
1081 r = RESUME_GUEST;
1082
1083 break;
1084 }
1085#endif
1086
bbf45ba5 1087 /* Check the guest TLB. */
fa86b8dd 1088 gtlb_index = kvmppc_mmu_dtlb_index(vcpu, eaddr);
7924bd41 1089 if (gtlb_index < 0) {
bbf45ba5 1090 /* The guest didn't have a mapping for it. */
daf5e271
LY		 1091 kvmppc_core_queue_dtlb_miss(vcpu,
1092 vcpu->arch.fault_dear,
1093 vcpu->arch.fault_esr);
b52a638c 1094 kvmppc_mmu_dtlb_miss(vcpu);
7b701591 1095 kvmppc_account_exit(vcpu, DTLB_REAL_MISS_EXITS);
bbf45ba5
HB		 1096 r = RESUME_GUEST;
1097 break;
1098 }
1099
f1e89028
SW		 1100 idx = srcu_read_lock(&vcpu->kvm->srcu);
1101
be8d1cae 1102 gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr);
475e7cdd 1103 gfn = gpaddr >> PAGE_SHIFT;
bbf45ba5
HB		 1104
1105 if (kvm_is_visible_gfn(vcpu->kvm, gfn)) {
1106 /* The guest TLB had a mapping, but the shadow TLB
1107 * didn't, and it is RAM. This could be because:
1108 * a) the entry is mapping the host kernel, or
1109 * b) the guest used a large mapping which we're faking
1110 * Either way, we need to satisfy the fault without
1111 * invoking the guest. */
58a96214 1112 kvmppc_mmu_map(vcpu, eaddr, gpaddr, gtlb_index);
7b701591 1113 kvmppc_account_exit(vcpu, DTLB_VIRT_MISS_EXITS);
bbf45ba5
HB		 1114 r = RESUME_GUEST;
1115 } else {
1116 /* Guest has mapped and accessed a page which is not
1117 * actually RAM. */
475e7cdd 1118 vcpu->arch.paddr_accessed = gpaddr;
6020c0f6 1119 vcpu->arch.vaddr_accessed = eaddr;
bbf45ba5 1120 r = kvmppc_emulate_mmio(run, vcpu);
7b701591 1121 kvmppc_account_exit(vcpu, MMIO_EXITS);
bbf45ba5
HB		 1122 }
1123
f1e89028 1124 srcu_read_unlock(&vcpu->kvm->srcu, idx);
bbf45ba5
HB		 1125 break;
1126 }
1127
1128 case BOOKE_INTERRUPT_ITLB_MISS: {
bbf45ba5 1129 unsigned long eaddr = vcpu->arch.pc;
89168618 1130 gpa_t gpaddr;
bbf45ba5 1131 gfn_t gfn;
7924bd41 1132 int gtlb_index;
bbf45ba5
HB		 1133
1134 r = RESUME_GUEST;
1135
1136 /* Check the guest TLB. */
fa86b8dd 1137 gtlb_index = kvmppc_mmu_itlb_index(vcpu, eaddr);
7924bd41 1138 if (gtlb_index < 0) {
bbf45ba5 1139 /* The guest didn't have a mapping for it. */
d4cf3892 1140 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_ITLB_MISS);
b52a638c 1141 kvmppc_mmu_itlb_miss(vcpu);
7b701591 1142 kvmppc_account_exit(vcpu, ITLB_REAL_MISS_EXITS);
bbf45ba5
HB		 1143 break;
1144 }
1145
7b701591 1146 kvmppc_account_exit(vcpu, ITLB_VIRT_MISS_EXITS);
bbf45ba5 1147
f1e89028
SW		 1148 idx = srcu_read_lock(&vcpu->kvm->srcu);
1149
be8d1cae 1150 gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr);
89168618 1151 gfn = gpaddr >> PAGE_SHIFT;
bbf45ba5
HB		 1152
1153 if (kvm_is_visible_gfn(vcpu->kvm, gfn)) {
1154 /* The guest TLB had a mapping, but the shadow TLB
1155 * didn't. This could be because:
1156 * a) the entry is mapping the host kernel, or
1157 * b) the guest used a large mapping which we're faking
1158 * Either way, we need to satisfy the fault without
1159 * invoking the guest. */
58a96214 1160 kvmppc_mmu_map(vcpu, eaddr, gpaddr, gtlb_index);
bbf45ba5
HB		 1161 } else {
1162 /* Guest mapped and leaped at non-RAM! */
d4cf3892 1163 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_MACHINE_CHECK);
bbf45ba5
HB		 1164 }
1165
f1e89028 1166 srcu_read_unlock(&vcpu->kvm->srcu, idx);
bbf45ba5
HB		 1167 break;
1168 }
1169
6a0ab738 1170 case BOOKE_INTERRUPT_DEBUG: {
ce11e48b
BB		 1171 r = kvmppc_handle_debug(run, vcpu);
1172 if (r == RESUME_HOST)
1173 run->exit_reason = KVM_EXIT_DEBUG;
7b701591 1174 kvmppc_account_exit(vcpu, DEBUG_EXITS);
6a0ab738
HB		 1175 break;
1176 }
1177
bbf45ba5
HB		 1178 default:
1179 printk(KERN_EMERG "exit_nr %d\n", exit_nr);
1180 BUG();
1181 }
1182
f5250471 1183out:
a8e4ef84
AG		 1184 /*
1185 * To avoid clobbering exit_reason, only check for signals if we
1186 * aren't already exiting to userspace for some other reason.
1187 */
03660ba2 1188 if (!(r & RESUME_HOST)) {
7ee78855 1189 s = kvmppc_prepare_to_enter(vcpu);
6c85f52b 1190 if (s <= 0)
7ee78855 1191 r = (s << 2) | RESUME_HOST | (r & RESUME_FLAG_NV);
6c85f52b
SW		 1192 else {
1193 /* interrupts now hard-disabled */
5f1c248f 1194 kvmppc_fix_ee_before_entry();
03660ba2 1195 }
bbf45ba5
HB		 1196 }
1197
1198 return r;
1199}
1200
d26f22c9
BB		 1201static void kvmppc_set_tsr(struct kvm_vcpu *vcpu, u32 new_tsr)
1202{
1203 u32 old_tsr = vcpu->arch.tsr;
1204
1205 vcpu->arch.tsr = new_tsr;
1206
1207 if ((old_tsr ^ vcpu->arch.tsr) & (TSR_ENW | TSR_WIS))
1208 arm_next_watchdog(vcpu);
1209
1210 update_timer_ints(vcpu);
1211}
1212
bbf45ba5
HB		 1213/* Initial guest state: 16MB mapping 0 -> 0, PC = 0, MSR = 0, R1 = 16MB */
1214int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
1215{
082decf2 1216 int i;
af8f38b3 1217 int r;
082decf2 1218
bbf45ba5 1219 vcpu->arch.pc = 0;
b5904972 1220 vcpu->arch.shared->pir = vcpu->vcpu_id;
8e5b26b5 1221 kvmppc_set_gpr(vcpu, 1, (16<<20) - 8); /* -8 for the callee-save LR slot */
d30f6e48 1222 kvmppc_set_msr(vcpu, 0);
bbf45ba5 1223
d30f6e48 1224#ifndef CONFIG_KVM_BOOKE_HV
ce11e48b 1225 vcpu->arch.shadow_msr = MSR_USER | MSR_IS | MSR_DS;
49dd2c49 1226 vcpu->arch.shadow_pid = 1;
d30f6e48
SW		 1227 vcpu->arch.shared->msr = 0;
1228#endif
49dd2c49 1229
082decf2
HB		 1230 /* Eye-catching numbers so we know if the guest takes an interrupt
1231 * before it's programmed its own IVPR/IVORs. */
bbf45ba5 1232 vcpu->arch.ivpr = 0x55550000;
082decf2
HB		 1233 for (i = 0; i < BOOKE_IRQPRIO_MAX; i++)
1234 vcpu->arch.ivor[i] = 0x7700 | i * 4;
bbf45ba5 1235
73e75b41
HB		 1236 kvmppc_init_timing_stats(vcpu);
1237
af8f38b3
AG		 1238 r = kvmppc_core_vcpu_setup(vcpu);
1239 kvmppc_sanity_check(vcpu);
1240 return r;
bbf45ba5
HB		 1241}
1242
f61c94bb
BB		 1243int kvmppc_subarch_vcpu_init(struct kvm_vcpu *vcpu)
1244{
1245 /* setup watchdog timer once */
1246 spin_lock_init(&vcpu->arch.wdt_lock);
1247 setup_timer(&vcpu->arch.wdt_timer, kvmppc_watchdog_func,
1248 (unsigned long)vcpu);
1249
1250 return 0;
1251}
1252
1253void kvmppc_subarch_vcpu_uninit(struct kvm_vcpu *vcpu)
1254{
1255 del_timer_sync(&vcpu->arch.wdt_timer);
1256}
1257
bbf45ba5
HB		 1258int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1259{
1260 int i;
1261
1262 regs->pc = vcpu->arch.pc;
992b5b29 1263 regs->cr = kvmppc_get_cr(vcpu);
bbf45ba5
HB		 1264 regs->ctr = vcpu->arch.ctr;
1265 regs->lr = vcpu->arch.lr;
992b5b29 1266 regs->xer = kvmppc_get_xer(vcpu);
666e7252 1267 regs->msr = vcpu->arch.shared->msr;
31579eea
BB		 1268 regs->srr0 = kvmppc_get_srr0(vcpu);
1269 regs->srr1 = kvmppc_get_srr1(vcpu);
bbf45ba5 1270 regs->pid = vcpu->arch.pid;
c1b8a01b
BB		 1271 regs->sprg0 = kvmppc_get_sprg0(vcpu);
1272 regs->sprg1 = kvmppc_get_sprg1(vcpu);
1273 regs->sprg2 = kvmppc_get_sprg2(vcpu);
1274 regs->sprg3 = kvmppc_get_sprg3(vcpu);
1275 regs->sprg4 = kvmppc_get_sprg4(vcpu);
1276 regs->sprg5 = kvmppc_get_sprg5(vcpu);
1277 regs->sprg6 = kvmppc_get_sprg6(vcpu);
1278 regs->sprg7 = kvmppc_get_sprg7(vcpu);
bbf45ba5
HB		 1279
1280 for (i = 0; i < ARRAY_SIZE(regs->gpr); i++)
8e5b26b5 1281 regs->gpr[i] = kvmppc_get_gpr(vcpu, i);
bbf45ba5
HB		 1282
1283 return 0;
1284}
1285
1286int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1287{
1288 int i;
1289
1290 vcpu->arch.pc = regs->pc;
992b5b29 1291 kvmppc_set_cr(vcpu, regs->cr);
bbf45ba5
HB		 1292 vcpu->arch.ctr = regs->ctr;
1293 vcpu->arch.lr = regs->lr;
992b5b29 1294 kvmppc_set_xer(vcpu, regs->xer);
b8fd68ac 1295 kvmppc_set_msr(vcpu, regs->msr);
31579eea
BB		 1296 kvmppc_set_srr0(vcpu, regs->srr0);
1297 kvmppc_set_srr1(vcpu, regs->srr1);
5ce941ee 1298 kvmppc_set_pid(vcpu, regs->pid);
c1b8a01b
BB		 1299 kvmppc_set_sprg0(vcpu, regs->sprg0);
1300 kvmppc_set_sprg1(vcpu, regs->sprg1);
1301 kvmppc_set_sprg2(vcpu, regs->sprg2);
1302 kvmppc_set_sprg3(vcpu, regs->sprg3);
1303 kvmppc_set_sprg4(vcpu, regs->sprg4);
1304 kvmppc_set_sprg5(vcpu, regs->sprg5);
1305 kvmppc_set_sprg6(vcpu, regs->sprg6);
1306 kvmppc_set_sprg7(vcpu, regs->sprg7);
bbf45ba5 1307
8e5b26b5
AG		 1308 for (i = 0; i < ARRAY_SIZE(regs->gpr); i++)
1309 kvmppc_set_gpr(vcpu, i, regs->gpr[i]);
bbf45ba5
HB		 1310
1311 return 0;
1312}
1313
5ce941ee
SW		 1314static void get_sregs_base(struct kvm_vcpu *vcpu,
1315 struct kvm_sregs *sregs)
1316{
1317 u64 tb = get_tb();
1318
1319 sregs->u.e.features |= KVM_SREGS_E_BASE;
1320
1321 sregs->u.e.csrr0 = vcpu->arch.csrr0;
1322 sregs->u.e.csrr1 = vcpu->arch.csrr1;
1323 sregs->u.e.mcsr = vcpu->arch.mcsr;
dc168549 1324 sregs->u.e.esr = kvmppc_get_esr(vcpu);
a5414d4b 1325 sregs->u.e.dear = kvmppc_get_dar(vcpu);
5ce941ee
SW		 1326 sregs->u.e.tsr = vcpu->arch.tsr;
1327 sregs->u.e.tcr = vcpu->arch.tcr;
1328 sregs->u.e.dec = kvmppc_get_dec(vcpu, tb);
1329 sregs->u.e.tb = tb;
1330 sregs->u.e.vrsave = vcpu->arch.vrsave;
1331}
1332
1333static int set_sregs_base(struct kvm_vcpu *vcpu,
1334 struct kvm_sregs *sregs)
1335{
1336 if (!(sregs->u.e.features & KVM_SREGS_E_BASE))
1337 return 0;
1338
1339 vcpu->arch.csrr0 = sregs->u.e.csrr0;
1340 vcpu->arch.csrr1 = sregs->u.e.csrr1;
1341 vcpu->arch.mcsr = sregs->u.e.mcsr;
dc168549 1342 kvmppc_set_esr(vcpu, sregs->u.e.esr);
a5414d4b 1343 kvmppc_set_dar(vcpu, sregs->u.e.dear);
5ce941ee 1344 vcpu->arch.vrsave = sregs->u.e.vrsave;
dfd4d47e 1345 kvmppc_set_tcr(vcpu, sregs->u.e.tcr);
5ce941ee 1346
dfd4d47e 1347 if (sregs->u.e.update_special & KVM_SREGS_E_UPDATE_DEC) {
5ce941ee 1348 vcpu->arch.dec = sregs->u.e.dec;
dfd4d47e
SW		 1349 kvmppc_emulate_dec(vcpu);
1350 }
5ce941ee 1351
d26f22c9
BB		 1352 if (sregs->u.e.update_special & KVM_SREGS_E_UPDATE_TSR)
1353 kvmppc_set_tsr(vcpu, sregs->u.e.tsr);
5ce941ee
SW		 1354
1355 return 0;
1356}
1357
1358static void get_sregs_arch206(struct kvm_vcpu *vcpu,
1359 struct kvm_sregs *sregs)
1360{
1361 sregs->u.e.features |= KVM_SREGS_E_ARCH206;
1362
841741f2 1363 sregs->u.e.pir = vcpu->vcpu_id;
5ce941ee
SW		 1364 sregs->u.e.mcsrr0 = vcpu->arch.mcsrr0;
1365 sregs->u.e.mcsrr1 = vcpu->arch.mcsrr1;
1366 sregs->u.e.decar = vcpu->arch.decar;
1367 sregs->u.e.ivpr = vcpu->arch.ivpr;
1368}
1369
1370static int set_sregs_arch206(struct kvm_vcpu *vcpu,
1371 struct kvm_sregs *sregs)
1372{
1373 if (!(sregs->u.e.features & KVM_SREGS_E_ARCH206))
1374 return 0;
1375
841741f2 1376 if (sregs->u.e.pir != vcpu->vcpu_id)
5ce941ee
SW		 1377 return -EINVAL;
1378
1379 vcpu->arch.mcsrr0 = sregs->u.e.mcsrr0;
1380 vcpu->arch.mcsrr1 = sregs->u.e.mcsrr1;
1381 vcpu->arch.decar = sregs->u.e.decar;
1382 vcpu->arch.ivpr = sregs->u.e.ivpr;
1383
1384 return 0;
1385}
1386
3a167bea 1387int kvmppc_get_sregs_ivor(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
5ce941ee
SW		 1388{
1389 sregs->u.e.features |= KVM_SREGS_E_IVOR;
1390
1391 sregs->u.e.ivor_low[0] = vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL];
1392 sregs->u.e.ivor_low[1] = vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK];
1393 sregs->u.e.ivor_low[2] = vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE];
1394 sregs->u.e.ivor_low[3] = vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE];
1395 sregs->u.e.ivor_low[4] = vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL];
1396 sregs->u.e.ivor_low[5] = vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT];
1397 sregs->u.e.ivor_low[6] = vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM];
1398 sregs->u.e.ivor_low[7] = vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL];
1399 sregs->u.e.ivor_low[8] = vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL];
1400 sregs->u.e.ivor_low[9] = vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL];
1401 sregs->u.e.ivor_low[10] = vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER];
1402 sregs->u.e.ivor_low[11] = vcpu->arch.ivor[BOOKE_IRQPRIO_FIT];
1403 sregs->u.e.ivor_low[12] = vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG];
1404 sregs->u.e.ivor_low[13] = vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS];
1405 sregs->u.e.ivor_low[14] = vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS];
1406 sregs->u.e.ivor_low[15] = vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG];
3a167bea 1407 return 0;
5ce941ee
SW		 1408}
1409
1410int kvmppc_set_sregs_ivor(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
1411{
1412 if (!(sregs->u.e.features & KVM_SREGS_E_IVOR))
1413 return 0;
1414
1415 vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL] = sregs->u.e.ivor_low[0];
1416 vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK] = sregs->u.e.ivor_low[1];
1417 vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE] = sregs->u.e.ivor_low[2];
1418 vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE] = sregs->u.e.ivor_low[3];
1419 vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL] = sregs->u.e.ivor_low[4];
1420 vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT] = sregs->u.e.ivor_low[5];
1421 vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM] = sregs->u.e.ivor_low[6];
1422 vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL] = sregs->u.e.ivor_low[7];
1423 vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL] = sregs->u.e.ivor_low[8];
1424 vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL] = sregs->u.e.ivor_low[9];
1425 vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER] = sregs->u.e.ivor_low[10];
1426 vcpu->arch.ivor[BOOKE_IRQPRIO_FIT] = sregs->u.e.ivor_low[11];
1427 vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG] = sregs->u.e.ivor_low[12];
1428 vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS] = sregs->u.e.ivor_low[13];
1429 vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS] = sregs->u.e.ivor_low[14];
1430 vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG] = sregs->u.e.ivor_low[15];
1431
1432 return 0;
1433}
1434
bbf45ba5
HB		 1435int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
1436 struct kvm_sregs *sregs)
1437{
5ce941ee
SW		 1438 sregs->pvr = vcpu->arch.pvr;
1439
1440 get_sregs_base(vcpu, sregs);
1441 get_sregs_arch206(vcpu, sregs);
cbbc58d4 1442 return vcpu->kvm->arch.kvm_ops->get_sregs(vcpu, sregs);
bbf45ba5
HB		 1443}
1444
1445int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
1446 struct kvm_sregs *sregs)
1447{
5ce941ee
SW		 1448 int ret;
1449
1450 if (vcpu->arch.pvr != sregs->pvr)
1451 return -EINVAL;
1452
1453 ret = set_sregs_base(vcpu, sregs);
1454 if (ret < 0)
1455 return ret;
1456
1457 ret = set_sregs_arch206(vcpu, sregs);
1458 if (ret < 0)
1459 return ret;
1460
cbbc58d4 1461 return vcpu->kvm->arch.kvm_ops->set_sregs(vcpu, sregs);
bbf45ba5
HB		 1462}
1463
31f3438e
PM		 1464int kvm_vcpu_ioctl_get_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
1465{
35b299e2
MC		 1466 int r = 0;
1467 union kvmppc_one_reg val;
1468 int size;
35b299e2
MC		 1469
1470 size = one_reg_size(reg->id);
1471 if (size > sizeof(val))
1472 return -EINVAL;
6df8d3fc
BB		 1473
1474 switch (reg->id) {
1475 case KVM_REG_PPC_IAC1:
547465ef
BB		 1476 val = get_reg_val(reg->id, vcpu->arch.dbg_reg.iac1);
1477 break;
6df8d3fc 1478 case KVM_REG_PPC_IAC2:
547465ef
BB		 1479 val = get_reg_val(reg->id, vcpu->arch.dbg_reg.iac2);
1480 break;
1481#if CONFIG_PPC_ADV_DEBUG_IACS > 2
6df8d3fc 1482 case KVM_REG_PPC_IAC3:
547465ef
BB		 1483 val = get_reg_val(reg->id, vcpu->arch.dbg_reg.iac3);
1484 break;
35b299e2 1485 case KVM_REG_PPC_IAC4:
547465ef 1486 val = get_reg_val(reg->id, vcpu->arch.dbg_reg.iac4);
6df8d3fc 1487 break;
547465ef 1488#endif
6df8d3fc 1489 case KVM_REG_PPC_DAC1:
547465ef
BB		 1490 val = get_reg_val(reg->id, vcpu->arch.dbg_reg.dac1);
1491 break;
35b299e2 1492 case KVM_REG_PPC_DAC2:
547465ef 1493 val = get_reg_val(reg->id, vcpu->arch.dbg_reg.dac2);
6df8d3fc 1494 break;
324b3e63 1495 case KVM_REG_PPC_EPR: {
34f754b9 1496 u32 epr = kvmppc_get_epr(vcpu);
35b299e2 1497 val = get_reg_val(reg->id, epr);
324b3e63
AG		 1498 break;
1499 }
352df1de
MC		 1500#if defined(CONFIG_64BIT)
1501 case KVM_REG_PPC_EPCR:
35b299e2 1502 val = get_reg_val(reg->id, vcpu->arch.epcr);
352df1de
MC		 1503 break;
1504#endif
78accda4 1505 case KVM_REG_PPC_TCR:
35b299e2 1506 val = get_reg_val(reg->id, vcpu->arch.tcr);
78accda4
BB		 1507 break;
1508 case KVM_REG_PPC_TSR:
35b299e2 1509 val = get_reg_val(reg->id, vcpu->arch.tsr);
78accda4 1510 break;
35b299e2 1511 case KVM_REG_PPC_DEBUG_INST:
b12c7841 1512 val = get_reg_val(reg->id, KVMPPC_INST_EHPRIV_DEBUG);
8c32a2ea 1513 break;
8b75cbbe
PM		 1514 case KVM_REG_PPC_VRSAVE:
1515 val = get_reg_val(reg->id, vcpu->arch.vrsave);
8c32a2ea 1516 break;
6df8d3fc 1517 default:
cbbc58d4 1518 r = vcpu->kvm->arch.kvm_ops->get_one_reg(vcpu, reg->id, &val);
6df8d3fc
BB		 1519 break;
1520 }
35b299e2
MC		 1521
1522 if (r)
1523 return r;
1524
1525 if (copy_to_user((char __user *)(unsigned long)reg->addr, &val, size))
1526 r = -EFAULT;
1527
6df8d3fc 1528 return r;
31f3438e
PM		 1529}
1530
1531int kvm_vcpu_ioctl_set_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
1532{
35b299e2
MC		 1533 int r = 0;
1534 union kvmppc_one_reg val;
1535 int size;
35b299e2
MC		 1536
1537 size = one_reg_size(reg->id);
1538 if (size > sizeof(val))
1539 return -EINVAL;
1540
1541 if (copy_from_user(&val, (char __user *)(unsigned long)reg->addr, size))
1542 return -EFAULT;
6df8d3fc
BB		 1543
1544 switch (reg->id) {
1545 case KVM_REG_PPC_IAC1:
547465ef
BB		 1546 vcpu->arch.dbg_reg.iac1 = set_reg_val(reg->id, val);
1547 break;
6df8d3fc 1548 case KVM_REG_PPC_IAC2:
547465ef
BB		 1549 vcpu->arch.dbg_reg.iac2 = set_reg_val(reg->id, val);
1550 break;
1551#if CONFIG_PPC_ADV_DEBUG_IACS > 2
6df8d3fc 1552 case KVM_REG_PPC_IAC3:
547465ef
BB		 1553 vcpu->arch.dbg_reg.iac3 = set_reg_val(reg->id, val);
1554 break;
35b299e2 1555 case KVM_REG_PPC_IAC4:
547465ef 1556 vcpu->arch.dbg_reg.iac4 = set_reg_val(reg->id, val);
6df8d3fc 1557 break;
547465ef 1558#endif
6df8d3fc 1559 case KVM_REG_PPC_DAC1:
547465ef
BB		 1560 vcpu->arch.dbg_reg.dac1 = set_reg_val(reg->id, val);
1561 break;
35b299e2 1562 case KVM_REG_PPC_DAC2:
547465ef 1563 vcpu->arch.dbg_reg.dac2 = set_reg_val(reg->id, val);
6df8d3fc 1564 break;
324b3e63 1565 case KVM_REG_PPC_EPR: {
35b299e2
MC		 1566 u32 new_epr = set_reg_val(reg->id, val);
1567 kvmppc_set_epr(vcpu, new_epr);
324b3e63
AG		 1568 break;
1569 }
352df1de
MC		 1570#if defined(CONFIG_64BIT)
1571 case KVM_REG_PPC_EPCR: {
35b299e2
MC		 1572 u32 new_epcr = set_reg_val(reg->id, val);
1573 kvmppc_set_epcr(vcpu, new_epcr);
352df1de
MC		 1574 break;
1575 }
1576#endif
78accda4 1577 case KVM_REG_PPC_OR_TSR: {
35b299e2 1578 u32 tsr_bits = set_reg_val(reg->id, val);
78accda4
BB		 1579 kvmppc_set_tsr_bits(vcpu, tsr_bits);
1580 break;
1581 }
1582 case KVM_REG_PPC_CLEAR_TSR: {
35b299e2 1583 u32 tsr_bits = set_reg_val(reg->id, val);
78accda4
BB		 1584 kvmppc_clr_tsr_bits(vcpu, tsr_bits);
1585 break;
1586 }
1587 case KVM_REG_PPC_TSR: {
35b299e2 1588 u32 tsr = set_reg_val(reg->id, val);
78accda4
BB		 1589 kvmppc_set_tsr(vcpu, tsr);
1590 break;
1591 }
1592 case KVM_REG_PPC_TCR: {
35b299e2 1593 u32 tcr = set_reg_val(reg->id, val);
78accda4
BB		 1594 kvmppc_set_tcr(vcpu, tcr);
1595 break;
1596 }
8b75cbbe
PM		 1597 case KVM_REG_PPC_VRSAVE:
1598 vcpu->arch.vrsave = set_reg_val(reg->id, val);
1599 break;
6df8d3fc 1600 default:
cbbc58d4 1601 r = vcpu->kvm->arch.kvm_ops->set_one_reg(vcpu, reg->id, &val);
6df8d3fc
BB		 1602 break;
1603 }
35b299e2 1604
6df8d3fc 1605 return r;
31f3438e
PM		 1606}
1607
bbf45ba5
HB		 1608int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1609{
1610 return -ENOTSUPP;
1611}
1612
1613int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1614{
1615 return -ENOTSUPP;
1616}
1617
bbf45ba5
HB		 1618int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1619 struct kvm_translation *tr)
1620{
98001d8d
AK		 1621 int r;
1622
98001d8d 1623 r = kvmppc_core_vcpu_translate(vcpu, tr);
98001d8d 1624 return r;
bbf45ba5 1625}
d9fbd03d 1626
4e755758
AG		 1627int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
1628{
1629 return -ENOTSUPP;
1630}
1631
5587027c 1632void kvmppc_core_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
a66b48c3
PM		 1633 struct kvm_memory_slot *dont)
1634{
1635}
1636
5587027c 1637int kvmppc_core_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
a66b48c3
PM		 1638 unsigned long npages)
1639{
1640 return 0;
1641}
1642
f9e0554d 1643int kvmppc_core_prepare_memory_region(struct kvm *kvm,
a66b48c3 1644 struct kvm_memory_slot *memslot,
f9e0554d
PM		 1645 struct kvm_userspace_memory_region *mem)
1646{
1647 return 0;
1648}
1649
1650void kvmppc_core_commit_memory_region(struct kvm *kvm,
dfe49dbd 1651 struct kvm_userspace_memory_region *mem,
8482644a 1652 const struct kvm_memory_slot *old)
dfe49dbd
PM		 1653{
1654}
1655
1656void kvmppc_core_flush_memslot(struct kvm *kvm, struct kvm_memory_slot *memslot)
f9e0554d
PM		 1657{
1658}
1659
38f98824
MC		 1660void kvmppc_set_epcr(struct kvm_vcpu *vcpu, u32 new_epcr)
1661{
1662#if defined(CONFIG_64BIT)
1663 vcpu->arch.epcr = new_epcr;
1664#ifdef CONFIG_KVM_BOOKE_HV
1665 vcpu->arch.shadow_epcr &= ~SPRN_EPCR_GICM;
1666 if (vcpu->arch.epcr & SPRN_EPCR_ICM)
1667 vcpu->arch.shadow_epcr |= SPRN_EPCR_GICM;
1668#endif
1669#endif
1670}
1671
dfd4d47e
SW		 1672void kvmppc_set_tcr(struct kvm_vcpu *vcpu, u32 new_tcr)
1673{
1674 vcpu->arch.tcr = new_tcr;
f61c94bb 1675 arm_next_watchdog(vcpu);
dfd4d47e
SW		 1676 update_timer_ints(vcpu);
1677}
1678
1679void kvmppc_set_tsr_bits(struct kvm_vcpu *vcpu, u32 tsr_bits)
1680{
1681 set_bits(tsr_bits, &vcpu->arch.tsr);
1682 smp_wmb();
1683 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1684 kvm_vcpu_kick(vcpu);
1685}
1686
1687void kvmppc_clr_tsr_bits(struct kvm_vcpu *vcpu, u32 tsr_bits)
1688{
1689 clear_bits(tsr_bits, &vcpu->arch.tsr);
f61c94bb
BB		 1690
1691 /*
1692 * We may have stopped the watchdog due to
1693 * being stuck on final expiration.
1694 */
1695 if (tsr_bits & (TSR_ENW | TSR_WIS))
1696 arm_next_watchdog(vcpu);
1697
dfd4d47e
SW		 1698 update_timer_ints(vcpu);
1699}
1700
1701void kvmppc_decrementer_func(unsigned long data)
1702{
1703 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
1704
21bd000a
BB		 1705 if (vcpu->arch.tcr & TCR_ARE) {
1706 vcpu->arch.dec = vcpu->arch.decar;
1707 kvmppc_emulate_dec(vcpu);
1708 }
1709
dfd4d47e
SW		 1710 kvmppc_set_tsr_bits(vcpu, TSR_DIS);
1711}
1712
ce11e48b
BB		 1713static int kvmppc_booke_add_breakpoint(struct debug_reg *dbg_reg,
1714 uint64_t addr, int index)
1715{
1716 switch (index) {
1717 case 0:
1718 dbg_reg->dbcr0 |= DBCR0_IAC1;
1719 dbg_reg->iac1 = addr;
1720 break;
1721 case 1:
1722 dbg_reg->dbcr0 |= DBCR0_IAC2;
1723 dbg_reg->iac2 = addr;
1724 break;
1725#if CONFIG_PPC_ADV_DEBUG_IACS > 2
1726 case 2:
1727 dbg_reg->dbcr0 |= DBCR0_IAC3;
1728 dbg_reg->iac3 = addr;
1729 break;
1730 case 3:
1731 dbg_reg->dbcr0 |= DBCR0_IAC4;
1732 dbg_reg->iac4 = addr;
1733 break;
1734#endif
1735 default:
1736 return -EINVAL;
1737 }
1738
1739 dbg_reg->dbcr0 |= DBCR0_IDM;
1740 return 0;
1741}
1742
1743static int kvmppc_booke_add_watchpoint(struct debug_reg *dbg_reg, uint64_t addr,
1744 int type, int index)
1745{
1746 switch (index) {
1747 case 0:
1748 if (type & KVMPPC_DEBUG_WATCH_READ)
1749 dbg_reg->dbcr0 |= DBCR0_DAC1R;
1750 if (type & KVMPPC_DEBUG_WATCH_WRITE)
1751 dbg_reg->dbcr0 |= DBCR0_DAC1W;
1752 dbg_reg->dac1 = addr;
1753 break;
1754 case 1:
1755 if (type & KVMPPC_DEBUG_WATCH_READ)
1756 dbg_reg->dbcr0 |= DBCR0_DAC2R;
1757 if (type & KVMPPC_DEBUG_WATCH_WRITE)
1758 dbg_reg->dbcr0 |= DBCR0_DAC2W;
1759 dbg_reg->dac2 = addr;
1760 break;
1761 default:
1762 return -EINVAL;
1763 }
1764
1765 dbg_reg->dbcr0 |= DBCR0_IDM;
1766 return 0;
1767}
1768void kvm_guest_protect_msr(struct kvm_vcpu *vcpu, ulong prot_bitmap, bool set)
1769{
1770 /* XXX: Add similar MSR protection for BookE-PR */
1771#ifdef CONFIG_KVM_BOOKE_HV
1772 BUG_ON(prot_bitmap & ~(MSRP_UCLEP | MSRP_DEP | MSRP_PMMP));
1773 if (set) {
1774 if (prot_bitmap & MSR_UCLE)
1775 vcpu->arch.shadow_msrp |= MSRP_UCLEP;
1776 if (prot_bitmap & MSR_DE)
1777 vcpu->arch.shadow_msrp |= MSRP_DEP;
1778 if (prot_bitmap & MSR_PMM)
1779 vcpu->arch.shadow_msrp |= MSRP_PMMP;
1780 } else {
1781 if (prot_bitmap & MSR_UCLE)
1782 vcpu->arch.shadow_msrp &= ~MSRP_UCLEP;
1783 if (prot_bitmap & MSR_DE)
1784 vcpu->arch.shadow_msrp &= ~MSRP_DEP;
1785 if (prot_bitmap & MSR_PMM)
1786 vcpu->arch.shadow_msrp &= ~MSRP_PMMP;
1787 }
1788#endif
1789}
1790
7d15c06f
AG		 1791int kvmppc_xlate(struct kvm_vcpu *vcpu, ulong eaddr, enum xlate_instdata xlid,
1792 enum xlate_readwrite xlrw, struct kvmppc_pte *pte)
1793{
1794 int gtlb_index;
1795 gpa_t gpaddr;
1796
1797#ifdef CONFIG_KVM_E500V2
1798 if (!(vcpu->arch.shared->msr & MSR_PR) &&
1799 (eaddr & PAGE_MASK) == vcpu->arch.magic_page_ea) {
1800 pte->eaddr = eaddr;
1801 pte->raddr = (vcpu->arch.magic_page_pa & PAGE_MASK) |
1802 (eaddr & ~PAGE_MASK);
1803 pte->vpage = eaddr >> PAGE_SHIFT;
1804 pte->may_read = true;
1805 pte->may_write = true;
1806 pte->may_execute = true;
1807
1808 return 0;
1809 }
1810#endif
1811
1812 /* Check the guest TLB. */
1813 switch (xlid) {
1814 case XLATE_INST:
1815 gtlb_index = kvmppc_mmu_itlb_index(vcpu, eaddr);
1816 break;
1817 case XLATE_DATA:
1818 gtlb_index = kvmppc_mmu_dtlb_index(vcpu, eaddr);
1819 break;
1820 default:
1821 BUG();
1822 }
1823
1824 /* Do we have a TLB entry at all? */
1825 if (gtlb_index < 0)
1826 return -ENOENT;
1827
1828 gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr);
1829
1830 pte->eaddr = eaddr;
1831 pte->raddr = (gpaddr & PAGE_MASK) | (eaddr & ~PAGE_MASK);
1832 pte->vpage = eaddr >> PAGE_SHIFT;
1833
1834 /* XXX read permissions from the guest TLB */
1835 pte->may_read = true;
1836 pte->may_write = true;
1837 pte->may_execute = true;
1838
1839 return 0;
1840}
1841
ce11e48b
BB		 1842int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
1843 struct kvm_guest_debug *dbg)
1844{
1845 struct debug_reg *dbg_reg;
1846 int n, b = 0, w = 0;
1847
1848 if (!(dbg->control & KVM_GUESTDBG_ENABLE)) {
1849 vcpu->arch.shadow_dbg_reg.dbcr0 = 0;
1850 vcpu->guest_debug = 0;
1851 kvm_guest_protect_msr(vcpu, MSR_DE, false);
1852 return 0;
1853 }
1854
1855 kvm_guest_protect_msr(vcpu, MSR_DE, true);
1856 vcpu->guest_debug = dbg->control;
1857 vcpu->arch.shadow_dbg_reg.dbcr0 = 0;
1858 /* Set DBCR0_EDM in guest visible DBCR0 register. */
1859 vcpu->arch.dbg_reg.dbcr0 = DBCR0_EDM;
1860
1861 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1862 vcpu->arch.shadow_dbg_reg.dbcr0 |= DBCR0_IDM | DBCR0_IC;
1863
1864 /* Code below handles only HW breakpoints */
1865 dbg_reg = &(vcpu->arch.shadow_dbg_reg);
1866
1867#ifdef CONFIG_KVM_BOOKE_HV
1868 /*
1869 * On BookE-HV (e500mc) the guest is always executed with MSR.GS=1
1870 * DBCR1 and DBCR2 are set to trigger debug events when MSR.PR is 0
1871 */
1872 dbg_reg->dbcr1 = 0;
1873 dbg_reg->dbcr2 = 0;
1874#else
1875 /*
1876 * On BookE-PR (e500v2) the guest is always executed with MSR.PR=1
1877 * We set DBCR1 and DBCR2 to only trigger debug events when MSR.PR
1878 * is set.
1879 */
1880 dbg_reg->dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | DBCR1_IAC3US |
1881 DBCR1_IAC4US;
1882 dbg_reg->dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
1883#endif
1884
1885 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1886 return 0;
1887
1888 for (n = 0; n < (KVMPPC_BOOKE_IAC_NUM + KVMPPC_BOOKE_DAC_NUM); n++) {
1889 uint64_t addr = dbg->arch.bp[n].addr;
1890 uint32_t type = dbg->arch.bp[n].type;
1891
1892 if (type == KVMPPC_DEBUG_NONE)
1893 continue;
1894
1895 if (type & !(KVMPPC_DEBUG_WATCH_READ |
1896 KVMPPC_DEBUG_WATCH_WRITE |
1897 KVMPPC_DEBUG_BREAKPOINT))
1898 return -EINVAL;
1899
1900 if (type & KVMPPC_DEBUG_BREAKPOINT) {
1901 /* Setting H/W breakpoint */
1902 if (kvmppc_booke_add_breakpoint(dbg_reg, addr, b++))
1903 return -EINVAL;
1904 } else {
1905 /* Setting H/W watchpoint */
1906 if (kvmppc_booke_add_watchpoint(dbg_reg, addr,
1907 type, w++))
1908 return -EINVAL;
1909 }
1910 }
1911
1912 return 0;
1913}
1914
94fa9d99
SW		 1915void kvmppc_booke_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1916{
a47d72f3 1917 vcpu->cpu = smp_processor_id();
d30f6e48 1918 current->thread.kvm_vcpu = vcpu;
94fa9d99
SW		 1919}
1920
1921void kvmppc_booke_vcpu_put(struct kvm_vcpu *vcpu)
1922{
d30f6e48 1923 current->thread.kvm_vcpu = NULL;
a47d72f3 1924 vcpu->cpu = -1;
ce11e48b
BB		 1925
1926 /* Clear pending debug event in DBSR */
1927 kvmppc_clear_dbsr();
94fa9d99
SW		 1928}
1929
3a167bea
AK		 1930void kvmppc_mmu_destroy(struct kvm_vcpu *vcpu)
1931{
cbbc58d4 1932 vcpu->kvm->arch.kvm_ops->mmu_destroy(vcpu);
3a167bea
AK		 1933}
1934
1935int kvmppc_core_init_vm(struct kvm *kvm)
1936{
cbbc58d4 1937 return kvm->arch.kvm_ops->init_vm(kvm);
3a167bea
AK		 1938}
1939
1940struct kvm_vcpu *kvmppc_core_vcpu_create(struct kvm *kvm, unsigned int id)
1941{
cbbc58d4 1942 return kvm->arch.kvm_ops->vcpu_create(kvm, id);
3a167bea
AK		 1943}
1944
1945void kvmppc_core_vcpu_free(struct kvm_vcpu *vcpu)
1946{
cbbc58d4 1947 vcpu->kvm->arch.kvm_ops->vcpu_free(vcpu);
3a167bea
AK		 1948}
1949
1950void kvmppc_core_destroy_vm(struct kvm *kvm)
1951{
cbbc58d4 1952 kvm->arch.kvm_ops->destroy_vm(kvm);
3a167bea
AK		 1953}
1954
1955void kvmppc_core_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1956{
cbbc58d4 1957 vcpu->kvm->arch.kvm_ops->vcpu_load(vcpu, cpu);
3a167bea
AK		 1958}
1959
1960void kvmppc_core_vcpu_put(struct kvm_vcpu *vcpu)
1961{
cbbc58d4 1962 vcpu->kvm->arch.kvm_ops->vcpu_put(vcpu);
94fa9d99
SW		 1963}
1964
2986b8c7 1965int __init kvmppc_booke_init(void)
d9fbd03d 1966{
d30f6e48 1967#ifndef CONFIG_KVM_BOOKE_HV
d9fbd03d 1968 unsigned long ivor[16];
1d542d9c 1969 unsigned long *handler = kvmppc_booke_handler_addr;
d9fbd03d 1970 unsigned long max_ivor = 0;
1d542d9c 1971 unsigned long handler_len;
d9fbd03d
HB		 1972 int i;
1973
1974 /* We install our own exception handlers by hijacking IVPR. IVPR must
1975 * be 16-bit aligned, so we need a 64KB allocation. */
1976 kvmppc_booke_handlers = __get_free_pages(GFP_KERNEL | __GFP_ZERO,
1977 VCPU_SIZE_ORDER);
1978 if (!kvmppc_booke_handlers)
1979 return -ENOMEM;
1980
1981 /* XXX make sure our handlers are smaller than Linux's */
1982
1983 /* Copy our interrupt handlers to match host IVORs. That way we don't
1984 * have to swap the IVORs on every guest/host transition. */
1985 ivor[0] = mfspr(SPRN_IVOR0);
1986 ivor[1] = mfspr(SPRN_IVOR1);
1987 ivor[2] = mfspr(SPRN_IVOR2);
1988 ivor[3] = mfspr(SPRN_IVOR3);
1989 ivor[4] = mfspr(SPRN_IVOR4);
1990 ivor[5] = mfspr(SPRN_IVOR5);
1991 ivor[6] = mfspr(SPRN_IVOR6);
1992 ivor[7] = mfspr(SPRN_IVOR7);
1993 ivor[8] = mfspr(SPRN_IVOR8);
1994 ivor[9] = mfspr(SPRN_IVOR9);
1995 ivor[10] = mfspr(SPRN_IVOR10);
1996 ivor[11] = mfspr(SPRN_IVOR11);
1997 ivor[12] = mfspr(SPRN_IVOR12);
1998 ivor[13] = mfspr(SPRN_IVOR13);
1999 ivor[14] = mfspr(SPRN_IVOR14);
2000 ivor[15] = mfspr(SPRN_IVOR15);
2001
2002 for (i = 0; i < 16; i++) {
2003 if (ivor[i] > max_ivor)
1d542d9c 2004 max_ivor = i;
d9fbd03d 2005
1d542d9c 2006 handler_len = handler[i + 1] - handler[i];
d9fbd03d 2007 memcpy((void *)kvmppc_booke_handlers + ivor[i],
1d542d9c 2008 (void *)handler[i], handler_len);
d9fbd03d 2009 }
1d542d9c
BB		 2010
2011 handler_len = handler[max_ivor + 1] - handler[max_ivor];
2012 flush_icache_range(kvmppc_booke_handlers, kvmppc_booke_handlers +
2013 ivor[max_ivor] + handler_len);
d30f6e48 2014#endif /* !BOOKE_HV */
db93f574 2015 return 0;
d9fbd03d
HB		 2016}
2017
db93f574 2018void __exit kvmppc_booke_exit(void)
d9fbd03d
HB		 2019{
2020 free_pages(kvmppc_booke_handlers, VCPU_SIZE_ORDER);
2021 kvm_exit();
2022}
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