]> git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blame - arch/powerpc/kvm/booke.c
kvm/ppc: Call trace_hardirqs_on before entry
[mirror_ubuntu-zesty-kernel.git] / arch / powerpc / kvm / booke.c
CommitLineData
bbf45ba5
HB
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
14 *
15 * Copyright IBM Corp. 2007
4cd35f67 16 * Copyright 2010-2011 Freescale Semiconductor, Inc.
bbf45ba5
HB
17 *
18 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
19 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
d30f6e48
SW
20 * Scott Wood <scottwood@freescale.com>
21 * Varun Sethi <varun.sethi@freescale.com>
bbf45ba5
HB
22 */
23
24#include <linux/errno.h>
25#include <linux/err.h>
26#include <linux/kvm_host.h>
5a0e3ad6 27#include <linux/gfp.h>
bbf45ba5
HB
28#include <linux/module.h>
29#include <linux/vmalloc.h>
30#include <linux/fs.h>
7924bd41 31
bbf45ba5
HB
32#include <asm/cputable.h>
33#include <asm/uaccess.h>
34#include <asm/kvm_ppc.h>
d9fbd03d 35#include <asm/cacheflush.h>
d30f6e48
SW
36#include <asm/dbell.h>
37#include <asm/hw_irq.h>
38#include <asm/irq.h>
b50df19c 39#include <asm/time.h>
bbf45ba5 40
d30f6e48 41#include "timing.h"
75f74f0d 42#include "booke.h"
97c95059 43#include "trace.h"
bbf45ba5 44
d9fbd03d
HB
45unsigned long kvmppc_booke_handlers;
46
bbf45ba5
HB
47#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
48#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
49
50struct kvm_stats_debugfs_item debugfs_entries[] = {
bbf45ba5
HB
51 { "mmio", VCPU_STAT(mmio_exits) },
52 { "dcr", VCPU_STAT(dcr_exits) },
53 { "sig", VCPU_STAT(signal_exits) },
bbf45ba5
HB
54 { "itlb_r", VCPU_STAT(itlb_real_miss_exits) },
55 { "itlb_v", VCPU_STAT(itlb_virt_miss_exits) },
56 { "dtlb_r", VCPU_STAT(dtlb_real_miss_exits) },
57 { "dtlb_v", VCPU_STAT(dtlb_virt_miss_exits) },
58 { "sysc", VCPU_STAT(syscall_exits) },
59 { "isi", VCPU_STAT(isi_exits) },
60 { "dsi", VCPU_STAT(dsi_exits) },
61 { "inst_emu", VCPU_STAT(emulated_inst_exits) },
62 { "dec", VCPU_STAT(dec_exits) },
63 { "ext_intr", VCPU_STAT(ext_intr_exits) },
45c5eb67 64 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
d30f6e48
SW
65 { "doorbell", VCPU_STAT(dbell_exits) },
66 { "guest doorbell", VCPU_STAT(gdbell_exits) },
cf1c5ca4 67 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
bbf45ba5
HB
68 { NULL }
69};
70
bbf45ba5
HB
71/* TODO: use vcpu_printf() */
72void kvmppc_dump_vcpu(struct kvm_vcpu *vcpu)
73{
74 int i;
75
666e7252 76 printk("pc: %08lx msr: %08llx\n", vcpu->arch.pc, vcpu->arch.shared->msr);
5cf8ca22 77 printk("lr: %08lx ctr: %08lx\n", vcpu->arch.lr, vcpu->arch.ctr);
de7906c3
AG
78 printk("srr0: %08llx srr1: %08llx\n", vcpu->arch.shared->srr0,
79 vcpu->arch.shared->srr1);
bbf45ba5
HB
80
81 printk("exceptions: %08lx\n", vcpu->arch.pending_exceptions);
82
83 for (i = 0; i < 32; i += 4) {
5cf8ca22 84 printk("gpr%02d: %08lx %08lx %08lx %08lx\n", i,
8e5b26b5
AG
85 kvmppc_get_gpr(vcpu, i),
86 kvmppc_get_gpr(vcpu, i+1),
87 kvmppc_get_gpr(vcpu, i+2),
88 kvmppc_get_gpr(vcpu, i+3));
bbf45ba5
HB
89 }
90}
91
4cd35f67
SW
92#ifdef CONFIG_SPE
93void kvmppc_vcpu_disable_spe(struct kvm_vcpu *vcpu)
94{
95 preempt_disable();
96 enable_kernel_spe();
97 kvmppc_save_guest_spe(vcpu);
98 vcpu->arch.shadow_msr &= ~MSR_SPE;
99 preempt_enable();
100}
101
102static void kvmppc_vcpu_enable_spe(struct kvm_vcpu *vcpu)
103{
104 preempt_disable();
105 enable_kernel_spe();
106 kvmppc_load_guest_spe(vcpu);
107 vcpu->arch.shadow_msr |= MSR_SPE;
108 preempt_enable();
109}
110
111static void kvmppc_vcpu_sync_spe(struct kvm_vcpu *vcpu)
112{
113 if (vcpu->arch.shared->msr & MSR_SPE) {
114 if (!(vcpu->arch.shadow_msr & MSR_SPE))
115 kvmppc_vcpu_enable_spe(vcpu);
116 } else if (vcpu->arch.shadow_msr & MSR_SPE) {
117 kvmppc_vcpu_disable_spe(vcpu);
118 }
119}
120#else
121static void kvmppc_vcpu_sync_spe(struct kvm_vcpu *vcpu)
122{
123}
124#endif
125
7a08c274
AG
126static void kvmppc_vcpu_sync_fpu(struct kvm_vcpu *vcpu)
127{
128#if defined(CONFIG_PPC_FPU) && !defined(CONFIG_KVM_BOOKE_HV)
129 /* We always treat the FP bit as enabled from the host
130 perspective, so only need to adjust the shadow MSR */
131 vcpu->arch.shadow_msr &= ~MSR_FP;
132 vcpu->arch.shadow_msr |= vcpu->arch.shared->msr & MSR_FP;
133#endif
134}
135
dd9ebf1f
LY
136/*
137 * Helper function for "full" MSR writes. No need to call this if only
138 * EE/CE/ME/DE/RI are changing.
139 */
4cd35f67
SW
140void kvmppc_set_msr(struct kvm_vcpu *vcpu, u32 new_msr)
141{
dd9ebf1f 142 u32 old_msr = vcpu->arch.shared->msr;
4cd35f67 143
d30f6e48
SW
144#ifdef CONFIG_KVM_BOOKE_HV
145 new_msr |= MSR_GS;
146#endif
147
4cd35f67
SW
148 vcpu->arch.shared->msr = new_msr;
149
dd9ebf1f 150 kvmppc_mmu_msr_notify(vcpu, old_msr);
4cd35f67 151 kvmppc_vcpu_sync_spe(vcpu);
7a08c274 152 kvmppc_vcpu_sync_fpu(vcpu);
4cd35f67
SW
153}
154
d4cf3892
HB
155static void kvmppc_booke_queue_irqprio(struct kvm_vcpu *vcpu,
156 unsigned int priority)
9dd921cf 157{
6346046c 158 trace_kvm_booke_queue_irqprio(vcpu, priority);
9dd921cf
HB
159 set_bit(priority, &vcpu->arch.pending_exceptions);
160}
161
daf5e271
LY
162static void kvmppc_core_queue_dtlb_miss(struct kvm_vcpu *vcpu,
163 ulong dear_flags, ulong esr_flags)
9dd921cf 164{
daf5e271
LY
165 vcpu->arch.queued_dear = dear_flags;
166 vcpu->arch.queued_esr = esr_flags;
167 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DTLB_MISS);
168}
169
170static void kvmppc_core_queue_data_storage(struct kvm_vcpu *vcpu,
171 ulong dear_flags, ulong esr_flags)
172{
173 vcpu->arch.queued_dear = dear_flags;
174 vcpu->arch.queued_esr = esr_flags;
175 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DATA_STORAGE);
176}
177
178static void kvmppc_core_queue_inst_storage(struct kvm_vcpu *vcpu,
179 ulong esr_flags)
180{
181 vcpu->arch.queued_esr = esr_flags;
182 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_INST_STORAGE);
183}
184
011da899
AG
185static void kvmppc_core_queue_alignment(struct kvm_vcpu *vcpu, ulong dear_flags,
186 ulong esr_flags)
187{
188 vcpu->arch.queued_dear = dear_flags;
189 vcpu->arch.queued_esr = esr_flags;
190 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_ALIGNMENT);
191}
192
daf5e271
LY
193void kvmppc_core_queue_program(struct kvm_vcpu *vcpu, ulong esr_flags)
194{
195 vcpu->arch.queued_esr = esr_flags;
d4cf3892 196 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_PROGRAM);
9dd921cf
HB
197}
198
199void kvmppc_core_queue_dec(struct kvm_vcpu *vcpu)
200{
d4cf3892 201 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DECREMENTER);
9dd921cf
HB
202}
203
204int kvmppc_core_pending_dec(struct kvm_vcpu *vcpu)
205{
d4cf3892 206 return test_bit(BOOKE_IRQPRIO_DECREMENTER, &vcpu->arch.pending_exceptions);
9dd921cf
HB
207}
208
7706664d
AG
209void kvmppc_core_dequeue_dec(struct kvm_vcpu *vcpu)
210{
211 clear_bit(BOOKE_IRQPRIO_DECREMENTER, &vcpu->arch.pending_exceptions);
212}
213
9dd921cf
HB
214void kvmppc_core_queue_external(struct kvm_vcpu *vcpu,
215 struct kvm_interrupt *irq)
216{
c5335f17
AG
217 unsigned int prio = BOOKE_IRQPRIO_EXTERNAL;
218
219 if (irq->irq == KVM_INTERRUPT_SET_LEVEL)
220 prio = BOOKE_IRQPRIO_EXTERNAL_LEVEL;
221
222 kvmppc_booke_queue_irqprio(vcpu, prio);
9dd921cf
HB
223}
224
4fe27d2a 225void kvmppc_core_dequeue_external(struct kvm_vcpu *vcpu)
4496f974
AG
226{
227 clear_bit(BOOKE_IRQPRIO_EXTERNAL, &vcpu->arch.pending_exceptions);
c5335f17 228 clear_bit(BOOKE_IRQPRIO_EXTERNAL_LEVEL, &vcpu->arch.pending_exceptions);
4496f974
AG
229}
230
f61c94bb
BB
231static void kvmppc_core_queue_watchdog(struct kvm_vcpu *vcpu)
232{
233 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_WATCHDOG);
234}
235
236static void kvmppc_core_dequeue_watchdog(struct kvm_vcpu *vcpu)
237{
238 clear_bit(BOOKE_IRQPRIO_WATCHDOG, &vcpu->arch.pending_exceptions);
239}
240
d30f6e48
SW
241static void set_guest_srr(struct kvm_vcpu *vcpu, unsigned long srr0, u32 srr1)
242{
243#ifdef CONFIG_KVM_BOOKE_HV
244 mtspr(SPRN_GSRR0, srr0);
245 mtspr(SPRN_GSRR1, srr1);
246#else
247 vcpu->arch.shared->srr0 = srr0;
248 vcpu->arch.shared->srr1 = srr1;
249#endif
250}
251
252static void set_guest_csrr(struct kvm_vcpu *vcpu, unsigned long srr0, u32 srr1)
253{
254 vcpu->arch.csrr0 = srr0;
255 vcpu->arch.csrr1 = srr1;
256}
257
258static void set_guest_dsrr(struct kvm_vcpu *vcpu, unsigned long srr0, u32 srr1)
259{
260 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC)) {
261 vcpu->arch.dsrr0 = srr0;
262 vcpu->arch.dsrr1 = srr1;
263 } else {
264 set_guest_csrr(vcpu, srr0, srr1);
265 }
266}
267
268static void set_guest_mcsrr(struct kvm_vcpu *vcpu, unsigned long srr0, u32 srr1)
269{
270 vcpu->arch.mcsrr0 = srr0;
271 vcpu->arch.mcsrr1 = srr1;
272}
273
274static unsigned long get_guest_dear(struct kvm_vcpu *vcpu)
275{
276#ifdef CONFIG_KVM_BOOKE_HV
277 return mfspr(SPRN_GDEAR);
278#else
279 return vcpu->arch.shared->dar;
280#endif
281}
282
283static void set_guest_dear(struct kvm_vcpu *vcpu, unsigned long dear)
284{
285#ifdef CONFIG_KVM_BOOKE_HV
286 mtspr(SPRN_GDEAR, dear);
287#else
288 vcpu->arch.shared->dar = dear;
289#endif
290}
291
292static unsigned long get_guest_esr(struct kvm_vcpu *vcpu)
293{
294#ifdef CONFIG_KVM_BOOKE_HV
295 return mfspr(SPRN_GESR);
296#else
297 return vcpu->arch.shared->esr;
298#endif
299}
300
301static void set_guest_esr(struct kvm_vcpu *vcpu, u32 esr)
302{
303#ifdef CONFIG_KVM_BOOKE_HV
304 mtspr(SPRN_GESR, esr);
305#else
306 vcpu->arch.shared->esr = esr;
307#endif
308}
309
324b3e63
AG
310static unsigned long get_guest_epr(struct kvm_vcpu *vcpu)
311{
312#ifdef CONFIG_KVM_BOOKE_HV
313 return mfspr(SPRN_GEPR);
314#else
315 return vcpu->arch.epr;
316#endif
317}
318
d4cf3892
HB
319/* Deliver the interrupt of the corresponding priority, if possible. */
320static int kvmppc_booke_irqprio_deliver(struct kvm_vcpu *vcpu,
321 unsigned int priority)
bbf45ba5 322{
d4cf3892 323 int allowed = 0;
79300f8c 324 ulong msr_mask = 0;
1c810636 325 bool update_esr = false, update_dear = false, update_epr = false;
5c6cedf4
AG
326 ulong crit_raw = vcpu->arch.shared->critical;
327 ulong crit_r1 = kvmppc_get_gpr(vcpu, 1);
328 bool crit;
c5335f17 329 bool keep_irq = false;
d30f6e48 330 enum int_class int_class;
95e90b43 331 ulong new_msr = vcpu->arch.shared->msr;
5c6cedf4
AG
332
333 /* Truncate crit indicators in 32 bit mode */
334 if (!(vcpu->arch.shared->msr & MSR_SF)) {
335 crit_raw &= 0xffffffff;
336 crit_r1 &= 0xffffffff;
337 }
338
339 /* Critical section when crit == r1 */
340 crit = (crit_raw == crit_r1);
341 /* ... and we're in supervisor mode */
342 crit = crit && !(vcpu->arch.shared->msr & MSR_PR);
d4cf3892 343
c5335f17
AG
344 if (priority == BOOKE_IRQPRIO_EXTERNAL_LEVEL) {
345 priority = BOOKE_IRQPRIO_EXTERNAL;
346 keep_irq = true;
347 }
348
5df554ad 349 if ((priority == BOOKE_IRQPRIO_EXTERNAL) && vcpu->arch.epr_flags)
1c810636
AG
350 update_epr = true;
351
d4cf3892 352 switch (priority) {
d4cf3892 353 case BOOKE_IRQPRIO_DTLB_MISS:
d4cf3892 354 case BOOKE_IRQPRIO_DATA_STORAGE:
011da899 355 case BOOKE_IRQPRIO_ALIGNMENT:
daf5e271
LY
356 update_dear = true;
357 /* fall through */
d4cf3892 358 case BOOKE_IRQPRIO_INST_STORAGE:
daf5e271
LY
359 case BOOKE_IRQPRIO_PROGRAM:
360 update_esr = true;
361 /* fall through */
362 case BOOKE_IRQPRIO_ITLB_MISS:
363 case BOOKE_IRQPRIO_SYSCALL:
d4cf3892 364 case BOOKE_IRQPRIO_FP_UNAVAIL:
bb3a8a17
HB
365 case BOOKE_IRQPRIO_SPE_UNAVAIL:
366 case BOOKE_IRQPRIO_SPE_FP_DATA:
367 case BOOKE_IRQPRIO_SPE_FP_ROUND:
d4cf3892 368 case BOOKE_IRQPRIO_AP_UNAVAIL:
d4cf3892 369 allowed = 1;
79300f8c 370 msr_mask = MSR_CE | MSR_ME | MSR_DE;
d30f6e48 371 int_class = INT_CLASS_NONCRIT;
bbf45ba5 372 break;
f61c94bb 373 case BOOKE_IRQPRIO_WATCHDOG:
d4cf3892 374 case BOOKE_IRQPRIO_CRITICAL:
4ab96919 375 case BOOKE_IRQPRIO_DBELL_CRIT:
666e7252 376 allowed = vcpu->arch.shared->msr & MSR_CE;
d30f6e48 377 allowed = allowed && !crit;
79300f8c 378 msr_mask = MSR_ME;
d30f6e48 379 int_class = INT_CLASS_CRIT;
bbf45ba5 380 break;
d4cf3892 381 case BOOKE_IRQPRIO_MACHINE_CHECK:
666e7252 382 allowed = vcpu->arch.shared->msr & MSR_ME;
d30f6e48 383 allowed = allowed && !crit;
d30f6e48 384 int_class = INT_CLASS_MC;
bbf45ba5 385 break;
d4cf3892
HB
386 case BOOKE_IRQPRIO_DECREMENTER:
387 case BOOKE_IRQPRIO_FIT:
dfd4d47e
SW
388 keep_irq = true;
389 /* fall through */
390 case BOOKE_IRQPRIO_EXTERNAL:
4ab96919 391 case BOOKE_IRQPRIO_DBELL:
666e7252 392 allowed = vcpu->arch.shared->msr & MSR_EE;
5c6cedf4 393 allowed = allowed && !crit;
79300f8c 394 msr_mask = MSR_CE | MSR_ME | MSR_DE;
d30f6e48 395 int_class = INT_CLASS_NONCRIT;
bbf45ba5 396 break;
d4cf3892 397 case BOOKE_IRQPRIO_DEBUG:
666e7252 398 allowed = vcpu->arch.shared->msr & MSR_DE;
d30f6e48 399 allowed = allowed && !crit;
79300f8c 400 msr_mask = MSR_ME;
d30f6e48 401 int_class = INT_CLASS_CRIT;
bbf45ba5 402 break;
bbf45ba5
HB
403 }
404
d4cf3892 405 if (allowed) {
d30f6e48
SW
406 switch (int_class) {
407 case INT_CLASS_NONCRIT:
408 set_guest_srr(vcpu, vcpu->arch.pc,
409 vcpu->arch.shared->msr);
410 break;
411 case INT_CLASS_CRIT:
412 set_guest_csrr(vcpu, vcpu->arch.pc,
413 vcpu->arch.shared->msr);
414 break;
415 case INT_CLASS_DBG:
416 set_guest_dsrr(vcpu, vcpu->arch.pc,
417 vcpu->arch.shared->msr);
418 break;
419 case INT_CLASS_MC:
420 set_guest_mcsrr(vcpu, vcpu->arch.pc,
421 vcpu->arch.shared->msr);
422 break;
423 }
424
d4cf3892 425 vcpu->arch.pc = vcpu->arch.ivpr | vcpu->arch.ivor[priority];
daf5e271 426 if (update_esr == true)
d30f6e48 427 set_guest_esr(vcpu, vcpu->arch.queued_esr);
daf5e271 428 if (update_dear == true)
d30f6e48 429 set_guest_dear(vcpu, vcpu->arch.queued_dear);
5df554ad
SW
430 if (update_epr == true) {
431 if (vcpu->arch.epr_flags & KVMPPC_EPR_USER)
432 kvm_make_request(KVM_REQ_EPR_EXIT, vcpu);
eb1e4f43
SW
433 else if (vcpu->arch.epr_flags & KVMPPC_EPR_KERNEL) {
434 BUG_ON(vcpu->arch.irq_type != KVMPPC_IRQ_MPIC);
435 kvmppc_mpic_set_epr(vcpu);
436 }
5df554ad 437 }
95e90b43
MC
438
439 new_msr &= msr_mask;
440#if defined(CONFIG_64BIT)
441 if (vcpu->arch.epcr & SPRN_EPCR_ICM)
442 new_msr |= MSR_CM;
443#endif
444 kvmppc_set_msr(vcpu, new_msr);
bbf45ba5 445
c5335f17
AG
446 if (!keep_irq)
447 clear_bit(priority, &vcpu->arch.pending_exceptions);
bbf45ba5
HB
448 }
449
d30f6e48
SW
450#ifdef CONFIG_KVM_BOOKE_HV
451 /*
452 * If an interrupt is pending but masked, raise a guest doorbell
453 * so that we are notified when the guest enables the relevant
454 * MSR bit.
455 */
456 if (vcpu->arch.pending_exceptions & BOOKE_IRQMASK_EE)
457 kvmppc_set_pending_interrupt(vcpu, INT_CLASS_NONCRIT);
458 if (vcpu->arch.pending_exceptions & BOOKE_IRQMASK_CE)
459 kvmppc_set_pending_interrupt(vcpu, INT_CLASS_CRIT);
460 if (vcpu->arch.pending_exceptions & BOOKE_IRQPRIO_MACHINE_CHECK)
461 kvmppc_set_pending_interrupt(vcpu, INT_CLASS_MC);
462#endif
463
d4cf3892 464 return allowed;
bbf45ba5
HB
465}
466
f61c94bb
BB
467/*
468 * Return the number of jiffies until the next timeout. If the timeout is
469 * longer than the NEXT_TIMER_MAX_DELTA, then return NEXT_TIMER_MAX_DELTA
470 * because the larger value can break the timer APIs.
471 */
472static unsigned long watchdog_next_timeout(struct kvm_vcpu *vcpu)
473{
474 u64 tb, wdt_tb, wdt_ticks = 0;
475 u64 nr_jiffies = 0;
476 u32 period = TCR_GET_WP(vcpu->arch.tcr);
477
478 wdt_tb = 1ULL << (63 - period);
479 tb = get_tb();
480 /*
481 * The watchdog timeout will hapeen when TB bit corresponding
482 * to watchdog will toggle from 0 to 1.
483 */
484 if (tb & wdt_tb)
485 wdt_ticks = wdt_tb;
486
487 wdt_ticks += wdt_tb - (tb & (wdt_tb - 1));
488
489 /* Convert timebase ticks to jiffies */
490 nr_jiffies = wdt_ticks;
491
492 if (do_div(nr_jiffies, tb_ticks_per_jiffy))
493 nr_jiffies++;
494
495 return min_t(unsigned long long, nr_jiffies, NEXT_TIMER_MAX_DELTA);
496}
497
498static void arm_next_watchdog(struct kvm_vcpu *vcpu)
499{
500 unsigned long nr_jiffies;
501 unsigned long flags;
502
503 /*
504 * If TSR_ENW and TSR_WIS are not set then no need to exit to
505 * userspace, so clear the KVM_REQ_WATCHDOG request.
506 */
507 if ((vcpu->arch.tsr & (TSR_ENW | TSR_WIS)) != (TSR_ENW | TSR_WIS))
508 clear_bit(KVM_REQ_WATCHDOG, &vcpu->requests);
509
510 spin_lock_irqsave(&vcpu->arch.wdt_lock, flags);
511 nr_jiffies = watchdog_next_timeout(vcpu);
512 /*
513 * If the number of jiffies of watchdog timer >= NEXT_TIMER_MAX_DELTA
514 * then do not run the watchdog timer as this can break timer APIs.
515 */
516 if (nr_jiffies < NEXT_TIMER_MAX_DELTA)
517 mod_timer(&vcpu->arch.wdt_timer, jiffies + nr_jiffies);
518 else
519 del_timer(&vcpu->arch.wdt_timer);
520 spin_unlock_irqrestore(&vcpu->arch.wdt_lock, flags);
521}
522
523void kvmppc_watchdog_func(unsigned long data)
524{
525 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
526 u32 tsr, new_tsr;
527 int final;
528
529 do {
530 new_tsr = tsr = vcpu->arch.tsr;
531 final = 0;
532
533 /* Time out event */
534 if (tsr & TSR_ENW) {
535 if (tsr & TSR_WIS)
536 final = 1;
537 else
538 new_tsr = tsr | TSR_WIS;
539 } else {
540 new_tsr = tsr | TSR_ENW;
541 }
542 } while (cmpxchg(&vcpu->arch.tsr, tsr, new_tsr) != tsr);
543
544 if (new_tsr & TSR_WIS) {
545 smp_wmb();
546 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
547 kvm_vcpu_kick(vcpu);
548 }
549
550 /*
551 * If this is final watchdog expiry and some action is required
552 * then exit to userspace.
553 */
554 if (final && (vcpu->arch.tcr & TCR_WRC_MASK) &&
555 vcpu->arch.watchdog_enabled) {
556 smp_wmb();
557 kvm_make_request(KVM_REQ_WATCHDOG, vcpu);
558 kvm_vcpu_kick(vcpu);
559 }
560
561 /*
562 * Stop running the watchdog timer after final expiration to
563 * prevent the host from being flooded with timers if the
564 * guest sets a short period.
565 * Timers will resume when TSR/TCR is updated next time.
566 */
567 if (!final)
568 arm_next_watchdog(vcpu);
569}
570
dfd4d47e
SW
571static void update_timer_ints(struct kvm_vcpu *vcpu)
572{
573 if ((vcpu->arch.tcr & TCR_DIE) && (vcpu->arch.tsr & TSR_DIS))
574 kvmppc_core_queue_dec(vcpu);
575 else
576 kvmppc_core_dequeue_dec(vcpu);
f61c94bb
BB
577
578 if ((vcpu->arch.tcr & TCR_WIE) && (vcpu->arch.tsr & TSR_WIS))
579 kvmppc_core_queue_watchdog(vcpu);
580 else
581 kvmppc_core_dequeue_watchdog(vcpu);
dfd4d47e
SW
582}
583
c59a6a3e 584static void kvmppc_core_check_exceptions(struct kvm_vcpu *vcpu)
bbf45ba5
HB
585{
586 unsigned long *pending = &vcpu->arch.pending_exceptions;
bbf45ba5
HB
587 unsigned int priority;
588
9ab80843 589 priority = __ffs(*pending);
8b3a00fc 590 while (priority < BOOKE_IRQPRIO_MAX) {
d4cf3892 591 if (kvmppc_booke_irqprio_deliver(vcpu, priority))
bbf45ba5 592 break;
bbf45ba5
HB
593
594 priority = find_next_bit(pending,
595 BITS_PER_BYTE * sizeof(*pending),
596 priority + 1);
597 }
90bba358
AG
598
599 /* Tell the guest about our interrupt status */
29ac26ef 600 vcpu->arch.shared->int_pending = !!*pending;
bbf45ba5
HB
601}
602
c59a6a3e 603/* Check pending exceptions and deliver one, if possible. */
a8e4ef84 604int kvmppc_core_prepare_to_enter(struct kvm_vcpu *vcpu)
c59a6a3e 605{
a8e4ef84 606 int r = 0;
c59a6a3e
SW
607 WARN_ON_ONCE(!irqs_disabled());
608
609 kvmppc_core_check_exceptions(vcpu);
610
b8c649a9
AG
611 if (vcpu->requests) {
612 /* Exception delivery raised request; start over */
613 return 1;
614 }
615
c59a6a3e
SW
616 if (vcpu->arch.shared->msr & MSR_WE) {
617 local_irq_enable();
618 kvm_vcpu_block(vcpu);
966cd0f3 619 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
c59a6a3e
SW
620 local_irq_disable();
621
622 kvmppc_set_exit_type(vcpu, EMULATED_MTMSRWE_EXITS);
a8e4ef84 623 r = 1;
c59a6a3e 624 };
a8e4ef84
AG
625
626 return r;
627}
628
7c973a2e 629int kvmppc_core_check_requests(struct kvm_vcpu *vcpu)
4ffc6356 630{
7c973a2e
AG
631 int r = 1; /* Indicate we want to get back into the guest */
632
2d8185d4
AG
633 if (kvm_check_request(KVM_REQ_PENDING_TIMER, vcpu))
634 update_timer_ints(vcpu);
862d31f7 635#if defined(CONFIG_KVM_E500V2) || defined(CONFIG_KVM_E500MC)
2d8185d4
AG
636 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
637 kvmppc_core_flush_tlb(vcpu);
862d31f7 638#endif
7c973a2e 639
f61c94bb
BB
640 if (kvm_check_request(KVM_REQ_WATCHDOG, vcpu)) {
641 vcpu->run->exit_reason = KVM_EXIT_WATCHDOG;
642 r = 0;
643 }
644
1c810636
AG
645 if (kvm_check_request(KVM_REQ_EPR_EXIT, vcpu)) {
646 vcpu->run->epr.epr = 0;
647 vcpu->arch.epr_needed = true;
648 vcpu->run->exit_reason = KVM_EXIT_EPR;
649 r = 0;
650 }
651
7c973a2e 652 return r;
4ffc6356
AG
653}
654
df6909e5
PM
655int kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
656{
7ee78855 657 int ret, s;
8fae845f
SW
658#ifdef CONFIG_PPC_FPU
659 unsigned int fpscr;
660 int fpexc_mode;
661 u64 fpr[32];
662#endif
df6909e5 663
af8f38b3
AG
664 if (!vcpu->arch.sane) {
665 kvm_run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
666 return -EINVAL;
667 }
668
df6909e5 669 local_irq_disable();
7ee78855
AG
670 s = kvmppc_prepare_to_enter(vcpu);
671 if (s <= 0) {
24afa37b 672 local_irq_enable();
7ee78855 673 ret = s;
1d1ef222
SW
674 goto out;
675 }
676
df6909e5 677 kvm_guest_enter();
8fae845f
SW
678
679#ifdef CONFIG_PPC_FPU
680 /* Save userspace FPU state in stack */
681 enable_kernel_fp();
682 memcpy(fpr, current->thread.fpr, sizeof(current->thread.fpr));
683 fpscr = current->thread.fpscr.val;
684 fpexc_mode = current->thread.fpexc_mode;
685
686 /* Restore guest FPU state to thread */
687 memcpy(current->thread.fpr, vcpu->arch.fpr, sizeof(vcpu->arch.fpr));
688 current->thread.fpscr.val = vcpu->arch.fpscr;
689
690 /*
691 * Since we can't trap on MSR_FP in GS-mode, we consider the guest
692 * as always using the FPU. Kernel usage of FP (via
693 * enable_kernel_fp()) in this thread must not occur while
694 * vcpu->fpu_active is set.
695 */
696 vcpu->fpu_active = 1;
697
698 kvmppc_load_guest_fp(vcpu);
699#endif
700
5f1c248f 701 kvmppc_fix_ee_before_entry();
f8941fbe 702
df6909e5 703 ret = __kvmppc_vcpu_run(kvm_run, vcpu);
8fae845f 704
24afa37b
AG
705 /* No need for kvm_guest_exit. It's done in handle_exit.
706 We also get here with interrupts enabled. */
707
8fae845f
SW
708#ifdef CONFIG_PPC_FPU
709 kvmppc_save_guest_fp(vcpu);
710
711 vcpu->fpu_active = 0;
712
713 /* Save guest FPU state from thread */
714 memcpy(vcpu->arch.fpr, current->thread.fpr, sizeof(vcpu->arch.fpr));
715 vcpu->arch.fpscr = current->thread.fpscr.val;
716
717 /* Restore userspace FPU state from stack */
718 memcpy(current->thread.fpr, fpr, sizeof(current->thread.fpr));
719 current->thread.fpscr.val = fpscr;
720 current->thread.fpexc_mode = fpexc_mode;
721#endif
722
1d1ef222 723out:
d69c6436 724 vcpu->mode = OUTSIDE_GUEST_MODE;
df6909e5
PM
725 return ret;
726}
727
d30f6e48
SW
728static int emulation_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
729{
730 enum emulation_result er;
731
732 er = kvmppc_emulate_instruction(run, vcpu);
733 switch (er) {
734 case EMULATE_DONE:
735 /* don't overwrite subtypes, just account kvm_stats */
736 kvmppc_account_exit_stat(vcpu, EMULATED_INST_EXITS);
737 /* Future optimization: only reload non-volatiles if
738 * they were actually modified by emulation. */
739 return RESUME_GUEST_NV;
740
741 case EMULATE_DO_DCR:
742 run->exit_reason = KVM_EXIT_DCR;
743 return RESUME_HOST;
744
745 case EMULATE_FAIL:
d30f6e48
SW
746 printk(KERN_CRIT "%s: emulation at %lx failed (%08x)\n",
747 __func__, vcpu->arch.pc, vcpu->arch.last_inst);
748 /* For debugging, encode the failing instruction and
749 * report it to userspace. */
750 run->hw.hardware_exit_reason = ~0ULL << 32;
751 run->hw.hardware_exit_reason |= vcpu->arch.last_inst;
d1ff5499 752 kvmppc_core_queue_program(vcpu, ESR_PIL);
d30f6e48
SW
753 return RESUME_HOST;
754
9b4f5308
BB
755 case EMULATE_EXIT_USER:
756 return RESUME_HOST;
757
d30f6e48
SW
758 default:
759 BUG();
760 }
761}
762
4e642ccb 763static void kvmppc_fill_pt_regs(struct pt_regs *regs)
bbf45ba5 764{
4e642ccb 765 ulong r1, ip, msr, lr;
bbf45ba5 766
4e642ccb
AG
767 asm("mr %0, 1" : "=r"(r1));
768 asm("mflr %0" : "=r"(lr));
769 asm("mfmsr %0" : "=r"(msr));
770 asm("bl 1f; 1: mflr %0" : "=r"(ip));
771
772 memset(regs, 0, sizeof(*regs));
773 regs->gpr[1] = r1;
774 regs->nip = ip;
775 regs->msr = msr;
776 regs->link = lr;
777}
778
6328e593
BB
779/*
780 * For interrupts needed to be handled by host interrupt handlers,
781 * corresponding host handler are called from here in similar way
782 * (but not exact) as they are called from low level handler
783 * (such as from arch/powerpc/kernel/head_fsl_booke.S).
784 */
4e642ccb
AG
785static void kvmppc_restart_interrupt(struct kvm_vcpu *vcpu,
786 unsigned int exit_nr)
787{
788 struct pt_regs regs;
73e75b41 789
d30f6e48
SW
790 switch (exit_nr) {
791 case BOOKE_INTERRUPT_EXTERNAL:
4e642ccb
AG
792 kvmppc_fill_pt_regs(&regs);
793 do_IRQ(&regs);
d30f6e48 794 break;
d30f6e48 795 case BOOKE_INTERRUPT_DECREMENTER:
4e642ccb
AG
796 kvmppc_fill_pt_regs(&regs);
797 timer_interrupt(&regs);
d30f6e48 798 break;
5f17ce8b 799#if defined(CONFIG_PPC_DOORBELL)
d30f6e48 800 case BOOKE_INTERRUPT_DOORBELL:
4e642ccb
AG
801 kvmppc_fill_pt_regs(&regs);
802 doorbell_exception(&regs);
d30f6e48
SW
803 break;
804#endif
805 case BOOKE_INTERRUPT_MACHINE_CHECK:
806 /* FIXME */
807 break;
7cc1e8ee
AG
808 case BOOKE_INTERRUPT_PERFORMANCE_MONITOR:
809 kvmppc_fill_pt_regs(&regs);
810 performance_monitor_exception(&regs);
811 break;
6328e593
BB
812 case BOOKE_INTERRUPT_WATCHDOG:
813 kvmppc_fill_pt_regs(&regs);
814#ifdef CONFIG_BOOKE_WDT
815 WatchdogException(&regs);
816#else
817 unknown_exception(&regs);
818#endif
819 break;
820 case BOOKE_INTERRUPT_CRITICAL:
821 unknown_exception(&regs);
822 break;
d30f6e48 823 }
4e642ccb
AG
824}
825
826/**
827 * kvmppc_handle_exit
828 *
829 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
830 */
831int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
832 unsigned int exit_nr)
833{
834 int r = RESUME_HOST;
7ee78855 835 int s;
f1e89028 836 int idx;
4e642ccb 837
7c11c0cc
SW
838#ifdef CONFIG_PPC64
839 WARN_ON(local_paca->irq_happened != 0);
840#endif
841
842 /*
843 * We enter with interrupts disabled in hardware, but
844 * we need to call hard_irq_disable anyway to ensure that
845 * the software state is kept in sync.
846 */
847 hard_irq_disable();
848
4e642ccb
AG
849 /* update before a new last_exit_type is rewritten */
850 kvmppc_update_timing_stats(vcpu);
851
852 /* restart interrupts if they were meant for the host */
853 kvmppc_restart_interrupt(vcpu, exit_nr);
d30f6e48 854
bbf45ba5
HB
855 local_irq_enable();
856
97c95059 857 trace_kvm_exit(exit_nr, vcpu);
706fb730 858 kvm_guest_exit();
97c95059 859
bbf45ba5
HB
860 run->exit_reason = KVM_EXIT_UNKNOWN;
861 run->ready_for_interrupt_injection = 1;
862
863 switch (exit_nr) {
864 case BOOKE_INTERRUPT_MACHINE_CHECK:
c35c9d84
AG
865 printk("MACHINE CHECK: %lx\n", mfspr(SPRN_MCSR));
866 kvmppc_dump_vcpu(vcpu);
867 /* For debugging, send invalid exit reason to user space */
868 run->hw.hardware_exit_reason = ~1ULL << 32;
869 run->hw.hardware_exit_reason |= mfspr(SPRN_MCSR);
870 r = RESUME_HOST;
bbf45ba5
HB
871 break;
872
873 case BOOKE_INTERRUPT_EXTERNAL:
7b701591 874 kvmppc_account_exit(vcpu, EXT_INTR_EXITS);
1b6766c7
HB
875 r = RESUME_GUEST;
876 break;
877
bbf45ba5 878 case BOOKE_INTERRUPT_DECREMENTER:
7b701591 879 kvmppc_account_exit(vcpu, DEC_EXITS);
bbf45ba5
HB
880 r = RESUME_GUEST;
881 break;
882
6328e593
BB
883 case BOOKE_INTERRUPT_WATCHDOG:
884 r = RESUME_GUEST;
885 break;
886
d30f6e48
SW
887 case BOOKE_INTERRUPT_DOORBELL:
888 kvmppc_account_exit(vcpu, DBELL_EXITS);
d30f6e48
SW
889 r = RESUME_GUEST;
890 break;
891
892 case BOOKE_INTERRUPT_GUEST_DBELL_CRIT:
893 kvmppc_account_exit(vcpu, GDBELL_EXITS);
894
895 /*
896 * We are here because there is a pending guest interrupt
897 * which could not be delivered as MSR_CE or MSR_ME was not
898 * set. Once we break from here we will retry delivery.
899 */
900 r = RESUME_GUEST;
901 break;
902
903 case BOOKE_INTERRUPT_GUEST_DBELL:
904 kvmppc_account_exit(vcpu, GDBELL_EXITS);
905
906 /*
907 * We are here because there is a pending guest interrupt
908 * which could not be delivered as MSR_EE was not set. Once
909 * we break from here we will retry delivery.
910 */
911 r = RESUME_GUEST;
912 break;
913
95f2e921
AG
914 case BOOKE_INTERRUPT_PERFORMANCE_MONITOR:
915 r = RESUME_GUEST;
916 break;
917
d30f6e48
SW
918 case BOOKE_INTERRUPT_HV_PRIV:
919 r = emulation_exit(run, vcpu);
920 break;
921
bbf45ba5 922 case BOOKE_INTERRUPT_PROGRAM:
d30f6e48 923 if (vcpu->arch.shared->msr & (MSR_PR | MSR_GS)) {
0268597c
AG
924 /*
925 * Program traps generated by user-level software must
926 * be handled by the guest kernel.
927 *
928 * In GS mode, hypervisor privileged instructions trap
929 * on BOOKE_INTERRUPT_HV_PRIV, not here, so these are
930 * actual program interrupts, handled by the guest.
931 */
daf5e271 932 kvmppc_core_queue_program(vcpu, vcpu->arch.fault_esr);
bbf45ba5 933 r = RESUME_GUEST;
7b701591 934 kvmppc_account_exit(vcpu, USR_PR_INST);
bbf45ba5
HB
935 break;
936 }
937
d30f6e48 938 r = emulation_exit(run, vcpu);
bbf45ba5
HB
939 break;
940
de368dce 941 case BOOKE_INTERRUPT_FP_UNAVAIL:
d4cf3892 942 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_FP_UNAVAIL);
7b701591 943 kvmppc_account_exit(vcpu, FP_UNAVAIL);
de368dce
CE
944 r = RESUME_GUEST;
945 break;
946
4cd35f67
SW
947#ifdef CONFIG_SPE
948 case BOOKE_INTERRUPT_SPE_UNAVAIL: {
949 if (vcpu->arch.shared->msr & MSR_SPE)
950 kvmppc_vcpu_enable_spe(vcpu);
951 else
952 kvmppc_booke_queue_irqprio(vcpu,
953 BOOKE_IRQPRIO_SPE_UNAVAIL);
bb3a8a17
HB
954 r = RESUME_GUEST;
955 break;
4cd35f67 956 }
bb3a8a17
HB
957
958 case BOOKE_INTERRUPT_SPE_FP_DATA:
959 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_SPE_FP_DATA);
960 r = RESUME_GUEST;
961 break;
962
963 case BOOKE_INTERRUPT_SPE_FP_ROUND:
964 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_SPE_FP_ROUND);
965 r = RESUME_GUEST;
966 break;
4cd35f67
SW
967#else
968 case BOOKE_INTERRUPT_SPE_UNAVAIL:
969 /*
970 * Guest wants SPE, but host kernel doesn't support it. Send
971 * an "unimplemented operation" program check to the guest.
972 */
973 kvmppc_core_queue_program(vcpu, ESR_PUO | ESR_SPV);
974 r = RESUME_GUEST;
975 break;
976
977 /*
978 * These really should never happen without CONFIG_SPE,
979 * as we should never enable the real MSR[SPE] in the guest.
980 */
981 case BOOKE_INTERRUPT_SPE_FP_DATA:
982 case BOOKE_INTERRUPT_SPE_FP_ROUND:
983 printk(KERN_CRIT "%s: unexpected SPE interrupt %u at %08lx\n",
984 __func__, exit_nr, vcpu->arch.pc);
985 run->hw.hardware_exit_reason = exit_nr;
986 r = RESUME_HOST;
987 break;
988#endif
bb3a8a17 989
bbf45ba5 990 case BOOKE_INTERRUPT_DATA_STORAGE:
daf5e271
LY
991 kvmppc_core_queue_data_storage(vcpu, vcpu->arch.fault_dear,
992 vcpu->arch.fault_esr);
7b701591 993 kvmppc_account_exit(vcpu, DSI_EXITS);
bbf45ba5
HB
994 r = RESUME_GUEST;
995 break;
996
997 case BOOKE_INTERRUPT_INST_STORAGE:
daf5e271 998 kvmppc_core_queue_inst_storage(vcpu, vcpu->arch.fault_esr);
7b701591 999 kvmppc_account_exit(vcpu, ISI_EXITS);
bbf45ba5
HB
1000 r = RESUME_GUEST;
1001 break;
1002
011da899
AG
1003 case BOOKE_INTERRUPT_ALIGNMENT:
1004 kvmppc_core_queue_alignment(vcpu, vcpu->arch.fault_dear,
1005 vcpu->arch.fault_esr);
1006 r = RESUME_GUEST;
1007 break;
1008
d30f6e48
SW
1009#ifdef CONFIG_KVM_BOOKE_HV
1010 case BOOKE_INTERRUPT_HV_SYSCALL:
1011 if (!(vcpu->arch.shared->msr & MSR_PR)) {
1012 kvmppc_set_gpr(vcpu, 3, kvmppc_kvm_pv(vcpu));
1013 } else {
1014 /*
1015 * hcall from guest userspace -- send privileged
1016 * instruction program check.
1017 */
1018 kvmppc_core_queue_program(vcpu, ESR_PPR);
1019 }
1020
1021 r = RESUME_GUEST;
1022 break;
1023#else
bbf45ba5 1024 case BOOKE_INTERRUPT_SYSCALL:
2a342ed5
AG
1025 if (!(vcpu->arch.shared->msr & MSR_PR) &&
1026 (((u32)kvmppc_get_gpr(vcpu, 0)) == KVM_SC_MAGIC_R0)) {
1027 /* KVM PV hypercalls */
1028 kvmppc_set_gpr(vcpu, 3, kvmppc_kvm_pv(vcpu));
1029 r = RESUME_GUEST;
1030 } else {
1031 /* Guest syscalls */
1032 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_SYSCALL);
1033 }
7b701591 1034 kvmppc_account_exit(vcpu, SYSCALL_EXITS);
bbf45ba5
HB
1035 r = RESUME_GUEST;
1036 break;
d30f6e48 1037#endif
bbf45ba5
HB
1038
1039 case BOOKE_INTERRUPT_DTLB_MISS: {
bbf45ba5 1040 unsigned long eaddr = vcpu->arch.fault_dear;
7924bd41 1041 int gtlb_index;
475e7cdd 1042 gpa_t gpaddr;
bbf45ba5
HB
1043 gfn_t gfn;
1044
bf7ca4bd 1045#ifdef CONFIG_KVM_E500V2
a4cd8b23
SW
1046 if (!(vcpu->arch.shared->msr & MSR_PR) &&
1047 (eaddr & PAGE_MASK) == vcpu->arch.magic_page_ea) {
1048 kvmppc_map_magic(vcpu);
1049 kvmppc_account_exit(vcpu, DTLB_VIRT_MISS_EXITS);
1050 r = RESUME_GUEST;
1051
1052 break;
1053 }
1054#endif
1055
bbf45ba5 1056 /* Check the guest TLB. */
fa86b8dd 1057 gtlb_index = kvmppc_mmu_dtlb_index(vcpu, eaddr);
7924bd41 1058 if (gtlb_index < 0) {
bbf45ba5 1059 /* The guest didn't have a mapping for it. */
daf5e271
LY
1060 kvmppc_core_queue_dtlb_miss(vcpu,
1061 vcpu->arch.fault_dear,
1062 vcpu->arch.fault_esr);
b52a638c 1063 kvmppc_mmu_dtlb_miss(vcpu);
7b701591 1064 kvmppc_account_exit(vcpu, DTLB_REAL_MISS_EXITS);
bbf45ba5
HB
1065 r = RESUME_GUEST;
1066 break;
1067 }
1068
f1e89028
SW
1069 idx = srcu_read_lock(&vcpu->kvm->srcu);
1070
be8d1cae 1071 gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr);
475e7cdd 1072 gfn = gpaddr >> PAGE_SHIFT;
bbf45ba5
HB
1073
1074 if (kvm_is_visible_gfn(vcpu->kvm, gfn)) {
1075 /* The guest TLB had a mapping, but the shadow TLB
1076 * didn't, and it is RAM. This could be because:
1077 * a) the entry is mapping the host kernel, or
1078 * b) the guest used a large mapping which we're faking
1079 * Either way, we need to satisfy the fault without
1080 * invoking the guest. */
58a96214 1081 kvmppc_mmu_map(vcpu, eaddr, gpaddr, gtlb_index);
7b701591 1082 kvmppc_account_exit(vcpu, DTLB_VIRT_MISS_EXITS);
bbf45ba5
HB
1083 r = RESUME_GUEST;
1084 } else {
1085 /* Guest has mapped and accessed a page which is not
1086 * actually RAM. */
475e7cdd 1087 vcpu->arch.paddr_accessed = gpaddr;
6020c0f6 1088 vcpu->arch.vaddr_accessed = eaddr;
bbf45ba5 1089 r = kvmppc_emulate_mmio(run, vcpu);
7b701591 1090 kvmppc_account_exit(vcpu, MMIO_EXITS);
bbf45ba5
HB
1091 }
1092
f1e89028 1093 srcu_read_unlock(&vcpu->kvm->srcu, idx);
bbf45ba5
HB
1094 break;
1095 }
1096
1097 case BOOKE_INTERRUPT_ITLB_MISS: {
bbf45ba5 1098 unsigned long eaddr = vcpu->arch.pc;
89168618 1099 gpa_t gpaddr;
bbf45ba5 1100 gfn_t gfn;
7924bd41 1101 int gtlb_index;
bbf45ba5
HB
1102
1103 r = RESUME_GUEST;
1104
1105 /* Check the guest TLB. */
fa86b8dd 1106 gtlb_index = kvmppc_mmu_itlb_index(vcpu, eaddr);
7924bd41 1107 if (gtlb_index < 0) {
bbf45ba5 1108 /* The guest didn't have a mapping for it. */
d4cf3892 1109 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_ITLB_MISS);
b52a638c 1110 kvmppc_mmu_itlb_miss(vcpu);
7b701591 1111 kvmppc_account_exit(vcpu, ITLB_REAL_MISS_EXITS);
bbf45ba5
HB
1112 break;
1113 }
1114
7b701591 1115 kvmppc_account_exit(vcpu, ITLB_VIRT_MISS_EXITS);
bbf45ba5 1116
f1e89028
SW
1117 idx = srcu_read_lock(&vcpu->kvm->srcu);
1118
be8d1cae 1119 gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr);
89168618 1120 gfn = gpaddr >> PAGE_SHIFT;
bbf45ba5
HB
1121
1122 if (kvm_is_visible_gfn(vcpu->kvm, gfn)) {
1123 /* The guest TLB had a mapping, but the shadow TLB
1124 * didn't. This could be because:
1125 * a) the entry is mapping the host kernel, or
1126 * b) the guest used a large mapping which we're faking
1127 * Either way, we need to satisfy the fault without
1128 * invoking the guest. */
58a96214 1129 kvmppc_mmu_map(vcpu, eaddr, gpaddr, gtlb_index);
bbf45ba5
HB
1130 } else {
1131 /* Guest mapped and leaped at non-RAM! */
d4cf3892 1132 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_MACHINE_CHECK);
bbf45ba5
HB
1133 }
1134
f1e89028 1135 srcu_read_unlock(&vcpu->kvm->srcu, idx);
bbf45ba5
HB
1136 break;
1137 }
1138
6a0ab738
HB
1139 case BOOKE_INTERRUPT_DEBUG: {
1140 u32 dbsr;
1141
1142 vcpu->arch.pc = mfspr(SPRN_CSRR0);
1143
1144 /* clear IAC events in DBSR register */
1145 dbsr = mfspr(SPRN_DBSR);
1146 dbsr &= DBSR_IAC1 | DBSR_IAC2 | DBSR_IAC3 | DBSR_IAC4;
1147 mtspr(SPRN_DBSR, dbsr);
1148
1149 run->exit_reason = KVM_EXIT_DEBUG;
7b701591 1150 kvmppc_account_exit(vcpu, DEBUG_EXITS);
6a0ab738
HB
1151 r = RESUME_HOST;
1152 break;
1153 }
1154
bbf45ba5
HB
1155 default:
1156 printk(KERN_EMERG "exit_nr %d\n", exit_nr);
1157 BUG();
1158 }
1159
a8e4ef84
AG
1160 /*
1161 * To avoid clobbering exit_reason, only check for signals if we
1162 * aren't already exiting to userspace for some other reason.
1163 */
03660ba2
AG
1164 if (!(r & RESUME_HOST)) {
1165 local_irq_disable();
7ee78855
AG
1166 s = kvmppc_prepare_to_enter(vcpu);
1167 if (s <= 0) {
24afa37b 1168 local_irq_enable();
7ee78855 1169 r = (s << 2) | RESUME_HOST | (r & RESUME_FLAG_NV);
24afa37b 1170 } else {
5f1c248f 1171 kvmppc_fix_ee_before_entry();
03660ba2 1172 }
bbf45ba5
HB
1173 }
1174
1175 return r;
1176}
1177
d26f22c9
BB
1178static void kvmppc_set_tsr(struct kvm_vcpu *vcpu, u32 new_tsr)
1179{
1180 u32 old_tsr = vcpu->arch.tsr;
1181
1182 vcpu->arch.tsr = new_tsr;
1183
1184 if ((old_tsr ^ vcpu->arch.tsr) & (TSR_ENW | TSR_WIS))
1185 arm_next_watchdog(vcpu);
1186
1187 update_timer_ints(vcpu);
1188}
1189
bbf45ba5
HB
1190/* Initial guest state: 16MB mapping 0 -> 0, PC = 0, MSR = 0, R1 = 16MB */
1191int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
1192{
082decf2 1193 int i;
af8f38b3 1194 int r;
082decf2 1195
bbf45ba5 1196 vcpu->arch.pc = 0;
b5904972 1197 vcpu->arch.shared->pir = vcpu->vcpu_id;
8e5b26b5 1198 kvmppc_set_gpr(vcpu, 1, (16<<20) - 8); /* -8 for the callee-save LR slot */
d30f6e48 1199 kvmppc_set_msr(vcpu, 0);
bbf45ba5 1200
d30f6e48
SW
1201#ifndef CONFIG_KVM_BOOKE_HV
1202 vcpu->arch.shadow_msr = MSR_USER | MSR_DE | MSR_IS | MSR_DS;
49dd2c49 1203 vcpu->arch.shadow_pid = 1;
d30f6e48
SW
1204 vcpu->arch.shared->msr = 0;
1205#endif
49dd2c49 1206
082decf2
HB
1207 /* Eye-catching numbers so we know if the guest takes an interrupt
1208 * before it's programmed its own IVPR/IVORs. */
bbf45ba5 1209 vcpu->arch.ivpr = 0x55550000;
082decf2
HB
1210 for (i = 0; i < BOOKE_IRQPRIO_MAX; i++)
1211 vcpu->arch.ivor[i] = 0x7700 | i * 4;
bbf45ba5 1212
73e75b41
HB
1213 kvmppc_init_timing_stats(vcpu);
1214
af8f38b3
AG
1215 r = kvmppc_core_vcpu_setup(vcpu);
1216 kvmppc_sanity_check(vcpu);
1217 return r;
bbf45ba5
HB
1218}
1219
f61c94bb
BB
1220int kvmppc_subarch_vcpu_init(struct kvm_vcpu *vcpu)
1221{
1222 /* setup watchdog timer once */
1223 spin_lock_init(&vcpu->arch.wdt_lock);
1224 setup_timer(&vcpu->arch.wdt_timer, kvmppc_watchdog_func,
1225 (unsigned long)vcpu);
1226
1227 return 0;
1228}
1229
1230void kvmppc_subarch_vcpu_uninit(struct kvm_vcpu *vcpu)
1231{
1232 del_timer_sync(&vcpu->arch.wdt_timer);
1233}
1234
bbf45ba5
HB
1235int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1236{
1237 int i;
1238
1239 regs->pc = vcpu->arch.pc;
992b5b29 1240 regs->cr = kvmppc_get_cr(vcpu);
bbf45ba5
HB
1241 regs->ctr = vcpu->arch.ctr;
1242 regs->lr = vcpu->arch.lr;
992b5b29 1243 regs->xer = kvmppc_get_xer(vcpu);
666e7252 1244 regs->msr = vcpu->arch.shared->msr;
de7906c3
AG
1245 regs->srr0 = vcpu->arch.shared->srr0;
1246 regs->srr1 = vcpu->arch.shared->srr1;
bbf45ba5 1247 regs->pid = vcpu->arch.pid;
a73a9599
AG
1248 regs->sprg0 = vcpu->arch.shared->sprg0;
1249 regs->sprg1 = vcpu->arch.shared->sprg1;
1250 regs->sprg2 = vcpu->arch.shared->sprg2;
1251 regs->sprg3 = vcpu->arch.shared->sprg3;
b5904972
SW
1252 regs->sprg4 = vcpu->arch.shared->sprg4;
1253 regs->sprg5 = vcpu->arch.shared->sprg5;
1254 regs->sprg6 = vcpu->arch.shared->sprg6;
1255 regs->sprg7 = vcpu->arch.shared->sprg7;
bbf45ba5
HB
1256
1257 for (i = 0; i < ARRAY_SIZE(regs->gpr); i++)
8e5b26b5 1258 regs->gpr[i] = kvmppc_get_gpr(vcpu, i);
bbf45ba5
HB
1259
1260 return 0;
1261}
1262
1263int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1264{
1265 int i;
1266
1267 vcpu->arch.pc = regs->pc;
992b5b29 1268 kvmppc_set_cr(vcpu, regs->cr);
bbf45ba5
HB
1269 vcpu->arch.ctr = regs->ctr;
1270 vcpu->arch.lr = regs->lr;
992b5b29 1271 kvmppc_set_xer(vcpu, regs->xer);
b8fd68ac 1272 kvmppc_set_msr(vcpu, regs->msr);
de7906c3
AG
1273 vcpu->arch.shared->srr0 = regs->srr0;
1274 vcpu->arch.shared->srr1 = regs->srr1;
5ce941ee 1275 kvmppc_set_pid(vcpu, regs->pid);
a73a9599
AG
1276 vcpu->arch.shared->sprg0 = regs->sprg0;
1277 vcpu->arch.shared->sprg1 = regs->sprg1;
1278 vcpu->arch.shared->sprg2 = regs->sprg2;
1279 vcpu->arch.shared->sprg3 = regs->sprg3;
b5904972
SW
1280 vcpu->arch.shared->sprg4 = regs->sprg4;
1281 vcpu->arch.shared->sprg5 = regs->sprg5;
1282 vcpu->arch.shared->sprg6 = regs->sprg6;
1283 vcpu->arch.shared->sprg7 = regs->sprg7;
bbf45ba5 1284
8e5b26b5
AG
1285 for (i = 0; i < ARRAY_SIZE(regs->gpr); i++)
1286 kvmppc_set_gpr(vcpu, i, regs->gpr[i]);
bbf45ba5
HB
1287
1288 return 0;
1289}
1290
5ce941ee
SW
1291static void get_sregs_base(struct kvm_vcpu *vcpu,
1292 struct kvm_sregs *sregs)
1293{
1294 u64 tb = get_tb();
1295
1296 sregs->u.e.features |= KVM_SREGS_E_BASE;
1297
1298 sregs->u.e.csrr0 = vcpu->arch.csrr0;
1299 sregs->u.e.csrr1 = vcpu->arch.csrr1;
1300 sregs->u.e.mcsr = vcpu->arch.mcsr;
d30f6e48
SW
1301 sregs->u.e.esr = get_guest_esr(vcpu);
1302 sregs->u.e.dear = get_guest_dear(vcpu);
5ce941ee
SW
1303 sregs->u.e.tsr = vcpu->arch.tsr;
1304 sregs->u.e.tcr = vcpu->arch.tcr;
1305 sregs->u.e.dec = kvmppc_get_dec(vcpu, tb);
1306 sregs->u.e.tb = tb;
1307 sregs->u.e.vrsave = vcpu->arch.vrsave;
1308}
1309
1310static int set_sregs_base(struct kvm_vcpu *vcpu,
1311 struct kvm_sregs *sregs)
1312{
1313 if (!(sregs->u.e.features & KVM_SREGS_E_BASE))
1314 return 0;
1315
1316 vcpu->arch.csrr0 = sregs->u.e.csrr0;
1317 vcpu->arch.csrr1 = sregs->u.e.csrr1;
1318 vcpu->arch.mcsr = sregs->u.e.mcsr;
d30f6e48
SW
1319 set_guest_esr(vcpu, sregs->u.e.esr);
1320 set_guest_dear(vcpu, sregs->u.e.dear);
5ce941ee 1321 vcpu->arch.vrsave = sregs->u.e.vrsave;
dfd4d47e 1322 kvmppc_set_tcr(vcpu, sregs->u.e.tcr);
5ce941ee 1323
dfd4d47e 1324 if (sregs->u.e.update_special & KVM_SREGS_E_UPDATE_DEC) {
5ce941ee 1325 vcpu->arch.dec = sregs->u.e.dec;
dfd4d47e
SW
1326 kvmppc_emulate_dec(vcpu);
1327 }
5ce941ee 1328
d26f22c9
BB
1329 if (sregs->u.e.update_special & KVM_SREGS_E_UPDATE_TSR)
1330 kvmppc_set_tsr(vcpu, sregs->u.e.tsr);
5ce941ee
SW
1331
1332 return 0;
1333}
1334
1335static void get_sregs_arch206(struct kvm_vcpu *vcpu,
1336 struct kvm_sregs *sregs)
1337{
1338 sregs->u.e.features |= KVM_SREGS_E_ARCH206;
1339
841741f2 1340 sregs->u.e.pir = vcpu->vcpu_id;
5ce941ee
SW
1341 sregs->u.e.mcsrr0 = vcpu->arch.mcsrr0;
1342 sregs->u.e.mcsrr1 = vcpu->arch.mcsrr1;
1343 sregs->u.e.decar = vcpu->arch.decar;
1344 sregs->u.e.ivpr = vcpu->arch.ivpr;
1345}
1346
1347static int set_sregs_arch206(struct kvm_vcpu *vcpu,
1348 struct kvm_sregs *sregs)
1349{
1350 if (!(sregs->u.e.features & KVM_SREGS_E_ARCH206))
1351 return 0;
1352
841741f2 1353 if (sregs->u.e.pir != vcpu->vcpu_id)
5ce941ee
SW
1354 return -EINVAL;
1355
1356 vcpu->arch.mcsrr0 = sregs->u.e.mcsrr0;
1357 vcpu->arch.mcsrr1 = sregs->u.e.mcsrr1;
1358 vcpu->arch.decar = sregs->u.e.decar;
1359 vcpu->arch.ivpr = sregs->u.e.ivpr;
1360
1361 return 0;
1362}
1363
1364void kvmppc_get_sregs_ivor(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
1365{
1366 sregs->u.e.features |= KVM_SREGS_E_IVOR;
1367
1368 sregs->u.e.ivor_low[0] = vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL];
1369 sregs->u.e.ivor_low[1] = vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK];
1370 sregs->u.e.ivor_low[2] = vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE];
1371 sregs->u.e.ivor_low[3] = vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE];
1372 sregs->u.e.ivor_low[4] = vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL];
1373 sregs->u.e.ivor_low[5] = vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT];
1374 sregs->u.e.ivor_low[6] = vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM];
1375 sregs->u.e.ivor_low[7] = vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL];
1376 sregs->u.e.ivor_low[8] = vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL];
1377 sregs->u.e.ivor_low[9] = vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL];
1378 sregs->u.e.ivor_low[10] = vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER];
1379 sregs->u.e.ivor_low[11] = vcpu->arch.ivor[BOOKE_IRQPRIO_FIT];
1380 sregs->u.e.ivor_low[12] = vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG];
1381 sregs->u.e.ivor_low[13] = vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS];
1382 sregs->u.e.ivor_low[14] = vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS];
1383 sregs->u.e.ivor_low[15] = vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG];
1384}
1385
1386int kvmppc_set_sregs_ivor(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
1387{
1388 if (!(sregs->u.e.features & KVM_SREGS_E_IVOR))
1389 return 0;
1390
1391 vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL] = sregs->u.e.ivor_low[0];
1392 vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK] = sregs->u.e.ivor_low[1];
1393 vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE] = sregs->u.e.ivor_low[2];
1394 vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE] = sregs->u.e.ivor_low[3];
1395 vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL] = sregs->u.e.ivor_low[4];
1396 vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT] = sregs->u.e.ivor_low[5];
1397 vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM] = sregs->u.e.ivor_low[6];
1398 vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL] = sregs->u.e.ivor_low[7];
1399 vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL] = sregs->u.e.ivor_low[8];
1400 vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL] = sregs->u.e.ivor_low[9];
1401 vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER] = sregs->u.e.ivor_low[10];
1402 vcpu->arch.ivor[BOOKE_IRQPRIO_FIT] = sregs->u.e.ivor_low[11];
1403 vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG] = sregs->u.e.ivor_low[12];
1404 vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS] = sregs->u.e.ivor_low[13];
1405 vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS] = sregs->u.e.ivor_low[14];
1406 vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG] = sregs->u.e.ivor_low[15];
1407
1408 return 0;
1409}
1410
bbf45ba5
HB
1411int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
1412 struct kvm_sregs *sregs)
1413{
5ce941ee
SW
1414 sregs->pvr = vcpu->arch.pvr;
1415
1416 get_sregs_base(vcpu, sregs);
1417 get_sregs_arch206(vcpu, sregs);
1418 kvmppc_core_get_sregs(vcpu, sregs);
1419 return 0;
bbf45ba5
HB
1420}
1421
1422int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
1423 struct kvm_sregs *sregs)
1424{
5ce941ee
SW
1425 int ret;
1426
1427 if (vcpu->arch.pvr != sregs->pvr)
1428 return -EINVAL;
1429
1430 ret = set_sregs_base(vcpu, sregs);
1431 if (ret < 0)
1432 return ret;
1433
1434 ret = set_sregs_arch206(vcpu, sregs);
1435 if (ret < 0)
1436 return ret;
1437
1438 return kvmppc_core_set_sregs(vcpu, sregs);
bbf45ba5
HB
1439}
1440
31f3438e
PM
1441int kvm_vcpu_ioctl_get_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
1442{
35b299e2
MC
1443 int r = 0;
1444 union kvmppc_one_reg val;
1445 int size;
1446 long int i;
1447
1448 size = one_reg_size(reg->id);
1449 if (size > sizeof(val))
1450 return -EINVAL;
6df8d3fc
BB
1451
1452 switch (reg->id) {
1453 case KVM_REG_PPC_IAC1:
1454 case KVM_REG_PPC_IAC2:
1455 case KVM_REG_PPC_IAC3:
35b299e2
MC
1456 case KVM_REG_PPC_IAC4:
1457 i = reg->id - KVM_REG_PPC_IAC1;
1458 val = get_reg_val(reg->id, vcpu->arch.dbg_reg.iac[i]);
6df8d3fc 1459 break;
6df8d3fc 1460 case KVM_REG_PPC_DAC1:
35b299e2
MC
1461 case KVM_REG_PPC_DAC2:
1462 i = reg->id - KVM_REG_PPC_DAC1;
1463 val = get_reg_val(reg->id, vcpu->arch.dbg_reg.dac[i]);
6df8d3fc 1464 break;
324b3e63
AG
1465 case KVM_REG_PPC_EPR: {
1466 u32 epr = get_guest_epr(vcpu);
35b299e2 1467 val = get_reg_val(reg->id, epr);
324b3e63
AG
1468 break;
1469 }
352df1de
MC
1470#if defined(CONFIG_64BIT)
1471 case KVM_REG_PPC_EPCR:
35b299e2 1472 val = get_reg_val(reg->id, vcpu->arch.epcr);
352df1de
MC
1473 break;
1474#endif
78accda4 1475 case KVM_REG_PPC_TCR:
35b299e2 1476 val = get_reg_val(reg->id, vcpu->arch.tcr);
78accda4
BB
1477 break;
1478 case KVM_REG_PPC_TSR:
35b299e2 1479 val = get_reg_val(reg->id, vcpu->arch.tsr);
78accda4 1480 break;
35b299e2
MC
1481 case KVM_REG_PPC_DEBUG_INST:
1482 val = get_reg_val(reg->id, KVMPPC_INST_EHPRIV);
8c32a2ea 1483 break;
6df8d3fc 1484 default:
35b299e2 1485 r = kvmppc_get_one_reg(vcpu, reg->id, &val);
6df8d3fc
BB
1486 break;
1487 }
35b299e2
MC
1488
1489 if (r)
1490 return r;
1491
1492 if (copy_to_user((char __user *)(unsigned long)reg->addr, &val, size))
1493 r = -EFAULT;
1494
6df8d3fc 1495 return r;
31f3438e
PM
1496}
1497
1498int kvm_vcpu_ioctl_set_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
1499{
35b299e2
MC
1500 int r = 0;
1501 union kvmppc_one_reg val;
1502 int size;
1503 long int i;
1504
1505 size = one_reg_size(reg->id);
1506 if (size > sizeof(val))
1507 return -EINVAL;
1508
1509 if (copy_from_user(&val, (char __user *)(unsigned long)reg->addr, size))
1510 return -EFAULT;
6df8d3fc
BB
1511
1512 switch (reg->id) {
1513 case KVM_REG_PPC_IAC1:
1514 case KVM_REG_PPC_IAC2:
1515 case KVM_REG_PPC_IAC3:
35b299e2
MC
1516 case KVM_REG_PPC_IAC4:
1517 i = reg->id - KVM_REG_PPC_IAC1;
1518 vcpu->arch.dbg_reg.iac[i] = set_reg_val(reg->id, val);
6df8d3fc 1519 break;
6df8d3fc 1520 case KVM_REG_PPC_DAC1:
35b299e2
MC
1521 case KVM_REG_PPC_DAC2:
1522 i = reg->id - KVM_REG_PPC_DAC1;
1523 vcpu->arch.dbg_reg.dac[i] = set_reg_val(reg->id, val);
6df8d3fc 1524 break;
324b3e63 1525 case KVM_REG_PPC_EPR: {
35b299e2
MC
1526 u32 new_epr = set_reg_val(reg->id, val);
1527 kvmppc_set_epr(vcpu, new_epr);
324b3e63
AG
1528 break;
1529 }
352df1de
MC
1530#if defined(CONFIG_64BIT)
1531 case KVM_REG_PPC_EPCR: {
35b299e2
MC
1532 u32 new_epcr = set_reg_val(reg->id, val);
1533 kvmppc_set_epcr(vcpu, new_epcr);
352df1de
MC
1534 break;
1535 }
1536#endif
78accda4 1537 case KVM_REG_PPC_OR_TSR: {
35b299e2 1538 u32 tsr_bits = set_reg_val(reg->id, val);
78accda4
BB
1539 kvmppc_set_tsr_bits(vcpu, tsr_bits);
1540 break;
1541 }
1542 case KVM_REG_PPC_CLEAR_TSR: {
35b299e2 1543 u32 tsr_bits = set_reg_val(reg->id, val);
78accda4
BB
1544 kvmppc_clr_tsr_bits(vcpu, tsr_bits);
1545 break;
1546 }
1547 case KVM_REG_PPC_TSR: {
35b299e2 1548 u32 tsr = set_reg_val(reg->id, val);
78accda4
BB
1549 kvmppc_set_tsr(vcpu, tsr);
1550 break;
1551 }
1552 case KVM_REG_PPC_TCR: {
35b299e2 1553 u32 tcr = set_reg_val(reg->id, val);
78accda4
BB
1554 kvmppc_set_tcr(vcpu, tcr);
1555 break;
1556 }
6df8d3fc 1557 default:
35b299e2 1558 r = kvmppc_set_one_reg(vcpu, reg->id, &val);
6df8d3fc
BB
1559 break;
1560 }
35b299e2 1561
6df8d3fc 1562 return r;
31f3438e
PM
1563}
1564
092d62ee
BB
1565int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
1566 struct kvm_guest_debug *dbg)
1567{
1568 return -EINVAL;
1569}
1570
bbf45ba5
HB
1571int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1572{
1573 return -ENOTSUPP;
1574}
1575
1576int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1577{
1578 return -ENOTSUPP;
1579}
1580
bbf45ba5
HB
1581int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1582 struct kvm_translation *tr)
1583{
98001d8d
AK
1584 int r;
1585
98001d8d 1586 r = kvmppc_core_vcpu_translate(vcpu, tr);
98001d8d 1587 return r;
bbf45ba5 1588}
d9fbd03d 1589
4e755758
AG
1590int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
1591{
1592 return -ENOTSUPP;
1593}
1594
a66b48c3
PM
1595void kvmppc_core_free_memslot(struct kvm_memory_slot *free,
1596 struct kvm_memory_slot *dont)
1597{
1598}
1599
1600int kvmppc_core_create_memslot(struct kvm_memory_slot *slot,
1601 unsigned long npages)
1602{
1603 return 0;
1604}
1605
f9e0554d 1606int kvmppc_core_prepare_memory_region(struct kvm *kvm,
a66b48c3 1607 struct kvm_memory_slot *memslot,
f9e0554d
PM
1608 struct kvm_userspace_memory_region *mem)
1609{
1610 return 0;
1611}
1612
1613void kvmppc_core_commit_memory_region(struct kvm *kvm,
dfe49dbd 1614 struct kvm_userspace_memory_region *mem,
8482644a 1615 const struct kvm_memory_slot *old)
dfe49dbd
PM
1616{
1617}
1618
1619void kvmppc_core_flush_memslot(struct kvm *kvm, struct kvm_memory_slot *memslot)
f9e0554d
PM
1620{
1621}
1622
38f98824
MC
1623void kvmppc_set_epcr(struct kvm_vcpu *vcpu, u32 new_epcr)
1624{
1625#if defined(CONFIG_64BIT)
1626 vcpu->arch.epcr = new_epcr;
1627#ifdef CONFIG_KVM_BOOKE_HV
1628 vcpu->arch.shadow_epcr &= ~SPRN_EPCR_GICM;
1629 if (vcpu->arch.epcr & SPRN_EPCR_ICM)
1630 vcpu->arch.shadow_epcr |= SPRN_EPCR_GICM;
1631#endif
1632#endif
1633}
1634
dfd4d47e
SW
1635void kvmppc_set_tcr(struct kvm_vcpu *vcpu, u32 new_tcr)
1636{
1637 vcpu->arch.tcr = new_tcr;
f61c94bb 1638 arm_next_watchdog(vcpu);
dfd4d47e
SW
1639 update_timer_ints(vcpu);
1640}
1641
1642void kvmppc_set_tsr_bits(struct kvm_vcpu *vcpu, u32 tsr_bits)
1643{
1644 set_bits(tsr_bits, &vcpu->arch.tsr);
1645 smp_wmb();
1646 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1647 kvm_vcpu_kick(vcpu);
1648}
1649
1650void kvmppc_clr_tsr_bits(struct kvm_vcpu *vcpu, u32 tsr_bits)
1651{
1652 clear_bits(tsr_bits, &vcpu->arch.tsr);
f61c94bb
BB
1653
1654 /*
1655 * We may have stopped the watchdog due to
1656 * being stuck on final expiration.
1657 */
1658 if (tsr_bits & (TSR_ENW | TSR_WIS))
1659 arm_next_watchdog(vcpu);
1660
dfd4d47e
SW
1661 update_timer_ints(vcpu);
1662}
1663
1664void kvmppc_decrementer_func(unsigned long data)
1665{
1666 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
1667
21bd000a
BB
1668 if (vcpu->arch.tcr & TCR_ARE) {
1669 vcpu->arch.dec = vcpu->arch.decar;
1670 kvmppc_emulate_dec(vcpu);
1671 }
1672
dfd4d47e
SW
1673 kvmppc_set_tsr_bits(vcpu, TSR_DIS);
1674}
1675
94fa9d99
SW
1676void kvmppc_booke_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1677{
a47d72f3 1678 vcpu->cpu = smp_processor_id();
d30f6e48 1679 current->thread.kvm_vcpu = vcpu;
94fa9d99
SW
1680}
1681
1682void kvmppc_booke_vcpu_put(struct kvm_vcpu *vcpu)
1683{
d30f6e48 1684 current->thread.kvm_vcpu = NULL;
a47d72f3 1685 vcpu->cpu = -1;
94fa9d99
SW
1686}
1687
2986b8c7 1688int __init kvmppc_booke_init(void)
d9fbd03d 1689{
d30f6e48 1690#ifndef CONFIG_KVM_BOOKE_HV
d9fbd03d 1691 unsigned long ivor[16];
1d542d9c 1692 unsigned long *handler = kvmppc_booke_handler_addr;
d9fbd03d 1693 unsigned long max_ivor = 0;
1d542d9c 1694 unsigned long handler_len;
d9fbd03d
HB
1695 int i;
1696
1697 /* We install our own exception handlers by hijacking IVPR. IVPR must
1698 * be 16-bit aligned, so we need a 64KB allocation. */
1699 kvmppc_booke_handlers = __get_free_pages(GFP_KERNEL | __GFP_ZERO,
1700 VCPU_SIZE_ORDER);
1701 if (!kvmppc_booke_handlers)
1702 return -ENOMEM;
1703
1704 /* XXX make sure our handlers are smaller than Linux's */
1705
1706 /* Copy our interrupt handlers to match host IVORs. That way we don't
1707 * have to swap the IVORs on every guest/host transition. */
1708 ivor[0] = mfspr(SPRN_IVOR0);
1709 ivor[1] = mfspr(SPRN_IVOR1);
1710 ivor[2] = mfspr(SPRN_IVOR2);
1711 ivor[3] = mfspr(SPRN_IVOR3);
1712 ivor[4] = mfspr(SPRN_IVOR4);
1713 ivor[5] = mfspr(SPRN_IVOR5);
1714 ivor[6] = mfspr(SPRN_IVOR6);
1715 ivor[7] = mfspr(SPRN_IVOR7);
1716 ivor[8] = mfspr(SPRN_IVOR8);
1717 ivor[9] = mfspr(SPRN_IVOR9);
1718 ivor[10] = mfspr(SPRN_IVOR10);
1719 ivor[11] = mfspr(SPRN_IVOR11);
1720 ivor[12] = mfspr(SPRN_IVOR12);
1721 ivor[13] = mfspr(SPRN_IVOR13);
1722 ivor[14] = mfspr(SPRN_IVOR14);
1723 ivor[15] = mfspr(SPRN_IVOR15);
1724
1725 for (i = 0; i < 16; i++) {
1726 if (ivor[i] > max_ivor)
1d542d9c 1727 max_ivor = i;
d9fbd03d 1728
1d542d9c 1729 handler_len = handler[i + 1] - handler[i];
d9fbd03d 1730 memcpy((void *)kvmppc_booke_handlers + ivor[i],
1d542d9c 1731 (void *)handler[i], handler_len);
d9fbd03d 1732 }
1d542d9c
BB
1733
1734 handler_len = handler[max_ivor + 1] - handler[max_ivor];
1735 flush_icache_range(kvmppc_booke_handlers, kvmppc_booke_handlers +
1736 ivor[max_ivor] + handler_len);
d30f6e48 1737#endif /* !BOOKE_HV */
db93f574 1738 return 0;
d9fbd03d
HB
1739}
1740
db93f574 1741void __exit kvmppc_booke_exit(void)
d9fbd03d
HB
1742{
1743 free_pages(kvmppc_booke_handlers, VCPU_SIZE_ORDER);
1744 kvm_exit();
1745}