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bbf45ba5 HB |
1 | /* |
2 | * This program is free software; you can redistribute it and/or modify | |
3 | * it under the terms of the GNU General Public License, version 2, as | |
4 | * published by the Free Software Foundation. | |
5 | * | |
6 | * This program is distributed in the hope that it will be useful, | |
7 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
8 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
9 | * GNU General Public License for more details. | |
10 | * | |
11 | * You should have received a copy of the GNU General Public License | |
12 | * along with this program; if not, write to the Free Software | |
13 | * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. | |
14 | * | |
15 | * Copyright IBM Corp. 2007 | |
4cd35f67 | 16 | * Copyright 2010-2011 Freescale Semiconductor, Inc. |
bbf45ba5 HB |
17 | * |
18 | * Authors: Hollis Blanchard <hollisb@us.ibm.com> | |
19 | * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com> | |
d30f6e48 SW |
20 | * Scott Wood <scottwood@freescale.com> |
21 | * Varun Sethi <varun.sethi@freescale.com> | |
bbf45ba5 HB |
22 | */ |
23 | ||
24 | #include <linux/errno.h> | |
25 | #include <linux/err.h> | |
26 | #include <linux/kvm_host.h> | |
5a0e3ad6 | 27 | #include <linux/gfp.h> |
bbf45ba5 HB |
28 | #include <linux/module.h> |
29 | #include <linux/vmalloc.h> | |
30 | #include <linux/fs.h> | |
7924bd41 | 31 | |
bbf45ba5 | 32 | #include <asm/cputable.h> |
7c0f6ba6 | 33 | #include <linux/uaccess.h> |
bbf45ba5 | 34 | #include <asm/kvm_ppc.h> |
d9fbd03d | 35 | #include <asm/cacheflush.h> |
d30f6e48 SW |
36 | #include <asm/dbell.h> |
37 | #include <asm/hw_irq.h> | |
38 | #include <asm/irq.h> | |
b50df19c | 39 | #include <asm/time.h> |
bbf45ba5 | 40 | |
d30f6e48 | 41 | #include "timing.h" |
75f74f0d | 42 | #include "booke.h" |
dba291f2 AK |
43 | |
44 | #define CREATE_TRACE_POINTS | |
45 | #include "trace_booke.h" | |
bbf45ba5 | 46 | |
d9fbd03d HB |
47 | unsigned long kvmppc_booke_handlers; |
48 | ||
bbf45ba5 HB |
49 | #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM |
50 | #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU | |
51 | ||
52 | struct kvm_stats_debugfs_item debugfs_entries[] = { | |
bbf45ba5 | 53 | { "mmio", VCPU_STAT(mmio_exits) }, |
bbf45ba5 | 54 | { "sig", VCPU_STAT(signal_exits) }, |
bbf45ba5 HB |
55 | { "itlb_r", VCPU_STAT(itlb_real_miss_exits) }, |
56 | { "itlb_v", VCPU_STAT(itlb_virt_miss_exits) }, | |
57 | { "dtlb_r", VCPU_STAT(dtlb_real_miss_exits) }, | |
58 | { "dtlb_v", VCPU_STAT(dtlb_virt_miss_exits) }, | |
59 | { "sysc", VCPU_STAT(syscall_exits) }, | |
60 | { "isi", VCPU_STAT(isi_exits) }, | |
61 | { "dsi", VCPU_STAT(dsi_exits) }, | |
62 | { "inst_emu", VCPU_STAT(emulated_inst_exits) }, | |
63 | { "dec", VCPU_STAT(dec_exits) }, | |
64 | { "ext_intr", VCPU_STAT(ext_intr_exits) }, | |
f7819512 | 65 | { "halt_successful_poll", VCPU_STAT(halt_successful_poll) }, |
62bea5bf | 66 | { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) }, |
3491caf2 | 67 | { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) }, |
45c5eb67 | 68 | { "halt_wakeup", VCPU_STAT(halt_wakeup) }, |
d30f6e48 SW |
69 | { "doorbell", VCPU_STAT(dbell_exits) }, |
70 | { "guest doorbell", VCPU_STAT(gdbell_exits) }, | |
cf1c5ca4 | 71 | { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, |
bbf45ba5 HB |
72 | { NULL } |
73 | }; | |
74 | ||
bbf45ba5 HB |
75 | /* TODO: use vcpu_printf() */ |
76 | void kvmppc_dump_vcpu(struct kvm_vcpu *vcpu) | |
77 | { | |
78 | int i; | |
79 | ||
666e7252 | 80 | printk("pc: %08lx msr: %08llx\n", vcpu->arch.pc, vcpu->arch.shared->msr); |
5cf8ca22 | 81 | printk("lr: %08lx ctr: %08lx\n", vcpu->arch.lr, vcpu->arch.ctr); |
de7906c3 AG |
82 | printk("srr0: %08llx srr1: %08llx\n", vcpu->arch.shared->srr0, |
83 | vcpu->arch.shared->srr1); | |
bbf45ba5 HB |
84 | |
85 | printk("exceptions: %08lx\n", vcpu->arch.pending_exceptions); | |
86 | ||
87 | for (i = 0; i < 32; i += 4) { | |
5cf8ca22 | 88 | printk("gpr%02d: %08lx %08lx %08lx %08lx\n", i, |
8e5b26b5 AG |
89 | kvmppc_get_gpr(vcpu, i), |
90 | kvmppc_get_gpr(vcpu, i+1), | |
91 | kvmppc_get_gpr(vcpu, i+2), | |
92 | kvmppc_get_gpr(vcpu, i+3)); | |
bbf45ba5 HB |
93 | } |
94 | } | |
95 | ||
4cd35f67 SW |
96 | #ifdef CONFIG_SPE |
97 | void kvmppc_vcpu_disable_spe(struct kvm_vcpu *vcpu) | |
98 | { | |
99 | preempt_disable(); | |
100 | enable_kernel_spe(); | |
101 | kvmppc_save_guest_spe(vcpu); | |
dc4fbba1 | 102 | disable_kernel_spe(); |
4cd35f67 SW |
103 | vcpu->arch.shadow_msr &= ~MSR_SPE; |
104 | preempt_enable(); | |
105 | } | |
106 | ||
107 | static void kvmppc_vcpu_enable_spe(struct kvm_vcpu *vcpu) | |
108 | { | |
109 | preempt_disable(); | |
110 | enable_kernel_spe(); | |
111 | kvmppc_load_guest_spe(vcpu); | |
dc4fbba1 | 112 | disable_kernel_spe(); |
4cd35f67 SW |
113 | vcpu->arch.shadow_msr |= MSR_SPE; |
114 | preempt_enable(); | |
115 | } | |
116 | ||
117 | static void kvmppc_vcpu_sync_spe(struct kvm_vcpu *vcpu) | |
118 | { | |
119 | if (vcpu->arch.shared->msr & MSR_SPE) { | |
120 | if (!(vcpu->arch.shadow_msr & MSR_SPE)) | |
121 | kvmppc_vcpu_enable_spe(vcpu); | |
122 | } else if (vcpu->arch.shadow_msr & MSR_SPE) { | |
123 | kvmppc_vcpu_disable_spe(vcpu); | |
124 | } | |
125 | } | |
126 | #else | |
127 | static void kvmppc_vcpu_sync_spe(struct kvm_vcpu *vcpu) | |
128 | { | |
129 | } | |
130 | #endif | |
131 | ||
3efc7da6 MC |
132 | /* |
133 | * Load up guest vcpu FP state if it's needed. | |
134 | * It also set the MSR_FP in thread so that host know | |
135 | * we're holding FPU, and then host can help to save | |
136 | * guest vcpu FP state if other threads require to use FPU. | |
137 | * This simulates an FP unavailable fault. | |
138 | * | |
139 | * It requires to be called with preemption disabled. | |
140 | */ | |
141 | static inline void kvmppc_load_guest_fp(struct kvm_vcpu *vcpu) | |
142 | { | |
143 | #ifdef CONFIG_PPC_FPU | |
144 | if (!(current->thread.regs->msr & MSR_FP)) { | |
145 | enable_kernel_fp(); | |
146 | load_fp_state(&vcpu->arch.fp); | |
dc4fbba1 | 147 | disable_kernel_fp(); |
3efc7da6 MC |
148 | current->thread.fp_save_area = &vcpu->arch.fp; |
149 | current->thread.regs->msr |= MSR_FP; | |
150 | } | |
151 | #endif | |
152 | } | |
153 | ||
154 | /* | |
155 | * Save guest vcpu FP state into thread. | |
156 | * It requires to be called with preemption disabled. | |
157 | */ | |
158 | static inline void kvmppc_save_guest_fp(struct kvm_vcpu *vcpu) | |
159 | { | |
160 | #ifdef CONFIG_PPC_FPU | |
161 | if (current->thread.regs->msr & MSR_FP) | |
162 | giveup_fpu(current); | |
163 | current->thread.fp_save_area = NULL; | |
164 | #endif | |
165 | } | |
166 | ||
7a08c274 AG |
167 | static void kvmppc_vcpu_sync_fpu(struct kvm_vcpu *vcpu) |
168 | { | |
169 | #if defined(CONFIG_PPC_FPU) && !defined(CONFIG_KVM_BOOKE_HV) | |
170 | /* We always treat the FP bit as enabled from the host | |
171 | perspective, so only need to adjust the shadow MSR */ | |
172 | vcpu->arch.shadow_msr &= ~MSR_FP; | |
173 | vcpu->arch.shadow_msr |= vcpu->arch.shared->msr & MSR_FP; | |
174 | #endif | |
175 | } | |
176 | ||
95d80a29 MC |
177 | /* |
178 | * Simulate AltiVec unavailable fault to load guest state | |
179 | * from thread to AltiVec unit. | |
180 | * It requires to be called with preemption disabled. | |
181 | */ | |
182 | static inline void kvmppc_load_guest_altivec(struct kvm_vcpu *vcpu) | |
183 | { | |
184 | #ifdef CONFIG_ALTIVEC | |
185 | if (cpu_has_feature(CPU_FTR_ALTIVEC)) { | |
186 | if (!(current->thread.regs->msr & MSR_VEC)) { | |
187 | enable_kernel_altivec(); | |
188 | load_vr_state(&vcpu->arch.vr); | |
dc4fbba1 | 189 | disable_kernel_altivec(); |
95d80a29 MC |
190 | current->thread.vr_save_area = &vcpu->arch.vr; |
191 | current->thread.regs->msr |= MSR_VEC; | |
192 | } | |
193 | } | |
194 | #endif | |
195 | } | |
196 | ||
197 | /* | |
198 | * Save guest vcpu AltiVec state into thread. | |
199 | * It requires to be called with preemption disabled. | |
200 | */ | |
201 | static inline void kvmppc_save_guest_altivec(struct kvm_vcpu *vcpu) | |
202 | { | |
203 | #ifdef CONFIG_ALTIVEC | |
204 | if (cpu_has_feature(CPU_FTR_ALTIVEC)) { | |
205 | if (current->thread.regs->msr & MSR_VEC) | |
206 | giveup_altivec(current); | |
207 | current->thread.vr_save_area = NULL; | |
208 | } | |
209 | #endif | |
210 | } | |
211 | ||
ce11e48b BB |
212 | static void kvmppc_vcpu_sync_debug(struct kvm_vcpu *vcpu) |
213 | { | |
214 | /* Synchronize guest's desire to get debug interrupts into shadow MSR */ | |
215 | #ifndef CONFIG_KVM_BOOKE_HV | |
216 | vcpu->arch.shadow_msr &= ~MSR_DE; | |
217 | vcpu->arch.shadow_msr |= vcpu->arch.shared->msr & MSR_DE; | |
218 | #endif | |
219 | ||
220 | /* Force enable debug interrupts when user space wants to debug */ | |
221 | if (vcpu->guest_debug) { | |
222 | #ifdef CONFIG_KVM_BOOKE_HV | |
223 | /* | |
224 | * Since there is no shadow MSR, sync MSR_DE into the guest | |
225 | * visible MSR. | |
226 | */ | |
227 | vcpu->arch.shared->msr |= MSR_DE; | |
228 | #else | |
229 | vcpu->arch.shadow_msr |= MSR_DE; | |
230 | vcpu->arch.shared->msr &= ~MSR_DE; | |
231 | #endif | |
232 | } | |
233 | } | |
234 | ||
dd9ebf1f LY |
235 | /* |
236 | * Helper function for "full" MSR writes. No need to call this if only | |
237 | * EE/CE/ME/DE/RI are changing. | |
238 | */ | |
4cd35f67 SW |
239 | void kvmppc_set_msr(struct kvm_vcpu *vcpu, u32 new_msr) |
240 | { | |
dd9ebf1f | 241 | u32 old_msr = vcpu->arch.shared->msr; |
4cd35f67 | 242 | |
d30f6e48 SW |
243 | #ifdef CONFIG_KVM_BOOKE_HV |
244 | new_msr |= MSR_GS; | |
245 | #endif | |
246 | ||
4cd35f67 SW |
247 | vcpu->arch.shared->msr = new_msr; |
248 | ||
dd9ebf1f | 249 | kvmppc_mmu_msr_notify(vcpu, old_msr); |
4cd35f67 | 250 | kvmppc_vcpu_sync_spe(vcpu); |
7a08c274 | 251 | kvmppc_vcpu_sync_fpu(vcpu); |
ce11e48b | 252 | kvmppc_vcpu_sync_debug(vcpu); |
4cd35f67 SW |
253 | } |
254 | ||
d4cf3892 HB |
255 | static void kvmppc_booke_queue_irqprio(struct kvm_vcpu *vcpu, |
256 | unsigned int priority) | |
9dd921cf | 257 | { |
6346046c | 258 | trace_kvm_booke_queue_irqprio(vcpu, priority); |
9dd921cf HB |
259 | set_bit(priority, &vcpu->arch.pending_exceptions); |
260 | } | |
261 | ||
8de12015 AG |
262 | void kvmppc_core_queue_dtlb_miss(struct kvm_vcpu *vcpu, |
263 | ulong dear_flags, ulong esr_flags) | |
9dd921cf | 264 | { |
daf5e271 LY |
265 | vcpu->arch.queued_dear = dear_flags; |
266 | vcpu->arch.queued_esr = esr_flags; | |
267 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DTLB_MISS); | |
268 | } | |
269 | ||
8de12015 AG |
270 | void kvmppc_core_queue_data_storage(struct kvm_vcpu *vcpu, |
271 | ulong dear_flags, ulong esr_flags) | |
daf5e271 LY |
272 | { |
273 | vcpu->arch.queued_dear = dear_flags; | |
274 | vcpu->arch.queued_esr = esr_flags; | |
275 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DATA_STORAGE); | |
276 | } | |
277 | ||
8de12015 AG |
278 | void kvmppc_core_queue_itlb_miss(struct kvm_vcpu *vcpu) |
279 | { | |
280 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_ITLB_MISS); | |
281 | } | |
282 | ||
283 | void kvmppc_core_queue_inst_storage(struct kvm_vcpu *vcpu, ulong esr_flags) | |
daf5e271 LY |
284 | { |
285 | vcpu->arch.queued_esr = esr_flags; | |
286 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_INST_STORAGE); | |
287 | } | |
288 | ||
011da899 AG |
289 | static void kvmppc_core_queue_alignment(struct kvm_vcpu *vcpu, ulong dear_flags, |
290 | ulong esr_flags) | |
291 | { | |
292 | vcpu->arch.queued_dear = dear_flags; | |
293 | vcpu->arch.queued_esr = esr_flags; | |
294 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_ALIGNMENT); | |
295 | } | |
296 | ||
daf5e271 LY |
297 | void kvmppc_core_queue_program(struct kvm_vcpu *vcpu, ulong esr_flags) |
298 | { | |
299 | vcpu->arch.queued_esr = esr_flags; | |
d4cf3892 | 300 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_PROGRAM); |
9dd921cf HB |
301 | } |
302 | ||
307d9279 PM |
303 | void kvmppc_core_queue_fpunavail(struct kvm_vcpu *vcpu) |
304 | { | |
305 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_FP_UNAVAIL); | |
306 | } | |
307 | ||
9dd921cf HB |
308 | void kvmppc_core_queue_dec(struct kvm_vcpu *vcpu) |
309 | { | |
d4cf3892 | 310 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DECREMENTER); |
9dd921cf HB |
311 | } |
312 | ||
313 | int kvmppc_core_pending_dec(struct kvm_vcpu *vcpu) | |
314 | { | |
d4cf3892 | 315 | return test_bit(BOOKE_IRQPRIO_DECREMENTER, &vcpu->arch.pending_exceptions); |
9dd921cf HB |
316 | } |
317 | ||
7706664d AG |
318 | void kvmppc_core_dequeue_dec(struct kvm_vcpu *vcpu) |
319 | { | |
320 | clear_bit(BOOKE_IRQPRIO_DECREMENTER, &vcpu->arch.pending_exceptions); | |
321 | } | |
322 | ||
9dd921cf HB |
323 | void kvmppc_core_queue_external(struct kvm_vcpu *vcpu, |
324 | struct kvm_interrupt *irq) | |
325 | { | |
c5335f17 AG |
326 | unsigned int prio = BOOKE_IRQPRIO_EXTERNAL; |
327 | ||
328 | if (irq->irq == KVM_INTERRUPT_SET_LEVEL) | |
329 | prio = BOOKE_IRQPRIO_EXTERNAL_LEVEL; | |
330 | ||
331 | kvmppc_booke_queue_irqprio(vcpu, prio); | |
9dd921cf HB |
332 | } |
333 | ||
4fe27d2a | 334 | void kvmppc_core_dequeue_external(struct kvm_vcpu *vcpu) |
4496f974 AG |
335 | { |
336 | clear_bit(BOOKE_IRQPRIO_EXTERNAL, &vcpu->arch.pending_exceptions); | |
c5335f17 | 337 | clear_bit(BOOKE_IRQPRIO_EXTERNAL_LEVEL, &vcpu->arch.pending_exceptions); |
4496f974 AG |
338 | } |
339 | ||
f61c94bb BB |
340 | static void kvmppc_core_queue_watchdog(struct kvm_vcpu *vcpu) |
341 | { | |
342 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_WATCHDOG); | |
343 | } | |
344 | ||
345 | static void kvmppc_core_dequeue_watchdog(struct kvm_vcpu *vcpu) | |
346 | { | |
347 | clear_bit(BOOKE_IRQPRIO_WATCHDOG, &vcpu->arch.pending_exceptions); | |
348 | } | |
349 | ||
2f699a59 BB |
350 | void kvmppc_core_queue_debug(struct kvm_vcpu *vcpu) |
351 | { | |
352 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DEBUG); | |
353 | } | |
354 | ||
355 | void kvmppc_core_dequeue_debug(struct kvm_vcpu *vcpu) | |
356 | { | |
357 | clear_bit(BOOKE_IRQPRIO_DEBUG, &vcpu->arch.pending_exceptions); | |
358 | } | |
359 | ||
d30f6e48 SW |
360 | static void set_guest_srr(struct kvm_vcpu *vcpu, unsigned long srr0, u32 srr1) |
361 | { | |
31579eea BB |
362 | kvmppc_set_srr0(vcpu, srr0); |
363 | kvmppc_set_srr1(vcpu, srr1); | |
d30f6e48 SW |
364 | } |
365 | ||
366 | static void set_guest_csrr(struct kvm_vcpu *vcpu, unsigned long srr0, u32 srr1) | |
367 | { | |
368 | vcpu->arch.csrr0 = srr0; | |
369 | vcpu->arch.csrr1 = srr1; | |
370 | } | |
371 | ||
372 | static void set_guest_dsrr(struct kvm_vcpu *vcpu, unsigned long srr0, u32 srr1) | |
373 | { | |
374 | if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC)) { | |
375 | vcpu->arch.dsrr0 = srr0; | |
376 | vcpu->arch.dsrr1 = srr1; | |
377 | } else { | |
378 | set_guest_csrr(vcpu, srr0, srr1); | |
379 | } | |
380 | } | |
381 | ||
382 | static void set_guest_mcsrr(struct kvm_vcpu *vcpu, unsigned long srr0, u32 srr1) | |
383 | { | |
384 | vcpu->arch.mcsrr0 = srr0; | |
385 | vcpu->arch.mcsrr1 = srr1; | |
386 | } | |
387 | ||
d4cf3892 HB |
388 | /* Deliver the interrupt of the corresponding priority, if possible. */ |
389 | static int kvmppc_booke_irqprio_deliver(struct kvm_vcpu *vcpu, | |
390 | unsigned int priority) | |
bbf45ba5 | 391 | { |
d4cf3892 | 392 | int allowed = 0; |
79300f8c | 393 | ulong msr_mask = 0; |
1c810636 | 394 | bool update_esr = false, update_dear = false, update_epr = false; |
5c6cedf4 AG |
395 | ulong crit_raw = vcpu->arch.shared->critical; |
396 | ulong crit_r1 = kvmppc_get_gpr(vcpu, 1); | |
397 | bool crit; | |
c5335f17 | 398 | bool keep_irq = false; |
d30f6e48 | 399 | enum int_class int_class; |
95e90b43 | 400 | ulong new_msr = vcpu->arch.shared->msr; |
5c6cedf4 AG |
401 | |
402 | /* Truncate crit indicators in 32 bit mode */ | |
403 | if (!(vcpu->arch.shared->msr & MSR_SF)) { | |
404 | crit_raw &= 0xffffffff; | |
405 | crit_r1 &= 0xffffffff; | |
406 | } | |
407 | ||
408 | /* Critical section when crit == r1 */ | |
409 | crit = (crit_raw == crit_r1); | |
410 | /* ... and we're in supervisor mode */ | |
411 | crit = crit && !(vcpu->arch.shared->msr & MSR_PR); | |
d4cf3892 | 412 | |
c5335f17 AG |
413 | if (priority == BOOKE_IRQPRIO_EXTERNAL_LEVEL) { |
414 | priority = BOOKE_IRQPRIO_EXTERNAL; | |
415 | keep_irq = true; | |
416 | } | |
417 | ||
5df554ad | 418 | if ((priority == BOOKE_IRQPRIO_EXTERNAL) && vcpu->arch.epr_flags) |
1c810636 AG |
419 | update_epr = true; |
420 | ||
d4cf3892 | 421 | switch (priority) { |
d4cf3892 | 422 | case BOOKE_IRQPRIO_DTLB_MISS: |
d4cf3892 | 423 | case BOOKE_IRQPRIO_DATA_STORAGE: |
011da899 | 424 | case BOOKE_IRQPRIO_ALIGNMENT: |
daf5e271 LY |
425 | update_dear = true; |
426 | /* fall through */ | |
d4cf3892 | 427 | case BOOKE_IRQPRIO_INST_STORAGE: |
daf5e271 LY |
428 | case BOOKE_IRQPRIO_PROGRAM: |
429 | update_esr = true; | |
430 | /* fall through */ | |
431 | case BOOKE_IRQPRIO_ITLB_MISS: | |
432 | case BOOKE_IRQPRIO_SYSCALL: | |
d4cf3892 | 433 | case BOOKE_IRQPRIO_FP_UNAVAIL: |
95d80a29 | 434 | #ifdef CONFIG_SPE_POSSIBLE |
bb3a8a17 HB |
435 | case BOOKE_IRQPRIO_SPE_UNAVAIL: |
436 | case BOOKE_IRQPRIO_SPE_FP_DATA: | |
437 | case BOOKE_IRQPRIO_SPE_FP_ROUND: | |
95d80a29 MC |
438 | #endif |
439 | #ifdef CONFIG_ALTIVEC | |
440 | case BOOKE_IRQPRIO_ALTIVEC_UNAVAIL: | |
441 | case BOOKE_IRQPRIO_ALTIVEC_ASSIST: | |
442 | #endif | |
d4cf3892 | 443 | case BOOKE_IRQPRIO_AP_UNAVAIL: |
d4cf3892 | 444 | allowed = 1; |
79300f8c | 445 | msr_mask = MSR_CE | MSR_ME | MSR_DE; |
d30f6e48 | 446 | int_class = INT_CLASS_NONCRIT; |
bbf45ba5 | 447 | break; |
f61c94bb | 448 | case BOOKE_IRQPRIO_WATCHDOG: |
d4cf3892 | 449 | case BOOKE_IRQPRIO_CRITICAL: |
4ab96919 | 450 | case BOOKE_IRQPRIO_DBELL_CRIT: |
666e7252 | 451 | allowed = vcpu->arch.shared->msr & MSR_CE; |
d30f6e48 | 452 | allowed = allowed && !crit; |
79300f8c | 453 | msr_mask = MSR_ME; |
d30f6e48 | 454 | int_class = INT_CLASS_CRIT; |
bbf45ba5 | 455 | break; |
d4cf3892 | 456 | case BOOKE_IRQPRIO_MACHINE_CHECK: |
666e7252 | 457 | allowed = vcpu->arch.shared->msr & MSR_ME; |
d30f6e48 | 458 | allowed = allowed && !crit; |
d30f6e48 | 459 | int_class = INT_CLASS_MC; |
bbf45ba5 | 460 | break; |
d4cf3892 HB |
461 | case BOOKE_IRQPRIO_DECREMENTER: |
462 | case BOOKE_IRQPRIO_FIT: | |
dfd4d47e SW |
463 | keep_irq = true; |
464 | /* fall through */ | |
465 | case BOOKE_IRQPRIO_EXTERNAL: | |
4ab96919 | 466 | case BOOKE_IRQPRIO_DBELL: |
666e7252 | 467 | allowed = vcpu->arch.shared->msr & MSR_EE; |
5c6cedf4 | 468 | allowed = allowed && !crit; |
79300f8c | 469 | msr_mask = MSR_CE | MSR_ME | MSR_DE; |
d30f6e48 | 470 | int_class = INT_CLASS_NONCRIT; |
bbf45ba5 | 471 | break; |
d4cf3892 | 472 | case BOOKE_IRQPRIO_DEBUG: |
666e7252 | 473 | allowed = vcpu->arch.shared->msr & MSR_DE; |
d30f6e48 | 474 | allowed = allowed && !crit; |
79300f8c | 475 | msr_mask = MSR_ME; |
9fee7563 BB |
476 | if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC)) |
477 | int_class = INT_CLASS_DBG; | |
478 | else | |
479 | int_class = INT_CLASS_CRIT; | |
480 | ||
bbf45ba5 | 481 | break; |
bbf45ba5 HB |
482 | } |
483 | ||
d4cf3892 | 484 | if (allowed) { |
d30f6e48 SW |
485 | switch (int_class) { |
486 | case INT_CLASS_NONCRIT: | |
487 | set_guest_srr(vcpu, vcpu->arch.pc, | |
488 | vcpu->arch.shared->msr); | |
489 | break; | |
490 | case INT_CLASS_CRIT: | |
491 | set_guest_csrr(vcpu, vcpu->arch.pc, | |
492 | vcpu->arch.shared->msr); | |
493 | break; | |
494 | case INT_CLASS_DBG: | |
495 | set_guest_dsrr(vcpu, vcpu->arch.pc, | |
496 | vcpu->arch.shared->msr); | |
497 | break; | |
498 | case INT_CLASS_MC: | |
499 | set_guest_mcsrr(vcpu, vcpu->arch.pc, | |
500 | vcpu->arch.shared->msr); | |
501 | break; | |
502 | } | |
503 | ||
d4cf3892 | 504 | vcpu->arch.pc = vcpu->arch.ivpr | vcpu->arch.ivor[priority]; |
daf5e271 | 505 | if (update_esr == true) |
dc168549 | 506 | kvmppc_set_esr(vcpu, vcpu->arch.queued_esr); |
daf5e271 | 507 | if (update_dear == true) |
a5414d4b | 508 | kvmppc_set_dar(vcpu, vcpu->arch.queued_dear); |
5df554ad SW |
509 | if (update_epr == true) { |
510 | if (vcpu->arch.epr_flags & KVMPPC_EPR_USER) | |
511 | kvm_make_request(KVM_REQ_EPR_EXIT, vcpu); | |
eb1e4f43 SW |
512 | else if (vcpu->arch.epr_flags & KVMPPC_EPR_KERNEL) { |
513 | BUG_ON(vcpu->arch.irq_type != KVMPPC_IRQ_MPIC); | |
514 | kvmppc_mpic_set_epr(vcpu); | |
515 | } | |
5df554ad | 516 | } |
95e90b43 MC |
517 | |
518 | new_msr &= msr_mask; | |
519 | #if defined(CONFIG_64BIT) | |
520 | if (vcpu->arch.epcr & SPRN_EPCR_ICM) | |
521 | new_msr |= MSR_CM; | |
522 | #endif | |
523 | kvmppc_set_msr(vcpu, new_msr); | |
bbf45ba5 | 524 | |
c5335f17 AG |
525 | if (!keep_irq) |
526 | clear_bit(priority, &vcpu->arch.pending_exceptions); | |
bbf45ba5 HB |
527 | } |
528 | ||
d30f6e48 SW |
529 | #ifdef CONFIG_KVM_BOOKE_HV |
530 | /* | |
531 | * If an interrupt is pending but masked, raise a guest doorbell | |
532 | * so that we are notified when the guest enables the relevant | |
533 | * MSR bit. | |
534 | */ | |
535 | if (vcpu->arch.pending_exceptions & BOOKE_IRQMASK_EE) | |
536 | kvmppc_set_pending_interrupt(vcpu, INT_CLASS_NONCRIT); | |
537 | if (vcpu->arch.pending_exceptions & BOOKE_IRQMASK_CE) | |
538 | kvmppc_set_pending_interrupt(vcpu, INT_CLASS_CRIT); | |
539 | if (vcpu->arch.pending_exceptions & BOOKE_IRQPRIO_MACHINE_CHECK) | |
540 | kvmppc_set_pending_interrupt(vcpu, INT_CLASS_MC); | |
541 | #endif | |
542 | ||
d4cf3892 | 543 | return allowed; |
bbf45ba5 HB |
544 | } |
545 | ||
f61c94bb BB |
546 | /* |
547 | * Return the number of jiffies until the next timeout. If the timeout is | |
548 | * longer than the NEXT_TIMER_MAX_DELTA, then return NEXT_TIMER_MAX_DELTA | |
549 | * because the larger value can break the timer APIs. | |
550 | */ | |
551 | static unsigned long watchdog_next_timeout(struct kvm_vcpu *vcpu) | |
552 | { | |
553 | u64 tb, wdt_tb, wdt_ticks = 0; | |
554 | u64 nr_jiffies = 0; | |
555 | u32 period = TCR_GET_WP(vcpu->arch.tcr); | |
556 | ||
557 | wdt_tb = 1ULL << (63 - period); | |
558 | tb = get_tb(); | |
559 | /* | |
560 | * The watchdog timeout will hapeen when TB bit corresponding | |
561 | * to watchdog will toggle from 0 to 1. | |
562 | */ | |
563 | if (tb & wdt_tb) | |
564 | wdt_ticks = wdt_tb; | |
565 | ||
566 | wdt_ticks += wdt_tb - (tb & (wdt_tb - 1)); | |
567 | ||
568 | /* Convert timebase ticks to jiffies */ | |
569 | nr_jiffies = wdt_ticks; | |
570 | ||
571 | if (do_div(nr_jiffies, tb_ticks_per_jiffy)) | |
572 | nr_jiffies++; | |
573 | ||
574 | return min_t(unsigned long long, nr_jiffies, NEXT_TIMER_MAX_DELTA); | |
575 | } | |
576 | ||
577 | static void arm_next_watchdog(struct kvm_vcpu *vcpu) | |
578 | { | |
579 | unsigned long nr_jiffies; | |
580 | unsigned long flags; | |
581 | ||
582 | /* | |
583 | * If TSR_ENW and TSR_WIS are not set then no need to exit to | |
584 | * userspace, so clear the KVM_REQ_WATCHDOG request. | |
585 | */ | |
586 | if ((vcpu->arch.tsr & (TSR_ENW | TSR_WIS)) != (TSR_ENW | TSR_WIS)) | |
72875d8a | 587 | kvm_clear_request(KVM_REQ_WATCHDOG, vcpu); |
f61c94bb BB |
588 | |
589 | spin_lock_irqsave(&vcpu->arch.wdt_lock, flags); | |
590 | nr_jiffies = watchdog_next_timeout(vcpu); | |
591 | /* | |
592 | * If the number of jiffies of watchdog timer >= NEXT_TIMER_MAX_DELTA | |
593 | * then do not run the watchdog timer as this can break timer APIs. | |
594 | */ | |
595 | if (nr_jiffies < NEXT_TIMER_MAX_DELTA) | |
596 | mod_timer(&vcpu->arch.wdt_timer, jiffies + nr_jiffies); | |
597 | else | |
598 | del_timer(&vcpu->arch.wdt_timer); | |
599 | spin_unlock_irqrestore(&vcpu->arch.wdt_lock, flags); | |
600 | } | |
601 | ||
86cb30ec | 602 | void kvmppc_watchdog_func(struct timer_list *t) |
f61c94bb | 603 | { |
86cb30ec | 604 | struct kvm_vcpu *vcpu = from_timer(vcpu, t, arch.wdt_timer); |
f61c94bb BB |
605 | u32 tsr, new_tsr; |
606 | int final; | |
607 | ||
608 | do { | |
609 | new_tsr = tsr = vcpu->arch.tsr; | |
610 | final = 0; | |
611 | ||
612 | /* Time out event */ | |
613 | if (tsr & TSR_ENW) { | |
614 | if (tsr & TSR_WIS) | |
615 | final = 1; | |
616 | else | |
617 | new_tsr = tsr | TSR_WIS; | |
618 | } else { | |
619 | new_tsr = tsr | TSR_ENW; | |
620 | } | |
621 | } while (cmpxchg(&vcpu->arch.tsr, tsr, new_tsr) != tsr); | |
622 | ||
623 | if (new_tsr & TSR_WIS) { | |
624 | smp_wmb(); | |
625 | kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); | |
626 | kvm_vcpu_kick(vcpu); | |
627 | } | |
628 | ||
629 | /* | |
630 | * If this is final watchdog expiry and some action is required | |
631 | * then exit to userspace. | |
632 | */ | |
633 | if (final && (vcpu->arch.tcr & TCR_WRC_MASK) && | |
634 | vcpu->arch.watchdog_enabled) { | |
635 | smp_wmb(); | |
636 | kvm_make_request(KVM_REQ_WATCHDOG, vcpu); | |
637 | kvm_vcpu_kick(vcpu); | |
638 | } | |
639 | ||
640 | /* | |
641 | * Stop running the watchdog timer after final expiration to | |
642 | * prevent the host from being flooded with timers if the | |
643 | * guest sets a short period. | |
644 | * Timers will resume when TSR/TCR is updated next time. | |
645 | */ | |
646 | if (!final) | |
647 | arm_next_watchdog(vcpu); | |
648 | } | |
649 | ||
dfd4d47e SW |
650 | static void update_timer_ints(struct kvm_vcpu *vcpu) |
651 | { | |
652 | if ((vcpu->arch.tcr & TCR_DIE) && (vcpu->arch.tsr & TSR_DIS)) | |
653 | kvmppc_core_queue_dec(vcpu); | |
654 | else | |
655 | kvmppc_core_dequeue_dec(vcpu); | |
f61c94bb BB |
656 | |
657 | if ((vcpu->arch.tcr & TCR_WIE) && (vcpu->arch.tsr & TSR_WIS)) | |
658 | kvmppc_core_queue_watchdog(vcpu); | |
659 | else | |
660 | kvmppc_core_dequeue_watchdog(vcpu); | |
dfd4d47e SW |
661 | } |
662 | ||
c59a6a3e | 663 | static void kvmppc_core_check_exceptions(struct kvm_vcpu *vcpu) |
bbf45ba5 HB |
664 | { |
665 | unsigned long *pending = &vcpu->arch.pending_exceptions; | |
bbf45ba5 HB |
666 | unsigned int priority; |
667 | ||
9ab80843 | 668 | priority = __ffs(*pending); |
8b3a00fc | 669 | while (priority < BOOKE_IRQPRIO_MAX) { |
d4cf3892 | 670 | if (kvmppc_booke_irqprio_deliver(vcpu, priority)) |
bbf45ba5 | 671 | break; |
bbf45ba5 HB |
672 | |
673 | priority = find_next_bit(pending, | |
674 | BITS_PER_BYTE * sizeof(*pending), | |
675 | priority + 1); | |
676 | } | |
90bba358 AG |
677 | |
678 | /* Tell the guest about our interrupt status */ | |
29ac26ef | 679 | vcpu->arch.shared->int_pending = !!*pending; |
bbf45ba5 HB |
680 | } |
681 | ||
c59a6a3e | 682 | /* Check pending exceptions and deliver one, if possible. */ |
a8e4ef84 | 683 | int kvmppc_core_prepare_to_enter(struct kvm_vcpu *vcpu) |
c59a6a3e | 684 | { |
a8e4ef84 | 685 | int r = 0; |
c59a6a3e SW |
686 | WARN_ON_ONCE(!irqs_disabled()); |
687 | ||
688 | kvmppc_core_check_exceptions(vcpu); | |
689 | ||
2fa6e1e1 | 690 | if (kvm_request_pending(vcpu)) { |
b8c649a9 AG |
691 | /* Exception delivery raised request; start over */ |
692 | return 1; | |
693 | } | |
694 | ||
c59a6a3e SW |
695 | if (vcpu->arch.shared->msr & MSR_WE) { |
696 | local_irq_enable(); | |
697 | kvm_vcpu_block(vcpu); | |
72875d8a | 698 | kvm_clear_request(KVM_REQ_UNHALT, vcpu); |
6c85f52b | 699 | hard_irq_disable(); |
c59a6a3e SW |
700 | |
701 | kvmppc_set_exit_type(vcpu, EMULATED_MTMSRWE_EXITS); | |
a8e4ef84 | 702 | r = 1; |
c59a6a3e | 703 | }; |
a8e4ef84 AG |
704 | |
705 | return r; | |
706 | } | |
707 | ||
7c973a2e | 708 | int kvmppc_core_check_requests(struct kvm_vcpu *vcpu) |
4ffc6356 | 709 | { |
7c973a2e AG |
710 | int r = 1; /* Indicate we want to get back into the guest */ |
711 | ||
2d8185d4 AG |
712 | if (kvm_check_request(KVM_REQ_PENDING_TIMER, vcpu)) |
713 | update_timer_ints(vcpu); | |
862d31f7 | 714 | #if defined(CONFIG_KVM_E500V2) || defined(CONFIG_KVM_E500MC) |
2d8185d4 AG |
715 | if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) |
716 | kvmppc_core_flush_tlb(vcpu); | |
862d31f7 | 717 | #endif |
7c973a2e | 718 | |
f61c94bb BB |
719 | if (kvm_check_request(KVM_REQ_WATCHDOG, vcpu)) { |
720 | vcpu->run->exit_reason = KVM_EXIT_WATCHDOG; | |
721 | r = 0; | |
722 | } | |
723 | ||
1c810636 AG |
724 | if (kvm_check_request(KVM_REQ_EPR_EXIT, vcpu)) { |
725 | vcpu->run->epr.epr = 0; | |
726 | vcpu->arch.epr_needed = true; | |
727 | vcpu->run->exit_reason = KVM_EXIT_EPR; | |
728 | r = 0; | |
729 | } | |
730 | ||
7c973a2e | 731 | return r; |
4ffc6356 AG |
732 | } |
733 | ||
df6909e5 PM |
734 | int kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu) |
735 | { | |
7ee78855 | 736 | int ret, s; |
f5f97210 | 737 | struct debug_reg debug; |
df6909e5 | 738 | |
af8f38b3 AG |
739 | if (!vcpu->arch.sane) { |
740 | kvm_run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
741 | return -EINVAL; | |
742 | } | |
743 | ||
7ee78855 AG |
744 | s = kvmppc_prepare_to_enter(vcpu); |
745 | if (s <= 0) { | |
7ee78855 | 746 | ret = s; |
1d1ef222 SW |
747 | goto out; |
748 | } | |
6c85f52b | 749 | /* interrupts now hard-disabled */ |
1d1ef222 | 750 | |
8fae845f SW |
751 | #ifdef CONFIG_PPC_FPU |
752 | /* Save userspace FPU state in stack */ | |
753 | enable_kernel_fp(); | |
8fae845f SW |
754 | |
755 | /* | |
756 | * Since we can't trap on MSR_FP in GS-mode, we consider the guest | |
3efc7da6 | 757 | * as always using the FPU. |
8fae845f | 758 | */ |
8fae845f SW |
759 | kvmppc_load_guest_fp(vcpu); |
760 | #endif | |
761 | ||
95d80a29 MC |
762 | #ifdef CONFIG_ALTIVEC |
763 | /* Save userspace AltiVec state in stack */ | |
764 | if (cpu_has_feature(CPU_FTR_ALTIVEC)) | |
765 | enable_kernel_altivec(); | |
766 | /* | |
767 | * Since we can't trap on MSR_VEC in GS-mode, we consider the guest | |
768 | * as always using the AltiVec. | |
769 | */ | |
770 | kvmppc_load_guest_altivec(vcpu); | |
771 | #endif | |
772 | ||
ce11e48b | 773 | /* Switch to guest debug context */ |
348ba710 | 774 | debug = vcpu->arch.dbg_reg; |
f5f97210 SW |
775 | switch_booke_debug_regs(&debug); |
776 | debug = current->thread.debug; | |
348ba710 | 777 | current->thread.debug = vcpu->arch.dbg_reg; |
ce11e48b | 778 | |
08c9a188 | 779 | vcpu->arch.pgdir = current->mm->pgd; |
5f1c248f | 780 | kvmppc_fix_ee_before_entry(); |
f8941fbe | 781 | |
df6909e5 | 782 | ret = __kvmppc_vcpu_run(kvm_run, vcpu); |
8fae845f | 783 | |
6edaa530 | 784 | /* No need for guest_exit. It's done in handle_exit. |
24afa37b AG |
785 | We also get here with interrupts enabled. */ |
786 | ||
ce11e48b | 787 | /* Switch back to user space debug context */ |
f5f97210 SW |
788 | switch_booke_debug_regs(&debug); |
789 | current->thread.debug = debug; | |
ce11e48b | 790 | |
8fae845f SW |
791 | #ifdef CONFIG_PPC_FPU |
792 | kvmppc_save_guest_fp(vcpu); | |
8fae845f SW |
793 | #endif |
794 | ||
95d80a29 MC |
795 | #ifdef CONFIG_ALTIVEC |
796 | kvmppc_save_guest_altivec(vcpu); | |
797 | #endif | |
798 | ||
1d1ef222 | 799 | out: |
d69c6436 | 800 | vcpu->mode = OUTSIDE_GUEST_MODE; |
df6909e5 PM |
801 | return ret; |
802 | } | |
803 | ||
d30f6e48 SW |
804 | static int emulation_exit(struct kvm_run *run, struct kvm_vcpu *vcpu) |
805 | { | |
806 | enum emulation_result er; | |
807 | ||
808 | er = kvmppc_emulate_instruction(run, vcpu); | |
809 | switch (er) { | |
810 | case EMULATE_DONE: | |
811 | /* don't overwrite subtypes, just account kvm_stats */ | |
812 | kvmppc_account_exit_stat(vcpu, EMULATED_INST_EXITS); | |
813 | /* Future optimization: only reload non-volatiles if | |
814 | * they were actually modified by emulation. */ | |
815 | return RESUME_GUEST_NV; | |
816 | ||
51f04726 MC |
817 | case EMULATE_AGAIN: |
818 | return RESUME_GUEST; | |
819 | ||
d30f6e48 | 820 | case EMULATE_FAIL: |
d30f6e48 SW |
821 | printk(KERN_CRIT "%s: emulation at %lx failed (%08x)\n", |
822 | __func__, vcpu->arch.pc, vcpu->arch.last_inst); | |
823 | /* For debugging, encode the failing instruction and | |
824 | * report it to userspace. */ | |
825 | run->hw.hardware_exit_reason = ~0ULL << 32; | |
826 | run->hw.hardware_exit_reason |= vcpu->arch.last_inst; | |
d1ff5499 | 827 | kvmppc_core_queue_program(vcpu, ESR_PIL); |
d30f6e48 SW |
828 | return RESUME_HOST; |
829 | ||
9b4f5308 BB |
830 | case EMULATE_EXIT_USER: |
831 | return RESUME_HOST; | |
832 | ||
d30f6e48 SW |
833 | default: |
834 | BUG(); | |
835 | } | |
836 | } | |
837 | ||
ce11e48b BB |
838 | static int kvmppc_handle_debug(struct kvm_run *run, struct kvm_vcpu *vcpu) |
839 | { | |
348ba710 | 840 | struct debug_reg *dbg_reg = &(vcpu->arch.dbg_reg); |
ce11e48b BB |
841 | u32 dbsr = vcpu->arch.dbsr; |
842 | ||
2f699a59 BB |
843 | if (vcpu->guest_debug == 0) { |
844 | /* | |
845 | * Debug resources belong to Guest. | |
846 | * Imprecise debug event is not injected | |
847 | */ | |
848 | if (dbsr & DBSR_IDE) { | |
849 | dbsr &= ~DBSR_IDE; | |
850 | if (!dbsr) | |
851 | return RESUME_GUEST; | |
852 | } | |
853 | ||
854 | if (dbsr && (vcpu->arch.shared->msr & MSR_DE) && | |
855 | (vcpu->arch.dbg_reg.dbcr0 & DBCR0_IDM)) | |
856 | kvmppc_core_queue_debug(vcpu); | |
857 | ||
858 | /* Inject a program interrupt if trap debug is not allowed */ | |
859 | if ((dbsr & DBSR_TIE) && !(vcpu->arch.shared->msr & MSR_DE)) | |
860 | kvmppc_core_queue_program(vcpu, ESR_PTR); | |
861 | ||
862 | return RESUME_GUEST; | |
863 | } | |
864 | ||
865 | /* | |
866 | * Debug resource owned by userspace. | |
867 | * Clear guest dbsr (vcpu->arch.dbsr) | |
868 | */ | |
2190991e | 869 | vcpu->arch.dbsr = 0; |
ce11e48b BB |
870 | run->debug.arch.status = 0; |
871 | run->debug.arch.address = vcpu->arch.pc; | |
872 | ||
873 | if (dbsr & (DBSR_IAC1 | DBSR_IAC2 | DBSR_IAC3 | DBSR_IAC4)) { | |
874 | run->debug.arch.status |= KVMPPC_DEBUG_BREAKPOINT; | |
875 | } else { | |
876 | if (dbsr & (DBSR_DAC1W | DBSR_DAC2W)) | |
877 | run->debug.arch.status |= KVMPPC_DEBUG_WATCH_WRITE; | |
878 | else if (dbsr & (DBSR_DAC1R | DBSR_DAC2R)) | |
879 | run->debug.arch.status |= KVMPPC_DEBUG_WATCH_READ; | |
880 | if (dbsr & (DBSR_DAC1R | DBSR_DAC1W)) | |
881 | run->debug.arch.address = dbg_reg->dac1; | |
882 | else if (dbsr & (DBSR_DAC2R | DBSR_DAC2W)) | |
883 | run->debug.arch.address = dbg_reg->dac2; | |
884 | } | |
885 | ||
886 | return RESUME_HOST; | |
887 | } | |
888 | ||
4e642ccb | 889 | static void kvmppc_fill_pt_regs(struct pt_regs *regs) |
bbf45ba5 | 890 | { |
4e642ccb | 891 | ulong r1, ip, msr, lr; |
bbf45ba5 | 892 | |
4e642ccb AG |
893 | asm("mr %0, 1" : "=r"(r1)); |
894 | asm("mflr %0" : "=r"(lr)); | |
895 | asm("mfmsr %0" : "=r"(msr)); | |
896 | asm("bl 1f; 1: mflr %0" : "=r"(ip)); | |
897 | ||
898 | memset(regs, 0, sizeof(*regs)); | |
899 | regs->gpr[1] = r1; | |
900 | regs->nip = ip; | |
901 | regs->msr = msr; | |
902 | regs->link = lr; | |
903 | } | |
904 | ||
6328e593 BB |
905 | /* |
906 | * For interrupts needed to be handled by host interrupt handlers, | |
907 | * corresponding host handler are called from here in similar way | |
908 | * (but not exact) as they are called from low level handler | |
909 | * (such as from arch/powerpc/kernel/head_fsl_booke.S). | |
910 | */ | |
4e642ccb AG |
911 | static void kvmppc_restart_interrupt(struct kvm_vcpu *vcpu, |
912 | unsigned int exit_nr) | |
913 | { | |
914 | struct pt_regs regs; | |
73e75b41 | 915 | |
d30f6e48 SW |
916 | switch (exit_nr) { |
917 | case BOOKE_INTERRUPT_EXTERNAL: | |
4e642ccb AG |
918 | kvmppc_fill_pt_regs(®s); |
919 | do_IRQ(®s); | |
d30f6e48 | 920 | break; |
d30f6e48 | 921 | case BOOKE_INTERRUPT_DECREMENTER: |
4e642ccb AG |
922 | kvmppc_fill_pt_regs(®s); |
923 | timer_interrupt(®s); | |
d30f6e48 | 924 | break; |
5f17ce8b | 925 | #if defined(CONFIG_PPC_DOORBELL) |
d30f6e48 | 926 | case BOOKE_INTERRUPT_DOORBELL: |
4e642ccb AG |
927 | kvmppc_fill_pt_regs(®s); |
928 | doorbell_exception(®s); | |
d30f6e48 SW |
929 | break; |
930 | #endif | |
931 | case BOOKE_INTERRUPT_MACHINE_CHECK: | |
932 | /* FIXME */ | |
933 | break; | |
7cc1e8ee AG |
934 | case BOOKE_INTERRUPT_PERFORMANCE_MONITOR: |
935 | kvmppc_fill_pt_regs(®s); | |
936 | performance_monitor_exception(®s); | |
937 | break; | |
6328e593 BB |
938 | case BOOKE_INTERRUPT_WATCHDOG: |
939 | kvmppc_fill_pt_regs(®s); | |
940 | #ifdef CONFIG_BOOKE_WDT | |
941 | WatchdogException(®s); | |
942 | #else | |
943 | unknown_exception(®s); | |
944 | #endif | |
945 | break; | |
946 | case BOOKE_INTERRUPT_CRITICAL: | |
845ac985 | 947 | kvmppc_fill_pt_regs(®s); |
6328e593 BB |
948 | unknown_exception(®s); |
949 | break; | |
ce11e48b BB |
950 | case BOOKE_INTERRUPT_DEBUG: |
951 | /* Save DBSR before preemption is enabled */ | |
952 | vcpu->arch.dbsr = mfspr(SPRN_DBSR); | |
953 | kvmppc_clear_dbsr(); | |
954 | break; | |
d30f6e48 | 955 | } |
4e642ccb AG |
956 | } |
957 | ||
f5250471 MC |
958 | static int kvmppc_resume_inst_load(struct kvm_run *run, struct kvm_vcpu *vcpu, |
959 | enum emulation_result emulated, u32 last_inst) | |
960 | { | |
961 | switch (emulated) { | |
962 | case EMULATE_AGAIN: | |
963 | return RESUME_GUEST; | |
964 | ||
965 | case EMULATE_FAIL: | |
966 | pr_debug("%s: load instruction from guest address %lx failed\n", | |
967 | __func__, vcpu->arch.pc); | |
968 | /* For debugging, encode the failing instruction and | |
969 | * report it to userspace. */ | |
970 | run->hw.hardware_exit_reason = ~0ULL << 32; | |
971 | run->hw.hardware_exit_reason |= last_inst; | |
972 | kvmppc_core_queue_program(vcpu, ESR_PIL); | |
973 | return RESUME_HOST; | |
974 | ||
975 | default: | |
976 | BUG(); | |
977 | } | |
978 | } | |
979 | ||
4e642ccb AG |
980 | /** |
981 | * kvmppc_handle_exit | |
982 | * | |
983 | * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV) | |
984 | */ | |
985 | int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu, | |
986 | unsigned int exit_nr) | |
987 | { | |
988 | int r = RESUME_HOST; | |
7ee78855 | 989 | int s; |
f1e89028 | 990 | int idx; |
f5250471 MC |
991 | u32 last_inst = KVM_INST_FETCH_FAILED; |
992 | enum emulation_result emulated = EMULATE_DONE; | |
4e642ccb AG |
993 | |
994 | /* update before a new last_exit_type is rewritten */ | |
995 | kvmppc_update_timing_stats(vcpu); | |
996 | ||
997 | /* restart interrupts if they were meant for the host */ | |
998 | kvmppc_restart_interrupt(vcpu, exit_nr); | |
d30f6e48 | 999 | |
f5250471 | 1000 | /* |
446957ba | 1001 | * get last instruction before being preempted |
f5250471 MC |
1002 | * TODO: for e6500 check also BOOKE_INTERRUPT_LRAT_ERROR & ESR_DATA |
1003 | */ | |
1004 | switch (exit_nr) { | |
1005 | case BOOKE_INTERRUPT_DATA_STORAGE: | |
1006 | case BOOKE_INTERRUPT_DTLB_MISS: | |
1007 | case BOOKE_INTERRUPT_HV_PRIV: | |
8d0eff63 | 1008 | emulated = kvmppc_get_last_inst(vcpu, INST_GENERIC, &last_inst); |
f5250471 | 1009 | break; |
033aaa14 MS |
1010 | case BOOKE_INTERRUPT_PROGRAM: |
1011 | /* SW breakpoints arrive as illegal instructions on HV */ | |
1012 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) | |
8d0eff63 | 1013 | emulated = kvmppc_get_last_inst(vcpu, INST_GENERIC, &last_inst); |
033aaa14 | 1014 | break; |
f5250471 MC |
1015 | default: |
1016 | break; | |
1017 | } | |
1018 | ||
97c95059 | 1019 | trace_kvm_exit(exit_nr, vcpu); |
6edaa530 | 1020 | guest_exit_irqoff(); |
e233d54d PB |
1021 | |
1022 | local_irq_enable(); | |
97c95059 | 1023 | |
bbf45ba5 HB |
1024 | run->exit_reason = KVM_EXIT_UNKNOWN; |
1025 | run->ready_for_interrupt_injection = 1; | |
1026 | ||
f5250471 MC |
1027 | if (emulated != EMULATE_DONE) { |
1028 | r = kvmppc_resume_inst_load(run, vcpu, emulated, last_inst); | |
1029 | goto out; | |
1030 | } | |
1031 | ||
bbf45ba5 HB |
1032 | switch (exit_nr) { |
1033 | case BOOKE_INTERRUPT_MACHINE_CHECK: | |
c35c9d84 AG |
1034 | printk("MACHINE CHECK: %lx\n", mfspr(SPRN_MCSR)); |
1035 | kvmppc_dump_vcpu(vcpu); | |
1036 | /* For debugging, send invalid exit reason to user space */ | |
1037 | run->hw.hardware_exit_reason = ~1ULL << 32; | |
1038 | run->hw.hardware_exit_reason |= mfspr(SPRN_MCSR); | |
1039 | r = RESUME_HOST; | |
bbf45ba5 HB |
1040 | break; |
1041 | ||
1042 | case BOOKE_INTERRUPT_EXTERNAL: | |
7b701591 | 1043 | kvmppc_account_exit(vcpu, EXT_INTR_EXITS); |
1b6766c7 HB |
1044 | r = RESUME_GUEST; |
1045 | break; | |
1046 | ||
bbf45ba5 | 1047 | case BOOKE_INTERRUPT_DECREMENTER: |
7b701591 | 1048 | kvmppc_account_exit(vcpu, DEC_EXITS); |
bbf45ba5 HB |
1049 | r = RESUME_GUEST; |
1050 | break; | |
1051 | ||
6328e593 BB |
1052 | case BOOKE_INTERRUPT_WATCHDOG: |
1053 | r = RESUME_GUEST; | |
1054 | break; | |
1055 | ||
d30f6e48 SW |
1056 | case BOOKE_INTERRUPT_DOORBELL: |
1057 | kvmppc_account_exit(vcpu, DBELL_EXITS); | |
d30f6e48 SW |
1058 | r = RESUME_GUEST; |
1059 | break; | |
1060 | ||
1061 | case BOOKE_INTERRUPT_GUEST_DBELL_CRIT: | |
1062 | kvmppc_account_exit(vcpu, GDBELL_EXITS); | |
1063 | ||
1064 | /* | |
1065 | * We are here because there is a pending guest interrupt | |
1066 | * which could not be delivered as MSR_CE or MSR_ME was not | |
1067 | * set. Once we break from here we will retry delivery. | |
1068 | */ | |
1069 | r = RESUME_GUEST; | |
1070 | break; | |
1071 | ||
1072 | case BOOKE_INTERRUPT_GUEST_DBELL: | |
1073 | kvmppc_account_exit(vcpu, GDBELL_EXITS); | |
1074 | ||
1075 | /* | |
1076 | * We are here because there is a pending guest interrupt | |
1077 | * which could not be delivered as MSR_EE was not set. Once | |
1078 | * we break from here we will retry delivery. | |
1079 | */ | |
1080 | r = RESUME_GUEST; | |
1081 | break; | |
1082 | ||
95f2e921 AG |
1083 | case BOOKE_INTERRUPT_PERFORMANCE_MONITOR: |
1084 | r = RESUME_GUEST; | |
1085 | break; | |
1086 | ||
d30f6e48 SW |
1087 | case BOOKE_INTERRUPT_HV_PRIV: |
1088 | r = emulation_exit(run, vcpu); | |
1089 | break; | |
1090 | ||
bbf45ba5 | 1091 | case BOOKE_INTERRUPT_PROGRAM: |
033aaa14 MS |
1092 | if ((vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) && |
1093 | (last_inst == KVMPPC_INST_SW_BREAKPOINT)) { | |
1094 | /* | |
1095 | * We are here because of an SW breakpoint instr, | |
1096 | * so lets return to host to handle. | |
1097 | */ | |
1098 | r = kvmppc_handle_debug(run, vcpu); | |
1099 | run->exit_reason = KVM_EXIT_DEBUG; | |
1100 | kvmppc_account_exit(vcpu, DEBUG_EXITS); | |
1101 | break; | |
1102 | } | |
1103 | ||
d30f6e48 | 1104 | if (vcpu->arch.shared->msr & (MSR_PR | MSR_GS)) { |
0268597c AG |
1105 | /* |
1106 | * Program traps generated by user-level software must | |
1107 | * be handled by the guest kernel. | |
1108 | * | |
1109 | * In GS mode, hypervisor privileged instructions trap | |
1110 | * on BOOKE_INTERRUPT_HV_PRIV, not here, so these are | |
1111 | * actual program interrupts, handled by the guest. | |
1112 | */ | |
daf5e271 | 1113 | kvmppc_core_queue_program(vcpu, vcpu->arch.fault_esr); |
bbf45ba5 | 1114 | r = RESUME_GUEST; |
7b701591 | 1115 | kvmppc_account_exit(vcpu, USR_PR_INST); |
bbf45ba5 HB |
1116 | break; |
1117 | } | |
1118 | ||
d30f6e48 | 1119 | r = emulation_exit(run, vcpu); |
bbf45ba5 HB |
1120 | break; |
1121 | ||
de368dce | 1122 | case BOOKE_INTERRUPT_FP_UNAVAIL: |
d4cf3892 | 1123 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_FP_UNAVAIL); |
7b701591 | 1124 | kvmppc_account_exit(vcpu, FP_UNAVAIL); |
de368dce CE |
1125 | r = RESUME_GUEST; |
1126 | break; | |
1127 | ||
4cd35f67 SW |
1128 | #ifdef CONFIG_SPE |
1129 | case BOOKE_INTERRUPT_SPE_UNAVAIL: { | |
1130 | if (vcpu->arch.shared->msr & MSR_SPE) | |
1131 | kvmppc_vcpu_enable_spe(vcpu); | |
1132 | else | |
1133 | kvmppc_booke_queue_irqprio(vcpu, | |
1134 | BOOKE_IRQPRIO_SPE_UNAVAIL); | |
bb3a8a17 HB |
1135 | r = RESUME_GUEST; |
1136 | break; | |
4cd35f67 | 1137 | } |
bb3a8a17 HB |
1138 | |
1139 | case BOOKE_INTERRUPT_SPE_FP_DATA: | |
1140 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_SPE_FP_DATA); | |
1141 | r = RESUME_GUEST; | |
1142 | break; | |
1143 | ||
1144 | case BOOKE_INTERRUPT_SPE_FP_ROUND: | |
1145 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_SPE_FP_ROUND); | |
1146 | r = RESUME_GUEST; | |
1147 | break; | |
95d80a29 | 1148 | #elif defined(CONFIG_SPE_POSSIBLE) |
4cd35f67 SW |
1149 | case BOOKE_INTERRUPT_SPE_UNAVAIL: |
1150 | /* | |
1151 | * Guest wants SPE, but host kernel doesn't support it. Send | |
1152 | * an "unimplemented operation" program check to the guest. | |
1153 | */ | |
1154 | kvmppc_core_queue_program(vcpu, ESR_PUO | ESR_SPV); | |
1155 | r = RESUME_GUEST; | |
1156 | break; | |
1157 | ||
1158 | /* | |
1159 | * These really should never happen without CONFIG_SPE, | |
1160 | * as we should never enable the real MSR[SPE] in the guest. | |
1161 | */ | |
1162 | case BOOKE_INTERRUPT_SPE_FP_DATA: | |
1163 | case BOOKE_INTERRUPT_SPE_FP_ROUND: | |
1164 | printk(KERN_CRIT "%s: unexpected SPE interrupt %u at %08lx\n", | |
1165 | __func__, exit_nr, vcpu->arch.pc); | |
1166 | run->hw.hardware_exit_reason = exit_nr; | |
1167 | r = RESUME_HOST; | |
1168 | break; | |
95d80a29 MC |
1169 | #endif /* CONFIG_SPE_POSSIBLE */ |
1170 | ||
1171 | /* | |
1172 | * On cores with Vector category, KVM is loaded only if CONFIG_ALTIVEC, | |
1173 | * see kvmppc_core_check_processor_compat(). | |
1174 | */ | |
1175 | #ifdef CONFIG_ALTIVEC | |
1176 | case BOOKE_INTERRUPT_ALTIVEC_UNAVAIL: | |
1177 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_ALTIVEC_UNAVAIL); | |
1178 | r = RESUME_GUEST; | |
1179 | break; | |
1180 | ||
1181 | case BOOKE_INTERRUPT_ALTIVEC_ASSIST: | |
1182 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_ALTIVEC_ASSIST); | |
1183 | r = RESUME_GUEST; | |
1184 | break; | |
4cd35f67 | 1185 | #endif |
bb3a8a17 | 1186 | |
bbf45ba5 | 1187 | case BOOKE_INTERRUPT_DATA_STORAGE: |
daf5e271 LY |
1188 | kvmppc_core_queue_data_storage(vcpu, vcpu->arch.fault_dear, |
1189 | vcpu->arch.fault_esr); | |
7b701591 | 1190 | kvmppc_account_exit(vcpu, DSI_EXITS); |
bbf45ba5 HB |
1191 | r = RESUME_GUEST; |
1192 | break; | |
1193 | ||
1194 | case BOOKE_INTERRUPT_INST_STORAGE: | |
daf5e271 | 1195 | kvmppc_core_queue_inst_storage(vcpu, vcpu->arch.fault_esr); |
7b701591 | 1196 | kvmppc_account_exit(vcpu, ISI_EXITS); |
bbf45ba5 HB |
1197 | r = RESUME_GUEST; |
1198 | break; | |
1199 | ||
011da899 AG |
1200 | case BOOKE_INTERRUPT_ALIGNMENT: |
1201 | kvmppc_core_queue_alignment(vcpu, vcpu->arch.fault_dear, | |
1202 | vcpu->arch.fault_esr); | |
1203 | r = RESUME_GUEST; | |
1204 | break; | |
1205 | ||
d30f6e48 SW |
1206 | #ifdef CONFIG_KVM_BOOKE_HV |
1207 | case BOOKE_INTERRUPT_HV_SYSCALL: | |
1208 | if (!(vcpu->arch.shared->msr & MSR_PR)) { | |
1209 | kvmppc_set_gpr(vcpu, 3, kvmppc_kvm_pv(vcpu)); | |
1210 | } else { | |
1211 | /* | |
1212 | * hcall from guest userspace -- send privileged | |
1213 | * instruction program check. | |
1214 | */ | |
1215 | kvmppc_core_queue_program(vcpu, ESR_PPR); | |
1216 | } | |
1217 | ||
1218 | r = RESUME_GUEST; | |
1219 | break; | |
1220 | #else | |
bbf45ba5 | 1221 | case BOOKE_INTERRUPT_SYSCALL: |
2a342ed5 AG |
1222 | if (!(vcpu->arch.shared->msr & MSR_PR) && |
1223 | (((u32)kvmppc_get_gpr(vcpu, 0)) == KVM_SC_MAGIC_R0)) { | |
1224 | /* KVM PV hypercalls */ | |
1225 | kvmppc_set_gpr(vcpu, 3, kvmppc_kvm_pv(vcpu)); | |
1226 | r = RESUME_GUEST; | |
1227 | } else { | |
1228 | /* Guest syscalls */ | |
1229 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_SYSCALL); | |
1230 | } | |
7b701591 | 1231 | kvmppc_account_exit(vcpu, SYSCALL_EXITS); |
bbf45ba5 HB |
1232 | r = RESUME_GUEST; |
1233 | break; | |
d30f6e48 | 1234 | #endif |
bbf45ba5 HB |
1235 | |
1236 | case BOOKE_INTERRUPT_DTLB_MISS: { | |
bbf45ba5 | 1237 | unsigned long eaddr = vcpu->arch.fault_dear; |
7924bd41 | 1238 | int gtlb_index; |
475e7cdd | 1239 | gpa_t gpaddr; |
bbf45ba5 HB |
1240 | gfn_t gfn; |
1241 | ||
bf7ca4bd | 1242 | #ifdef CONFIG_KVM_E500V2 |
a4cd8b23 SW |
1243 | if (!(vcpu->arch.shared->msr & MSR_PR) && |
1244 | (eaddr & PAGE_MASK) == vcpu->arch.magic_page_ea) { | |
1245 | kvmppc_map_magic(vcpu); | |
1246 | kvmppc_account_exit(vcpu, DTLB_VIRT_MISS_EXITS); | |
1247 | r = RESUME_GUEST; | |
1248 | ||
1249 | break; | |
1250 | } | |
1251 | #endif | |
1252 | ||
bbf45ba5 | 1253 | /* Check the guest TLB. */ |
fa86b8dd | 1254 | gtlb_index = kvmppc_mmu_dtlb_index(vcpu, eaddr); |
7924bd41 | 1255 | if (gtlb_index < 0) { |
bbf45ba5 | 1256 | /* The guest didn't have a mapping for it. */ |
daf5e271 LY |
1257 | kvmppc_core_queue_dtlb_miss(vcpu, |
1258 | vcpu->arch.fault_dear, | |
1259 | vcpu->arch.fault_esr); | |
b52a638c | 1260 | kvmppc_mmu_dtlb_miss(vcpu); |
7b701591 | 1261 | kvmppc_account_exit(vcpu, DTLB_REAL_MISS_EXITS); |
bbf45ba5 HB |
1262 | r = RESUME_GUEST; |
1263 | break; | |
1264 | } | |
1265 | ||
f1e89028 SW |
1266 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
1267 | ||
be8d1cae | 1268 | gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr); |
475e7cdd | 1269 | gfn = gpaddr >> PAGE_SHIFT; |
bbf45ba5 HB |
1270 | |
1271 | if (kvm_is_visible_gfn(vcpu->kvm, gfn)) { | |
1272 | /* The guest TLB had a mapping, but the shadow TLB | |
1273 | * didn't, and it is RAM. This could be because: | |
1274 | * a) the entry is mapping the host kernel, or | |
1275 | * b) the guest used a large mapping which we're faking | |
1276 | * Either way, we need to satisfy the fault without | |
1277 | * invoking the guest. */ | |
58a96214 | 1278 | kvmppc_mmu_map(vcpu, eaddr, gpaddr, gtlb_index); |
7b701591 | 1279 | kvmppc_account_exit(vcpu, DTLB_VIRT_MISS_EXITS); |
bbf45ba5 HB |
1280 | r = RESUME_GUEST; |
1281 | } else { | |
1282 | /* Guest has mapped and accessed a page which is not | |
1283 | * actually RAM. */ | |
475e7cdd | 1284 | vcpu->arch.paddr_accessed = gpaddr; |
6020c0f6 | 1285 | vcpu->arch.vaddr_accessed = eaddr; |
bbf45ba5 | 1286 | r = kvmppc_emulate_mmio(run, vcpu); |
7b701591 | 1287 | kvmppc_account_exit(vcpu, MMIO_EXITS); |
bbf45ba5 HB |
1288 | } |
1289 | ||
f1e89028 | 1290 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
bbf45ba5 HB |
1291 | break; |
1292 | } | |
1293 | ||
1294 | case BOOKE_INTERRUPT_ITLB_MISS: { | |
bbf45ba5 | 1295 | unsigned long eaddr = vcpu->arch.pc; |
89168618 | 1296 | gpa_t gpaddr; |
bbf45ba5 | 1297 | gfn_t gfn; |
7924bd41 | 1298 | int gtlb_index; |
bbf45ba5 HB |
1299 | |
1300 | r = RESUME_GUEST; | |
1301 | ||
1302 | /* Check the guest TLB. */ | |
fa86b8dd | 1303 | gtlb_index = kvmppc_mmu_itlb_index(vcpu, eaddr); |
7924bd41 | 1304 | if (gtlb_index < 0) { |
bbf45ba5 | 1305 | /* The guest didn't have a mapping for it. */ |
d4cf3892 | 1306 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_ITLB_MISS); |
b52a638c | 1307 | kvmppc_mmu_itlb_miss(vcpu); |
7b701591 | 1308 | kvmppc_account_exit(vcpu, ITLB_REAL_MISS_EXITS); |
bbf45ba5 HB |
1309 | break; |
1310 | } | |
1311 | ||
7b701591 | 1312 | kvmppc_account_exit(vcpu, ITLB_VIRT_MISS_EXITS); |
bbf45ba5 | 1313 | |
f1e89028 SW |
1314 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
1315 | ||
be8d1cae | 1316 | gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr); |
89168618 | 1317 | gfn = gpaddr >> PAGE_SHIFT; |
bbf45ba5 HB |
1318 | |
1319 | if (kvm_is_visible_gfn(vcpu->kvm, gfn)) { | |
1320 | /* The guest TLB had a mapping, but the shadow TLB | |
1321 | * didn't. This could be because: | |
1322 | * a) the entry is mapping the host kernel, or | |
1323 | * b) the guest used a large mapping which we're faking | |
1324 | * Either way, we need to satisfy the fault without | |
1325 | * invoking the guest. */ | |
58a96214 | 1326 | kvmppc_mmu_map(vcpu, eaddr, gpaddr, gtlb_index); |
bbf45ba5 HB |
1327 | } else { |
1328 | /* Guest mapped and leaped at non-RAM! */ | |
d4cf3892 | 1329 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_MACHINE_CHECK); |
bbf45ba5 HB |
1330 | } |
1331 | ||
f1e89028 | 1332 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
bbf45ba5 HB |
1333 | break; |
1334 | } | |
1335 | ||
6a0ab738 | 1336 | case BOOKE_INTERRUPT_DEBUG: { |
ce11e48b BB |
1337 | r = kvmppc_handle_debug(run, vcpu); |
1338 | if (r == RESUME_HOST) | |
1339 | run->exit_reason = KVM_EXIT_DEBUG; | |
7b701591 | 1340 | kvmppc_account_exit(vcpu, DEBUG_EXITS); |
6a0ab738 HB |
1341 | break; |
1342 | } | |
1343 | ||
bbf45ba5 HB |
1344 | default: |
1345 | printk(KERN_EMERG "exit_nr %d\n", exit_nr); | |
1346 | BUG(); | |
1347 | } | |
1348 | ||
f5250471 | 1349 | out: |
a8e4ef84 AG |
1350 | /* |
1351 | * To avoid clobbering exit_reason, only check for signals if we | |
1352 | * aren't already exiting to userspace for some other reason. | |
1353 | */ | |
03660ba2 | 1354 | if (!(r & RESUME_HOST)) { |
7ee78855 | 1355 | s = kvmppc_prepare_to_enter(vcpu); |
6c85f52b | 1356 | if (s <= 0) |
7ee78855 | 1357 | r = (s << 2) | RESUME_HOST | (r & RESUME_FLAG_NV); |
6c85f52b SW |
1358 | else { |
1359 | /* interrupts now hard-disabled */ | |
5f1c248f | 1360 | kvmppc_fix_ee_before_entry(); |
3efc7da6 | 1361 | kvmppc_load_guest_fp(vcpu); |
95d80a29 | 1362 | kvmppc_load_guest_altivec(vcpu); |
03660ba2 | 1363 | } |
bbf45ba5 HB |
1364 | } |
1365 | ||
1366 | return r; | |
1367 | } | |
1368 | ||
d26f22c9 BB |
1369 | static void kvmppc_set_tsr(struct kvm_vcpu *vcpu, u32 new_tsr) |
1370 | { | |
1371 | u32 old_tsr = vcpu->arch.tsr; | |
1372 | ||
1373 | vcpu->arch.tsr = new_tsr; | |
1374 | ||
1375 | if ((old_tsr ^ vcpu->arch.tsr) & (TSR_ENW | TSR_WIS)) | |
1376 | arm_next_watchdog(vcpu); | |
1377 | ||
1378 | update_timer_ints(vcpu); | |
1379 | } | |
1380 | ||
bbf45ba5 HB |
1381 | /* Initial guest state: 16MB mapping 0 -> 0, PC = 0, MSR = 0, R1 = 16MB */ |
1382 | int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) | |
1383 | { | |
082decf2 | 1384 | int i; |
af8f38b3 | 1385 | int r; |
082decf2 | 1386 | |
bbf45ba5 | 1387 | vcpu->arch.pc = 0; |
b5904972 | 1388 | vcpu->arch.shared->pir = vcpu->vcpu_id; |
8e5b26b5 | 1389 | kvmppc_set_gpr(vcpu, 1, (16<<20) - 8); /* -8 for the callee-save LR slot */ |
d30f6e48 | 1390 | kvmppc_set_msr(vcpu, 0); |
bbf45ba5 | 1391 | |
d30f6e48 | 1392 | #ifndef CONFIG_KVM_BOOKE_HV |
ce11e48b | 1393 | vcpu->arch.shadow_msr = MSR_USER | MSR_IS | MSR_DS; |
49dd2c49 | 1394 | vcpu->arch.shadow_pid = 1; |
d30f6e48 SW |
1395 | vcpu->arch.shared->msr = 0; |
1396 | #endif | |
49dd2c49 | 1397 | |
082decf2 HB |
1398 | /* Eye-catching numbers so we know if the guest takes an interrupt |
1399 | * before it's programmed its own IVPR/IVORs. */ | |
bbf45ba5 | 1400 | vcpu->arch.ivpr = 0x55550000; |
082decf2 HB |
1401 | for (i = 0; i < BOOKE_IRQPRIO_MAX; i++) |
1402 | vcpu->arch.ivor[i] = 0x7700 | i * 4; | |
bbf45ba5 | 1403 | |
73e75b41 HB |
1404 | kvmppc_init_timing_stats(vcpu); |
1405 | ||
af8f38b3 AG |
1406 | r = kvmppc_core_vcpu_setup(vcpu); |
1407 | kvmppc_sanity_check(vcpu); | |
1408 | return r; | |
bbf45ba5 HB |
1409 | } |
1410 | ||
f61c94bb BB |
1411 | int kvmppc_subarch_vcpu_init(struct kvm_vcpu *vcpu) |
1412 | { | |
1413 | /* setup watchdog timer once */ | |
1414 | spin_lock_init(&vcpu->arch.wdt_lock); | |
86cb30ec | 1415 | timer_setup(&vcpu->arch.wdt_timer, kvmppc_watchdog_func, 0); |
f61c94bb | 1416 | |
2f699a59 BB |
1417 | /* |
1418 | * Clear DBSR.MRR to avoid guest debug interrupt as | |
1419 | * this is of host interest | |
1420 | */ | |
1421 | mtspr(SPRN_DBSR, DBSR_MRR); | |
f61c94bb BB |
1422 | return 0; |
1423 | } | |
1424 | ||
1425 | void kvmppc_subarch_vcpu_uninit(struct kvm_vcpu *vcpu) | |
1426 | { | |
1427 | del_timer_sync(&vcpu->arch.wdt_timer); | |
1428 | } | |
1429 | ||
bbf45ba5 HB |
1430 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
1431 | { | |
1432 | int i; | |
1433 | ||
1434 | regs->pc = vcpu->arch.pc; | |
992b5b29 | 1435 | regs->cr = kvmppc_get_cr(vcpu); |
bbf45ba5 HB |
1436 | regs->ctr = vcpu->arch.ctr; |
1437 | regs->lr = vcpu->arch.lr; | |
992b5b29 | 1438 | regs->xer = kvmppc_get_xer(vcpu); |
666e7252 | 1439 | regs->msr = vcpu->arch.shared->msr; |
31579eea BB |
1440 | regs->srr0 = kvmppc_get_srr0(vcpu); |
1441 | regs->srr1 = kvmppc_get_srr1(vcpu); | |
bbf45ba5 | 1442 | regs->pid = vcpu->arch.pid; |
c1b8a01b BB |
1443 | regs->sprg0 = kvmppc_get_sprg0(vcpu); |
1444 | regs->sprg1 = kvmppc_get_sprg1(vcpu); | |
1445 | regs->sprg2 = kvmppc_get_sprg2(vcpu); | |
1446 | regs->sprg3 = kvmppc_get_sprg3(vcpu); | |
1447 | regs->sprg4 = kvmppc_get_sprg4(vcpu); | |
1448 | regs->sprg5 = kvmppc_get_sprg5(vcpu); | |
1449 | regs->sprg6 = kvmppc_get_sprg6(vcpu); | |
1450 | regs->sprg7 = kvmppc_get_sprg7(vcpu); | |
bbf45ba5 HB |
1451 | |
1452 | for (i = 0; i < ARRAY_SIZE(regs->gpr); i++) | |
8e5b26b5 | 1453 | regs->gpr[i] = kvmppc_get_gpr(vcpu, i); |
bbf45ba5 HB |
1454 | |
1455 | return 0; | |
1456 | } | |
1457 | ||
1458 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
1459 | { | |
1460 | int i; | |
1461 | ||
1462 | vcpu->arch.pc = regs->pc; | |
992b5b29 | 1463 | kvmppc_set_cr(vcpu, regs->cr); |
bbf45ba5 HB |
1464 | vcpu->arch.ctr = regs->ctr; |
1465 | vcpu->arch.lr = regs->lr; | |
992b5b29 | 1466 | kvmppc_set_xer(vcpu, regs->xer); |
b8fd68ac | 1467 | kvmppc_set_msr(vcpu, regs->msr); |
31579eea BB |
1468 | kvmppc_set_srr0(vcpu, regs->srr0); |
1469 | kvmppc_set_srr1(vcpu, regs->srr1); | |
5ce941ee | 1470 | kvmppc_set_pid(vcpu, regs->pid); |
c1b8a01b BB |
1471 | kvmppc_set_sprg0(vcpu, regs->sprg0); |
1472 | kvmppc_set_sprg1(vcpu, regs->sprg1); | |
1473 | kvmppc_set_sprg2(vcpu, regs->sprg2); | |
1474 | kvmppc_set_sprg3(vcpu, regs->sprg3); | |
1475 | kvmppc_set_sprg4(vcpu, regs->sprg4); | |
1476 | kvmppc_set_sprg5(vcpu, regs->sprg5); | |
1477 | kvmppc_set_sprg6(vcpu, regs->sprg6); | |
1478 | kvmppc_set_sprg7(vcpu, regs->sprg7); | |
bbf45ba5 | 1479 | |
8e5b26b5 AG |
1480 | for (i = 0; i < ARRAY_SIZE(regs->gpr); i++) |
1481 | kvmppc_set_gpr(vcpu, i, regs->gpr[i]); | |
bbf45ba5 HB |
1482 | |
1483 | return 0; | |
1484 | } | |
1485 | ||
5ce941ee SW |
1486 | static void get_sregs_base(struct kvm_vcpu *vcpu, |
1487 | struct kvm_sregs *sregs) | |
1488 | { | |
1489 | u64 tb = get_tb(); | |
1490 | ||
1491 | sregs->u.e.features |= KVM_SREGS_E_BASE; | |
1492 | ||
1493 | sregs->u.e.csrr0 = vcpu->arch.csrr0; | |
1494 | sregs->u.e.csrr1 = vcpu->arch.csrr1; | |
1495 | sregs->u.e.mcsr = vcpu->arch.mcsr; | |
dc168549 | 1496 | sregs->u.e.esr = kvmppc_get_esr(vcpu); |
a5414d4b | 1497 | sregs->u.e.dear = kvmppc_get_dar(vcpu); |
5ce941ee SW |
1498 | sregs->u.e.tsr = vcpu->arch.tsr; |
1499 | sregs->u.e.tcr = vcpu->arch.tcr; | |
1500 | sregs->u.e.dec = kvmppc_get_dec(vcpu, tb); | |
1501 | sregs->u.e.tb = tb; | |
1502 | sregs->u.e.vrsave = vcpu->arch.vrsave; | |
1503 | } | |
1504 | ||
1505 | static int set_sregs_base(struct kvm_vcpu *vcpu, | |
1506 | struct kvm_sregs *sregs) | |
1507 | { | |
1508 | if (!(sregs->u.e.features & KVM_SREGS_E_BASE)) | |
1509 | return 0; | |
1510 | ||
1511 | vcpu->arch.csrr0 = sregs->u.e.csrr0; | |
1512 | vcpu->arch.csrr1 = sregs->u.e.csrr1; | |
1513 | vcpu->arch.mcsr = sregs->u.e.mcsr; | |
dc168549 | 1514 | kvmppc_set_esr(vcpu, sregs->u.e.esr); |
a5414d4b | 1515 | kvmppc_set_dar(vcpu, sregs->u.e.dear); |
5ce941ee | 1516 | vcpu->arch.vrsave = sregs->u.e.vrsave; |
dfd4d47e | 1517 | kvmppc_set_tcr(vcpu, sregs->u.e.tcr); |
5ce941ee | 1518 | |
dfd4d47e | 1519 | if (sregs->u.e.update_special & KVM_SREGS_E_UPDATE_DEC) { |
5ce941ee | 1520 | vcpu->arch.dec = sregs->u.e.dec; |
dfd4d47e SW |
1521 | kvmppc_emulate_dec(vcpu); |
1522 | } | |
5ce941ee | 1523 | |
d26f22c9 BB |
1524 | if (sregs->u.e.update_special & KVM_SREGS_E_UPDATE_TSR) |
1525 | kvmppc_set_tsr(vcpu, sregs->u.e.tsr); | |
5ce941ee SW |
1526 | |
1527 | return 0; | |
1528 | } | |
1529 | ||
1530 | static void get_sregs_arch206(struct kvm_vcpu *vcpu, | |
1531 | struct kvm_sregs *sregs) | |
1532 | { | |
1533 | sregs->u.e.features |= KVM_SREGS_E_ARCH206; | |
1534 | ||
841741f2 | 1535 | sregs->u.e.pir = vcpu->vcpu_id; |
5ce941ee SW |
1536 | sregs->u.e.mcsrr0 = vcpu->arch.mcsrr0; |
1537 | sregs->u.e.mcsrr1 = vcpu->arch.mcsrr1; | |
1538 | sregs->u.e.decar = vcpu->arch.decar; | |
1539 | sregs->u.e.ivpr = vcpu->arch.ivpr; | |
1540 | } | |
1541 | ||
1542 | static int set_sregs_arch206(struct kvm_vcpu *vcpu, | |
1543 | struct kvm_sregs *sregs) | |
1544 | { | |
1545 | if (!(sregs->u.e.features & KVM_SREGS_E_ARCH206)) | |
1546 | return 0; | |
1547 | ||
841741f2 | 1548 | if (sregs->u.e.pir != vcpu->vcpu_id) |
5ce941ee SW |
1549 | return -EINVAL; |
1550 | ||
1551 | vcpu->arch.mcsrr0 = sregs->u.e.mcsrr0; | |
1552 | vcpu->arch.mcsrr1 = sregs->u.e.mcsrr1; | |
1553 | vcpu->arch.decar = sregs->u.e.decar; | |
1554 | vcpu->arch.ivpr = sregs->u.e.ivpr; | |
1555 | ||
1556 | return 0; | |
1557 | } | |
1558 | ||
3a167bea | 1559 | int kvmppc_get_sregs_ivor(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
5ce941ee SW |
1560 | { |
1561 | sregs->u.e.features |= KVM_SREGS_E_IVOR; | |
1562 | ||
1563 | sregs->u.e.ivor_low[0] = vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL]; | |
1564 | sregs->u.e.ivor_low[1] = vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK]; | |
1565 | sregs->u.e.ivor_low[2] = vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE]; | |
1566 | sregs->u.e.ivor_low[3] = vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE]; | |
1567 | sregs->u.e.ivor_low[4] = vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL]; | |
1568 | sregs->u.e.ivor_low[5] = vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT]; | |
1569 | sregs->u.e.ivor_low[6] = vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM]; | |
1570 | sregs->u.e.ivor_low[7] = vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL]; | |
1571 | sregs->u.e.ivor_low[8] = vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL]; | |
1572 | sregs->u.e.ivor_low[9] = vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL]; | |
1573 | sregs->u.e.ivor_low[10] = vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER]; | |
1574 | sregs->u.e.ivor_low[11] = vcpu->arch.ivor[BOOKE_IRQPRIO_FIT]; | |
1575 | sregs->u.e.ivor_low[12] = vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG]; | |
1576 | sregs->u.e.ivor_low[13] = vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS]; | |
1577 | sregs->u.e.ivor_low[14] = vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS]; | |
1578 | sregs->u.e.ivor_low[15] = vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG]; | |
3a167bea | 1579 | return 0; |
5ce941ee SW |
1580 | } |
1581 | ||
1582 | int kvmppc_set_sregs_ivor(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) | |
1583 | { | |
1584 | if (!(sregs->u.e.features & KVM_SREGS_E_IVOR)) | |
1585 | return 0; | |
1586 | ||
1587 | vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL] = sregs->u.e.ivor_low[0]; | |
1588 | vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK] = sregs->u.e.ivor_low[1]; | |
1589 | vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE] = sregs->u.e.ivor_low[2]; | |
1590 | vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE] = sregs->u.e.ivor_low[3]; | |
1591 | vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL] = sregs->u.e.ivor_low[4]; | |
1592 | vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT] = sregs->u.e.ivor_low[5]; | |
1593 | vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM] = sregs->u.e.ivor_low[6]; | |
1594 | vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL] = sregs->u.e.ivor_low[7]; | |
1595 | vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL] = sregs->u.e.ivor_low[8]; | |
1596 | vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL] = sregs->u.e.ivor_low[9]; | |
1597 | vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER] = sregs->u.e.ivor_low[10]; | |
1598 | vcpu->arch.ivor[BOOKE_IRQPRIO_FIT] = sregs->u.e.ivor_low[11]; | |
1599 | vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG] = sregs->u.e.ivor_low[12]; | |
1600 | vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS] = sregs->u.e.ivor_low[13]; | |
1601 | vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS] = sregs->u.e.ivor_low[14]; | |
1602 | vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG] = sregs->u.e.ivor_low[15]; | |
1603 | ||
1604 | return 0; | |
1605 | } | |
1606 | ||
bbf45ba5 HB |
1607 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, |
1608 | struct kvm_sregs *sregs) | |
1609 | { | |
5ce941ee SW |
1610 | sregs->pvr = vcpu->arch.pvr; |
1611 | ||
1612 | get_sregs_base(vcpu, sregs); | |
1613 | get_sregs_arch206(vcpu, sregs); | |
cbbc58d4 | 1614 | return vcpu->kvm->arch.kvm_ops->get_sregs(vcpu, sregs); |
bbf45ba5 HB |
1615 | } |
1616 | ||
1617 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, | |
1618 | struct kvm_sregs *sregs) | |
1619 | { | |
5ce941ee SW |
1620 | int ret; |
1621 | ||
1622 | if (vcpu->arch.pvr != sregs->pvr) | |
1623 | return -EINVAL; | |
1624 | ||
1625 | ret = set_sregs_base(vcpu, sregs); | |
1626 | if (ret < 0) | |
1627 | return ret; | |
1628 | ||
1629 | ret = set_sregs_arch206(vcpu, sregs); | |
1630 | if (ret < 0) | |
1631 | return ret; | |
1632 | ||
cbbc58d4 | 1633 | return vcpu->kvm->arch.kvm_ops->set_sregs(vcpu, sregs); |
bbf45ba5 HB |
1634 | } |
1635 | ||
8a41ea53 MC |
1636 | int kvmppc_get_one_reg(struct kvm_vcpu *vcpu, u64 id, |
1637 | union kvmppc_one_reg *val) | |
31f3438e | 1638 | { |
35b299e2 | 1639 | int r = 0; |
35b299e2 | 1640 | |
8a41ea53 | 1641 | switch (id) { |
6df8d3fc | 1642 | case KVM_REG_PPC_IAC1: |
8a41ea53 | 1643 | *val = get_reg_val(id, vcpu->arch.dbg_reg.iac1); |
547465ef | 1644 | break; |
6df8d3fc | 1645 | case KVM_REG_PPC_IAC2: |
8a41ea53 | 1646 | *val = get_reg_val(id, vcpu->arch.dbg_reg.iac2); |
547465ef BB |
1647 | break; |
1648 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 | |
6df8d3fc | 1649 | case KVM_REG_PPC_IAC3: |
8a41ea53 | 1650 | *val = get_reg_val(id, vcpu->arch.dbg_reg.iac3); |
547465ef | 1651 | break; |
35b299e2 | 1652 | case KVM_REG_PPC_IAC4: |
8a41ea53 | 1653 | *val = get_reg_val(id, vcpu->arch.dbg_reg.iac4); |
6df8d3fc | 1654 | break; |
547465ef | 1655 | #endif |
6df8d3fc | 1656 | case KVM_REG_PPC_DAC1: |
8a41ea53 | 1657 | *val = get_reg_val(id, vcpu->arch.dbg_reg.dac1); |
547465ef | 1658 | break; |
35b299e2 | 1659 | case KVM_REG_PPC_DAC2: |
8a41ea53 | 1660 | *val = get_reg_val(id, vcpu->arch.dbg_reg.dac2); |
2c509672 | 1661 | break; |
324b3e63 | 1662 | case KVM_REG_PPC_EPR: { |
34f754b9 | 1663 | u32 epr = kvmppc_get_epr(vcpu); |
8a41ea53 | 1664 | *val = get_reg_val(id, epr); |
324b3e63 AG |
1665 | break; |
1666 | } | |
352df1de MC |
1667 | #if defined(CONFIG_64BIT) |
1668 | case KVM_REG_PPC_EPCR: | |
8a41ea53 | 1669 | *val = get_reg_val(id, vcpu->arch.epcr); |
352df1de MC |
1670 | break; |
1671 | #endif | |
78accda4 | 1672 | case KVM_REG_PPC_TCR: |
8a41ea53 | 1673 | *val = get_reg_val(id, vcpu->arch.tcr); |
78accda4 BB |
1674 | break; |
1675 | case KVM_REG_PPC_TSR: | |
8a41ea53 | 1676 | *val = get_reg_val(id, vcpu->arch.tsr); |
78accda4 | 1677 | break; |
35b299e2 | 1678 | case KVM_REG_PPC_DEBUG_INST: |
033aaa14 | 1679 | *val = get_reg_val(id, KVMPPC_INST_SW_BREAKPOINT); |
8c32a2ea | 1680 | break; |
8b75cbbe | 1681 | case KVM_REG_PPC_VRSAVE: |
8a41ea53 | 1682 | *val = get_reg_val(id, vcpu->arch.vrsave); |
8c32a2ea | 1683 | break; |
6df8d3fc | 1684 | default: |
8a41ea53 | 1685 | r = vcpu->kvm->arch.kvm_ops->get_one_reg(vcpu, id, val); |
6df8d3fc BB |
1686 | break; |
1687 | } | |
35b299e2 | 1688 | |
6df8d3fc | 1689 | return r; |
31f3438e PM |
1690 | } |
1691 | ||
8a41ea53 MC |
1692 | int kvmppc_set_one_reg(struct kvm_vcpu *vcpu, u64 id, |
1693 | union kvmppc_one_reg *val) | |
31f3438e | 1694 | { |
35b299e2 | 1695 | int r = 0; |
35b299e2 | 1696 | |
8a41ea53 | 1697 | switch (id) { |
6df8d3fc | 1698 | case KVM_REG_PPC_IAC1: |
8a41ea53 | 1699 | vcpu->arch.dbg_reg.iac1 = set_reg_val(id, *val); |
547465ef | 1700 | break; |
6df8d3fc | 1701 | case KVM_REG_PPC_IAC2: |
8a41ea53 | 1702 | vcpu->arch.dbg_reg.iac2 = set_reg_val(id, *val); |
547465ef BB |
1703 | break; |
1704 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 | |
6df8d3fc | 1705 | case KVM_REG_PPC_IAC3: |
8a41ea53 | 1706 | vcpu->arch.dbg_reg.iac3 = set_reg_val(id, *val); |
547465ef | 1707 | break; |
35b299e2 | 1708 | case KVM_REG_PPC_IAC4: |
8a41ea53 | 1709 | vcpu->arch.dbg_reg.iac4 = set_reg_val(id, *val); |
6df8d3fc | 1710 | break; |
547465ef | 1711 | #endif |
6df8d3fc | 1712 | case KVM_REG_PPC_DAC1: |
8a41ea53 | 1713 | vcpu->arch.dbg_reg.dac1 = set_reg_val(id, *val); |
547465ef | 1714 | break; |
35b299e2 | 1715 | case KVM_REG_PPC_DAC2: |
8a41ea53 | 1716 | vcpu->arch.dbg_reg.dac2 = set_reg_val(id, *val); |
2c509672 | 1717 | break; |
324b3e63 | 1718 | case KVM_REG_PPC_EPR: { |
8a41ea53 | 1719 | u32 new_epr = set_reg_val(id, *val); |
35b299e2 | 1720 | kvmppc_set_epr(vcpu, new_epr); |
324b3e63 AG |
1721 | break; |
1722 | } | |
352df1de MC |
1723 | #if defined(CONFIG_64BIT) |
1724 | case KVM_REG_PPC_EPCR: { | |
8a41ea53 | 1725 | u32 new_epcr = set_reg_val(id, *val); |
35b299e2 | 1726 | kvmppc_set_epcr(vcpu, new_epcr); |
352df1de MC |
1727 | break; |
1728 | } | |
1729 | #endif | |
78accda4 | 1730 | case KVM_REG_PPC_OR_TSR: { |
8a41ea53 | 1731 | u32 tsr_bits = set_reg_val(id, *val); |
78accda4 BB |
1732 | kvmppc_set_tsr_bits(vcpu, tsr_bits); |
1733 | break; | |
1734 | } | |
1735 | case KVM_REG_PPC_CLEAR_TSR: { | |
8a41ea53 | 1736 | u32 tsr_bits = set_reg_val(id, *val); |
78accda4 BB |
1737 | kvmppc_clr_tsr_bits(vcpu, tsr_bits); |
1738 | break; | |
1739 | } | |
1740 | case KVM_REG_PPC_TSR: { | |
8a41ea53 | 1741 | u32 tsr = set_reg_val(id, *val); |
78accda4 BB |
1742 | kvmppc_set_tsr(vcpu, tsr); |
1743 | break; | |
1744 | } | |
1745 | case KVM_REG_PPC_TCR: { | |
8a41ea53 | 1746 | u32 tcr = set_reg_val(id, *val); |
78accda4 BB |
1747 | kvmppc_set_tcr(vcpu, tcr); |
1748 | break; | |
1749 | } | |
8b75cbbe | 1750 | case KVM_REG_PPC_VRSAVE: |
8a41ea53 | 1751 | vcpu->arch.vrsave = set_reg_val(id, *val); |
8b75cbbe | 1752 | break; |
6df8d3fc | 1753 | default: |
8a41ea53 | 1754 | r = vcpu->kvm->arch.kvm_ops->set_one_reg(vcpu, id, val); |
6df8d3fc BB |
1755 | break; |
1756 | } | |
35b299e2 | 1757 | |
6df8d3fc | 1758 | return r; |
31f3438e PM |
1759 | } |
1760 | ||
bbf45ba5 HB |
1761 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) |
1762 | { | |
1763 | return -ENOTSUPP; | |
1764 | } | |
1765 | ||
1766 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
1767 | { | |
1768 | return -ENOTSUPP; | |
1769 | } | |
1770 | ||
bbf45ba5 HB |
1771 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, |
1772 | struct kvm_translation *tr) | |
1773 | { | |
98001d8d AK |
1774 | int r; |
1775 | ||
98001d8d | 1776 | r = kvmppc_core_vcpu_translate(vcpu, tr); |
98001d8d | 1777 | return r; |
bbf45ba5 | 1778 | } |
d9fbd03d | 1779 | |
4e755758 AG |
1780 | int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) |
1781 | { | |
1782 | return -ENOTSUPP; | |
1783 | } | |
1784 | ||
5587027c | 1785 | void kvmppc_core_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, |
a66b48c3 PM |
1786 | struct kvm_memory_slot *dont) |
1787 | { | |
1788 | } | |
1789 | ||
5587027c | 1790 | int kvmppc_core_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, |
a66b48c3 PM |
1791 | unsigned long npages) |
1792 | { | |
1793 | return 0; | |
1794 | } | |
1795 | ||
f9e0554d | 1796 | int kvmppc_core_prepare_memory_region(struct kvm *kvm, |
a66b48c3 | 1797 | struct kvm_memory_slot *memslot, |
09170a49 | 1798 | const struct kvm_userspace_memory_region *mem) |
f9e0554d PM |
1799 | { |
1800 | return 0; | |
1801 | } | |
1802 | ||
1803 | void kvmppc_core_commit_memory_region(struct kvm *kvm, | |
09170a49 | 1804 | const struct kvm_userspace_memory_region *mem, |
f36f3f28 PB |
1805 | const struct kvm_memory_slot *old, |
1806 | const struct kvm_memory_slot *new) | |
dfe49dbd PM |
1807 | { |
1808 | } | |
1809 | ||
1810 | void kvmppc_core_flush_memslot(struct kvm *kvm, struct kvm_memory_slot *memslot) | |
f9e0554d PM |
1811 | { |
1812 | } | |
1813 | ||
38f98824 MC |
1814 | void kvmppc_set_epcr(struct kvm_vcpu *vcpu, u32 new_epcr) |
1815 | { | |
1816 | #if defined(CONFIG_64BIT) | |
1817 | vcpu->arch.epcr = new_epcr; | |
1818 | #ifdef CONFIG_KVM_BOOKE_HV | |
1819 | vcpu->arch.shadow_epcr &= ~SPRN_EPCR_GICM; | |
1820 | if (vcpu->arch.epcr & SPRN_EPCR_ICM) | |
1821 | vcpu->arch.shadow_epcr |= SPRN_EPCR_GICM; | |
1822 | #endif | |
1823 | #endif | |
1824 | } | |
1825 | ||
dfd4d47e SW |
1826 | void kvmppc_set_tcr(struct kvm_vcpu *vcpu, u32 new_tcr) |
1827 | { | |
1828 | vcpu->arch.tcr = new_tcr; | |
f61c94bb | 1829 | arm_next_watchdog(vcpu); |
dfd4d47e SW |
1830 | update_timer_ints(vcpu); |
1831 | } | |
1832 | ||
1833 | void kvmppc_set_tsr_bits(struct kvm_vcpu *vcpu, u32 tsr_bits) | |
1834 | { | |
1835 | set_bits(tsr_bits, &vcpu->arch.tsr); | |
1836 | smp_wmb(); | |
1837 | kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); | |
1838 | kvm_vcpu_kick(vcpu); | |
1839 | } | |
1840 | ||
1841 | void kvmppc_clr_tsr_bits(struct kvm_vcpu *vcpu, u32 tsr_bits) | |
1842 | { | |
1843 | clear_bits(tsr_bits, &vcpu->arch.tsr); | |
f61c94bb BB |
1844 | |
1845 | /* | |
1846 | * We may have stopped the watchdog due to | |
1847 | * being stuck on final expiration. | |
1848 | */ | |
1849 | if (tsr_bits & (TSR_ENW | TSR_WIS)) | |
1850 | arm_next_watchdog(vcpu); | |
1851 | ||
dfd4d47e SW |
1852 | update_timer_ints(vcpu); |
1853 | } | |
1854 | ||
d02d4d15 | 1855 | void kvmppc_decrementer_func(struct kvm_vcpu *vcpu) |
dfd4d47e | 1856 | { |
21bd000a BB |
1857 | if (vcpu->arch.tcr & TCR_ARE) { |
1858 | vcpu->arch.dec = vcpu->arch.decar; | |
1859 | kvmppc_emulate_dec(vcpu); | |
1860 | } | |
1861 | ||
dfd4d47e SW |
1862 | kvmppc_set_tsr_bits(vcpu, TSR_DIS); |
1863 | } | |
1864 | ||
ce11e48b BB |
1865 | static int kvmppc_booke_add_breakpoint(struct debug_reg *dbg_reg, |
1866 | uint64_t addr, int index) | |
1867 | { | |
1868 | switch (index) { | |
1869 | case 0: | |
1870 | dbg_reg->dbcr0 |= DBCR0_IAC1; | |
1871 | dbg_reg->iac1 = addr; | |
1872 | break; | |
1873 | case 1: | |
1874 | dbg_reg->dbcr0 |= DBCR0_IAC2; | |
1875 | dbg_reg->iac2 = addr; | |
1876 | break; | |
1877 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 | |
1878 | case 2: | |
1879 | dbg_reg->dbcr0 |= DBCR0_IAC3; | |
1880 | dbg_reg->iac3 = addr; | |
1881 | break; | |
1882 | case 3: | |
1883 | dbg_reg->dbcr0 |= DBCR0_IAC4; | |
1884 | dbg_reg->iac4 = addr; | |
1885 | break; | |
1886 | #endif | |
1887 | default: | |
1888 | return -EINVAL; | |
1889 | } | |
1890 | ||
1891 | dbg_reg->dbcr0 |= DBCR0_IDM; | |
1892 | return 0; | |
1893 | } | |
1894 | ||
1895 | static int kvmppc_booke_add_watchpoint(struct debug_reg *dbg_reg, uint64_t addr, | |
1896 | int type, int index) | |
1897 | { | |
1898 | switch (index) { | |
1899 | case 0: | |
1900 | if (type & KVMPPC_DEBUG_WATCH_READ) | |
1901 | dbg_reg->dbcr0 |= DBCR0_DAC1R; | |
1902 | if (type & KVMPPC_DEBUG_WATCH_WRITE) | |
1903 | dbg_reg->dbcr0 |= DBCR0_DAC1W; | |
1904 | dbg_reg->dac1 = addr; | |
1905 | break; | |
1906 | case 1: | |
1907 | if (type & KVMPPC_DEBUG_WATCH_READ) | |
1908 | dbg_reg->dbcr0 |= DBCR0_DAC2R; | |
1909 | if (type & KVMPPC_DEBUG_WATCH_WRITE) | |
1910 | dbg_reg->dbcr0 |= DBCR0_DAC2W; | |
1911 | dbg_reg->dac2 = addr; | |
1912 | break; | |
1913 | default: | |
1914 | return -EINVAL; | |
1915 | } | |
1916 | ||
1917 | dbg_reg->dbcr0 |= DBCR0_IDM; | |
1918 | return 0; | |
1919 | } | |
1920 | void kvm_guest_protect_msr(struct kvm_vcpu *vcpu, ulong prot_bitmap, bool set) | |
1921 | { | |
1922 | /* XXX: Add similar MSR protection for BookE-PR */ | |
1923 | #ifdef CONFIG_KVM_BOOKE_HV | |
1924 | BUG_ON(prot_bitmap & ~(MSRP_UCLEP | MSRP_DEP | MSRP_PMMP)); | |
1925 | if (set) { | |
1926 | if (prot_bitmap & MSR_UCLE) | |
1927 | vcpu->arch.shadow_msrp |= MSRP_UCLEP; | |
1928 | if (prot_bitmap & MSR_DE) | |
1929 | vcpu->arch.shadow_msrp |= MSRP_DEP; | |
1930 | if (prot_bitmap & MSR_PMM) | |
1931 | vcpu->arch.shadow_msrp |= MSRP_PMMP; | |
1932 | } else { | |
1933 | if (prot_bitmap & MSR_UCLE) | |
1934 | vcpu->arch.shadow_msrp &= ~MSRP_UCLEP; | |
1935 | if (prot_bitmap & MSR_DE) | |
1936 | vcpu->arch.shadow_msrp &= ~MSRP_DEP; | |
1937 | if (prot_bitmap & MSR_PMM) | |
1938 | vcpu->arch.shadow_msrp &= ~MSRP_PMMP; | |
1939 | } | |
1940 | #endif | |
1941 | } | |
1942 | ||
7d15c06f AG |
1943 | int kvmppc_xlate(struct kvm_vcpu *vcpu, ulong eaddr, enum xlate_instdata xlid, |
1944 | enum xlate_readwrite xlrw, struct kvmppc_pte *pte) | |
1945 | { | |
1946 | int gtlb_index; | |
1947 | gpa_t gpaddr; | |
1948 | ||
1949 | #ifdef CONFIG_KVM_E500V2 | |
1950 | if (!(vcpu->arch.shared->msr & MSR_PR) && | |
1951 | (eaddr & PAGE_MASK) == vcpu->arch.magic_page_ea) { | |
1952 | pte->eaddr = eaddr; | |
1953 | pte->raddr = (vcpu->arch.magic_page_pa & PAGE_MASK) | | |
1954 | (eaddr & ~PAGE_MASK); | |
1955 | pte->vpage = eaddr >> PAGE_SHIFT; | |
1956 | pte->may_read = true; | |
1957 | pte->may_write = true; | |
1958 | pte->may_execute = true; | |
1959 | ||
1960 | return 0; | |
1961 | } | |
1962 | #endif | |
1963 | ||
1964 | /* Check the guest TLB. */ | |
1965 | switch (xlid) { | |
1966 | case XLATE_INST: | |
1967 | gtlb_index = kvmppc_mmu_itlb_index(vcpu, eaddr); | |
1968 | break; | |
1969 | case XLATE_DATA: | |
1970 | gtlb_index = kvmppc_mmu_dtlb_index(vcpu, eaddr); | |
1971 | break; | |
1972 | default: | |
1973 | BUG(); | |
1974 | } | |
1975 | ||
1976 | /* Do we have a TLB entry at all? */ | |
1977 | if (gtlb_index < 0) | |
1978 | return -ENOENT; | |
1979 | ||
1980 | gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr); | |
1981 | ||
1982 | pte->eaddr = eaddr; | |
1983 | pte->raddr = (gpaddr & PAGE_MASK) | (eaddr & ~PAGE_MASK); | |
1984 | pte->vpage = eaddr >> PAGE_SHIFT; | |
1985 | ||
1986 | /* XXX read permissions from the guest TLB */ | |
1987 | pte->may_read = true; | |
1988 | pte->may_write = true; | |
1989 | pte->may_execute = true; | |
1990 | ||
1991 | return 0; | |
1992 | } | |
1993 | ||
ce11e48b BB |
1994 | int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, |
1995 | struct kvm_guest_debug *dbg) | |
1996 | { | |
1997 | struct debug_reg *dbg_reg; | |
1998 | int n, b = 0, w = 0; | |
1999 | ||
2000 | if (!(dbg->control & KVM_GUESTDBG_ENABLE)) { | |
348ba710 | 2001 | vcpu->arch.dbg_reg.dbcr0 = 0; |
ce11e48b BB |
2002 | vcpu->guest_debug = 0; |
2003 | kvm_guest_protect_msr(vcpu, MSR_DE, false); | |
2004 | return 0; | |
2005 | } | |
2006 | ||
2007 | kvm_guest_protect_msr(vcpu, MSR_DE, true); | |
2008 | vcpu->guest_debug = dbg->control; | |
348ba710 | 2009 | vcpu->arch.dbg_reg.dbcr0 = 0; |
ce11e48b BB |
2010 | |
2011 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | |
348ba710 | 2012 | vcpu->arch.dbg_reg.dbcr0 |= DBCR0_IDM | DBCR0_IC; |
ce11e48b BB |
2013 | |
2014 | /* Code below handles only HW breakpoints */ | |
348ba710 | 2015 | dbg_reg = &(vcpu->arch.dbg_reg); |
ce11e48b BB |
2016 | |
2017 | #ifdef CONFIG_KVM_BOOKE_HV | |
2018 | /* | |
2019 | * On BookE-HV (e500mc) the guest is always executed with MSR.GS=1 | |
2020 | * DBCR1 and DBCR2 are set to trigger debug events when MSR.PR is 0 | |
2021 | */ | |
2022 | dbg_reg->dbcr1 = 0; | |
2023 | dbg_reg->dbcr2 = 0; | |
2024 | #else | |
2025 | /* | |
2026 | * On BookE-PR (e500v2) the guest is always executed with MSR.PR=1 | |
2027 | * We set DBCR1 and DBCR2 to only trigger debug events when MSR.PR | |
2028 | * is set. | |
2029 | */ | |
2030 | dbg_reg->dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | DBCR1_IAC3US | | |
2031 | DBCR1_IAC4US; | |
2032 | dbg_reg->dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US; | |
2033 | #endif | |
2034 | ||
2035 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) | |
2036 | return 0; | |
2037 | ||
2038 | for (n = 0; n < (KVMPPC_BOOKE_IAC_NUM + KVMPPC_BOOKE_DAC_NUM); n++) { | |
2039 | uint64_t addr = dbg->arch.bp[n].addr; | |
2040 | uint32_t type = dbg->arch.bp[n].type; | |
2041 | ||
2042 | if (type == KVMPPC_DEBUG_NONE) | |
2043 | continue; | |
2044 | ||
ac0e89bb | 2045 | if (type & ~(KVMPPC_DEBUG_WATCH_READ | |
ce11e48b BB |
2046 | KVMPPC_DEBUG_WATCH_WRITE | |
2047 | KVMPPC_DEBUG_BREAKPOINT)) | |
2048 | return -EINVAL; | |
2049 | ||
2050 | if (type & KVMPPC_DEBUG_BREAKPOINT) { | |
2051 | /* Setting H/W breakpoint */ | |
2052 | if (kvmppc_booke_add_breakpoint(dbg_reg, addr, b++)) | |
2053 | return -EINVAL; | |
2054 | } else { | |
2055 | /* Setting H/W watchpoint */ | |
2056 | if (kvmppc_booke_add_watchpoint(dbg_reg, addr, | |
2057 | type, w++)) | |
2058 | return -EINVAL; | |
2059 | } | |
2060 | } | |
2061 | ||
2062 | return 0; | |
2063 | } | |
2064 | ||
94fa9d99 SW |
2065 | void kvmppc_booke_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
2066 | { | |
a47d72f3 | 2067 | vcpu->cpu = smp_processor_id(); |
d30f6e48 | 2068 | current->thread.kvm_vcpu = vcpu; |
94fa9d99 SW |
2069 | } |
2070 | ||
2071 | void kvmppc_booke_vcpu_put(struct kvm_vcpu *vcpu) | |
2072 | { | |
d30f6e48 | 2073 | current->thread.kvm_vcpu = NULL; |
a47d72f3 | 2074 | vcpu->cpu = -1; |
ce11e48b BB |
2075 | |
2076 | /* Clear pending debug event in DBSR */ | |
2077 | kvmppc_clear_dbsr(); | |
94fa9d99 SW |
2078 | } |
2079 | ||
3a167bea AK |
2080 | void kvmppc_mmu_destroy(struct kvm_vcpu *vcpu) |
2081 | { | |
cbbc58d4 | 2082 | vcpu->kvm->arch.kvm_ops->mmu_destroy(vcpu); |
3a167bea AK |
2083 | } |
2084 | ||
2085 | int kvmppc_core_init_vm(struct kvm *kvm) | |
2086 | { | |
cbbc58d4 | 2087 | return kvm->arch.kvm_ops->init_vm(kvm); |
3a167bea AK |
2088 | } |
2089 | ||
2090 | struct kvm_vcpu *kvmppc_core_vcpu_create(struct kvm *kvm, unsigned int id) | |
2091 | { | |
cbbc58d4 | 2092 | return kvm->arch.kvm_ops->vcpu_create(kvm, id); |
3a167bea AK |
2093 | } |
2094 | ||
2095 | void kvmppc_core_vcpu_free(struct kvm_vcpu *vcpu) | |
2096 | { | |
cbbc58d4 | 2097 | vcpu->kvm->arch.kvm_ops->vcpu_free(vcpu); |
3a167bea AK |
2098 | } |
2099 | ||
2100 | void kvmppc_core_destroy_vm(struct kvm *kvm) | |
2101 | { | |
cbbc58d4 | 2102 | kvm->arch.kvm_ops->destroy_vm(kvm); |
3a167bea AK |
2103 | } |
2104 | ||
2105 | void kvmppc_core_vcpu_load(struct kvm_vcpu *vcpu, int cpu) | |
2106 | { | |
cbbc58d4 | 2107 | vcpu->kvm->arch.kvm_ops->vcpu_load(vcpu, cpu); |
3a167bea AK |
2108 | } |
2109 | ||
2110 | void kvmppc_core_vcpu_put(struct kvm_vcpu *vcpu) | |
2111 | { | |
cbbc58d4 | 2112 | vcpu->kvm->arch.kvm_ops->vcpu_put(vcpu); |
94fa9d99 SW |
2113 | } |
2114 | ||
2986b8c7 | 2115 | int __init kvmppc_booke_init(void) |
d9fbd03d | 2116 | { |
d30f6e48 | 2117 | #ifndef CONFIG_KVM_BOOKE_HV |
d9fbd03d | 2118 | unsigned long ivor[16]; |
1d542d9c | 2119 | unsigned long *handler = kvmppc_booke_handler_addr; |
d9fbd03d | 2120 | unsigned long max_ivor = 0; |
1d542d9c | 2121 | unsigned long handler_len; |
d9fbd03d HB |
2122 | int i; |
2123 | ||
2124 | /* We install our own exception handlers by hijacking IVPR. IVPR must | |
2125 | * be 16-bit aligned, so we need a 64KB allocation. */ | |
2126 | kvmppc_booke_handlers = __get_free_pages(GFP_KERNEL | __GFP_ZERO, | |
2127 | VCPU_SIZE_ORDER); | |
2128 | if (!kvmppc_booke_handlers) | |
2129 | return -ENOMEM; | |
2130 | ||
2131 | /* XXX make sure our handlers are smaller than Linux's */ | |
2132 | ||
2133 | /* Copy our interrupt handlers to match host IVORs. That way we don't | |
2134 | * have to swap the IVORs on every guest/host transition. */ | |
2135 | ivor[0] = mfspr(SPRN_IVOR0); | |
2136 | ivor[1] = mfspr(SPRN_IVOR1); | |
2137 | ivor[2] = mfspr(SPRN_IVOR2); | |
2138 | ivor[3] = mfspr(SPRN_IVOR3); | |
2139 | ivor[4] = mfspr(SPRN_IVOR4); | |
2140 | ivor[5] = mfspr(SPRN_IVOR5); | |
2141 | ivor[6] = mfspr(SPRN_IVOR6); | |
2142 | ivor[7] = mfspr(SPRN_IVOR7); | |
2143 | ivor[8] = mfspr(SPRN_IVOR8); | |
2144 | ivor[9] = mfspr(SPRN_IVOR9); | |
2145 | ivor[10] = mfspr(SPRN_IVOR10); | |
2146 | ivor[11] = mfspr(SPRN_IVOR11); | |
2147 | ivor[12] = mfspr(SPRN_IVOR12); | |
2148 | ivor[13] = mfspr(SPRN_IVOR13); | |
2149 | ivor[14] = mfspr(SPRN_IVOR14); | |
2150 | ivor[15] = mfspr(SPRN_IVOR15); | |
2151 | ||
2152 | for (i = 0; i < 16; i++) { | |
2153 | if (ivor[i] > max_ivor) | |
1d542d9c | 2154 | max_ivor = i; |
d9fbd03d | 2155 | |
1d542d9c | 2156 | handler_len = handler[i + 1] - handler[i]; |
d9fbd03d | 2157 | memcpy((void *)kvmppc_booke_handlers + ivor[i], |
1d542d9c | 2158 | (void *)handler[i], handler_len); |
d9fbd03d | 2159 | } |
1d542d9c BB |
2160 | |
2161 | handler_len = handler[max_ivor + 1] - handler[max_ivor]; | |
2162 | flush_icache_range(kvmppc_booke_handlers, kvmppc_booke_handlers + | |
2163 | ivor[max_ivor] + handler_len); | |
d30f6e48 | 2164 | #endif /* !BOOKE_HV */ |
db93f574 | 2165 | return 0; |
d9fbd03d HB |
2166 | } |
2167 | ||
db93f574 | 2168 | void __exit kvmppc_booke_exit(void) |
d9fbd03d HB |
2169 | { |
2170 | free_pages(kvmppc_booke_handlers, VCPU_SIZE_ORDER); | |
2171 | kvm_exit(); | |
2172 | } |