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Merge tag 'for-v3.13-fixes' of git://git.infradead.org/battery-2.6
[mirror_ubuntu-jammy-kernel.git] / arch / powerpc / kvm / booke.c
CommitLineData
bbf45ba5
HB		 1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
14 *
15 * Copyright IBM Corp. 2007
4cd35f67 16 * Copyright 2010-2011 Freescale Semiconductor, Inc.
bbf45ba5
HB		 17 *
18 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
19 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
d30f6e48
SW		 20 * Scott Wood <scottwood@freescale.com>
21 * Varun Sethi <varun.sethi@freescale.com>
bbf45ba5
HB		 22 */
23
24#include <linux/errno.h>
25#include <linux/err.h>
26#include <linux/kvm_host.h>
5a0e3ad6 27#include <linux/gfp.h>
bbf45ba5
HB		 28#include <linux/module.h>
29#include <linux/vmalloc.h>
30#include <linux/fs.h>
7924bd41 31
bbf45ba5
HB		 32#include <asm/cputable.h>
33#include <asm/uaccess.h>
34#include <asm/kvm_ppc.h>
d9fbd03d 35#include <asm/cacheflush.h>
d30f6e48
SW		 36#include <asm/dbell.h>
37#include <asm/hw_irq.h>
38#include <asm/irq.h>
b50df19c 39#include <asm/time.h>
bbf45ba5 40
d30f6e48 41#include "timing.h"
75f74f0d 42#include "booke.h"
dba291f2
AK		 43
44#define CREATE_TRACE_POINTS
45#include "trace_booke.h"
bbf45ba5 46
d9fbd03d
HB		 47unsigned long kvmppc_booke_handlers;
48
bbf45ba5
HB		 49#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
50#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
51
52struct kvm_stats_debugfs_item debugfs_entries[] = {
bbf45ba5
HB		 53 { "mmio", VCPU_STAT(mmio_exits) },
54 { "dcr", VCPU_STAT(dcr_exits) },
55 { "sig", VCPU_STAT(signal_exits) },
bbf45ba5
HB		 56 { "itlb_r", VCPU_STAT(itlb_real_miss_exits) },
57 { "itlb_v", VCPU_STAT(itlb_virt_miss_exits) },
58 { "dtlb_r", VCPU_STAT(dtlb_real_miss_exits) },
59 { "dtlb_v", VCPU_STAT(dtlb_virt_miss_exits) },
60 { "sysc", VCPU_STAT(syscall_exits) },
61 { "isi", VCPU_STAT(isi_exits) },
62 { "dsi", VCPU_STAT(dsi_exits) },
63 { "inst_emu", VCPU_STAT(emulated_inst_exits) },
64 { "dec", VCPU_STAT(dec_exits) },
65 { "ext_intr", VCPU_STAT(ext_intr_exits) },
45c5eb67 66 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
d30f6e48
SW		 67 { "doorbell", VCPU_STAT(dbell_exits) },
68 { "guest doorbell", VCPU_STAT(gdbell_exits) },
cf1c5ca4 69 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
bbf45ba5
HB		 70 { NULL }
71};
72
bbf45ba5
HB		 73/* TODO: use vcpu_printf() */
74void kvmppc_dump_vcpu(struct kvm_vcpu *vcpu)
75{
76 int i;
77
666e7252 78 printk("pc: %08lx msr: %08llx\n", vcpu->arch.pc, vcpu->arch.shared->msr);
5cf8ca22 79 printk("lr: %08lx ctr: %08lx\n", vcpu->arch.lr, vcpu->arch.ctr);
de7906c3
AG		 80 printk("srr0: %08llx srr1: %08llx\n", vcpu->arch.shared->srr0,
81 vcpu->arch.shared->srr1);
bbf45ba5
HB		 82
83 printk("exceptions: %08lx\n", vcpu->arch.pending_exceptions);
84
85 for (i = 0; i < 32; i += 4) {
5cf8ca22 86 printk("gpr%02d: %08lx %08lx %08lx %08lx\n", i,
8e5b26b5
AG		 87 kvmppc_get_gpr(vcpu, i),
88 kvmppc_get_gpr(vcpu, i+1),
89 kvmppc_get_gpr(vcpu, i+2),
90 kvmppc_get_gpr(vcpu, i+3));
bbf45ba5
HB		 91 }
92}
93
4cd35f67
SW		 94#ifdef CONFIG_SPE
95void kvmppc_vcpu_disable_spe(struct kvm_vcpu *vcpu)
96{
97 preempt_disable();
98 enable_kernel_spe();
99 kvmppc_save_guest_spe(vcpu);
100 vcpu->arch.shadow_msr &= ~MSR_SPE;
101 preempt_enable();
102}
103
104static void kvmppc_vcpu_enable_spe(struct kvm_vcpu *vcpu)
105{
106 preempt_disable();
107 enable_kernel_spe();
108 kvmppc_load_guest_spe(vcpu);
109 vcpu->arch.shadow_msr |= MSR_SPE;
110 preempt_enable();
111}
112
113static void kvmppc_vcpu_sync_spe(struct kvm_vcpu *vcpu)
114{
115 if (vcpu->arch.shared->msr & MSR_SPE) {
116 if (!(vcpu->arch.shadow_msr & MSR_SPE))
117 kvmppc_vcpu_enable_spe(vcpu);
118 } else if (vcpu->arch.shadow_msr & MSR_SPE) {
119 kvmppc_vcpu_disable_spe(vcpu);
120 }
121}
122#else
123static void kvmppc_vcpu_sync_spe(struct kvm_vcpu *vcpu)
124{
125}
126#endif
127
7a08c274
AG		 128static void kvmppc_vcpu_sync_fpu(struct kvm_vcpu *vcpu)
129{
130#if defined(CONFIG_PPC_FPU) && !defined(CONFIG_KVM_BOOKE_HV)
131 /* We always treat the FP bit as enabled from the host
132 perspective, so only need to adjust the shadow MSR */
133 vcpu->arch.shadow_msr &= ~MSR_FP;
134 vcpu->arch.shadow_msr |= vcpu->arch.shared->msr & MSR_FP;
135#endif
136}
137
ce11e48b
BB		 138static void kvmppc_vcpu_sync_debug(struct kvm_vcpu *vcpu)
139{
140 /* Synchronize guest's desire to get debug interrupts into shadow MSR */
141#ifndef CONFIG_KVM_BOOKE_HV
142 vcpu->arch.shadow_msr &= ~MSR_DE;
143 vcpu->arch.shadow_msr |= vcpu->arch.shared->msr & MSR_DE;
144#endif
145
146 /* Force enable debug interrupts when user space wants to debug */
147 if (vcpu->guest_debug) {
148#ifdef CONFIG_KVM_BOOKE_HV
149 /*
150 * Since there is no shadow MSR, sync MSR_DE into the guest
151 * visible MSR.
152 */
153 vcpu->arch.shared->msr |= MSR_DE;
154#else
155 vcpu->arch.shadow_msr |= MSR_DE;
156 vcpu->arch.shared->msr &= ~MSR_DE;
157#endif
158 }
159}
160
dd9ebf1f
LY		 161/*
162 * Helper function for "full" MSR writes. No need to call this if only
163 * EE/CE/ME/DE/RI are changing.
164 */
4cd35f67
SW		 165void kvmppc_set_msr(struct kvm_vcpu *vcpu, u32 new_msr)
166{
dd9ebf1f 167 u32 old_msr = vcpu->arch.shared->msr;
4cd35f67 168
d30f6e48
SW		 169#ifdef CONFIG_KVM_BOOKE_HV
170 new_msr |= MSR_GS;
171#endif
172
4cd35f67
SW		 173 vcpu->arch.shared->msr = new_msr;
174
dd9ebf1f 175 kvmppc_mmu_msr_notify(vcpu, old_msr);
4cd35f67 176 kvmppc_vcpu_sync_spe(vcpu);
7a08c274 177 kvmppc_vcpu_sync_fpu(vcpu);
ce11e48b 178 kvmppc_vcpu_sync_debug(vcpu);
4cd35f67
SW		 179}
180
d4cf3892
HB		 181static void kvmppc_booke_queue_irqprio(struct kvm_vcpu *vcpu,
182 unsigned int priority)
9dd921cf 183{
6346046c 184 trace_kvm_booke_queue_irqprio(vcpu, priority);
9dd921cf
HB		 185 set_bit(priority, &vcpu->arch.pending_exceptions);
186}
187
daf5e271
LY		 188static void kvmppc_core_queue_dtlb_miss(struct kvm_vcpu *vcpu,
189 ulong dear_flags, ulong esr_flags)
9dd921cf 190{
daf5e271
LY		 191 vcpu->arch.queued_dear = dear_flags;
192 vcpu->arch.queued_esr = esr_flags;
193 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DTLB_MISS);
194}
195
196static void kvmppc_core_queue_data_storage(struct kvm_vcpu *vcpu,
197 ulong dear_flags, ulong esr_flags)
198{
199 vcpu->arch.queued_dear = dear_flags;
200 vcpu->arch.queued_esr = esr_flags;
201 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DATA_STORAGE);
202}
203
204static void kvmppc_core_queue_inst_storage(struct kvm_vcpu *vcpu,
205 ulong esr_flags)
206{
207 vcpu->arch.queued_esr = esr_flags;
208 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_INST_STORAGE);
209}
210
011da899
AG		 211static void kvmppc_core_queue_alignment(struct kvm_vcpu *vcpu, ulong dear_flags,
212 ulong esr_flags)
213{
214 vcpu->arch.queued_dear = dear_flags;
215 vcpu->arch.queued_esr = esr_flags;
216 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_ALIGNMENT);
217}
218
daf5e271
LY		 219void kvmppc_core_queue_program(struct kvm_vcpu *vcpu, ulong esr_flags)
220{
221 vcpu->arch.queued_esr = esr_flags;
d4cf3892 222 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_PROGRAM);
9dd921cf
HB		 223}
224
225void kvmppc_core_queue_dec(struct kvm_vcpu *vcpu)
226{
d4cf3892 227 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DECREMENTER);
9dd921cf
HB		 228}
229
230int kvmppc_core_pending_dec(struct kvm_vcpu *vcpu)
231{
d4cf3892 232 return test_bit(BOOKE_IRQPRIO_DECREMENTER, &vcpu->arch.pending_exceptions);
9dd921cf
HB		 233}
234
7706664d
AG		 235void kvmppc_core_dequeue_dec(struct kvm_vcpu *vcpu)
236{
237 clear_bit(BOOKE_IRQPRIO_DECREMENTER, &vcpu->arch.pending_exceptions);
238}
239
9dd921cf
HB		 240void kvmppc_core_queue_external(struct kvm_vcpu *vcpu,
241 struct kvm_interrupt *irq)
242{
c5335f17
AG		 243 unsigned int prio = BOOKE_IRQPRIO_EXTERNAL;
244
245 if (irq->irq == KVM_INTERRUPT_SET_LEVEL)
246 prio = BOOKE_IRQPRIO_EXTERNAL_LEVEL;
247
248 kvmppc_booke_queue_irqprio(vcpu, prio);
9dd921cf
HB		 249}
250
4fe27d2a 251void kvmppc_core_dequeue_external(struct kvm_vcpu *vcpu)
4496f974
AG		 252{
253 clear_bit(BOOKE_IRQPRIO_EXTERNAL, &vcpu->arch.pending_exceptions);
c5335f17 254 clear_bit(BOOKE_IRQPRIO_EXTERNAL_LEVEL, &vcpu->arch.pending_exceptions);
4496f974
AG		 255}
256
f61c94bb
BB		 257static void kvmppc_core_queue_watchdog(struct kvm_vcpu *vcpu)
258{
259 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_WATCHDOG);
260}
261
262static void kvmppc_core_dequeue_watchdog(struct kvm_vcpu *vcpu)
263{
264 clear_bit(BOOKE_IRQPRIO_WATCHDOG, &vcpu->arch.pending_exceptions);
265}
266
d30f6e48
SW		 267static void set_guest_srr(struct kvm_vcpu *vcpu, unsigned long srr0, u32 srr1)
268{
269#ifdef CONFIG_KVM_BOOKE_HV
270 mtspr(SPRN_GSRR0, srr0);
271 mtspr(SPRN_GSRR1, srr1);
272#else
273 vcpu->arch.shared->srr0 = srr0;
274 vcpu->arch.shared->srr1 = srr1;
275#endif
276}
277
278static void set_guest_csrr(struct kvm_vcpu *vcpu, unsigned long srr0, u32 srr1)
279{
280 vcpu->arch.csrr0 = srr0;
281 vcpu->arch.csrr1 = srr1;
282}
283
284static void set_guest_dsrr(struct kvm_vcpu *vcpu, unsigned long srr0, u32 srr1)
285{
286 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC)) {
287 vcpu->arch.dsrr0 = srr0;
288 vcpu->arch.dsrr1 = srr1;
289 } else {
290 set_guest_csrr(vcpu, srr0, srr1);
291 }
292}
293
294static void set_guest_mcsrr(struct kvm_vcpu *vcpu, unsigned long srr0, u32 srr1)
295{
296 vcpu->arch.mcsrr0 = srr0;
297 vcpu->arch.mcsrr1 = srr1;
298}
299
300static unsigned long get_guest_dear(struct kvm_vcpu *vcpu)
301{
302#ifdef CONFIG_KVM_BOOKE_HV
303 return mfspr(SPRN_GDEAR);
304#else
305 return vcpu->arch.shared->dar;
306#endif
307}
308
309static void set_guest_dear(struct kvm_vcpu *vcpu, unsigned long dear)
310{
311#ifdef CONFIG_KVM_BOOKE_HV
312 mtspr(SPRN_GDEAR, dear);
313#else
314 vcpu->arch.shared->dar = dear;
315#endif
316}
317
318static unsigned long get_guest_esr(struct kvm_vcpu *vcpu)
319{
320#ifdef CONFIG_KVM_BOOKE_HV
321 return mfspr(SPRN_GESR);
322#else
323 return vcpu->arch.shared->esr;
324#endif
325}
326
327static void set_guest_esr(struct kvm_vcpu *vcpu, u32 esr)
328{
329#ifdef CONFIG_KVM_BOOKE_HV
330 mtspr(SPRN_GESR, esr);
331#else
332 vcpu->arch.shared->esr = esr;
333#endif
334}
335
324b3e63
AG		 336static unsigned long get_guest_epr(struct kvm_vcpu *vcpu)
337{
338#ifdef CONFIG_KVM_BOOKE_HV
339 return mfspr(SPRN_GEPR);
340#else
341 return vcpu->arch.epr;
342#endif
343}
344
d4cf3892
HB		 345/* Deliver the interrupt of the corresponding priority, if possible. */
346static int kvmppc_booke_irqprio_deliver(struct kvm_vcpu *vcpu,
347 unsigned int priority)
bbf45ba5 348{
d4cf3892 349 int allowed = 0;
79300f8c 350 ulong msr_mask = 0;
1c810636 351 bool update_esr = false, update_dear = false, update_epr = false;
5c6cedf4
AG		 352 ulong crit_raw = vcpu->arch.shared->critical;
353 ulong crit_r1 = kvmppc_get_gpr(vcpu, 1);
354 bool crit;
c5335f17 355 bool keep_irq = false;
d30f6e48 356 enum int_class int_class;
95e90b43 357 ulong new_msr = vcpu->arch.shared->msr;
5c6cedf4
AG		 358
359 /* Truncate crit indicators in 32 bit mode */
360 if (!(vcpu->arch.shared->msr & MSR_SF)) {
361 crit_raw &= 0xffffffff;
362 crit_r1 &= 0xffffffff;
363 }
364
365 /* Critical section when crit == r1 */
366 crit = (crit_raw == crit_r1);
367 /* ... and we're in supervisor mode */
368 crit = crit && !(vcpu->arch.shared->msr & MSR_PR);
d4cf3892 369
c5335f17
AG		 370 if (priority == BOOKE_IRQPRIO_EXTERNAL_LEVEL) {
371 priority = BOOKE_IRQPRIO_EXTERNAL;
372 keep_irq = true;
373 }
374
5df554ad 375 if ((priority == BOOKE_IRQPRIO_EXTERNAL) && vcpu->arch.epr_flags)
1c810636
AG		 376 update_epr = true;
377
d4cf3892 378 switch (priority) {
d4cf3892 379 case BOOKE_IRQPRIO_DTLB_MISS:
d4cf3892 380 case BOOKE_IRQPRIO_DATA_STORAGE:
011da899 381 case BOOKE_IRQPRIO_ALIGNMENT:
daf5e271
LY		 382 update_dear = true;
383 /* fall through */
d4cf3892 384 case BOOKE_IRQPRIO_INST_STORAGE:
daf5e271
LY		 385 case BOOKE_IRQPRIO_PROGRAM:
386 update_esr = true;
387 /* fall through */
388 case BOOKE_IRQPRIO_ITLB_MISS:
389 case BOOKE_IRQPRIO_SYSCALL:
d4cf3892 390 case BOOKE_IRQPRIO_FP_UNAVAIL:
bb3a8a17
HB		 391 case BOOKE_IRQPRIO_SPE_UNAVAIL:
392 case BOOKE_IRQPRIO_SPE_FP_DATA:
393 case BOOKE_IRQPRIO_SPE_FP_ROUND:
d4cf3892 394 case BOOKE_IRQPRIO_AP_UNAVAIL:
d4cf3892 395 allowed = 1;
79300f8c 396 msr_mask = MSR_CE | MSR_ME | MSR_DE;
d30f6e48 397 int_class = INT_CLASS_NONCRIT;
bbf45ba5 398 break;
f61c94bb 399 case BOOKE_IRQPRIO_WATCHDOG:
d4cf3892 400 case BOOKE_IRQPRIO_CRITICAL:
4ab96919 401 case BOOKE_IRQPRIO_DBELL_CRIT:
666e7252 402 allowed = vcpu->arch.shared->msr & MSR_CE;
d30f6e48 403 allowed = allowed && !crit;
79300f8c 404 msr_mask = MSR_ME;
d30f6e48 405 int_class = INT_CLASS_CRIT;
bbf45ba5 406 break;
d4cf3892 407 case BOOKE_IRQPRIO_MACHINE_CHECK:
666e7252 408 allowed = vcpu->arch.shared->msr & MSR_ME;
d30f6e48 409 allowed = allowed && !crit;
d30f6e48 410 int_class = INT_CLASS_MC;
bbf45ba5 411 break;
d4cf3892
HB		 412 case BOOKE_IRQPRIO_DECREMENTER:
413 case BOOKE_IRQPRIO_FIT:
dfd4d47e
SW		 414 keep_irq = true;
415 /* fall through */
416 case BOOKE_IRQPRIO_EXTERNAL:
4ab96919 417 case BOOKE_IRQPRIO_DBELL:
666e7252 418 allowed = vcpu->arch.shared->msr & MSR_EE;
5c6cedf4 419 allowed = allowed && !crit;
79300f8c 420 msr_mask = MSR_CE | MSR_ME | MSR_DE;
d30f6e48 421 int_class = INT_CLASS_NONCRIT;
bbf45ba5 422 break;
d4cf3892 423 case BOOKE_IRQPRIO_DEBUG:
666e7252 424 allowed = vcpu->arch.shared->msr & MSR_DE;
d30f6e48 425 allowed = allowed && !crit;
79300f8c 426 msr_mask = MSR_ME;
d30f6e48 427 int_class = INT_CLASS_CRIT;
bbf45ba5 428 break;
bbf45ba5
HB		 429 }
430
d4cf3892 431 if (allowed) {
d30f6e48
SW		 432 switch (int_class) {
433 case INT_CLASS_NONCRIT:
434 set_guest_srr(vcpu, vcpu->arch.pc,
435 vcpu->arch.shared->msr);
436 break;
437 case INT_CLASS_CRIT:
438 set_guest_csrr(vcpu, vcpu->arch.pc,
439 vcpu->arch.shared->msr);
440 break;
441 case INT_CLASS_DBG:
442 set_guest_dsrr(vcpu, vcpu->arch.pc,
443 vcpu->arch.shared->msr);
444 break;
445 case INT_CLASS_MC:
446 set_guest_mcsrr(vcpu, vcpu->arch.pc,
447 vcpu->arch.shared->msr);
448 break;
449 }
450
d4cf3892 451 vcpu->arch.pc = vcpu->arch.ivpr | vcpu->arch.ivor[priority];
daf5e271 452 if (update_esr == true)
d30f6e48 453 set_guest_esr(vcpu, vcpu->arch.queued_esr);
daf5e271 454 if (update_dear == true)
d30f6e48 455 set_guest_dear(vcpu, vcpu->arch.queued_dear);
5df554ad
SW		 456 if (update_epr == true) {
457 if (vcpu->arch.epr_flags & KVMPPC_EPR_USER)
458 kvm_make_request(KVM_REQ_EPR_EXIT, vcpu);
eb1e4f43
SW		 459 else if (vcpu->arch.epr_flags & KVMPPC_EPR_KERNEL) {
460 BUG_ON(vcpu->arch.irq_type != KVMPPC_IRQ_MPIC);
461 kvmppc_mpic_set_epr(vcpu);
462 }
5df554ad 463 }
95e90b43
MC		 464
465 new_msr &= msr_mask;
466#if defined(CONFIG_64BIT)
467 if (vcpu->arch.epcr & SPRN_EPCR_ICM)
468 new_msr |= MSR_CM;
469#endif
470 kvmppc_set_msr(vcpu, new_msr);
bbf45ba5 471
c5335f17
AG		 472 if (!keep_irq)
473 clear_bit(priority, &vcpu->arch.pending_exceptions);
bbf45ba5
HB		 474 }
475
d30f6e48
SW		 476#ifdef CONFIG_KVM_BOOKE_HV
477 /*
478 * If an interrupt is pending but masked, raise a guest doorbell
479 * so that we are notified when the guest enables the relevant
480 * MSR bit.
481 */
482 if (vcpu->arch.pending_exceptions & BOOKE_IRQMASK_EE)
483 kvmppc_set_pending_interrupt(vcpu, INT_CLASS_NONCRIT);
484 if (vcpu->arch.pending_exceptions & BOOKE_IRQMASK_CE)
485 kvmppc_set_pending_interrupt(vcpu, INT_CLASS_CRIT);
486 if (vcpu->arch.pending_exceptions & BOOKE_IRQPRIO_MACHINE_CHECK)
487 kvmppc_set_pending_interrupt(vcpu, INT_CLASS_MC);
488#endif
489
d4cf3892 490 return allowed;
bbf45ba5
HB		 491}
492
f61c94bb
BB		 493/*
494 * Return the number of jiffies until the next timeout. If the timeout is
495 * longer than the NEXT_TIMER_MAX_DELTA, then return NEXT_TIMER_MAX_DELTA
496 * because the larger value can break the timer APIs.
497 */
498static unsigned long watchdog_next_timeout(struct kvm_vcpu *vcpu)
499{
500 u64 tb, wdt_tb, wdt_ticks = 0;
501 u64 nr_jiffies = 0;
502 u32 period = TCR_GET_WP(vcpu->arch.tcr);
503
504 wdt_tb = 1ULL << (63 - period);
505 tb = get_tb();
506 /*
507 * The watchdog timeout will hapeen when TB bit corresponding
508 * to watchdog will toggle from 0 to 1.
509 */
510 if (tb & wdt_tb)
511 wdt_ticks = wdt_tb;
512
513 wdt_ticks += wdt_tb - (tb & (wdt_tb - 1));
514
515 /* Convert timebase ticks to jiffies */
516 nr_jiffies = wdt_ticks;
517
518 if (do_div(nr_jiffies, tb_ticks_per_jiffy))
519 nr_jiffies++;
520
521 return min_t(unsigned long long, nr_jiffies, NEXT_TIMER_MAX_DELTA);
522}
523
524static void arm_next_watchdog(struct kvm_vcpu *vcpu)
525{
526 unsigned long nr_jiffies;
527 unsigned long flags;
528
529 /*
530 * If TSR_ENW and TSR_WIS are not set then no need to exit to
531 * userspace, so clear the KVM_REQ_WATCHDOG request.
532 */
533 if ((vcpu->arch.tsr & (TSR_ENW | TSR_WIS)) != (TSR_ENW | TSR_WIS))
534 clear_bit(KVM_REQ_WATCHDOG, &vcpu->requests);
535
536 spin_lock_irqsave(&vcpu->arch.wdt_lock, flags);
537 nr_jiffies = watchdog_next_timeout(vcpu);
538 /*
539 * If the number of jiffies of watchdog timer >= NEXT_TIMER_MAX_DELTA
540 * then do not run the watchdog timer as this can break timer APIs.
541 */
542 if (nr_jiffies < NEXT_TIMER_MAX_DELTA)
543 mod_timer(&vcpu->arch.wdt_timer, jiffies + nr_jiffies);
544 else
545 del_timer(&vcpu->arch.wdt_timer);
546 spin_unlock_irqrestore(&vcpu->arch.wdt_lock, flags);
547}
548
549void kvmppc_watchdog_func(unsigned long data)
550{
551 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
552 u32 tsr, new_tsr;
553 int final;
554
555 do {
556 new_tsr = tsr = vcpu->arch.tsr;
557 final = 0;
558
559 /* Time out event */
560 if (tsr & TSR_ENW) {
561 if (tsr & TSR_WIS)
562 final = 1;
563 else
564 new_tsr = tsr | TSR_WIS;
565 } else {
566 new_tsr = tsr | TSR_ENW;
567 }
568 } while (cmpxchg(&vcpu->arch.tsr, tsr, new_tsr) != tsr);
569
570 if (new_tsr & TSR_WIS) {
571 smp_wmb();
572 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
573 kvm_vcpu_kick(vcpu);
574 }
575
576 /*
577 * If this is final watchdog expiry and some action is required
578 * then exit to userspace.
579 */
580 if (final && (vcpu->arch.tcr & TCR_WRC_MASK) &&
581 vcpu->arch.watchdog_enabled) {
582 smp_wmb();
583 kvm_make_request(KVM_REQ_WATCHDOG, vcpu);
584 kvm_vcpu_kick(vcpu);
585 }
586
587 /*
588 * Stop running the watchdog timer after final expiration to
589 * prevent the host from being flooded with timers if the
590 * guest sets a short period.
591 * Timers will resume when TSR/TCR is updated next time.
592 */
593 if (!final)
594 arm_next_watchdog(vcpu);
595}
596
dfd4d47e
SW		 597static void update_timer_ints(struct kvm_vcpu *vcpu)
598{
599 if ((vcpu->arch.tcr & TCR_DIE) && (vcpu->arch.tsr & TSR_DIS))
600 kvmppc_core_queue_dec(vcpu);
601 else
602 kvmppc_core_dequeue_dec(vcpu);
f61c94bb
BB		 603
604 if ((vcpu->arch.tcr & TCR_WIE) && (vcpu->arch.tsr & TSR_WIS))
605 kvmppc_core_queue_watchdog(vcpu);
606 else
607 kvmppc_core_dequeue_watchdog(vcpu);
dfd4d47e
SW		 608}
609
c59a6a3e 610static void kvmppc_core_check_exceptions(struct kvm_vcpu *vcpu)
bbf45ba5
HB		 611{
612 unsigned long *pending = &vcpu->arch.pending_exceptions;
bbf45ba5
HB		 613 unsigned int priority;
614
9ab80843 615 priority = __ffs(*pending);
8b3a00fc 616 while (priority < BOOKE_IRQPRIO_MAX) {
d4cf3892 617 if (kvmppc_booke_irqprio_deliver(vcpu, priority))
bbf45ba5 618 break;
bbf45ba5
HB		 619
620 priority = find_next_bit(pending,
621 BITS_PER_BYTE * sizeof(*pending),
622 priority + 1);
623 }
90bba358
AG		 624
625 /* Tell the guest about our interrupt status */
29ac26ef 626 vcpu->arch.shared->int_pending = !!*pending;
bbf45ba5
HB		 627}
628
c59a6a3e 629/* Check pending exceptions and deliver one, if possible. */
a8e4ef84 630int kvmppc_core_prepare_to_enter(struct kvm_vcpu *vcpu)
c59a6a3e 631{
a8e4ef84 632 int r = 0;
c59a6a3e
SW		 633 WARN_ON_ONCE(!irqs_disabled());
634
635 kvmppc_core_check_exceptions(vcpu);
636
b8c649a9
AG		 637 if (vcpu->requests) {
638 /* Exception delivery raised request; start over */
639 return 1;
640 }
641
c59a6a3e
SW		 642 if (vcpu->arch.shared->msr & MSR_WE) {
643 local_irq_enable();
644 kvm_vcpu_block(vcpu);
966cd0f3 645 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
c59a6a3e
SW		 646 local_irq_disable();
647
648 kvmppc_set_exit_type(vcpu, EMULATED_MTMSRWE_EXITS);
a8e4ef84 649 r = 1;
c59a6a3e 650 };
a8e4ef84
AG		 651
652 return r;
653}
654
7c973a2e 655int kvmppc_core_check_requests(struct kvm_vcpu *vcpu)
4ffc6356 656{
7c973a2e
AG		 657 int r = 1; /* Indicate we want to get back into the guest */
658
2d8185d4
AG		 659 if (kvm_check_request(KVM_REQ_PENDING_TIMER, vcpu))
660 update_timer_ints(vcpu);
862d31f7 661#if defined(CONFIG_KVM_E500V2) || defined(CONFIG_KVM_E500MC)
2d8185d4
AG		 662 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
663 kvmppc_core_flush_tlb(vcpu);
862d31f7 664#endif
7c973a2e 665
f61c94bb
BB		 666 if (kvm_check_request(KVM_REQ_WATCHDOG, vcpu)) {
667 vcpu->run->exit_reason = KVM_EXIT_WATCHDOG;
668 r = 0;
669 }
670
1c810636
AG		 671 if (kvm_check_request(KVM_REQ_EPR_EXIT, vcpu)) {
672 vcpu->run->epr.epr = 0;
673 vcpu->arch.epr_needed = true;
674 vcpu->run->exit_reason = KVM_EXIT_EPR;
675 r = 0;
676 }
677
7c973a2e 678 return r;
4ffc6356
AG		 679}
680
df6909e5
PM		 681int kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
682{
7ee78855 683 int ret, s;
f5f97210 684 struct debug_reg debug;
8fae845f 685#ifdef CONFIG_PPC_FPU
de79f7b9 686 struct thread_fp_state fp;
8fae845f 687 int fpexc_mode;
8fae845f 688#endif
df6909e5 689
af8f38b3
AG		 690 if (!vcpu->arch.sane) {
691 kvm_run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
692 return -EINVAL;
693 }
694
df6909e5 695 local_irq_disable();
7ee78855
AG		 696 s = kvmppc_prepare_to_enter(vcpu);
697 if (s <= 0) {
24afa37b 698 local_irq_enable();
7ee78855 699 ret = s;
1d1ef222
SW		 700 goto out;
701 }
702
8fae845f
SW		 703#ifdef CONFIG_PPC_FPU
704 /* Save userspace FPU state in stack */
705 enable_kernel_fp();
de79f7b9 706 fp = current->thread.fp_state;
8fae845f
SW		 707 fpexc_mode = current->thread.fpexc_mode;
708
709 /* Restore guest FPU state to thread */
de79f7b9
PM		 710 memcpy(current->thread.fp_state.fpr, vcpu->arch.fpr,
711 sizeof(vcpu->arch.fpr));
712 current->thread.fp_state.fpscr = vcpu->arch.fpscr;
8fae845f
SW		 713
714 /*
715 * Since we can't trap on MSR_FP in GS-mode, we consider the guest
716 * as always using the FPU. Kernel usage of FP (via
717 * enable_kernel_fp()) in this thread must not occur while
718 * vcpu->fpu_active is set.
719 */
720 vcpu->fpu_active = 1;
721
722 kvmppc_load_guest_fp(vcpu);
723#endif
724
ce11e48b 725 /* Switch to guest debug context */
f5f97210
SW		 726 debug = vcpu->arch.shadow_dbg_reg;
727 switch_booke_debug_regs(&debug);
728 debug = current->thread.debug;
ce11e48b
BB		 729 current->thread.debug = vcpu->arch.shadow_dbg_reg;
730
5f1c248f 731 kvmppc_fix_ee_before_entry();
f8941fbe 732
df6909e5 733 ret = __kvmppc_vcpu_run(kvm_run, vcpu);
8fae845f 734
24afa37b
AG		 735 /* No need for kvm_guest_exit. It's done in handle_exit.
736 We also get here with interrupts enabled. */
737
ce11e48b 738 /* Switch back to user space debug context */
f5f97210
SW		 739 switch_booke_debug_regs(&debug);
740 current->thread.debug = debug;
ce11e48b 741
8fae845f
SW		 742#ifdef CONFIG_PPC_FPU
743 kvmppc_save_guest_fp(vcpu);
744
745 vcpu->fpu_active = 0;
746
747 /* Save guest FPU state from thread */
de79f7b9
PM		 748 memcpy(vcpu->arch.fpr, current->thread.fp_state.fpr,
749 sizeof(vcpu->arch.fpr));
750 vcpu->arch.fpscr = current->thread.fp_state.fpscr;
8fae845f
SW		 751
752 /* Restore userspace FPU state from stack */
de79f7b9 753 current->thread.fp_state = fp;
8fae845f
SW		 754 current->thread.fpexc_mode = fpexc_mode;
755#endif
756
1d1ef222 757out:
d69c6436 758 vcpu->mode = OUTSIDE_GUEST_MODE;
df6909e5
PM		 759 return ret;
760}
761
d30f6e48
SW		 762static int emulation_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
763{
764 enum emulation_result er;
765
766 er = kvmppc_emulate_instruction(run, vcpu);
767 switch (er) {
768 case EMULATE_DONE:
769 /* don't overwrite subtypes, just account kvm_stats */
770 kvmppc_account_exit_stat(vcpu, EMULATED_INST_EXITS);
771 /* Future optimization: only reload non-volatiles if
772 * they were actually modified by emulation. */
773 return RESUME_GUEST_NV;
774
775 case EMULATE_DO_DCR:
776 run->exit_reason = KVM_EXIT_DCR;
777 return RESUME_HOST;
778
779 case EMULATE_FAIL:
d30f6e48
SW		 780 printk(KERN_CRIT "%s: emulation at %lx failed (%08x)\n",
781 __func__, vcpu->arch.pc, vcpu->arch.last_inst);
782 /* For debugging, encode the failing instruction and
783 * report it to userspace. */
784 run->hw.hardware_exit_reason = ~0ULL << 32;
785 run->hw.hardware_exit_reason |= vcpu->arch.last_inst;
d1ff5499 786 kvmppc_core_queue_program(vcpu, ESR_PIL);
d30f6e48
SW		 787 return RESUME_HOST;
788
9b4f5308
BB		 789 case EMULATE_EXIT_USER:
790 return RESUME_HOST;
791
d30f6e48
SW		 792 default:
793 BUG();
794 }
795}
796
ce11e48b
BB		 797static int kvmppc_handle_debug(struct kvm_run *run, struct kvm_vcpu *vcpu)
798{
799 struct debug_reg *dbg_reg = &(vcpu->arch.shadow_dbg_reg);
800 u32 dbsr = vcpu->arch.dbsr;
801
802 run->debug.arch.status = 0;
803 run->debug.arch.address = vcpu->arch.pc;
804
805 if (dbsr & (DBSR_IAC1 | DBSR_IAC2 | DBSR_IAC3 | DBSR_IAC4)) {
806 run->debug.arch.status |= KVMPPC_DEBUG_BREAKPOINT;
807 } else {
808 if (dbsr & (DBSR_DAC1W | DBSR_DAC2W))
809 run->debug.arch.status |= KVMPPC_DEBUG_WATCH_WRITE;
810 else if (dbsr & (DBSR_DAC1R | DBSR_DAC2R))
811 run->debug.arch.status |= KVMPPC_DEBUG_WATCH_READ;
812 if (dbsr & (DBSR_DAC1R | DBSR_DAC1W))
813 run->debug.arch.address = dbg_reg->dac1;
814 else if (dbsr & (DBSR_DAC2R | DBSR_DAC2W))
815 run->debug.arch.address = dbg_reg->dac2;
816 }
817
818 return RESUME_HOST;
819}
820
4e642ccb 821static void kvmppc_fill_pt_regs(struct pt_regs *regs)
bbf45ba5 822{
4e642ccb 823 ulong r1, ip, msr, lr;
bbf45ba5 824
4e642ccb
AG		 825 asm("mr %0, 1" : "=r"(r1));
826 asm("mflr %0" : "=r"(lr));
827 asm("mfmsr %0" : "=r"(msr));
828 asm("bl 1f; 1: mflr %0" : "=r"(ip));
829
830 memset(regs, 0, sizeof(*regs));
831 regs->gpr[1] = r1;
832 regs->nip = ip;
833 regs->msr = msr;
834 regs->link = lr;
835}
836
6328e593
BB		 837/*
838 * For interrupts needed to be handled by host interrupt handlers,
839 * corresponding host handler are called from here in similar way
840 * (but not exact) as they are called from low level handler
841 * (such as from arch/powerpc/kernel/head_fsl_booke.S).
842 */
4e642ccb
AG		 843static void kvmppc_restart_interrupt(struct kvm_vcpu *vcpu,
844 unsigned int exit_nr)
845{
846 struct pt_regs regs;
73e75b41 847
d30f6e48
SW		 848 switch (exit_nr) {
849 case BOOKE_INTERRUPT_EXTERNAL:
4e642ccb
AG		 850 kvmppc_fill_pt_regs(&regs);
851 do_IRQ(&regs);
d30f6e48 852 break;
d30f6e48 853 case BOOKE_INTERRUPT_DECREMENTER:
4e642ccb
AG		 854 kvmppc_fill_pt_regs(&regs);
855 timer_interrupt(&regs);
d30f6e48 856 break;
5f17ce8b 857#if defined(CONFIG_PPC_DOORBELL)
d30f6e48 858 case BOOKE_INTERRUPT_DOORBELL:
4e642ccb
AG		 859 kvmppc_fill_pt_regs(&regs);
860 doorbell_exception(&regs);
d30f6e48
SW		 861 break;
862#endif
863 case BOOKE_INTERRUPT_MACHINE_CHECK:
864 /* FIXME */
865 break;
7cc1e8ee
AG		 866 case BOOKE_INTERRUPT_PERFORMANCE_MONITOR:
867 kvmppc_fill_pt_regs(&regs);
868 performance_monitor_exception(&regs);
869 break;
6328e593
BB		 870 case BOOKE_INTERRUPT_WATCHDOG:
871 kvmppc_fill_pt_regs(&regs);
872#ifdef CONFIG_BOOKE_WDT
873 WatchdogException(&regs);
874#else
875 unknown_exception(&regs);
876#endif
877 break;
878 case BOOKE_INTERRUPT_CRITICAL:
879 unknown_exception(&regs);
880 break;
ce11e48b
BB		 881 case BOOKE_INTERRUPT_DEBUG:
882 /* Save DBSR before preemption is enabled */
883 vcpu->arch.dbsr = mfspr(SPRN_DBSR);
884 kvmppc_clear_dbsr();
885 break;
d30f6e48 886 }
4e642ccb
AG		 887}
888
889/**
890 * kvmppc_handle_exit
891 *
892 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
893 */
894int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
895 unsigned int exit_nr)
896{
897 int r = RESUME_HOST;
7ee78855 898 int s;
f1e89028 899 int idx;
4e642ccb 900
7c11c0cc
SW		 901#ifdef CONFIG_PPC64
902 WARN_ON(local_paca->irq_happened != 0);
903#endif
904
905 /*
906 * We enter with interrupts disabled in hardware, but
907 * we need to call hard_irq_disable anyway to ensure that
908 * the software state is kept in sync.
909 */
910 hard_irq_disable();
911
4e642ccb
AG		 912 /* update before a new last_exit_type is rewritten */
913 kvmppc_update_timing_stats(vcpu);
914
915 /* restart interrupts if they were meant for the host */
916 kvmppc_restart_interrupt(vcpu, exit_nr);
d30f6e48 917
bbf45ba5
HB		 918 local_irq_enable();
919
97c95059 920 trace_kvm_exit(exit_nr, vcpu);
706fb730 921 kvm_guest_exit();
97c95059 922
bbf45ba5
HB		 923 run->exit_reason = KVM_EXIT_UNKNOWN;
924 run->ready_for_interrupt_injection = 1;
925
926 switch (exit_nr) {
927 case BOOKE_INTERRUPT_MACHINE_CHECK:
c35c9d84
AG		 928 printk("MACHINE CHECK: %lx\n", mfspr(SPRN_MCSR));
929 kvmppc_dump_vcpu(vcpu);
930 /* For debugging, send invalid exit reason to user space */
931 run->hw.hardware_exit_reason = ~1ULL << 32;
932 run->hw.hardware_exit_reason |= mfspr(SPRN_MCSR);
933 r = RESUME_HOST;
bbf45ba5
HB		 934 break;
935
936 case BOOKE_INTERRUPT_EXTERNAL:
7b701591 937 kvmppc_account_exit(vcpu, EXT_INTR_EXITS);
1b6766c7
HB		 938 r = RESUME_GUEST;
939 break;
940
bbf45ba5 941 case BOOKE_INTERRUPT_DECREMENTER:
7b701591 942 kvmppc_account_exit(vcpu, DEC_EXITS);
bbf45ba5
HB		 943 r = RESUME_GUEST;
944 break;
945
6328e593
BB		 946 case BOOKE_INTERRUPT_WATCHDOG:
947 r = RESUME_GUEST;
948 break;
949
d30f6e48
SW		 950 case BOOKE_INTERRUPT_DOORBELL:
951 kvmppc_account_exit(vcpu, DBELL_EXITS);
d30f6e48
SW		 952 r = RESUME_GUEST;
953 break;
954
955 case BOOKE_INTERRUPT_GUEST_DBELL_CRIT:
956 kvmppc_account_exit(vcpu, GDBELL_EXITS);
957
958 /*
959 * We are here because there is a pending guest interrupt
960 * which could not be delivered as MSR_CE or MSR_ME was not
961 * set. Once we break from here we will retry delivery.
962 */
963 r = RESUME_GUEST;
964 break;
965
966 case BOOKE_INTERRUPT_GUEST_DBELL:
967 kvmppc_account_exit(vcpu, GDBELL_EXITS);
968
969 /*
970 * We are here because there is a pending guest interrupt
971 * which could not be delivered as MSR_EE was not set. Once
972 * we break from here we will retry delivery.
973 */
974 r = RESUME_GUEST;
975 break;
976
95f2e921
AG		 977 case BOOKE_INTERRUPT_PERFORMANCE_MONITOR:
978 r = RESUME_GUEST;
979 break;
980
d30f6e48
SW		 981 case BOOKE_INTERRUPT_HV_PRIV:
982 r = emulation_exit(run, vcpu);
983 break;
984
bbf45ba5 985 case BOOKE_INTERRUPT_PROGRAM:
d30f6e48 986 if (vcpu->arch.shared->msr & (MSR_PR | MSR_GS)) {
0268597c
AG		 987 /*
988 * Program traps generated by user-level software must
989 * be handled by the guest kernel.
990 *
991 * In GS mode, hypervisor privileged instructions trap
992 * on BOOKE_INTERRUPT_HV_PRIV, not here, so these are
993 * actual program interrupts, handled by the guest.
994 */
daf5e271 995 kvmppc_core_queue_program(vcpu, vcpu->arch.fault_esr);
bbf45ba5 996 r = RESUME_GUEST;
7b701591 997 kvmppc_account_exit(vcpu, USR_PR_INST);
bbf45ba5
HB		 998 break;
999 }
1000
d30f6e48 1001 r = emulation_exit(run, vcpu);
bbf45ba5
HB		 1002 break;
1003
de368dce 1004 case BOOKE_INTERRUPT_FP_UNAVAIL:
d4cf3892 1005 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_FP_UNAVAIL);
7b701591 1006 kvmppc_account_exit(vcpu, FP_UNAVAIL);
de368dce
CE		 1007 r = RESUME_GUEST;
1008 break;
1009
4cd35f67
SW		 1010#ifdef CONFIG_SPE
1011 case BOOKE_INTERRUPT_SPE_UNAVAIL: {
1012 if (vcpu->arch.shared->msr & MSR_SPE)
1013 kvmppc_vcpu_enable_spe(vcpu);
1014 else
1015 kvmppc_booke_queue_irqprio(vcpu,
1016 BOOKE_IRQPRIO_SPE_UNAVAIL);
bb3a8a17
HB		 1017 r = RESUME_GUEST;
1018 break;
4cd35f67 1019 }
bb3a8a17
HB		 1020
1021 case BOOKE_INTERRUPT_SPE_FP_DATA:
1022 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_SPE_FP_DATA);
1023 r = RESUME_GUEST;
1024 break;
1025
1026 case BOOKE_INTERRUPT_SPE_FP_ROUND:
1027 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_SPE_FP_ROUND);
1028 r = RESUME_GUEST;
1029 break;
4cd35f67
SW		 1030#else
1031 case BOOKE_INTERRUPT_SPE_UNAVAIL:
1032 /*
1033 * Guest wants SPE, but host kernel doesn't support it. Send
1034 * an "unimplemented operation" program check to the guest.
1035 */
1036 kvmppc_core_queue_program(vcpu, ESR_PUO | ESR_SPV);
1037 r = RESUME_GUEST;
1038 break;
1039
1040 /*
1041 * These really should never happen without CONFIG_SPE,
1042 * as we should never enable the real MSR[SPE] in the guest.
1043 */
1044 case BOOKE_INTERRUPT_SPE_FP_DATA:
1045 case BOOKE_INTERRUPT_SPE_FP_ROUND:
1046 printk(KERN_CRIT "%s: unexpected SPE interrupt %u at %08lx\n",
1047 __func__, exit_nr, vcpu->arch.pc);
1048 run->hw.hardware_exit_reason = exit_nr;
1049 r = RESUME_HOST;
1050 break;
1051#endif
bb3a8a17 1052
bbf45ba5 1053 case BOOKE_INTERRUPT_DATA_STORAGE:
daf5e271
LY		 1054 kvmppc_core_queue_data_storage(vcpu, vcpu->arch.fault_dear,
1055 vcpu->arch.fault_esr);
7b701591 1056 kvmppc_account_exit(vcpu, DSI_EXITS);
bbf45ba5
HB		 1057 r = RESUME_GUEST;
1058 break;
1059
1060 case BOOKE_INTERRUPT_INST_STORAGE:
daf5e271 1061 kvmppc_core_queue_inst_storage(vcpu, vcpu->arch.fault_esr);
7b701591 1062 kvmppc_account_exit(vcpu, ISI_EXITS);
bbf45ba5
HB		 1063 r = RESUME_GUEST;
1064 break;
1065
011da899
AG		 1066 case BOOKE_INTERRUPT_ALIGNMENT:
1067 kvmppc_core_queue_alignment(vcpu, vcpu->arch.fault_dear,
1068 vcpu->arch.fault_esr);
1069 r = RESUME_GUEST;
1070 break;
1071
d30f6e48
SW		 1072#ifdef CONFIG_KVM_BOOKE_HV
1073 case BOOKE_INTERRUPT_HV_SYSCALL:
1074 if (!(vcpu->arch.shared->msr & MSR_PR)) {
1075 kvmppc_set_gpr(vcpu, 3, kvmppc_kvm_pv(vcpu));
1076 } else {
1077 /*
1078 * hcall from guest userspace -- send privileged
1079 * instruction program check.
1080 */
1081 kvmppc_core_queue_program(vcpu, ESR_PPR);
1082 }
1083
1084 r = RESUME_GUEST;
1085 break;
1086#else
bbf45ba5 1087 case BOOKE_INTERRUPT_SYSCALL:
2a342ed5
AG		 1088 if (!(vcpu->arch.shared->msr & MSR_PR) &&
1089 (((u32)kvmppc_get_gpr(vcpu, 0)) == KVM_SC_MAGIC_R0)) {
1090 /* KVM PV hypercalls */
1091 kvmppc_set_gpr(vcpu, 3, kvmppc_kvm_pv(vcpu));
1092 r = RESUME_GUEST;
1093 } else {
1094 /* Guest syscalls */
1095 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_SYSCALL);
1096 }
7b701591 1097 kvmppc_account_exit(vcpu, SYSCALL_EXITS);
bbf45ba5
HB		 1098 r = RESUME_GUEST;
1099 break;
d30f6e48 1100#endif
bbf45ba5
HB		 1101
1102 case BOOKE_INTERRUPT_DTLB_MISS: {
bbf45ba5 1103 unsigned long eaddr = vcpu->arch.fault_dear;
7924bd41 1104 int gtlb_index;
475e7cdd 1105 gpa_t gpaddr;
bbf45ba5
HB		 1106 gfn_t gfn;
1107
bf7ca4bd 1108#ifdef CONFIG_KVM_E500V2
a4cd8b23
SW		 1109 if (!(vcpu->arch.shared->msr & MSR_PR) &&
1110 (eaddr & PAGE_MASK) == vcpu->arch.magic_page_ea) {
1111 kvmppc_map_magic(vcpu);
1112 kvmppc_account_exit(vcpu, DTLB_VIRT_MISS_EXITS);
1113 r = RESUME_GUEST;
1114
1115 break;
1116 }
1117#endif
1118
bbf45ba5 1119 /* Check the guest TLB. */
fa86b8dd 1120 gtlb_index = kvmppc_mmu_dtlb_index(vcpu, eaddr);
7924bd41 1121 if (gtlb_index < 0) {
bbf45ba5 1122 /* The guest didn't have a mapping for it. */
daf5e271
LY		 1123 kvmppc_core_queue_dtlb_miss(vcpu,
1124 vcpu->arch.fault_dear,
1125 vcpu->arch.fault_esr);
b52a638c 1126 kvmppc_mmu_dtlb_miss(vcpu);
7b701591 1127 kvmppc_account_exit(vcpu, DTLB_REAL_MISS_EXITS);
bbf45ba5
HB		 1128 r = RESUME_GUEST;
1129 break;
1130 }
1131
f1e89028
SW		 1132 idx = srcu_read_lock(&vcpu->kvm->srcu);
1133
be8d1cae 1134 gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr);
475e7cdd 1135 gfn = gpaddr >> PAGE_SHIFT;
bbf45ba5
HB		 1136
1137 if (kvm_is_visible_gfn(vcpu->kvm, gfn)) {
1138 /* The guest TLB had a mapping, but the shadow TLB
1139 * didn't, and it is RAM. This could be because:
1140 * a) the entry is mapping the host kernel, or
1141 * b) the guest used a large mapping which we're faking
1142 * Either way, we need to satisfy the fault without
1143 * invoking the guest. */
58a96214 1144 kvmppc_mmu_map(vcpu, eaddr, gpaddr, gtlb_index);
7b701591 1145 kvmppc_account_exit(vcpu, DTLB_VIRT_MISS_EXITS);
bbf45ba5
HB		 1146 r = RESUME_GUEST;
1147 } else {
1148 /* Guest has mapped and accessed a page which is not
1149 * actually RAM. */
475e7cdd 1150 vcpu->arch.paddr_accessed = gpaddr;
6020c0f6 1151 vcpu->arch.vaddr_accessed = eaddr;
bbf45ba5 1152 r = kvmppc_emulate_mmio(run, vcpu);
7b701591 1153 kvmppc_account_exit(vcpu, MMIO_EXITS);
bbf45ba5
HB		 1154 }
1155
f1e89028 1156 srcu_read_unlock(&vcpu->kvm->srcu, idx);
bbf45ba5
HB		 1157 break;
1158 }
1159
1160 case BOOKE_INTERRUPT_ITLB_MISS: {
bbf45ba5 1161 unsigned long eaddr = vcpu->arch.pc;
89168618 1162 gpa_t gpaddr;
bbf45ba5 1163 gfn_t gfn;
7924bd41 1164 int gtlb_index;
bbf45ba5
HB		 1165
1166 r = RESUME_GUEST;
1167
1168 /* Check the guest TLB. */
fa86b8dd 1169 gtlb_index = kvmppc_mmu_itlb_index(vcpu, eaddr);
7924bd41 1170 if (gtlb_index < 0) {
bbf45ba5 1171 /* The guest didn't have a mapping for it. */
d4cf3892 1172 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_ITLB_MISS);
b52a638c 1173 kvmppc_mmu_itlb_miss(vcpu);
7b701591 1174 kvmppc_account_exit(vcpu, ITLB_REAL_MISS_EXITS);
bbf45ba5
HB		 1175 break;
1176 }
1177
7b701591 1178 kvmppc_account_exit(vcpu, ITLB_VIRT_MISS_EXITS);
bbf45ba5 1179
f1e89028
SW		 1180 idx = srcu_read_lock(&vcpu->kvm->srcu);
1181
be8d1cae 1182 gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr);
89168618 1183 gfn = gpaddr >> PAGE_SHIFT;
bbf45ba5
HB		 1184
1185 if (kvm_is_visible_gfn(vcpu->kvm, gfn)) {
1186 /* The guest TLB had a mapping, but the shadow TLB
1187 * didn't. This could be because:
1188 * a) the entry is mapping the host kernel, or
1189 * b) the guest used a large mapping which we're faking
1190 * Either way, we need to satisfy the fault without
1191 * invoking the guest. */
58a96214 1192 kvmppc_mmu_map(vcpu, eaddr, gpaddr, gtlb_index);
bbf45ba5
HB		 1193 } else {
1194 /* Guest mapped and leaped at non-RAM! */
d4cf3892 1195 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_MACHINE_CHECK);
bbf45ba5
HB		 1196 }
1197
f1e89028 1198 srcu_read_unlock(&vcpu->kvm->srcu, idx);
bbf45ba5
HB		 1199 break;
1200 }
1201
6a0ab738 1202 case BOOKE_INTERRUPT_DEBUG: {
ce11e48b
BB		 1203 r = kvmppc_handle_debug(run, vcpu);
1204 if (r == RESUME_HOST)
1205 run->exit_reason = KVM_EXIT_DEBUG;
7b701591 1206 kvmppc_account_exit(vcpu, DEBUG_EXITS);
6a0ab738
HB		 1207 break;
1208 }
1209
bbf45ba5
HB		 1210 default:
1211 printk(KERN_EMERG "exit_nr %d\n", exit_nr);
1212 BUG();
1213 }
1214
a8e4ef84
AG		 1215 /*
1216 * To avoid clobbering exit_reason, only check for signals if we
1217 * aren't already exiting to userspace for some other reason.
1218 */
03660ba2
AG		 1219 if (!(r & RESUME_HOST)) {
1220 local_irq_disable();
7ee78855
AG		 1221 s = kvmppc_prepare_to_enter(vcpu);
1222 if (s <= 0) {
24afa37b 1223 local_irq_enable();
7ee78855 1224 r = (s << 2) | RESUME_HOST | (r & RESUME_FLAG_NV);
24afa37b 1225 } else {
5f1c248f 1226 kvmppc_fix_ee_before_entry();
03660ba2 1227 }
bbf45ba5
HB		 1228 }
1229
1230 return r;
1231}
1232
d26f22c9
BB		 1233static void kvmppc_set_tsr(struct kvm_vcpu *vcpu, u32 new_tsr)
1234{
1235 u32 old_tsr = vcpu->arch.tsr;
1236
1237 vcpu->arch.tsr = new_tsr;
1238
1239 if ((old_tsr ^ vcpu->arch.tsr) & (TSR_ENW | TSR_WIS))
1240 arm_next_watchdog(vcpu);
1241
1242 update_timer_ints(vcpu);
1243}
1244
bbf45ba5
HB		 1245/* Initial guest state: 16MB mapping 0 -> 0, PC = 0, MSR = 0, R1 = 16MB */
1246int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
1247{
082decf2 1248 int i;
af8f38b3 1249 int r;
082decf2 1250
bbf45ba5 1251 vcpu->arch.pc = 0;
b5904972 1252 vcpu->arch.shared->pir = vcpu->vcpu_id;
8e5b26b5 1253 kvmppc_set_gpr(vcpu, 1, (16<<20) - 8); /* -8 for the callee-save LR slot */
d30f6e48 1254 kvmppc_set_msr(vcpu, 0);
bbf45ba5 1255
d30f6e48 1256#ifndef CONFIG_KVM_BOOKE_HV
ce11e48b 1257 vcpu->arch.shadow_msr = MSR_USER | MSR_IS | MSR_DS;
49dd2c49 1258 vcpu->arch.shadow_pid = 1;
d30f6e48
SW		 1259 vcpu->arch.shared->msr = 0;
1260#endif
49dd2c49 1261
082decf2
HB		 1262 /* Eye-catching numbers so we know if the guest takes an interrupt
1263 * before it's programmed its own IVPR/IVORs. */
bbf45ba5 1264 vcpu->arch.ivpr = 0x55550000;
082decf2
HB		 1265 for (i = 0; i < BOOKE_IRQPRIO_MAX; i++)
1266 vcpu->arch.ivor[i] = 0x7700 | i * 4;
bbf45ba5 1267
73e75b41
HB		 1268 kvmppc_init_timing_stats(vcpu);
1269
af8f38b3
AG		 1270 r = kvmppc_core_vcpu_setup(vcpu);
1271 kvmppc_sanity_check(vcpu);
1272 return r;
bbf45ba5
HB		 1273}
1274
f61c94bb
BB		 1275int kvmppc_subarch_vcpu_init(struct kvm_vcpu *vcpu)
1276{
1277 /* setup watchdog timer once */
1278 spin_lock_init(&vcpu->arch.wdt_lock);
1279 setup_timer(&vcpu->arch.wdt_timer, kvmppc_watchdog_func,
1280 (unsigned long)vcpu);
1281
1282 return 0;
1283}
1284
1285void kvmppc_subarch_vcpu_uninit(struct kvm_vcpu *vcpu)
1286{
1287 del_timer_sync(&vcpu->arch.wdt_timer);
1288}
1289
bbf45ba5
HB		 1290int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1291{
1292 int i;
1293
1294 regs->pc = vcpu->arch.pc;
992b5b29 1295 regs->cr = kvmppc_get_cr(vcpu);
bbf45ba5
HB		 1296 regs->ctr = vcpu->arch.ctr;
1297 regs->lr = vcpu->arch.lr;
992b5b29 1298 regs->xer = kvmppc_get_xer(vcpu);
666e7252 1299 regs->msr = vcpu->arch.shared->msr;
de7906c3
AG		 1300 regs->srr0 = vcpu->arch.shared->srr0;
1301 regs->srr1 = vcpu->arch.shared->srr1;
bbf45ba5 1302 regs->pid = vcpu->arch.pid;
a73a9599
AG		 1303 regs->sprg0 = vcpu->arch.shared->sprg0;
1304 regs->sprg1 = vcpu->arch.shared->sprg1;
1305 regs->sprg2 = vcpu->arch.shared->sprg2;
1306 regs->sprg3 = vcpu->arch.shared->sprg3;
b5904972
SW		 1307 regs->sprg4 = vcpu->arch.shared->sprg4;
1308 regs->sprg5 = vcpu->arch.shared->sprg5;
1309 regs->sprg6 = vcpu->arch.shared->sprg6;
1310 regs->sprg7 = vcpu->arch.shared->sprg7;
bbf45ba5
HB		 1311
1312 for (i = 0; i < ARRAY_SIZE(regs->gpr); i++)
8e5b26b5 1313 regs->gpr[i] = kvmppc_get_gpr(vcpu, i);
bbf45ba5
HB		 1314
1315 return 0;
1316}
1317
1318int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1319{
1320 int i;
1321
1322 vcpu->arch.pc = regs->pc;
992b5b29 1323 kvmppc_set_cr(vcpu, regs->cr);
bbf45ba5
HB		 1324 vcpu->arch.ctr = regs->ctr;
1325 vcpu->arch.lr = regs->lr;
992b5b29 1326 kvmppc_set_xer(vcpu, regs->xer);
b8fd68ac 1327 kvmppc_set_msr(vcpu, regs->msr);
de7906c3
AG		 1328 vcpu->arch.shared->srr0 = regs->srr0;
1329 vcpu->arch.shared->srr1 = regs->srr1;
5ce941ee 1330 kvmppc_set_pid(vcpu, regs->pid);
a73a9599
AG		 1331 vcpu->arch.shared->sprg0 = regs->sprg0;
1332 vcpu->arch.shared->sprg1 = regs->sprg1;
1333 vcpu->arch.shared->sprg2 = regs->sprg2;
1334 vcpu->arch.shared->sprg3 = regs->sprg3;
b5904972
SW		 1335 vcpu->arch.shared->sprg4 = regs->sprg4;
1336 vcpu->arch.shared->sprg5 = regs->sprg5;
1337 vcpu->arch.shared->sprg6 = regs->sprg6;
1338 vcpu->arch.shared->sprg7 = regs->sprg7;
bbf45ba5 1339
8e5b26b5
AG		 1340 for (i = 0; i < ARRAY_SIZE(regs->gpr); i++)
1341 kvmppc_set_gpr(vcpu, i, regs->gpr[i]);
bbf45ba5
HB		 1342
1343 return 0;
1344}
1345
5ce941ee
SW		 1346static void get_sregs_base(struct kvm_vcpu *vcpu,
1347 struct kvm_sregs *sregs)
1348{
1349 u64 tb = get_tb();
1350
1351 sregs->u.e.features |= KVM_SREGS_E_BASE;
1352
1353 sregs->u.e.csrr0 = vcpu->arch.csrr0;
1354 sregs->u.e.csrr1 = vcpu->arch.csrr1;
1355 sregs->u.e.mcsr = vcpu->arch.mcsr;
d30f6e48
SW		 1356 sregs->u.e.esr = get_guest_esr(vcpu);
1357 sregs->u.e.dear = get_guest_dear(vcpu);
5ce941ee
SW		 1358 sregs->u.e.tsr = vcpu->arch.tsr;
1359 sregs->u.e.tcr = vcpu->arch.tcr;
1360 sregs->u.e.dec = kvmppc_get_dec(vcpu, tb);
1361 sregs->u.e.tb = tb;
1362 sregs->u.e.vrsave = vcpu->arch.vrsave;
1363}
1364
1365static int set_sregs_base(struct kvm_vcpu *vcpu,
1366 struct kvm_sregs *sregs)
1367{
1368 if (!(sregs->u.e.features & KVM_SREGS_E_BASE))
1369 return 0;
1370
1371 vcpu->arch.csrr0 = sregs->u.e.csrr0;
1372 vcpu->arch.csrr1 = sregs->u.e.csrr1;
1373 vcpu->arch.mcsr = sregs->u.e.mcsr;
d30f6e48
SW		 1374 set_guest_esr(vcpu, sregs->u.e.esr);
1375 set_guest_dear(vcpu, sregs->u.e.dear);
5ce941ee 1376 vcpu->arch.vrsave = sregs->u.e.vrsave;
dfd4d47e 1377 kvmppc_set_tcr(vcpu, sregs->u.e.tcr);
5ce941ee 1378
dfd4d47e 1379 if (sregs->u.e.update_special & KVM_SREGS_E_UPDATE_DEC) {
5ce941ee 1380 vcpu->arch.dec = sregs->u.e.dec;
dfd4d47e
SW		 1381 kvmppc_emulate_dec(vcpu);
1382 }
5ce941ee 1383
d26f22c9
BB		 1384 if (sregs->u.e.update_special & KVM_SREGS_E_UPDATE_TSR)
1385 kvmppc_set_tsr(vcpu, sregs->u.e.tsr);
5ce941ee
SW		 1386
1387 return 0;
1388}
1389
1390static void get_sregs_arch206(struct kvm_vcpu *vcpu,
1391 struct kvm_sregs *sregs)
1392{
1393 sregs->u.e.features |= KVM_SREGS_E_ARCH206;
1394
841741f2 1395 sregs->u.e.pir = vcpu->vcpu_id;
5ce941ee
SW		 1396 sregs->u.e.mcsrr0 = vcpu->arch.mcsrr0;
1397 sregs->u.e.mcsrr1 = vcpu->arch.mcsrr1;
1398 sregs->u.e.decar = vcpu->arch.decar;
1399 sregs->u.e.ivpr = vcpu->arch.ivpr;
1400}
1401
1402static int set_sregs_arch206(struct kvm_vcpu *vcpu,
1403 struct kvm_sregs *sregs)
1404{
1405 if (!(sregs->u.e.features & KVM_SREGS_E_ARCH206))
1406 return 0;
1407
841741f2 1408 if (sregs->u.e.pir != vcpu->vcpu_id)
5ce941ee
SW		 1409 return -EINVAL;
1410
1411 vcpu->arch.mcsrr0 = sregs->u.e.mcsrr0;
1412 vcpu->arch.mcsrr1 = sregs->u.e.mcsrr1;
1413 vcpu->arch.decar = sregs->u.e.decar;
1414 vcpu->arch.ivpr = sregs->u.e.ivpr;
1415
1416 return 0;
1417}
1418
3a167bea 1419int kvmppc_get_sregs_ivor(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
5ce941ee
SW		 1420{
1421 sregs->u.e.features |= KVM_SREGS_E_IVOR;
1422
1423 sregs->u.e.ivor_low[0] = vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL];
1424 sregs->u.e.ivor_low[1] = vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK];
1425 sregs->u.e.ivor_low[2] = vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE];
1426 sregs->u.e.ivor_low[3] = vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE];
1427 sregs->u.e.ivor_low[4] = vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL];
1428 sregs->u.e.ivor_low[5] = vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT];
1429 sregs->u.e.ivor_low[6] = vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM];
1430 sregs->u.e.ivor_low[7] = vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL];
1431 sregs->u.e.ivor_low[8] = vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL];
1432 sregs->u.e.ivor_low[9] = vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL];
1433 sregs->u.e.ivor_low[10] = vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER];
1434 sregs->u.e.ivor_low[11] = vcpu->arch.ivor[BOOKE_IRQPRIO_FIT];
1435 sregs->u.e.ivor_low[12] = vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG];
1436 sregs->u.e.ivor_low[13] = vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS];
1437 sregs->u.e.ivor_low[14] = vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS];
1438 sregs->u.e.ivor_low[15] = vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG];
3a167bea 1439 return 0;
5ce941ee
SW		 1440}
1441
1442int kvmppc_set_sregs_ivor(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
1443{
1444 if (!(sregs->u.e.features & KVM_SREGS_E_IVOR))
1445 return 0;
1446
1447 vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL] = sregs->u.e.ivor_low[0];
1448 vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK] = sregs->u.e.ivor_low[1];
1449 vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE] = sregs->u.e.ivor_low[2];
1450 vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE] = sregs->u.e.ivor_low[3];
1451 vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL] = sregs->u.e.ivor_low[4];
1452 vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT] = sregs->u.e.ivor_low[5];
1453 vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM] = sregs->u.e.ivor_low[6];
1454 vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL] = sregs->u.e.ivor_low[7];
1455 vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL] = sregs->u.e.ivor_low[8];
1456 vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL] = sregs->u.e.ivor_low[9];
1457 vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER] = sregs->u.e.ivor_low[10];
1458 vcpu->arch.ivor[BOOKE_IRQPRIO_FIT] = sregs->u.e.ivor_low[11];
1459 vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG] = sregs->u.e.ivor_low[12];
1460 vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS] = sregs->u.e.ivor_low[13];
1461 vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS] = sregs->u.e.ivor_low[14];
1462 vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG] = sregs->u.e.ivor_low[15];
1463
1464 return 0;
1465}
1466
bbf45ba5
HB		 1467int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
1468 struct kvm_sregs *sregs)
1469{
5ce941ee
SW		 1470 sregs->pvr = vcpu->arch.pvr;
1471
1472 get_sregs_base(vcpu, sregs);
1473 get_sregs_arch206(vcpu, sregs);
cbbc58d4 1474 return vcpu->kvm->arch.kvm_ops->get_sregs(vcpu, sregs);
bbf45ba5
HB		 1475}
1476
1477int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
1478 struct kvm_sregs *sregs)
1479{
5ce941ee
SW		 1480 int ret;
1481
1482 if (vcpu->arch.pvr != sregs->pvr)
1483 return -EINVAL;
1484
1485 ret = set_sregs_base(vcpu, sregs);
1486 if (ret < 0)
1487 return ret;
1488
1489 ret = set_sregs_arch206(vcpu, sregs);
1490 if (ret < 0)
1491 return ret;
1492
cbbc58d4 1493 return vcpu->kvm->arch.kvm_ops->set_sregs(vcpu, sregs);
bbf45ba5
HB		 1494}
1495
31f3438e
PM		 1496int kvm_vcpu_ioctl_get_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
1497{
35b299e2
MC		 1498 int r = 0;
1499 union kvmppc_one_reg val;
1500 int size;
35b299e2
MC		 1501
1502 size = one_reg_size(reg->id);
1503 if (size > sizeof(val))
1504 return -EINVAL;
6df8d3fc
BB		 1505
1506 switch (reg->id) {
1507 case KVM_REG_PPC_IAC1:
547465ef
BB		 1508 val = get_reg_val(reg->id, vcpu->arch.dbg_reg.iac1);
1509 break;
6df8d3fc 1510 case KVM_REG_PPC_IAC2:
547465ef
BB		 1511 val = get_reg_val(reg->id, vcpu->arch.dbg_reg.iac2);
1512 break;
1513#if CONFIG_PPC_ADV_DEBUG_IACS > 2
6df8d3fc 1514 case KVM_REG_PPC_IAC3:
547465ef
BB		 1515 val = get_reg_val(reg->id, vcpu->arch.dbg_reg.iac3);
1516 break;
35b299e2 1517 case KVM_REG_PPC_IAC4:
547465ef 1518 val = get_reg_val(reg->id, vcpu->arch.dbg_reg.iac4);
6df8d3fc 1519 break;
547465ef 1520#endif
6df8d3fc 1521 case KVM_REG_PPC_DAC1:
547465ef
BB		 1522 val = get_reg_val(reg->id, vcpu->arch.dbg_reg.dac1);
1523 break;
35b299e2 1524 case KVM_REG_PPC_DAC2:
547465ef 1525 val = get_reg_val(reg->id, vcpu->arch.dbg_reg.dac2);
6df8d3fc 1526 break;
324b3e63
AG		 1527 case KVM_REG_PPC_EPR: {
1528 u32 epr = get_guest_epr(vcpu);
35b299e2 1529 val = get_reg_val(reg->id, epr);
324b3e63
AG		 1530 break;
1531 }
352df1de
MC		 1532#if defined(CONFIG_64BIT)
1533 case KVM_REG_PPC_EPCR:
35b299e2 1534 val = get_reg_val(reg->id, vcpu->arch.epcr);
352df1de
MC		 1535 break;
1536#endif
78accda4 1537 case KVM_REG_PPC_TCR:
35b299e2 1538 val = get_reg_val(reg->id, vcpu->arch.tcr);
78accda4
BB		 1539 break;
1540 case KVM_REG_PPC_TSR:
35b299e2 1541 val = get_reg_val(reg->id, vcpu->arch.tsr);
78accda4 1542 break;
35b299e2 1543 case KVM_REG_PPC_DEBUG_INST:
b12c7841 1544 val = get_reg_val(reg->id, KVMPPC_INST_EHPRIV_DEBUG);
8c32a2ea 1545 break;
8b75cbbe
PM		 1546 case KVM_REG_PPC_VRSAVE:
1547 val = get_reg_val(reg->id, vcpu->arch.vrsave);
8c32a2ea 1548 break;
6df8d3fc 1549 default:
cbbc58d4 1550 r = vcpu->kvm->arch.kvm_ops->get_one_reg(vcpu, reg->id, &val);
6df8d3fc
BB		 1551 break;
1552 }
35b299e2
MC		 1553
1554 if (r)
1555 return r;
1556
1557 if (copy_to_user((char __user *)(unsigned long)reg->addr, &val, size))
1558 r = -EFAULT;
1559
6df8d3fc 1560 return r;
31f3438e
PM		 1561}
1562
1563int kvm_vcpu_ioctl_set_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
1564{
35b299e2
MC		 1565 int r = 0;
1566 union kvmppc_one_reg val;
1567 int size;
35b299e2
MC		 1568
1569 size = one_reg_size(reg->id);
1570 if (size > sizeof(val))
1571 return -EINVAL;
1572
1573 if (copy_from_user(&val, (char __user *)(unsigned long)reg->addr, size))
1574 return -EFAULT;
6df8d3fc
BB		 1575
1576 switch (reg->id) {
1577 case KVM_REG_PPC_IAC1:
547465ef
BB		 1578 vcpu->arch.dbg_reg.iac1 = set_reg_val(reg->id, val);
1579 break;
6df8d3fc 1580 case KVM_REG_PPC_IAC2:
547465ef
BB		 1581 vcpu->arch.dbg_reg.iac2 = set_reg_val(reg->id, val);
1582 break;
1583#if CONFIG_PPC_ADV_DEBUG_IACS > 2
6df8d3fc 1584 case KVM_REG_PPC_IAC3:
547465ef
BB		 1585 vcpu->arch.dbg_reg.iac3 = set_reg_val(reg->id, val);
1586 break;
35b299e2 1587 case KVM_REG_PPC_IAC4:
547465ef 1588 vcpu->arch.dbg_reg.iac4 = set_reg_val(reg->id, val);
6df8d3fc 1589 break;
547465ef 1590#endif
6df8d3fc 1591 case KVM_REG_PPC_DAC1:
547465ef
BB		 1592 vcpu->arch.dbg_reg.dac1 = set_reg_val(reg->id, val);
1593 break;
35b299e2 1594 case KVM_REG_PPC_DAC2:
547465ef 1595 vcpu->arch.dbg_reg.dac2 = set_reg_val(reg->id, val);
6df8d3fc 1596 break;
324b3e63 1597 case KVM_REG_PPC_EPR: {
35b299e2
MC		 1598 u32 new_epr = set_reg_val(reg->id, val);
1599 kvmppc_set_epr(vcpu, new_epr);
324b3e63
AG		 1600 break;
1601 }
352df1de
MC		 1602#if defined(CONFIG_64BIT)
1603 case KVM_REG_PPC_EPCR: {
35b299e2
MC		 1604 u32 new_epcr = set_reg_val(reg->id, val);
1605 kvmppc_set_epcr(vcpu, new_epcr);
352df1de
MC		 1606 break;
1607 }
1608#endif
78accda4 1609 case KVM_REG_PPC_OR_TSR: {
35b299e2 1610 u32 tsr_bits = set_reg_val(reg->id, val);
78accda4
BB		 1611 kvmppc_set_tsr_bits(vcpu, tsr_bits);
1612 break;
1613 }
1614 case KVM_REG_PPC_CLEAR_TSR: {
35b299e2 1615 u32 tsr_bits = set_reg_val(reg->id, val);
78accda4
BB		 1616 kvmppc_clr_tsr_bits(vcpu, tsr_bits);
1617 break;
1618 }
1619 case KVM_REG_PPC_TSR: {
35b299e2 1620 u32 tsr = set_reg_val(reg->id, val);
78accda4
BB		 1621 kvmppc_set_tsr(vcpu, tsr);
1622 break;
1623 }
1624 case KVM_REG_PPC_TCR: {
35b299e2 1625 u32 tcr = set_reg_val(reg->id, val);
78accda4
BB		 1626 kvmppc_set_tcr(vcpu, tcr);
1627 break;
1628 }
8b75cbbe
PM		 1629 case KVM_REG_PPC_VRSAVE:
1630 vcpu->arch.vrsave = set_reg_val(reg->id, val);
1631 break;
6df8d3fc 1632 default:
cbbc58d4 1633 r = vcpu->kvm->arch.kvm_ops->set_one_reg(vcpu, reg->id, &val);
6df8d3fc
BB		 1634 break;
1635 }
35b299e2 1636
6df8d3fc 1637 return r;
31f3438e
PM		 1638}
1639
bbf45ba5
HB		 1640int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1641{
1642 return -ENOTSUPP;
1643}
1644
1645int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1646{
1647 return -ENOTSUPP;
1648}
1649
bbf45ba5
HB		 1650int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1651 struct kvm_translation *tr)
1652{
98001d8d
AK		 1653 int r;
1654
98001d8d 1655 r = kvmppc_core_vcpu_translate(vcpu, tr);
98001d8d 1656 return r;
bbf45ba5 1657}
d9fbd03d 1658
4e755758
AG		 1659int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
1660{
1661 return -ENOTSUPP;
1662}
1663
5587027c 1664void kvmppc_core_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
a66b48c3
PM		 1665 struct kvm_memory_slot *dont)
1666{
1667}
1668
5587027c 1669int kvmppc_core_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
a66b48c3
PM		 1670 unsigned long npages)
1671{
1672 return 0;
1673}
1674
f9e0554d 1675int kvmppc_core_prepare_memory_region(struct kvm *kvm,
a66b48c3 1676 struct kvm_memory_slot *memslot,
f9e0554d
PM		 1677 struct kvm_userspace_memory_region *mem)
1678{
1679 return 0;
1680}
1681
1682void kvmppc_core_commit_memory_region(struct kvm *kvm,
dfe49dbd 1683 struct kvm_userspace_memory_region *mem,
8482644a 1684 const struct kvm_memory_slot *old)
dfe49dbd
PM		 1685{
1686}
1687
1688void kvmppc_core_flush_memslot(struct kvm *kvm, struct kvm_memory_slot *memslot)
f9e0554d
PM		 1689{
1690}
1691
38f98824
MC		 1692void kvmppc_set_epcr(struct kvm_vcpu *vcpu, u32 new_epcr)
1693{
1694#if defined(CONFIG_64BIT)
1695 vcpu->arch.epcr = new_epcr;
1696#ifdef CONFIG_KVM_BOOKE_HV
1697 vcpu->arch.shadow_epcr &= ~SPRN_EPCR_GICM;
1698 if (vcpu->arch.epcr & SPRN_EPCR_ICM)
1699 vcpu->arch.shadow_epcr |= SPRN_EPCR_GICM;
1700#endif
1701#endif
1702}
1703
dfd4d47e
SW		 1704void kvmppc_set_tcr(struct kvm_vcpu *vcpu, u32 new_tcr)
1705{
1706 vcpu->arch.tcr = new_tcr;
f61c94bb 1707 arm_next_watchdog(vcpu);
dfd4d47e
SW		 1708 update_timer_ints(vcpu);
1709}
1710
1711void kvmppc_set_tsr_bits(struct kvm_vcpu *vcpu, u32 tsr_bits)
1712{
1713 set_bits(tsr_bits, &vcpu->arch.tsr);
1714 smp_wmb();
1715 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1716 kvm_vcpu_kick(vcpu);
1717}
1718
1719void kvmppc_clr_tsr_bits(struct kvm_vcpu *vcpu, u32 tsr_bits)
1720{
1721 clear_bits(tsr_bits, &vcpu->arch.tsr);
f61c94bb
BB		 1722
1723 /*
1724 * We may have stopped the watchdog due to
1725 * being stuck on final expiration.
1726 */
1727 if (tsr_bits & (TSR_ENW | TSR_WIS))
1728 arm_next_watchdog(vcpu);
1729
dfd4d47e
SW		 1730 update_timer_ints(vcpu);
1731}
1732
1733void kvmppc_decrementer_func(unsigned long data)
1734{
1735 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
1736
21bd000a
BB		 1737 if (vcpu->arch.tcr & TCR_ARE) {
1738 vcpu->arch.dec = vcpu->arch.decar;
1739 kvmppc_emulate_dec(vcpu);
1740 }
1741
dfd4d47e
SW		 1742 kvmppc_set_tsr_bits(vcpu, TSR_DIS);
1743}
1744
ce11e48b
BB		 1745static int kvmppc_booke_add_breakpoint(struct debug_reg *dbg_reg,
1746 uint64_t addr, int index)
1747{
1748 switch (index) {
1749 case 0:
1750 dbg_reg->dbcr0 |= DBCR0_IAC1;
1751 dbg_reg->iac1 = addr;
1752 break;
1753 case 1:
1754 dbg_reg->dbcr0 |= DBCR0_IAC2;
1755 dbg_reg->iac2 = addr;
1756 break;
1757#if CONFIG_PPC_ADV_DEBUG_IACS > 2
1758 case 2:
1759 dbg_reg->dbcr0 |= DBCR0_IAC3;
1760 dbg_reg->iac3 = addr;
1761 break;
1762 case 3:
1763 dbg_reg->dbcr0 |= DBCR0_IAC4;
1764 dbg_reg->iac4 = addr;
1765 break;
1766#endif
1767 default:
1768 return -EINVAL;
1769 }
1770
1771 dbg_reg->dbcr0 |= DBCR0_IDM;
1772 return 0;
1773}
1774
1775static int kvmppc_booke_add_watchpoint(struct debug_reg *dbg_reg, uint64_t addr,
1776 int type, int index)
1777{
1778 switch (index) {
1779 case 0:
1780 if (type & KVMPPC_DEBUG_WATCH_READ)
1781 dbg_reg->dbcr0 |= DBCR0_DAC1R;
1782 if (type & KVMPPC_DEBUG_WATCH_WRITE)
1783 dbg_reg->dbcr0 |= DBCR0_DAC1W;
1784 dbg_reg->dac1 = addr;
1785 break;
1786 case 1:
1787 if (type & KVMPPC_DEBUG_WATCH_READ)
1788 dbg_reg->dbcr0 |= DBCR0_DAC2R;
1789 if (type & KVMPPC_DEBUG_WATCH_WRITE)
1790 dbg_reg->dbcr0 |= DBCR0_DAC2W;
1791 dbg_reg->dac2 = addr;
1792 break;
1793 default:
1794 return -EINVAL;
1795 }
1796
1797 dbg_reg->dbcr0 |= DBCR0_IDM;
1798 return 0;
1799}
1800void kvm_guest_protect_msr(struct kvm_vcpu *vcpu, ulong prot_bitmap, bool set)
1801{
1802 /* XXX: Add similar MSR protection for BookE-PR */
1803#ifdef CONFIG_KVM_BOOKE_HV
1804 BUG_ON(prot_bitmap & ~(MSRP_UCLEP | MSRP_DEP | MSRP_PMMP));
1805 if (set) {
1806 if (prot_bitmap & MSR_UCLE)
1807 vcpu->arch.shadow_msrp |= MSRP_UCLEP;
1808 if (prot_bitmap & MSR_DE)
1809 vcpu->arch.shadow_msrp |= MSRP_DEP;
1810 if (prot_bitmap & MSR_PMM)
1811 vcpu->arch.shadow_msrp |= MSRP_PMMP;
1812 } else {
1813 if (prot_bitmap & MSR_UCLE)
1814 vcpu->arch.shadow_msrp &= ~MSRP_UCLEP;
1815 if (prot_bitmap & MSR_DE)
1816 vcpu->arch.shadow_msrp &= ~MSRP_DEP;
1817 if (prot_bitmap & MSR_PMM)
1818 vcpu->arch.shadow_msrp &= ~MSRP_PMMP;
1819 }
1820#endif
1821}
1822
1823int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
1824 struct kvm_guest_debug *dbg)
1825{
1826 struct debug_reg *dbg_reg;
1827 int n, b = 0, w = 0;
1828
1829 if (!(dbg->control & KVM_GUESTDBG_ENABLE)) {
1830 vcpu->arch.shadow_dbg_reg.dbcr0 = 0;
1831 vcpu->guest_debug = 0;
1832 kvm_guest_protect_msr(vcpu, MSR_DE, false);
1833 return 0;
1834 }
1835
1836 kvm_guest_protect_msr(vcpu, MSR_DE, true);
1837 vcpu->guest_debug = dbg->control;
1838 vcpu->arch.shadow_dbg_reg.dbcr0 = 0;
1839 /* Set DBCR0_EDM in guest visible DBCR0 register. */
1840 vcpu->arch.dbg_reg.dbcr0 = DBCR0_EDM;
1841
1842 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1843 vcpu->arch.shadow_dbg_reg.dbcr0 |= DBCR0_IDM | DBCR0_IC;
1844
1845 /* Code below handles only HW breakpoints */
1846 dbg_reg = &(vcpu->arch.shadow_dbg_reg);
1847
1848#ifdef CONFIG_KVM_BOOKE_HV
1849 /*
1850 * On BookE-HV (e500mc) the guest is always executed with MSR.GS=1
1851 * DBCR1 and DBCR2 are set to trigger debug events when MSR.PR is 0
1852 */
1853 dbg_reg->dbcr1 = 0;
1854 dbg_reg->dbcr2 = 0;
1855#else
1856 /*
1857 * On BookE-PR (e500v2) the guest is always executed with MSR.PR=1
1858 * We set DBCR1 and DBCR2 to only trigger debug events when MSR.PR
1859 * is set.
1860 */
1861 dbg_reg->dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | DBCR1_IAC3US |
1862 DBCR1_IAC4US;
1863 dbg_reg->dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
1864#endif
1865
1866 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1867 return 0;
1868
1869 for (n = 0; n < (KVMPPC_BOOKE_IAC_NUM + KVMPPC_BOOKE_DAC_NUM); n++) {
1870 uint64_t addr = dbg->arch.bp[n].addr;
1871 uint32_t type = dbg->arch.bp[n].type;
1872
1873 if (type == KVMPPC_DEBUG_NONE)
1874 continue;
1875
1876 if (type & !(KVMPPC_DEBUG_WATCH_READ |
1877 KVMPPC_DEBUG_WATCH_WRITE |
1878 KVMPPC_DEBUG_BREAKPOINT))
1879 return -EINVAL;
1880
1881 if (type & KVMPPC_DEBUG_BREAKPOINT) {
1882 /* Setting H/W breakpoint */
1883 if (kvmppc_booke_add_breakpoint(dbg_reg, addr, b++))
1884 return -EINVAL;
1885 } else {
1886 /* Setting H/W watchpoint */
1887 if (kvmppc_booke_add_watchpoint(dbg_reg, addr,
1888 type, w++))
1889 return -EINVAL;
1890 }
1891 }
1892
1893 return 0;
1894}
1895
94fa9d99
SW		 1896void kvmppc_booke_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1897{
a47d72f3 1898 vcpu->cpu = smp_processor_id();
d30f6e48 1899 current->thread.kvm_vcpu = vcpu;
94fa9d99
SW		 1900}
1901
1902void kvmppc_booke_vcpu_put(struct kvm_vcpu *vcpu)
1903{
d30f6e48 1904 current->thread.kvm_vcpu = NULL;
a47d72f3 1905 vcpu->cpu = -1;
ce11e48b
BB		 1906
1907 /* Clear pending debug event in DBSR */
1908 kvmppc_clear_dbsr();
94fa9d99
SW		 1909}
1910
3a167bea
AK		 1911void kvmppc_mmu_destroy(struct kvm_vcpu *vcpu)
1912{
cbbc58d4 1913 vcpu->kvm->arch.kvm_ops->mmu_destroy(vcpu);
3a167bea
AK		 1914}
1915
1916int kvmppc_core_init_vm(struct kvm *kvm)
1917{
cbbc58d4 1918 return kvm->arch.kvm_ops->init_vm(kvm);
3a167bea
AK		 1919}
1920
1921struct kvm_vcpu *kvmppc_core_vcpu_create(struct kvm *kvm, unsigned int id)
1922{
cbbc58d4 1923 return kvm->arch.kvm_ops->vcpu_create(kvm, id);
3a167bea
AK		 1924}
1925
1926void kvmppc_core_vcpu_free(struct kvm_vcpu *vcpu)
1927{
cbbc58d4 1928 vcpu->kvm->arch.kvm_ops->vcpu_free(vcpu);
3a167bea
AK		 1929}
1930
1931void kvmppc_core_destroy_vm(struct kvm *kvm)
1932{
cbbc58d4 1933 kvm->arch.kvm_ops->destroy_vm(kvm);
3a167bea
AK		 1934}
1935
1936void kvmppc_core_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1937{
cbbc58d4 1938 vcpu->kvm->arch.kvm_ops->vcpu_load(vcpu, cpu);
3a167bea
AK		 1939}
1940
1941void kvmppc_core_vcpu_put(struct kvm_vcpu *vcpu)
1942{
cbbc58d4 1943 vcpu->kvm->arch.kvm_ops->vcpu_put(vcpu);
94fa9d99
SW		 1944}
1945
2986b8c7 1946int __init kvmppc_booke_init(void)
d9fbd03d 1947{
d30f6e48 1948#ifndef CONFIG_KVM_BOOKE_HV
d9fbd03d 1949 unsigned long ivor[16];
1d542d9c 1950 unsigned long *handler = kvmppc_booke_handler_addr;
d9fbd03d 1951 unsigned long max_ivor = 0;
1d542d9c 1952 unsigned long handler_len;
d9fbd03d
HB		 1953 int i;
1954
1955 /* We install our own exception handlers by hijacking IVPR. IVPR must
1956 * be 16-bit aligned, so we need a 64KB allocation. */
1957 kvmppc_booke_handlers = __get_free_pages(GFP_KERNEL | __GFP_ZERO,
1958 VCPU_SIZE_ORDER);
1959 if (!kvmppc_booke_handlers)
1960 return -ENOMEM;
1961
1962 /* XXX make sure our handlers are smaller than Linux's */
1963
1964 /* Copy our interrupt handlers to match host IVORs. That way we don't
1965 * have to swap the IVORs on every guest/host transition. */
1966 ivor[0] = mfspr(SPRN_IVOR0);
1967 ivor[1] = mfspr(SPRN_IVOR1);
1968 ivor[2] = mfspr(SPRN_IVOR2);
1969 ivor[3] = mfspr(SPRN_IVOR3);
1970 ivor[4] = mfspr(SPRN_IVOR4);
1971 ivor[5] = mfspr(SPRN_IVOR5);
1972 ivor[6] = mfspr(SPRN_IVOR6);
1973 ivor[7] = mfspr(SPRN_IVOR7);
1974 ivor[8] = mfspr(SPRN_IVOR8);
1975 ivor[9] = mfspr(SPRN_IVOR9);
1976 ivor[10] = mfspr(SPRN_IVOR10);
1977 ivor[11] = mfspr(SPRN_IVOR11);
1978 ivor[12] = mfspr(SPRN_IVOR12);
1979 ivor[13] = mfspr(SPRN_IVOR13);
1980 ivor[14] = mfspr(SPRN_IVOR14);
1981 ivor[15] = mfspr(SPRN_IVOR15);
1982
1983 for (i = 0; i < 16; i++) {
1984 if (ivor[i] > max_ivor)
1d542d9c 1985 max_ivor = i;
d9fbd03d 1986
1d542d9c 1987 handler_len = handler[i + 1] - handler[i];
d9fbd03d 1988 memcpy((void *)kvmppc_booke_handlers + ivor[i],
1d542d9c 1989 (void *)handler[i], handler_len);
d9fbd03d 1990 }
1d542d9c
BB		 1991
1992 handler_len = handler[max_ivor + 1] - handler[max_ivor];
1993 flush_icache_range(kvmppc_booke_handlers, kvmppc_booke_handlers +
1994 ivor[max_ivor] + handler_len);
d30f6e48 1995#endif /* !BOOKE_HV */
db93f574 1996 return 0;
d9fbd03d
HB		 1997}
1998
db93f574 1999void __exit kvmppc_booke_exit(void)
d9fbd03d
HB		 2000{
2001 free_pages(kvmppc_booke_handlers, VCPU_SIZE_ORDER);
2002 kvm_exit();
2003}
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