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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500
[mirror_ubuntu-jammy-kernel.git] / arch / powerpc / kvm / e500_mmu.c
CommitLineData
d2912cb1 1// SPDX-License-Identifier: GPL-2.0-only
bc8080cb 2/*
b71c9e2f 3 * Copyright (C) 2008-2013 Freescale Semiconductor, Inc. All rights reserved.
bc8080cb
HB		 4 *
5 * Author: Yu Liu, yu.liu@freescale.com
73196cd3 6 * Scott Wood, scottwood@freescale.com
4f802fe9 7 * Ashish Kalra, ashish.kalra@freescale.com
73196cd3 8 * Varun Sethi, varun.sethi@freescale.com
b71c9e2f 9 * Alexander Graf, agraf@suse.de
bc8080cb
HB		 10 *
11 * Description:
12 * This file is based on arch/powerpc/kvm/44x_tlb.c,
13 * by Hollis Blanchard <hollisb@us.ibm.com>.
bc8080cb
HB		 14 */
15
0164c0f0 16#include <linux/kernel.h>
bc8080cb 17#include <linux/types.h>
5a0e3ad6 18#include <linux/slab.h>
bc8080cb
HB		 19#include <linux/string.h>
20#include <linux/kvm.h>
21#include <linux/kvm_host.h>
22#include <linux/highmem.h>
dc83b8bc
SW		 23#include <linux/log2.h>
24#include <linux/uaccess.h>
25#include <linux/sched.h>
26#include <linux/rwsem.h>
27#include <linux/vmalloc.h>
95325e6b 28#include <linux/hugetlb.h>
bc8080cb 29#include <asm/kvm_ppc.h>
bc8080cb 30
29a5a6f9 31#include "e500.h"
dba291f2 32#include "trace_booke.h"
49ea0695 33#include "timing.h"
b71c9e2f 34#include "e500_mmu_host.h"
bc8080cb 35
0164c0f0 36static inline unsigned int gtlb0_get_next_victim(
bc8080cb
HB		 37 struct kvmppc_vcpu_e500 *vcpu_e500)
38{
39 unsigned int victim;
40
08b7fa92 41 victim = vcpu_e500->gtlb_nv[0]++;
dc83b8bc 42 if (unlikely(vcpu_e500->gtlb_nv[0] >= vcpu_e500->gtlb_params[0].ways))
08b7fa92 43 vcpu_e500->gtlb_nv[0] = 0;
bc8080cb
HB		 44
45 return victim;
46}
47
0164c0f0
SW		 48static int tlb0_set_base(gva_t addr, int sets, int ways)
49{
50 int set_base;
51
52 set_base = (addr >> PAGE_SHIFT) & (sets - 1);
53 set_base *= ways;
54
55 return set_base;
56}
57
58static int gtlb0_set_base(struct kvmppc_vcpu_e500 *vcpu_e500, gva_t addr)
59{
dc83b8bc
SW		 60 return tlb0_set_base(addr, vcpu_e500->gtlb_params[0].sets,
61 vcpu_e500->gtlb_params[0].ways);
0164c0f0
SW		 62}
63
b5904972 64static unsigned int get_tlb_esel(struct kvm_vcpu *vcpu, int tlbsel)
0164c0f0 65{
b5904972
SW		 66 struct kvmppc_vcpu_e500 *vcpu_e500 = to_e500(vcpu);
67 int esel = get_tlb_esel_bit(vcpu);
0164c0f0
SW		 68
69 if (tlbsel == 0) {
dc83b8bc 70 esel &= vcpu_e500->gtlb_params[0].ways - 1;
b5904972 71 esel += gtlb0_set_base(vcpu_e500, vcpu->arch.shared->mas2);
0164c0f0 72 } else {
dc83b8bc 73 esel &= vcpu_e500->gtlb_params[tlbsel].entries - 1;
0164c0f0
SW		 74 }
75
76 return esel;
77}
78
bc8080cb
HB		 79/* Search the guest TLB for a matching entry. */
80static int kvmppc_e500_tlb_index(struct kvmppc_vcpu_e500 *vcpu_e500,
81 gva_t eaddr, int tlbsel, unsigned int pid, int as)
82{
dc83b8bc
SW		 83 int size = vcpu_e500->gtlb_params[tlbsel].entries;
84 unsigned int set_base, offset;
bc8080cb
HB		 85 int i;
86
1aee47a0 87 if (tlbsel == 0) {
0164c0f0 88 set_base = gtlb0_set_base(vcpu_e500, eaddr);
dc83b8bc 89 size = vcpu_e500->gtlb_params[0].ways;
1aee47a0 90 } else {
cc902ad4
BB		 91 if (eaddr < vcpu_e500->tlb1_min_eaddr ||
92 eaddr > vcpu_e500->tlb1_max_eaddr)
93 return -1;
1aee47a0
SW		 94 set_base = 0;
95 }
96
dc83b8bc
SW		 97 offset = vcpu_e500->gtlb_offset[tlbsel];
98
1aee47a0 99 for (i = 0; i < size; i++) {
dc83b8bc
SW		 100 struct kvm_book3e_206_tlb_entry *tlbe =
101 &vcpu_e500->gtlb_arch[offset + set_base + i];
bc8080cb
HB		 102 unsigned int tid;
103
104 if (eaddr < get_tlb_eaddr(tlbe))
105 continue;
106
107 if (eaddr > get_tlb_end(tlbe))
108 continue;
109
110 tid = get_tlb_tid(tlbe);
111 if (tid && (tid != pid))
112 continue;
113
114 if (!get_tlb_v(tlbe))
115 continue;
116
117 if (get_tlb_ts(tlbe) != as && as != -1)
118 continue;
119
1aee47a0 120 return set_base + i;
bc8080cb
HB		 121 }
122
123 return -1;
124}
125
bc8080cb 126static inline void kvmppc_e500_deliver_tlb_miss(struct kvm_vcpu *vcpu,
70713fe3 127 gva_t eaddr, int as)
bc8080cb
HB		 128{
129 struct kvmppc_vcpu_e500 *vcpu_e500 = to_e500(vcpu);
8fdd21a2 130 unsigned int victim, tsized;
bc8080cb
HB		 131 int tlbsel;
132
fb2838d4 133 /* since we only have two TLBs, only lower bit is used. */
b5904972 134 tlbsel = (vcpu->arch.shared->mas4 >> 28) & 0x1;
0164c0f0 135 victim = (tlbsel == 0) ? gtlb0_get_next_victim(vcpu_e500) : 0;
b5904972 136 tsized = (vcpu->arch.shared->mas4 >> 7) & 0x1f;
bc8080cb 137
b5904972 138 vcpu->arch.shared->mas0 = MAS0_TLBSEL(tlbsel) | MAS0_ESEL(victim)
08b7fa92 139 | MAS0_NV(vcpu_e500->gtlb_nv[tlbsel]);
b5904972 140 vcpu->arch.shared->mas1 = MAS1_VALID | (as ? MAS1_TS : 0)
8fdd21a2 141 | MAS1_TID(get_tlbmiss_tid(vcpu))
bc8080cb 142 | MAS1_TSIZE(tsized);
b5904972
SW		 143 vcpu->arch.shared->mas2 = (eaddr & MAS2_EPN)
144 | (vcpu->arch.shared->mas4 & MAS2_ATTRIB_MASK);
145 vcpu->arch.shared->mas7_3 &= MAS3_U0 | MAS3_U1 | MAS3_U2 | MAS3_U3;
146 vcpu->arch.shared->mas6 = (vcpu->arch.shared->mas6 & MAS6_SPID1)
bc8080cb
HB		 147 | (get_cur_pid(vcpu) << 16)
148 | (as ? MAS6_SAS : 0);
bc8080cb
HB		 149}
150
cc902ad4
BB		 151static void kvmppc_recalc_tlb1map_range(struct kvmppc_vcpu_e500 *vcpu_e500)
152{
153 int size = vcpu_e500->gtlb_params[1].entries;
154 unsigned int offset;
155 gva_t eaddr;
156 int i;
157
158 vcpu_e500->tlb1_min_eaddr = ~0UL;
159 vcpu_e500->tlb1_max_eaddr = 0;
160 offset = vcpu_e500->gtlb_offset[1];
161
162 for (i = 0; i < size; i++) {
163 struct kvm_book3e_206_tlb_entry *tlbe =
164 &vcpu_e500->gtlb_arch[offset + i];
165
166 if (!get_tlb_v(tlbe))
167 continue;
168
169 eaddr = get_tlb_eaddr(tlbe);
170 vcpu_e500->tlb1_min_eaddr =
171 min(vcpu_e500->tlb1_min_eaddr, eaddr);
172
173 eaddr = get_tlb_end(tlbe);
174 vcpu_e500->tlb1_max_eaddr =
175 max(vcpu_e500->tlb1_max_eaddr, eaddr);
176 }
177}
178
179static int kvmppc_need_recalc_tlb1map_range(struct kvmppc_vcpu_e500 *vcpu_e500,
180 struct kvm_book3e_206_tlb_entry *gtlbe)
181{
182 unsigned long start, end, size;
183
184 size = get_tlb_bytes(gtlbe);
185 start = get_tlb_eaddr(gtlbe) & ~(size - 1);
186 end = start + size - 1;
187
188 return vcpu_e500->tlb1_min_eaddr == start ||
189 vcpu_e500->tlb1_max_eaddr == end;
190}
191
192/* This function is supposed to be called for a adding a new valid tlb entry */
193static void kvmppc_set_tlb1map_range(struct kvm_vcpu *vcpu,
194 struct kvm_book3e_206_tlb_entry *gtlbe)
195{
196 unsigned long start, end, size;
197 struct kvmppc_vcpu_e500 *vcpu_e500 = to_e500(vcpu);
198
199 if (!get_tlb_v(gtlbe))
200 return;
201
202 size = get_tlb_bytes(gtlbe);
203 start = get_tlb_eaddr(gtlbe) & ~(size - 1);
204 end = start + size - 1;
205
206 vcpu_e500->tlb1_min_eaddr = min(vcpu_e500->tlb1_min_eaddr, start);
207 vcpu_e500->tlb1_max_eaddr = max(vcpu_e500->tlb1_max_eaddr, end);
208}
209
08b7fa92
LY		 210static inline int kvmppc_e500_gtlbe_invalidate(
211 struct kvmppc_vcpu_e500 *vcpu_e500,
212 int tlbsel, int esel)
bc8080cb 213{
dc83b8bc
SW		 214 struct kvm_book3e_206_tlb_entry *gtlbe =
215 get_entry(vcpu_e500, tlbsel, esel);
bc8080cb
HB		 216
217 if (unlikely(get_tlb_iprot(gtlbe)))
218 return -1;
219
cc902ad4
BB		 220 if (tlbsel == 1 && kvmppc_need_recalc_tlb1map_range(vcpu_e500, gtlbe))
221 kvmppc_recalc_tlb1map_range(vcpu_e500);
222
bc8080cb
HB		 223 gtlbe->mas1 = 0;
224
225 return 0;
226}
227
b0a1835d
LY		 228int kvmppc_e500_emul_mt_mmucsr0(struct kvmppc_vcpu_e500 *vcpu_e500, ulong value)
229{
230 int esel;
231
232 if (value & MMUCSR0_TLB0FI)
dc83b8bc 233 for (esel = 0; esel < vcpu_e500->gtlb_params[0].entries; esel++)
b0a1835d
LY		 234 kvmppc_e500_gtlbe_invalidate(vcpu_e500, 0, esel);
235 if (value & MMUCSR0_TLB1FI)
dc83b8bc 236 for (esel = 0; esel < vcpu_e500->gtlb_params[1].entries; esel++)
b0a1835d
LY		 237 kvmppc_e500_gtlbe_invalidate(vcpu_e500, 1, esel);
238
b9e3e208
AG		 239 /* Invalidate all host shadow mappings */
240 kvmppc_core_flush_tlb(&vcpu_e500->vcpu);
b0a1835d
LY		 241
242 return EMULATE_DONE;
243}
244
7cdd7a95 245int kvmppc_e500_emul_tlbivax(struct kvm_vcpu *vcpu, gva_t ea)
bc8080cb
HB		 246{
247 struct kvmppc_vcpu_e500 *vcpu_e500 = to_e500(vcpu);
248 unsigned int ia;
249 int esel, tlbsel;
bc8080cb
HB		 250
251 ia = (ea >> 2) & 0x1;
252
fb2838d4 253 /* since we only have two TLBs, only lower bit is used. */
bc8080cb
HB		 254 tlbsel = (ea >> 3) & 0x1;
255
256 if (ia) {
257 /* invalidate all entries */
dc83b8bc
SW		 258 for (esel = 0; esel < vcpu_e500->gtlb_params[tlbsel].entries;
259 esel++)
bc8080cb
HB		 260 kvmppc_e500_gtlbe_invalidate(vcpu_e500, tlbsel, esel);
261 } else {
262 ea &= 0xfffff000;
263 esel = kvmppc_e500_tlb_index(vcpu_e500, ea, tlbsel,
264 get_cur_pid(vcpu), -1);
265 if (esel >= 0)
266 kvmppc_e500_gtlbe_invalidate(vcpu_e500, tlbsel, esel);
267 }
268
b9e3e208
AG		 269 /* Invalidate all host shadow mappings */
270 kvmppc_core_flush_tlb(&vcpu_e500->vcpu);
bc8080cb
HB		 271
272 return EMULATE_DONE;
273}
274
ab9fc405 275static void tlbilx_all(struct kvmppc_vcpu_e500 *vcpu_e500, int tlbsel,
7cdd7a95 276 int pid, int type)
ab9fc405
SW		 277{
278 struct kvm_book3e_206_tlb_entry *tlbe;
279 int tid, esel;
280
281 /* invalidate all entries */
282 for (esel = 0; esel < vcpu_e500->gtlb_params[tlbsel].entries; esel++) {
283 tlbe = get_entry(vcpu_e500, tlbsel, esel);
284 tid = get_tlb_tid(tlbe);
7cdd7a95 285 if (type == 0 || tid == pid) {
ab9fc405
SW		 286 inval_gtlbe_on_host(vcpu_e500, tlbsel, esel);
287 kvmppc_e500_gtlbe_invalidate(vcpu_e500, tlbsel, esel);
288 }
289 }
290}
291
292static void tlbilx_one(struct kvmppc_vcpu_e500 *vcpu_e500, int pid,
7cdd7a95 293 gva_t ea)
ab9fc405
SW		 294{
295 int tlbsel, esel;
ab9fc405
SW		 296
297 for (tlbsel = 0; tlbsel < 2; tlbsel++) {
298 esel = kvmppc_e500_tlb_index(vcpu_e500, ea, tlbsel, pid, -1);
299 if (esel >= 0) {
300 inval_gtlbe_on_host(vcpu_e500, tlbsel, esel);
301 kvmppc_e500_gtlbe_invalidate(vcpu_e500, tlbsel, esel);
302 break;
303 }
304 }
305}
306
7cdd7a95 307int kvmppc_e500_emul_tlbilx(struct kvm_vcpu *vcpu, int type, gva_t ea)
ab9fc405
SW		 308{
309 struct kvmppc_vcpu_e500 *vcpu_e500 = to_e500(vcpu);
310 int pid = get_cur_spid(vcpu);
311
7cdd7a95
MC		 312 if (type == 0 || type == 1) {
313 tlbilx_all(vcpu_e500, 0, pid, type);
314 tlbilx_all(vcpu_e500, 1, pid, type);
315 } else if (type == 3) {
316 tlbilx_one(vcpu_e500, pid, ea);
ab9fc405
SW		 317 }
318
319 return EMULATE_DONE;
320}
321
bc8080cb
HB		 322int kvmppc_e500_emul_tlbre(struct kvm_vcpu *vcpu)
323{
324 struct kvmppc_vcpu_e500 *vcpu_e500 = to_e500(vcpu);
325 int tlbsel, esel;
dc83b8bc 326 struct kvm_book3e_206_tlb_entry *gtlbe;
bc8080cb 327
b5904972
SW		 328 tlbsel = get_tlb_tlbsel(vcpu);
329 esel = get_tlb_esel(vcpu, tlbsel);
bc8080cb 330
dc83b8bc 331 gtlbe = get_entry(vcpu_e500, tlbsel, esel);
b5904972
SW		 332 vcpu->arch.shared->mas0 &= ~MAS0_NV(~0);
333 vcpu->arch.shared->mas0 |= MAS0_NV(vcpu_e500->gtlb_nv[tlbsel]);
334 vcpu->arch.shared->mas1 = gtlbe->mas1;
335 vcpu->arch.shared->mas2 = gtlbe->mas2;
336 vcpu->arch.shared->mas7_3 = gtlbe->mas7_3;
bc8080cb
HB		 337
338 return EMULATE_DONE;
339}
340
7cdd7a95 341int kvmppc_e500_emul_tlbsx(struct kvm_vcpu *vcpu, gva_t ea)
bc8080cb
HB		 342{
343 struct kvmppc_vcpu_e500 *vcpu_e500 = to_e500(vcpu);
b5904972
SW		 344 int as = !!get_cur_sas(vcpu);
345 unsigned int pid = get_cur_spid(vcpu);
bc8080cb 346 int esel, tlbsel;
dc83b8bc 347 struct kvm_book3e_206_tlb_entry *gtlbe = NULL;
bc8080cb
HB		 348
349 for (tlbsel = 0; tlbsel < 2; tlbsel++) {
350 esel = kvmppc_e500_tlb_index(vcpu_e500, ea, tlbsel, pid, as);
351 if (esel >= 0) {
dc83b8bc 352 gtlbe = get_entry(vcpu_e500, tlbsel, esel);
bc8080cb
HB		 353 break;
354 }
355 }
356
357 if (gtlbe) {
303b7c97
SW		 358 esel &= vcpu_e500->gtlb_params[tlbsel].ways - 1;
359
b5904972 360 vcpu->arch.shared->mas0 = MAS0_TLBSEL(tlbsel) | MAS0_ESEL(esel)
08b7fa92 361 | MAS0_NV(vcpu_e500->gtlb_nv[tlbsel]);
b5904972
SW		 362 vcpu->arch.shared->mas1 = gtlbe->mas1;
363 vcpu->arch.shared->mas2 = gtlbe->mas2;
364 vcpu->arch.shared->mas7_3 = gtlbe->mas7_3;
bc8080cb
HB		 365 } else {
366 int victim;
367
fb2838d4 368 /* since we only have two TLBs, only lower bit is used. */
b5904972 369 tlbsel = vcpu->arch.shared->mas4 >> 28 & 0x1;
0164c0f0 370 victim = (tlbsel == 0) ? gtlb0_get_next_victim(vcpu_e500) : 0;
bc8080cb 371
b5904972
SW		 372 vcpu->arch.shared->mas0 = MAS0_TLBSEL(tlbsel)
373 | MAS0_ESEL(victim)
08b7fa92 374 | MAS0_NV(vcpu_e500->gtlb_nv[tlbsel]);
b5904972
SW		 375 vcpu->arch.shared->mas1 =
376 (vcpu->arch.shared->mas6 & MAS6_SPID0)
f5ffe330 377 | ((vcpu->arch.shared->mas6 & MAS6_SAS) ? MAS1_TS : 0)
b5904972
SW		 378 | (vcpu->arch.shared->mas4 & MAS4_TSIZED(~0));
379 vcpu->arch.shared->mas2 &= MAS2_EPN;
380 vcpu->arch.shared->mas2 |= vcpu->arch.shared->mas4 &
381 MAS2_ATTRIB_MASK;
382 vcpu->arch.shared->mas7_3 &= MAS3_U0 | MAS3_U1 |
383 MAS3_U2 | MAS3_U3;
bc8080cb
HB		 384 }
385
49ea0695 386 kvmppc_set_exit_type(vcpu, EMULATED_TLBSX_EXITS);
bc8080cb
HB		 387 return EMULATE_DONE;
388}
389
390int kvmppc_e500_emul_tlbwe(struct kvm_vcpu *vcpu)
391{
392 struct kvmppc_vcpu_e500 *vcpu_e500 = to_e500(vcpu);
9d98b3ff
AG		 393 struct kvm_book3e_206_tlb_entry *gtlbe;
394 int tlbsel, esel;
cc902ad4 395 int recal = 0;
f1e89028 396 int idx;
bc8080cb 397
b5904972
SW		 398 tlbsel = get_tlb_tlbsel(vcpu);
399 esel = get_tlb_esel(vcpu, tlbsel);
bc8080cb 400
dc83b8bc 401 gtlbe = get_entry(vcpu_e500, tlbsel, esel);
bc8080cb 402
cc902ad4 403 if (get_tlb_v(gtlbe)) {
0164c0f0 404 inval_gtlbe_on_host(vcpu_e500, tlbsel, esel);
cc902ad4
BB		 405 if ((tlbsel == 1) &&
406 kvmppc_need_recalc_tlb1map_range(vcpu_e500, gtlbe))
407 recal = 1;
408 }
bc8080cb 409
b5904972
SW		 410 gtlbe->mas1 = vcpu->arch.shared->mas1;
411 gtlbe->mas2 = vcpu->arch.shared->mas2;
9e2fa646
MC		 412 if (!(vcpu->arch.shared->msr & MSR_CM))
413 gtlbe->mas2 &= 0xffffffffUL;
b5904972 414 gtlbe->mas7_3 = vcpu->arch.shared->mas7_3;
bc8080cb 415
d37b1a03
LY		 416 trace_kvm_booke206_gtlb_write(vcpu->arch.shared->mas0, gtlbe->mas1,
417 gtlbe->mas2, gtlbe->mas7_3);
bc8080cb 418
cc902ad4
BB		 419 if (tlbsel == 1) {
420 /*
421 * If a valid tlb1 entry is overwritten then recalculate the
422 * min/max TLB1 map address range otherwise no need to look
423 * in tlb1 array.
424 */
425 if (recal)
426 kvmppc_recalc_tlb1map_range(vcpu_e500);
427 else
428 kvmppc_set_tlb1map_range(vcpu, gtlbe);
429 }
430
f1e89028
SW		 431 idx = srcu_read_lock(&vcpu->kvm->srcu);
432
bc8080cb
HB		 433 /* Invalidate shadow mappings for the about-to-be-clobbered TLBE. */
434 if (tlbe_is_host_safe(vcpu, gtlbe)) {
9d98b3ff
AG		 435 u64 eaddr = get_tlb_eaddr(gtlbe);
436 u64 raddr = get_tlb_raddr(gtlbe);
08b7fa92 437
9d98b3ff 438 if (tlbsel == 0) {
bc8080cb 439 gtlbe->mas1 &= ~MAS1_TSIZE(~0);
0cfb50e5 440 gtlbe->mas1 |= MAS1_TSIZE(BOOK3E_PAGESZ_4K);
bc8080cb 441 }
3bf3cdcc 442
9d98b3ff
AG		 443 /* Premap the faulting page */
444 kvmppc_mmu_map(vcpu, eaddr, raddr, index_of(tlbsel, esel));
bc8080cb
HB		 445 }
446
f1e89028
SW		 447 srcu_read_unlock(&vcpu->kvm->srcu, idx);
448
49ea0695 449 kvmppc_set_exit_type(vcpu, EMULATED_TLBWE_EXITS);
bc8080cb
HB		 450 return EMULATE_DONE;
451}
452
8fdd21a2
SW		 453static int kvmppc_e500_tlb_search(struct kvm_vcpu *vcpu,
454 gva_t eaddr, unsigned int pid, int as)
455{
456 struct kvmppc_vcpu_e500 *vcpu_e500 = to_e500(vcpu);
457 int esel, tlbsel;
458
459 for (tlbsel = 0; tlbsel < 2; tlbsel++) {
460 esel = kvmppc_e500_tlb_index(vcpu_e500, eaddr, tlbsel, pid, as);
461 if (esel >= 0)
462 return index_of(tlbsel, esel);
463 }
464
465 return -1;
466}
467
468/* 'linear_address' is actually an encoding of AS|PID|EADDR . */
469int kvmppc_core_vcpu_translate(struct kvm_vcpu *vcpu,
470 struct kvm_translation *tr)
471{
472 int index;
473 gva_t eaddr;
474 u8 pid;
475 u8 as;
476
477 eaddr = tr->linear_address;
478 pid = (tr->linear_address >> 32) & 0xff;
479 as = (tr->linear_address >> 40) & 0x1;
480
481 index = kvmppc_e500_tlb_search(vcpu, eaddr, pid, as);
482 if (index < 0) {
483 tr->valid = 0;
484 return 0;
485 }
486
487 tr->physical_address = kvmppc_mmu_xlate(vcpu, index, eaddr);
488 /* XXX what does "writeable" and "usermode" even mean? */
489 tr->valid = 1;
490
491 return 0;
492}
493
494
bc8080cb
HB		 495int kvmppc_mmu_itlb_index(struct kvm_vcpu *vcpu, gva_t eaddr)
496{
666e7252 497 unsigned int as = !!(vcpu->arch.shared->msr & MSR_IS);
bc8080cb
HB		 498
499 return kvmppc_e500_tlb_search(vcpu, eaddr, get_cur_pid(vcpu), as);
500}
501
502int kvmppc_mmu_dtlb_index(struct kvm_vcpu *vcpu, gva_t eaddr)
503{
666e7252 504 unsigned int as = !!(vcpu->arch.shared->msr & MSR_DS);
bc8080cb
HB		 505
506 return kvmppc_e500_tlb_search(vcpu, eaddr, get_cur_pid(vcpu), as);
507}
508
509void kvmppc_mmu_itlb_miss(struct kvm_vcpu *vcpu)
510{
666e7252 511 unsigned int as = !!(vcpu->arch.shared->msr & MSR_IS);
bc8080cb 512
173c520a 513 kvmppc_e500_deliver_tlb_miss(vcpu, vcpu->arch.regs.nip, as);
bc8080cb
HB		 514}
515
516void kvmppc_mmu_dtlb_miss(struct kvm_vcpu *vcpu)
517{
666e7252 518 unsigned int as = !!(vcpu->arch.shared->msr & MSR_DS);
bc8080cb
HB		 519
520 kvmppc_e500_deliver_tlb_miss(vcpu, vcpu->arch.fault_dear, as);
521}
522
523gpa_t kvmppc_mmu_xlate(struct kvm_vcpu *vcpu, unsigned int index,
524 gva_t eaddr)
525{
526 struct kvmppc_vcpu_e500 *vcpu_e500 = to_e500(vcpu);
dc83b8bc
SW		 527 struct kvm_book3e_206_tlb_entry *gtlbe;
528 u64 pgmask;
529
530 gtlbe = get_entry(vcpu_e500, tlbsel_of(index), esel_of(index));
531 pgmask = get_tlb_bytes(gtlbe) - 1;
bc8080cb
HB		 532
533 return get_tlb_raddr(gtlbe) | (eaddr & pgmask);
534}
535
3a167bea 536void kvmppc_mmu_destroy_e500(struct kvm_vcpu *vcpu)
bc8080cb 537{
bc8080cb
HB		 538}
539
862d31f7
AG		 540/*****************************************/
541
dc83b8bc
SW		 542static void free_gtlb(struct kvmppc_vcpu_e500 *vcpu_e500)
543{
544 int i;
545
483ba97c 546 kvmppc_core_flush_tlb(&vcpu_e500->vcpu);
4f802fe9 547 kfree(vcpu_e500->g2h_tlb1_map);
dc83b8bc
SW		 548 kfree(vcpu_e500->gtlb_priv[0]);
549 kfree(vcpu_e500->gtlb_priv[1]);
550
551 if (vcpu_e500->shared_tlb_pages) {
552 vfree((void *)(round_down((uintptr_t)vcpu_e500->gtlb_arch,
553 PAGE_SIZE)));
554
555 for (i = 0; i < vcpu_e500->num_shared_tlb_pages; i++) {
556 set_page_dirty_lock(vcpu_e500->shared_tlb_pages[i]);
557 put_page(vcpu_e500->shared_tlb_pages[i]);
558 }
559
560 vcpu_e500->num_shared_tlb_pages = 0;
adbb48a8
SW		 561
562 kfree(vcpu_e500->shared_tlb_pages);
dc83b8bc
SW		 563 vcpu_e500->shared_tlb_pages = NULL;
564 } else {
565 kfree(vcpu_e500->gtlb_arch);
566 }
567
568 vcpu_e500->gtlb_arch = NULL;
569}
570
8fdd21a2
SW		 571void kvmppc_get_sregs_e500_tlb(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
572{
573 sregs->u.e.mas0 = vcpu->arch.shared->mas0;
574 sregs->u.e.mas1 = vcpu->arch.shared->mas1;
575 sregs->u.e.mas2 = vcpu->arch.shared->mas2;
576 sregs->u.e.mas7_3 = vcpu->arch.shared->mas7_3;
577 sregs->u.e.mas4 = vcpu->arch.shared->mas4;
578 sregs->u.e.mas6 = vcpu->arch.shared->mas6;
579
580 sregs->u.e.mmucfg = vcpu->arch.mmucfg;
581 sregs->u.e.tlbcfg[0] = vcpu->arch.tlbcfg[0];
582 sregs->u.e.tlbcfg[1] = vcpu->arch.tlbcfg[1];
583 sregs->u.e.tlbcfg[2] = 0;
584 sregs->u.e.tlbcfg[3] = 0;
585}
586
587int kvmppc_set_sregs_e500_tlb(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
588{
589 if (sregs->u.e.features & KVM_SREGS_E_ARCH206_MMU) {
590 vcpu->arch.shared->mas0 = sregs->u.e.mas0;
591 vcpu->arch.shared->mas1 = sregs->u.e.mas1;
592 vcpu->arch.shared->mas2 = sregs->u.e.mas2;
593 vcpu->arch.shared->mas7_3 = sregs->u.e.mas7_3;
594 vcpu->arch.shared->mas4 = sregs->u.e.mas4;
595 vcpu->arch.shared->mas6 = sregs->u.e.mas6;
596 }
597
598 return 0;
599}
600
a85d2aa2
MC		 601int kvmppc_get_one_reg_e500_tlb(struct kvm_vcpu *vcpu, u64 id,
602 union kvmppc_one_reg *val)
603{
604 int r = 0;
605 long int i;
606
607 switch (id) {
608 case KVM_REG_PPC_MAS0:
609 *val = get_reg_val(id, vcpu->arch.shared->mas0);
610 break;
611 case KVM_REG_PPC_MAS1:
612 *val = get_reg_val(id, vcpu->arch.shared->mas1);
613 break;
614 case KVM_REG_PPC_MAS2:
615 *val = get_reg_val(id, vcpu->arch.shared->mas2);
616 break;
617 case KVM_REG_PPC_MAS7_3:
618 *val = get_reg_val(id, vcpu->arch.shared->mas7_3);
619 break;
620 case KVM_REG_PPC_MAS4:
621 *val = get_reg_val(id, vcpu->arch.shared->mas4);
622 break;
623 case KVM_REG_PPC_MAS6:
624 *val = get_reg_val(id, vcpu->arch.shared->mas6);
625 break;
626 case KVM_REG_PPC_MMUCFG:
627 *val = get_reg_val(id, vcpu->arch.mmucfg);
628 break;
9a6061d7
MC		 629 case KVM_REG_PPC_EPTCFG:
630 *val = get_reg_val(id, vcpu->arch.eptcfg);
631 break;
a85d2aa2
MC		 632 case KVM_REG_PPC_TLB0CFG:
633 case KVM_REG_PPC_TLB1CFG:
634 case KVM_REG_PPC_TLB2CFG:
635 case KVM_REG_PPC_TLB3CFG:
636 i = id - KVM_REG_PPC_TLB0CFG;
637 *val = get_reg_val(id, vcpu->arch.tlbcfg[i]);
638 break;
307d9008
MC		 639 case KVM_REG_PPC_TLB0PS:
640 case KVM_REG_PPC_TLB1PS:
641 case KVM_REG_PPC_TLB2PS:
642 case KVM_REG_PPC_TLB3PS:
643 i = id - KVM_REG_PPC_TLB0PS;
644 *val = get_reg_val(id, vcpu->arch.tlbps[i]);
645 break;
a85d2aa2
MC		 646 default:
647 r = -EINVAL;
648 break;
649 }
650
651 return r;
652}
653
654int kvmppc_set_one_reg_e500_tlb(struct kvm_vcpu *vcpu, u64 id,
655 union kvmppc_one_reg *val)
656{
657 int r = 0;
658 long int i;
659
660 switch (id) {
661 case KVM_REG_PPC_MAS0:
662 vcpu->arch.shared->mas0 = set_reg_val(id, *val);
663 break;
664 case KVM_REG_PPC_MAS1:
665 vcpu->arch.shared->mas1 = set_reg_val(id, *val);
666 break;
667 case KVM_REG_PPC_MAS2:
668 vcpu->arch.shared->mas2 = set_reg_val(id, *val);
669 break;
670 case KVM_REG_PPC_MAS7_3:
671 vcpu->arch.shared->mas7_3 = set_reg_val(id, *val);
672 break;
673 case KVM_REG_PPC_MAS4:
674 vcpu->arch.shared->mas4 = set_reg_val(id, *val);
675 break;
676 case KVM_REG_PPC_MAS6:
677 vcpu->arch.shared->mas6 = set_reg_val(id, *val);
678 break;
679 /* Only allow MMU registers to be set to the config supported by KVM */
680 case KVM_REG_PPC_MMUCFG: {
681 u32 reg = set_reg_val(id, *val);
682 if (reg != vcpu->arch.mmucfg)
683 r = -EINVAL;
684 break;
685 }
9a6061d7
MC		 686 case KVM_REG_PPC_EPTCFG: {
687 u32 reg = set_reg_val(id, *val);
688 if (reg != vcpu->arch.eptcfg)
689 r = -EINVAL;
690 break;
691 }
a85d2aa2
MC		 692 case KVM_REG_PPC_TLB0CFG:
693 case KVM_REG_PPC_TLB1CFG:
694 case KVM_REG_PPC_TLB2CFG:
695 case KVM_REG_PPC_TLB3CFG: {
696 /* MMU geometry (N_ENTRY/ASSOC) can be set only using SW_TLB */
697 u32 reg = set_reg_val(id, *val);
698 i = id - KVM_REG_PPC_TLB0CFG;
699 if (reg != vcpu->arch.tlbcfg[i])
700 r = -EINVAL;
701 break;
702 }
307d9008
MC		 703 case KVM_REG_PPC_TLB0PS:
704 case KVM_REG_PPC_TLB1PS:
705 case KVM_REG_PPC_TLB2PS:
706 case KVM_REG_PPC_TLB3PS: {
707 u32 reg = set_reg_val(id, *val);
708 i = id - KVM_REG_PPC_TLB0PS;
709 if (reg != vcpu->arch.tlbps[i])
710 r = -EINVAL;
711 break;
712 }
a85d2aa2
MC		 713 default:
714 r = -EINVAL;
715 break;
716 }
717
718 return r;
719}
720
8893a188
MC		 721static int vcpu_mmu_geometry_update(struct kvm_vcpu *vcpu,
722 struct kvm_book3e_206_tlb_params *params)
723{
724 vcpu->arch.tlbcfg[0] &= ~(TLBnCFG_N_ENTRY | TLBnCFG_ASSOC);
725 if (params->tlb_sizes[0] <= 2048)
726 vcpu->arch.tlbcfg[0] |= params->tlb_sizes[0];
727 vcpu->arch.tlbcfg[0] |= params->tlb_ways[0] << TLBnCFG_ASSOC_SHIFT;
728
729 vcpu->arch.tlbcfg[1] &= ~(TLBnCFG_N_ENTRY | TLBnCFG_ASSOC);
730 vcpu->arch.tlbcfg[1] |= params->tlb_sizes[1];
731 vcpu->arch.tlbcfg[1] |= params->tlb_ways[1] << TLBnCFG_ASSOC_SHIFT;
732 return 0;
733}
734
dc83b8bc
SW		 735int kvm_vcpu_ioctl_config_tlb(struct kvm_vcpu *vcpu,
736 struct kvm_config_tlb *cfg)
737{
738 struct kvmppc_vcpu_e500 *vcpu_e500 = to_e500(vcpu);
739 struct kvm_book3e_206_tlb_params params;
740 char *virt;
741 struct page **pages;
742 struct tlbe_priv *privs[2] = {};
cfb60813 743 u64 *g2h_bitmap;
dc83b8bc
SW		 744 size_t array_len;
745 u32 sets;
746 int num_pages, ret, i;
747
748 if (cfg->mmu_type != KVM_MMU_FSL_BOOKE_NOHV)
749 return -EINVAL;
750
751 if (copy_from_user(&params, (void __user *)(uintptr_t)cfg->params,
752 sizeof(params)))
753 return -EFAULT;
754
755 if (params.tlb_sizes[1] > 64)
756 return -EINVAL;
757 if (params.tlb_ways[1] != params.tlb_sizes[1])
758 return -EINVAL;
759 if (params.tlb_sizes[2] != 0 || params.tlb_sizes[3] != 0)
760 return -EINVAL;
761 if (params.tlb_ways[2] != 0 || params.tlb_ways[3] != 0)
762 return -EINVAL;
763
764 if (!is_power_of_2(params.tlb_ways[0]))
765 return -EINVAL;
766
767 sets = params.tlb_sizes[0] >> ilog2(params.tlb_ways[0]);
768 if (!is_power_of_2(sets))
769 return -EINVAL;
770
771 array_len = params.tlb_sizes[0] + params.tlb_sizes[1];
772 array_len *= sizeof(struct kvm_book3e_206_tlb_entry);
773
774 if (cfg->array_len < array_len)
775 return -EINVAL;
776
777 num_pages = DIV_ROUND_UP(cfg->array + array_len - 1, PAGE_SIZE) -
778 cfg->array / PAGE_SIZE;
f3c0ce86 779 pages = kmalloc_array(num_pages, sizeof(*pages), GFP_KERNEL);
dc83b8bc
SW		 780 if (!pages)
781 return -ENOMEM;
782
73b0140b 783 ret = get_user_pages_fast(cfg->array, num_pages, FOLL_WRITE, pages);
dc83b8bc 784 if (ret < 0)
46d4e747 785 goto free_pages;
dc83b8bc
SW		 786
787 if (ret != num_pages) {
788 num_pages = ret;
789 ret = -EFAULT;
46d4e747 790 goto put_pages;
dc83b8bc
SW		 791 }
792
793 virt = vmap(pages, num_pages, VM_MAP, PAGE_KERNEL);
12ecd957
JL		 794 if (!virt) {
795 ret = -ENOMEM;
46d4e747 796 goto put_pages;
12ecd957 797 }
dc83b8bc 798
b0ac477b 799 privs[0] = kcalloc(params.tlb_sizes[0], sizeof(*privs[0]), GFP_KERNEL);
46d4e747
ME		 800 if (!privs[0]) {
801 ret = -ENOMEM;
802 goto put_pages;
803 }
804
b0ac477b 805 privs[1] = kcalloc(params.tlb_sizes[1], sizeof(*privs[1]), GFP_KERNEL);
46d4e747 806 if (!privs[1]) {
12ecd957 807 ret = -ENOMEM;
46d4e747 808 goto free_privs_first;
12ecd957 809 }
dc83b8bc 810
b0ac477b
ME		 811 g2h_bitmap = kcalloc(params.tlb_sizes[1],
812 sizeof(*g2h_bitmap),
813 GFP_KERNEL);
12ecd957
JL		 814 if (!g2h_bitmap) {
815 ret = -ENOMEM;
46d4e747 816 goto free_privs_second;
12ecd957 817 }
4f802fe9 818
dc83b8bc
SW		 819 free_gtlb(vcpu_e500);
820
821 vcpu_e500->gtlb_priv[0] = privs[0];
822 vcpu_e500->gtlb_priv[1] = privs[1];
4f802fe9 823 vcpu_e500->g2h_tlb1_map = g2h_bitmap;
dc83b8bc
SW		 824
825 vcpu_e500->gtlb_arch = (struct kvm_book3e_206_tlb_entry *)
826 (virt + (cfg->array & (PAGE_SIZE - 1)));
827
828 vcpu_e500->gtlb_params[0].entries = params.tlb_sizes[0];
829 vcpu_e500->gtlb_params[1].entries = params.tlb_sizes[1];
830
831 vcpu_e500->gtlb_offset[0] = 0;
832 vcpu_e500->gtlb_offset[1] = params.tlb_sizes[0];
833
8893a188
MC		 834 /* Update vcpu's MMU geometry based on SW_TLB input */
835 vcpu_mmu_geometry_update(vcpu, &params);
dc83b8bc
SW		 836
837 vcpu_e500->shared_tlb_pages = pages;
838 vcpu_e500->num_shared_tlb_pages = num_pages;
839
840 vcpu_e500->gtlb_params[0].ways = params.tlb_ways[0];
841 vcpu_e500->gtlb_params[0].sets = sets;
842
843 vcpu_e500->gtlb_params[1].ways = params.tlb_sizes[1];
844 vcpu_e500->gtlb_params[1].sets = 1;
845
cc902ad4 846 kvmppc_recalc_tlb1map_range(vcpu_e500);
dc83b8bc 847 return 0;
46d4e747 848 free_privs_second:
dc83b8bc 849 kfree(privs[1]);
46d4e747
ME		 850 free_privs_first:
851 kfree(privs[0]);
852 put_pages:
dc83b8bc
SW		 853 for (i = 0; i < num_pages; i++)
854 put_page(pages[i]);
46d4e747 855 free_pages:
dc83b8bc
SW		 856 kfree(pages);
857 return ret;
858}
859
860int kvm_vcpu_ioctl_dirty_tlb(struct kvm_vcpu *vcpu,
861 struct kvm_dirty_tlb *dirty)
862{
863 struct kvmppc_vcpu_e500 *vcpu_e500 = to_e500(vcpu);
cc902ad4 864 kvmppc_recalc_tlb1map_range(vcpu_e500);
483ba97c 865 kvmppc_core_flush_tlb(vcpu);
dc83b8bc 866 return 0;
bc8080cb
HB		 867}
868
8893a188
MC		 869/* Vcpu's MMU default configuration */
870static int vcpu_mmu_init(struct kvm_vcpu *vcpu,
871 struct kvmppc_e500_tlb_params *params)
872{
873 /* Initialize RASIZE, PIDSIZE, NTLBS and MAVN fields with host values*/
874 vcpu->arch.mmucfg = mfspr(SPRN_MMUCFG) & ~MMUCFG_LPIDSIZE;
875
876 /* Initialize TLBnCFG fields with host values and SW_TLB geometry*/
877 vcpu->arch.tlbcfg[0] = mfspr(SPRN_TLB0CFG) &
878 ~(TLBnCFG_N_ENTRY | TLBnCFG_ASSOC);
879 vcpu->arch.tlbcfg[0] |= params[0].entries;
880 vcpu->arch.tlbcfg[0] |= params[0].ways << TLBnCFG_ASSOC_SHIFT;
881
882 vcpu->arch.tlbcfg[1] = mfspr(SPRN_TLB1CFG) &
883 ~(TLBnCFG_N_ENTRY | TLBnCFG_ASSOC);
884 vcpu->arch.tlbcfg[1] |= params[1].entries;
885 vcpu->arch.tlbcfg[1] |= params[1].ways << TLBnCFG_ASSOC_SHIFT;
886
307d9008
MC		 887 if (has_feature(vcpu, VCPU_FTR_MMU_V2)) {
888 vcpu->arch.tlbps[0] = mfspr(SPRN_TLB0PS);
889 vcpu->arch.tlbps[1] = mfspr(SPRN_TLB1PS);
9a6061d7 890
5b215010
MC		 891 vcpu->arch.mmucfg &= ~MMUCFG_LRAT;
892
9a6061d7
MC		 893 /* Guest mmu emulation currently doesn't handle E.PT */
894 vcpu->arch.eptcfg = 0;
5b215010
MC		 895 vcpu->arch.tlbcfg[0] &= ~TLBnCFG_PT;
896 vcpu->arch.tlbcfg[1] &= ~TLBnCFG_IND;
307d9008
MC		 897 }
898
8893a188
MC		 899 return 0;
900}
901
bc8080cb
HB		 902int kvmppc_e500_tlb_init(struct kvmppc_vcpu_e500 *vcpu_e500)
903{
8fdd21a2 904 struct kvm_vcpu *vcpu = &vcpu_e500->vcpu;
dc83b8bc 905
b71c9e2f 906 if (e500_mmu_host_init(vcpu_e500))
aad9e5ba 907 goto free_vcpu;
bc8080cb 908
dc83b8bc
SW		 909 vcpu_e500->gtlb_params[0].entries = KVM_E500_TLB0_SIZE;
910 vcpu_e500->gtlb_params[1].entries = KVM_E500_TLB1_SIZE;
bc8080cb 911
dc83b8bc
SW		 912 vcpu_e500->gtlb_params[0].ways = KVM_E500_TLB0_WAY_NUM;
913 vcpu_e500->gtlb_params[0].sets =
914 KVM_E500_TLB0_SIZE / KVM_E500_TLB0_WAY_NUM;
915
916 vcpu_e500->gtlb_params[1].ways = KVM_E500_TLB1_SIZE;
917 vcpu_e500->gtlb_params[1].sets = 1;
918
90235dc1
ME		 919 vcpu_e500->gtlb_arch = kmalloc_array(KVM_E500_TLB0_SIZE +
920 KVM_E500_TLB1_SIZE,
921 sizeof(*vcpu_e500->gtlb_arch),
922 GFP_KERNEL);
dc83b8bc
SW		 923 if (!vcpu_e500->gtlb_arch)
924 return -ENOMEM;
925
926 vcpu_e500->gtlb_offset[0] = 0;
927 vcpu_e500->gtlb_offset[1] = KVM_E500_TLB0_SIZE;
0164c0f0 928
b0ac477b
ME		 929 vcpu_e500->gtlb_priv[0] = kcalloc(vcpu_e500->gtlb_params[0].entries,
930 sizeof(struct tlbe_ref),
dc83b8bc 931 GFP_KERNEL);
0164c0f0 932 if (!vcpu_e500->gtlb_priv[0])
aad9e5ba 933 goto free_vcpu;
0164c0f0 934
b0ac477b
ME		 935 vcpu_e500->gtlb_priv[1] = kcalloc(vcpu_e500->gtlb_params[1].entries,
936 sizeof(struct tlbe_ref),
dc83b8bc 937 GFP_KERNEL);
0164c0f0 938 if (!vcpu_e500->gtlb_priv[1])
aad9e5ba 939 goto free_vcpu;
bc8080cb 940
b0ac477b
ME		 941 vcpu_e500->g2h_tlb1_map = kcalloc(vcpu_e500->gtlb_params[1].entries,
942 sizeof(*vcpu_e500->g2h_tlb1_map),
4f802fe9
SW		 943 GFP_KERNEL);
944 if (!vcpu_e500->g2h_tlb1_map)
aad9e5ba 945 goto free_vcpu;
4f802fe9 946
8893a188 947 vcpu_mmu_init(vcpu, vcpu_e500->gtlb_params);
da15bf43 948
cc902ad4 949 kvmppc_recalc_tlb1map_range(vcpu_e500);
bc8080cb 950 return 0;
aad9e5ba 951 free_vcpu:
dc83b8bc 952 free_gtlb(vcpu_e500);
bc8080cb
HB		 953 return -1;
954}
955
956void kvmppc_e500_tlb_uninit(struct kvmppc_vcpu_e500 *vcpu_e500)
957{
dc83b8bc 958 free_gtlb(vcpu_e500);
b71c9e2f 959 e500_mmu_host_uninit(vcpu_e500);
bc8080cb 960}
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