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Commit | Line | Data |
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bbf45ba5 HB |
1 | /* |
2 | * This program is free software; you can redistribute it and/or modify | |
3 | * it under the terms of the GNU General Public License, version 2, as | |
4 | * published by the Free Software Foundation. | |
5 | * | |
6 | * This program is distributed in the hope that it will be useful, | |
7 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
8 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
9 | * GNU General Public License for more details. | |
10 | * | |
11 | * You should have received a copy of the GNU General Public License | |
12 | * along with this program; if not, write to the Free Software | |
13 | * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. | |
14 | * | |
15 | * Copyright IBM Corp. 2007 | |
16 | * | |
17 | * Authors: Hollis Blanchard <hollisb@us.ibm.com> | |
18 | * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com> | |
19 | */ | |
20 | ||
21 | #include <linux/errno.h> | |
22 | #include <linux/err.h> | |
23 | #include <linux/kvm_host.h> | |
bbf45ba5 | 24 | #include <linux/vmalloc.h> |
544c6761 | 25 | #include <linux/hrtimer.h> |
174cd4b1 | 26 | #include <linux/sched/signal.h> |
bbf45ba5 | 27 | #include <linux/fs.h> |
5a0e3ad6 | 28 | #include <linux/slab.h> |
eb1e4f43 | 29 | #include <linux/file.h> |
cbbc58d4 | 30 | #include <linux/module.h> |
9576730d SW |
31 | #include <linux/irqbypass.h> |
32 | #include <linux/kvm_irqfd.h> | |
bbf45ba5 | 33 | #include <asm/cputable.h> |
7c0f6ba6 | 34 | #include <linux/uaccess.h> |
bbf45ba5 | 35 | #include <asm/kvm_ppc.h> |
83aae4a8 | 36 | #include <asm/tlbflush.h> |
371fefd6 | 37 | #include <asm/cputhreads.h> |
bd2be683 | 38 | #include <asm/irqflags.h> |
58ded420 | 39 | #include <asm/iommu.h> |
6f63e81b | 40 | #include <asm/switch_to.h> |
5af50993 BH |
41 | #include <asm/xive.h> |
42 | ||
73e75b41 | 43 | #include "timing.h" |
5efdb4be | 44 | #include "irq.h" |
fad7b9b5 | 45 | #include "../mm/mmu_decl.h" |
bbf45ba5 | 46 | |
46f43c6e MT |
47 | #define CREATE_TRACE_POINTS |
48 | #include "trace.h" | |
49 | ||
cbbc58d4 AK |
50 | struct kvmppc_ops *kvmppc_hv_ops; |
51 | EXPORT_SYMBOL_GPL(kvmppc_hv_ops); | |
52 | struct kvmppc_ops *kvmppc_pr_ops; | |
53 | EXPORT_SYMBOL_GPL(kvmppc_pr_ops); | |
54 | ||
3a167bea | 55 | |
bbf45ba5 HB |
56 | int kvm_arch_vcpu_runnable(struct kvm_vcpu *v) |
57 | { | |
9202e076 | 58 | return !!(v->arch.pending_exceptions) || |
dfd4d47e | 59 | v->requests; |
bbf45ba5 HB |
60 | } |
61 | ||
b6d33834 CD |
62 | int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) |
63 | { | |
64 | return 1; | |
65 | } | |
66 | ||
03d25c5b AG |
67 | /* |
68 | * Common checks before entering the guest world. Call with interrupts | |
69 | * disabled. | |
70 | * | |
7ee78855 AG |
71 | * returns: |
72 | * | |
73 | * == 1 if we're ready to go into guest state | |
74 | * <= 0 if we need to go back to the host with return value | |
03d25c5b AG |
75 | */ |
76 | int kvmppc_prepare_to_enter(struct kvm_vcpu *vcpu) | |
77 | { | |
6c85f52b SW |
78 | int r; |
79 | ||
80 | WARN_ON(irqs_disabled()); | |
81 | hard_irq_disable(); | |
03d25c5b | 82 | |
03d25c5b AG |
83 | while (true) { |
84 | if (need_resched()) { | |
85 | local_irq_enable(); | |
86 | cond_resched(); | |
6c85f52b | 87 | hard_irq_disable(); |
03d25c5b AG |
88 | continue; |
89 | } | |
90 | ||
91 | if (signal_pending(current)) { | |
7ee78855 AG |
92 | kvmppc_account_exit(vcpu, SIGNAL_EXITS); |
93 | vcpu->run->exit_reason = KVM_EXIT_INTR; | |
94 | r = -EINTR; | |
03d25c5b AG |
95 | break; |
96 | } | |
97 | ||
5bd1cf11 SW |
98 | vcpu->mode = IN_GUEST_MODE; |
99 | ||
100 | /* | |
101 | * Reading vcpu->requests must happen after setting vcpu->mode, | |
102 | * so we don't miss a request because the requester sees | |
103 | * OUTSIDE_GUEST_MODE and assumes we'll be checking requests | |
104 | * before next entering the guest (and thus doesn't IPI). | |
489153c7 LT |
105 | * This also orders the write to mode from any reads |
106 | * to the page tables done while the VCPU is running. | |
107 | * Please see the comment in kvm_flush_remote_tlbs. | |
5bd1cf11 | 108 | */ |
03d25c5b | 109 | smp_mb(); |
5bd1cf11 | 110 | |
03d25c5b AG |
111 | if (vcpu->requests) { |
112 | /* Make sure we process requests preemptable */ | |
113 | local_irq_enable(); | |
114 | trace_kvm_check_requests(vcpu); | |
7c973a2e | 115 | r = kvmppc_core_check_requests(vcpu); |
6c85f52b | 116 | hard_irq_disable(); |
7c973a2e AG |
117 | if (r > 0) |
118 | continue; | |
119 | break; | |
03d25c5b AG |
120 | } |
121 | ||
122 | if (kvmppc_core_prepare_to_enter(vcpu)) { | |
123 | /* interrupts got enabled in between, so we | |
124 | are back at square 1 */ | |
125 | continue; | |
126 | } | |
127 | ||
6edaa530 | 128 | guest_enter_irqoff(); |
6c85f52b | 129 | return 1; |
03d25c5b AG |
130 | } |
131 | ||
6c85f52b SW |
132 | /* return to host */ |
133 | local_irq_enable(); | |
03d25c5b AG |
134 | return r; |
135 | } | |
2ba9f0d8 | 136 | EXPORT_SYMBOL_GPL(kvmppc_prepare_to_enter); |
03d25c5b | 137 | |
5deb8e7a AG |
138 | #if defined(CONFIG_PPC_BOOK3S_64) && defined(CONFIG_KVM_BOOK3S_PR_POSSIBLE) |
139 | static void kvmppc_swab_shared(struct kvm_vcpu *vcpu) | |
140 | { | |
141 | struct kvm_vcpu_arch_shared *shared = vcpu->arch.shared; | |
142 | int i; | |
143 | ||
144 | shared->sprg0 = swab64(shared->sprg0); | |
145 | shared->sprg1 = swab64(shared->sprg1); | |
146 | shared->sprg2 = swab64(shared->sprg2); | |
147 | shared->sprg3 = swab64(shared->sprg3); | |
148 | shared->srr0 = swab64(shared->srr0); | |
149 | shared->srr1 = swab64(shared->srr1); | |
150 | shared->dar = swab64(shared->dar); | |
151 | shared->msr = swab64(shared->msr); | |
152 | shared->dsisr = swab32(shared->dsisr); | |
153 | shared->int_pending = swab32(shared->int_pending); | |
154 | for (i = 0; i < ARRAY_SIZE(shared->sr); i++) | |
155 | shared->sr[i] = swab32(shared->sr[i]); | |
156 | } | |
157 | #endif | |
158 | ||
2a342ed5 AG |
159 | int kvmppc_kvm_pv(struct kvm_vcpu *vcpu) |
160 | { | |
161 | int nr = kvmppc_get_gpr(vcpu, 11); | |
162 | int r; | |
163 | unsigned long __maybe_unused param1 = kvmppc_get_gpr(vcpu, 3); | |
164 | unsigned long __maybe_unused param2 = kvmppc_get_gpr(vcpu, 4); | |
165 | unsigned long __maybe_unused param3 = kvmppc_get_gpr(vcpu, 5); | |
166 | unsigned long __maybe_unused param4 = kvmppc_get_gpr(vcpu, 6); | |
167 | unsigned long r2 = 0; | |
168 | ||
5deb8e7a | 169 | if (!(kvmppc_get_msr(vcpu) & MSR_SF)) { |
2a342ed5 AG |
170 | /* 32 bit mode */ |
171 | param1 &= 0xffffffff; | |
172 | param2 &= 0xffffffff; | |
173 | param3 &= 0xffffffff; | |
174 | param4 &= 0xffffffff; | |
175 | } | |
176 | ||
177 | switch (nr) { | |
fdcf8bd7 | 178 | case KVM_HCALL_TOKEN(KVM_HC_PPC_MAP_MAGIC_PAGE): |
5fc87407 | 179 | { |
5deb8e7a AG |
180 | #if defined(CONFIG_PPC_BOOK3S_64) && defined(CONFIG_KVM_BOOK3S_PR_POSSIBLE) |
181 | /* Book3S can be little endian, find it out here */ | |
182 | int shared_big_endian = true; | |
183 | if (vcpu->arch.intr_msr & MSR_LE) | |
184 | shared_big_endian = false; | |
185 | if (shared_big_endian != vcpu->arch.shared_big_endian) | |
186 | kvmppc_swab_shared(vcpu); | |
187 | vcpu->arch.shared_big_endian = shared_big_endian; | |
188 | #endif | |
189 | ||
f3383cf8 AG |
190 | if (!(param2 & MAGIC_PAGE_FLAG_NOT_MAPPED_NX)) { |
191 | /* | |
192 | * Older versions of the Linux magic page code had | |
193 | * a bug where they would map their trampoline code | |
194 | * NX. If that's the case, remove !PR NX capability. | |
195 | */ | |
196 | vcpu->arch.disable_kernel_nx = true; | |
197 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); | |
198 | } | |
199 | ||
200 | vcpu->arch.magic_page_pa = param1 & ~0xfffULL; | |
201 | vcpu->arch.magic_page_ea = param2 & ~0xfffULL; | |
5fc87407 | 202 | |
89b68c96 AG |
203 | #ifdef CONFIG_PPC_64K_PAGES |
204 | /* | |
205 | * Make sure our 4k magic page is in the same window of a 64k | |
206 | * page within the guest and within the host's page. | |
207 | */ | |
208 | if ((vcpu->arch.magic_page_pa & 0xf000) != | |
209 | ((ulong)vcpu->arch.shared & 0xf000)) { | |
210 | void *old_shared = vcpu->arch.shared; | |
211 | ulong shared = (ulong)vcpu->arch.shared; | |
212 | void *new_shared; | |
213 | ||
214 | shared &= PAGE_MASK; | |
215 | shared |= vcpu->arch.magic_page_pa & 0xf000; | |
216 | new_shared = (void*)shared; | |
217 | memcpy(new_shared, old_shared, 0x1000); | |
218 | vcpu->arch.shared = new_shared; | |
219 | } | |
220 | #endif | |
221 | ||
b5904972 | 222 | r2 = KVM_MAGIC_FEAT_SR | KVM_MAGIC_FEAT_MAS0_TO_SPRG7; |
7508e16c | 223 | |
fdcf8bd7 | 224 | r = EV_SUCCESS; |
5fc87407 AG |
225 | break; |
226 | } | |
fdcf8bd7 SY |
227 | case KVM_HCALL_TOKEN(KVM_HC_FEATURES): |
228 | r = EV_SUCCESS; | |
bf7ca4bd | 229 | #if defined(CONFIG_PPC_BOOK3S) || defined(CONFIG_KVM_E500V2) |
5fc87407 AG |
230 | r2 |= (1 << KVM_FEATURE_MAGIC_PAGE); |
231 | #endif | |
2a342ed5 AG |
232 | |
233 | /* Second return value is in r4 */ | |
2a342ed5 | 234 | break; |
9202e076 LYB |
235 | case EV_HCALL_TOKEN(EV_IDLE): |
236 | r = EV_SUCCESS; | |
237 | kvm_vcpu_block(vcpu); | |
72875d8a | 238 | kvm_clear_request(KVM_REQ_UNHALT, vcpu); |
9202e076 | 239 | break; |
2a342ed5 | 240 | default: |
fdcf8bd7 | 241 | r = EV_UNIMPLEMENTED; |
2a342ed5 AG |
242 | break; |
243 | } | |
244 | ||
7508e16c AG |
245 | kvmppc_set_gpr(vcpu, 4, r2); |
246 | ||
2a342ed5 AG |
247 | return r; |
248 | } | |
2ba9f0d8 | 249 | EXPORT_SYMBOL_GPL(kvmppc_kvm_pv); |
bbf45ba5 | 250 | |
af8f38b3 AG |
251 | int kvmppc_sanity_check(struct kvm_vcpu *vcpu) |
252 | { | |
253 | int r = false; | |
254 | ||
255 | /* We have to know what CPU to virtualize */ | |
256 | if (!vcpu->arch.pvr) | |
257 | goto out; | |
258 | ||
259 | /* PAPR only works with book3s_64 */ | |
260 | if ((vcpu->arch.cpu_type != KVM_CPU_3S_64) && vcpu->arch.papr_enabled) | |
261 | goto out; | |
262 | ||
af8f38b3 | 263 | /* HV KVM can only do PAPR mode for now */ |
a78b55d1 | 264 | if (!vcpu->arch.papr_enabled && is_kvmppc_hv_enabled(vcpu->kvm)) |
af8f38b3 | 265 | goto out; |
af8f38b3 | 266 | |
d30f6e48 SW |
267 | #ifdef CONFIG_KVM_BOOKE_HV |
268 | if (!cpu_has_feature(CPU_FTR_EMB_HV)) | |
269 | goto out; | |
270 | #endif | |
271 | ||
af8f38b3 AG |
272 | r = true; |
273 | ||
274 | out: | |
275 | vcpu->arch.sane = r; | |
276 | return r ? 0 : -EINVAL; | |
277 | } | |
2ba9f0d8 | 278 | EXPORT_SYMBOL_GPL(kvmppc_sanity_check); |
af8f38b3 | 279 | |
bbf45ba5 HB |
280 | int kvmppc_emulate_mmio(struct kvm_run *run, struct kvm_vcpu *vcpu) |
281 | { | |
282 | enum emulation_result er; | |
283 | int r; | |
284 | ||
d69614a2 | 285 | er = kvmppc_emulate_loadstore(vcpu); |
bbf45ba5 HB |
286 | switch (er) { |
287 | case EMULATE_DONE: | |
288 | /* Future optimization: only reload non-volatiles if they were | |
289 | * actually modified. */ | |
290 | r = RESUME_GUEST_NV; | |
291 | break; | |
51f04726 MC |
292 | case EMULATE_AGAIN: |
293 | r = RESUME_GUEST; | |
294 | break; | |
bbf45ba5 HB |
295 | case EMULATE_DO_MMIO: |
296 | run->exit_reason = KVM_EXIT_MMIO; | |
297 | /* We must reload nonvolatiles because "update" load/store | |
298 | * instructions modify register state. */ | |
299 | /* Future optimization: only reload non-volatiles if they were | |
300 | * actually modified. */ | |
301 | r = RESUME_HOST_NV; | |
302 | break; | |
303 | case EMULATE_FAIL: | |
51f04726 MC |
304 | { |
305 | u32 last_inst; | |
306 | ||
8d0eff63 | 307 | kvmppc_get_last_inst(vcpu, INST_GENERIC, &last_inst); |
bbf45ba5 | 308 | /* XXX Deliver Program interrupt to guest. */ |
51f04726 | 309 | pr_emerg("%s: emulation failed (%08x)\n", __func__, last_inst); |
bbf45ba5 HB |
310 | r = RESUME_HOST; |
311 | break; | |
51f04726 | 312 | } |
bbf45ba5 | 313 | default: |
5a33169e AG |
314 | WARN_ON(1); |
315 | r = RESUME_GUEST; | |
bbf45ba5 HB |
316 | } |
317 | ||
318 | return r; | |
319 | } | |
2ba9f0d8 | 320 | EXPORT_SYMBOL_GPL(kvmppc_emulate_mmio); |
bbf45ba5 | 321 | |
35c4a733 AG |
322 | int kvmppc_st(struct kvm_vcpu *vcpu, ulong *eaddr, int size, void *ptr, |
323 | bool data) | |
324 | { | |
c12fb43c | 325 | ulong mp_pa = vcpu->arch.magic_page_pa & KVM_PAM & PAGE_MASK; |
35c4a733 AG |
326 | struct kvmppc_pte pte; |
327 | int r; | |
328 | ||
329 | vcpu->stat.st++; | |
330 | ||
331 | r = kvmppc_xlate(vcpu, *eaddr, data ? XLATE_DATA : XLATE_INST, | |
332 | XLATE_WRITE, &pte); | |
333 | if (r < 0) | |
334 | return r; | |
335 | ||
336 | *eaddr = pte.raddr; | |
337 | ||
338 | if (!pte.may_write) | |
339 | return -EPERM; | |
340 | ||
c12fb43c AG |
341 | /* Magic page override */ |
342 | if (kvmppc_supports_magic_page(vcpu) && mp_pa && | |
343 | ((pte.raddr & KVM_PAM & PAGE_MASK) == mp_pa) && | |
344 | !(kvmppc_get_msr(vcpu) & MSR_PR)) { | |
345 | void *magic = vcpu->arch.shared; | |
346 | magic += pte.eaddr & 0xfff; | |
347 | memcpy(magic, ptr, size); | |
348 | return EMULATE_DONE; | |
349 | } | |
350 | ||
35c4a733 AG |
351 | if (kvm_write_guest(vcpu->kvm, pte.raddr, ptr, size)) |
352 | return EMULATE_DO_MMIO; | |
353 | ||
354 | return EMULATE_DONE; | |
355 | } | |
356 | EXPORT_SYMBOL_GPL(kvmppc_st); | |
357 | ||
358 | int kvmppc_ld(struct kvm_vcpu *vcpu, ulong *eaddr, int size, void *ptr, | |
359 | bool data) | |
360 | { | |
c12fb43c | 361 | ulong mp_pa = vcpu->arch.magic_page_pa & KVM_PAM & PAGE_MASK; |
35c4a733 | 362 | struct kvmppc_pte pte; |
35c4a733 AG |
363 | int rc; |
364 | ||
365 | vcpu->stat.ld++; | |
366 | ||
367 | rc = kvmppc_xlate(vcpu, *eaddr, data ? XLATE_DATA : XLATE_INST, | |
368 | XLATE_READ, &pte); | |
369 | if (rc) | |
370 | return rc; | |
371 | ||
372 | *eaddr = pte.raddr; | |
373 | ||
374 | if (!pte.may_read) | |
375 | return -EPERM; | |
376 | ||
377 | if (!data && !pte.may_execute) | |
378 | return -ENOEXEC; | |
379 | ||
c12fb43c AG |
380 | /* Magic page override */ |
381 | if (kvmppc_supports_magic_page(vcpu) && mp_pa && | |
382 | ((pte.raddr & KVM_PAM & PAGE_MASK) == mp_pa) && | |
383 | !(kvmppc_get_msr(vcpu) & MSR_PR)) { | |
384 | void *magic = vcpu->arch.shared; | |
385 | magic += pte.eaddr & 0xfff; | |
386 | memcpy(ptr, magic, size); | |
387 | return EMULATE_DONE; | |
388 | } | |
389 | ||
c45c5514 AG |
390 | if (kvm_read_guest(vcpu->kvm, pte.raddr, ptr, size)) |
391 | return EMULATE_DO_MMIO; | |
35c4a733 AG |
392 | |
393 | return EMULATE_DONE; | |
35c4a733 AG |
394 | } |
395 | EXPORT_SYMBOL_GPL(kvmppc_ld); | |
396 | ||
13a34e06 | 397 | int kvm_arch_hardware_enable(void) |
bbf45ba5 | 398 | { |
10474ae8 | 399 | return 0; |
bbf45ba5 HB |
400 | } |
401 | ||
bbf45ba5 HB |
402 | int kvm_arch_hardware_setup(void) |
403 | { | |
404 | return 0; | |
405 | } | |
406 | ||
bbf45ba5 HB |
407 | void kvm_arch_check_processor_compat(void *rtn) |
408 | { | |
9dd921cf | 409 | *(int *)rtn = kvmppc_core_check_processor_compat(); |
bbf45ba5 HB |
410 | } |
411 | ||
e08b9637 | 412 | int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) |
bbf45ba5 | 413 | { |
cbbc58d4 AK |
414 | struct kvmppc_ops *kvm_ops = NULL; |
415 | /* | |
416 | * if we have both HV and PR enabled, default is HV | |
417 | */ | |
418 | if (type == 0) { | |
419 | if (kvmppc_hv_ops) | |
420 | kvm_ops = kvmppc_hv_ops; | |
421 | else | |
422 | kvm_ops = kvmppc_pr_ops; | |
423 | if (!kvm_ops) | |
424 | goto err_out; | |
425 | } else if (type == KVM_VM_PPC_HV) { | |
426 | if (!kvmppc_hv_ops) | |
427 | goto err_out; | |
428 | kvm_ops = kvmppc_hv_ops; | |
429 | } else if (type == KVM_VM_PPC_PR) { | |
430 | if (!kvmppc_pr_ops) | |
431 | goto err_out; | |
432 | kvm_ops = kvmppc_pr_ops; | |
433 | } else | |
434 | goto err_out; | |
435 | ||
436 | if (kvm_ops->owner && !try_module_get(kvm_ops->owner)) | |
437 | return -ENOENT; | |
438 | ||
439 | kvm->arch.kvm_ops = kvm_ops; | |
f9e0554d | 440 | return kvmppc_core_init_vm(kvm); |
cbbc58d4 AK |
441 | err_out: |
442 | return -EINVAL; | |
bbf45ba5 HB |
443 | } |
444 | ||
235539b4 LC |
445 | bool kvm_arch_has_vcpu_debugfs(void) |
446 | { | |
447 | return false; | |
448 | } | |
449 | ||
450 | int kvm_arch_create_vcpu_debugfs(struct kvm_vcpu *vcpu) | |
451 | { | |
452 | return 0; | |
453 | } | |
454 | ||
d89f5eff | 455 | void kvm_arch_destroy_vm(struct kvm *kvm) |
bbf45ba5 HB |
456 | { |
457 | unsigned int i; | |
988a2cae | 458 | struct kvm_vcpu *vcpu; |
bbf45ba5 | 459 | |
e17769eb SW |
460 | #ifdef CONFIG_KVM_XICS |
461 | /* | |
462 | * We call kick_all_cpus_sync() to ensure that all | |
463 | * CPUs have executed any pending IPIs before we | |
464 | * continue and free VCPUs structures below. | |
465 | */ | |
466 | if (is_kvmppc_hv_enabled(kvm)) | |
467 | kick_all_cpus_sync(); | |
468 | #endif | |
469 | ||
988a2cae GN |
470 | kvm_for_each_vcpu(i, vcpu, kvm) |
471 | kvm_arch_vcpu_free(vcpu); | |
472 | ||
473 | mutex_lock(&kvm->lock); | |
474 | for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) | |
475 | kvm->vcpus[i] = NULL; | |
476 | ||
477 | atomic_set(&kvm->online_vcpus, 0); | |
f9e0554d PM |
478 | |
479 | kvmppc_core_destroy_vm(kvm); | |
480 | ||
988a2cae | 481 | mutex_unlock(&kvm->lock); |
cbbc58d4 AK |
482 | |
483 | /* drop the module reference */ | |
484 | module_put(kvm->arch.kvm_ops->owner); | |
bbf45ba5 HB |
485 | } |
486 | ||
784aa3d7 | 487 | int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) |
bbf45ba5 HB |
488 | { |
489 | int r; | |
7a58777a | 490 | /* Assume we're using HV mode when the HV module is loaded */ |
cbbc58d4 | 491 | int hv_enabled = kvmppc_hv_ops ? 1 : 0; |
bbf45ba5 | 492 | |
7a58777a AG |
493 | if (kvm) { |
494 | /* | |
495 | * Hooray - we know which VM type we're running on. Depend on | |
496 | * that rather than the guess above. | |
497 | */ | |
498 | hv_enabled = is_kvmppc_hv_enabled(kvm); | |
499 | } | |
500 | ||
bbf45ba5 | 501 | switch (ext) { |
5ce941ee SW |
502 | #ifdef CONFIG_BOOKE |
503 | case KVM_CAP_PPC_BOOKE_SREGS: | |
f61c94bb | 504 | case KVM_CAP_PPC_BOOKE_WATCHDOG: |
1c810636 | 505 | case KVM_CAP_PPC_EPR: |
5ce941ee | 506 | #else |
e15a1137 | 507 | case KVM_CAP_PPC_SEGSTATE: |
1022fc3d | 508 | case KVM_CAP_PPC_HIOR: |
930b412a | 509 | case KVM_CAP_PPC_PAPR: |
5ce941ee | 510 | #endif |
18978768 | 511 | case KVM_CAP_PPC_UNSET_IRQ: |
7b4203e8 | 512 | case KVM_CAP_PPC_IRQ_LEVEL: |
71fbfd5f | 513 | case KVM_CAP_ENABLE_CAP: |
699a0ea0 | 514 | case KVM_CAP_ENABLE_CAP_VM: |
e24ed81f | 515 | case KVM_CAP_ONE_REG: |
0e673fb6 | 516 | case KVM_CAP_IOEVENTFD: |
5df554ad | 517 | case KVM_CAP_DEVICE_CTRL: |
460df4c1 | 518 | case KVM_CAP_IMMEDIATE_EXIT: |
de56a948 PM |
519 | r = 1; |
520 | break; | |
de56a948 | 521 | case KVM_CAP_PPC_PAIRED_SINGLES: |
ad0a048b | 522 | case KVM_CAP_PPC_OSI: |
15711e9c | 523 | case KVM_CAP_PPC_GET_PVINFO: |
bf7ca4bd | 524 | #if defined(CONFIG_KVM_E500V2) || defined(CONFIG_KVM_E500MC) |
dc83b8bc | 525 | case KVM_CAP_SW_TLB: |
eb1e4f43 | 526 | #endif |
699cc876 | 527 | /* We support this only for PR */ |
cbbc58d4 | 528 | r = !hv_enabled; |
e15a1137 | 529 | break; |
699cc876 AK |
530 | #ifdef CONFIG_KVM_MPIC |
531 | case KVM_CAP_IRQ_MPIC: | |
532 | r = 1; | |
533 | break; | |
534 | #endif | |
535 | ||
f31e65e1 | 536 | #ifdef CONFIG_PPC_BOOK3S_64 |
54738c09 | 537 | case KVM_CAP_SPAPR_TCE: |
58ded420 | 538 | case KVM_CAP_SPAPR_TCE_64: |
121f80ba AK |
539 | /* fallthrough */ |
540 | case KVM_CAP_SPAPR_TCE_VFIO: | |
8e591cb7 | 541 | case KVM_CAP_PPC_RTAS: |
f2e91042 | 542 | case KVM_CAP_PPC_FIXUP_HCALL: |
699a0ea0 | 543 | case KVM_CAP_PPC_ENABLE_HCALL: |
5975a2e0 PM |
544 | #ifdef CONFIG_KVM_XICS |
545 | case KVM_CAP_IRQ_XICS: | |
546 | #endif | |
54738c09 DG |
547 | r = 1; |
548 | break; | |
a8acaece DG |
549 | |
550 | case KVM_CAP_PPC_ALLOC_HTAB: | |
551 | r = hv_enabled; | |
552 | break; | |
f31e65e1 | 553 | #endif /* CONFIG_PPC_BOOK3S_64 */ |
699cc876 | 554 | #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE |
371fefd6 | 555 | case KVM_CAP_PPC_SMT: |
45c940ba | 556 | r = 0; |
57900694 PM |
557 | if (kvm) { |
558 | if (kvm->arch.emul_smt_mode > 1) | |
559 | r = kvm->arch.emul_smt_mode; | |
560 | else | |
561 | r = kvm->arch.smt_mode; | |
562 | } else if (hv_enabled) { | |
45c940ba PM |
563 | if (cpu_has_feature(CPU_FTR_ARCH_300)) |
564 | r = 1; | |
565 | else | |
566 | r = threads_per_subcore; | |
567 | } | |
371fefd6 | 568 | break; |
2ed4f9dd PM |
569 | case KVM_CAP_PPC_SMT_POSSIBLE: |
570 | r = 1; | |
571 | if (hv_enabled) { | |
572 | if (!cpu_has_feature(CPU_FTR_ARCH_300)) | |
573 | r = ((threads_per_subcore << 1) - 1); | |
574 | else | |
575 | /* P9 can emulate dbells, so allow any mode */ | |
576 | r = 8 | 4 | 2 | 1; | |
577 | } | |
578 | break; | |
aa04b4cc | 579 | case KVM_CAP_PPC_RMA: |
c17b98cf | 580 | r = 0; |
aa04b4cc | 581 | break; |
e928e9cb ME |
582 | case KVM_CAP_PPC_HWRNG: |
583 | r = kvmppc_hwrng_present(); | |
584 | break; | |
c9270132 | 585 | case KVM_CAP_PPC_MMU_RADIX: |
8cf4ecc0 | 586 | r = !!(hv_enabled && radix_enabled()); |
c9270132 PM |
587 | break; |
588 | case KVM_CAP_PPC_MMU_HASH_V3: | |
468808bd | 589 | r = !!(hv_enabled && !radix_enabled() && |
c9270132 PM |
590 | cpu_has_feature(CPU_FTR_ARCH_300)); |
591 | break; | |
f4800b1f | 592 | #endif |
342d3db7 | 593 | case KVM_CAP_SYNC_MMU: |
699cc876 | 594 | #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE |
c17b98cf | 595 | r = hv_enabled; |
f4800b1f AG |
596 | #elif defined(KVM_ARCH_WANT_MMU_NOTIFIER) |
597 | r = 1; | |
598 | #else | |
599 | r = 0; | |
a2932923 | 600 | #endif |
699cc876 AK |
601 | break; |
602 | #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE | |
a2932923 | 603 | case KVM_CAP_PPC_HTAB_FD: |
cbbc58d4 | 604 | r = hv_enabled; |
a2932923 | 605 | break; |
de56a948 | 606 | #endif |
b5434032 ME |
607 | case KVM_CAP_NR_VCPUS: |
608 | /* | |
609 | * Recommending a number of CPUs is somewhat arbitrary; we | |
610 | * return the number of present CPUs for -HV (since a host | |
611 | * will have secondary threads "offline"), and for other KVM | |
612 | * implementations just count online CPUs. | |
613 | */ | |
cbbc58d4 | 614 | if (hv_enabled) |
699cc876 AK |
615 | r = num_present_cpus(); |
616 | else | |
617 | r = num_online_cpus(); | |
b5434032 | 618 | break; |
bfec5c2c ND |
619 | case KVM_CAP_NR_MEMSLOTS: |
620 | r = KVM_USER_MEM_SLOTS; | |
621 | break; | |
b5434032 ME |
622 | case KVM_CAP_MAX_VCPUS: |
623 | r = KVM_MAX_VCPUS; | |
624 | break; | |
5b74716e BH |
625 | #ifdef CONFIG_PPC_BOOK3S_64 |
626 | case KVM_CAP_PPC_GET_SMMU_INFO: | |
627 | r = 1; | |
628 | break; | |
d3695aa4 AK |
629 | case KVM_CAP_SPAPR_MULTITCE: |
630 | r = 1; | |
631 | break; | |
050f2339 | 632 | case KVM_CAP_SPAPR_RESIZE_HPT: |
bcd3bb63 PM |
633 | /* Disable this on POWER9 until code handles new HPTE format */ |
634 | r = !!hv_enabled && !cpu_has_feature(CPU_FTR_ARCH_300); | |
050f2339 | 635 | break; |
134764ed AP |
636 | #endif |
637 | #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE | |
638 | case KVM_CAP_PPC_FWNMI: | |
639 | r = hv_enabled; | |
640 | break; | |
5b74716e | 641 | #endif |
23528bb2 SB |
642 | case KVM_CAP_PPC_HTM: |
643 | r = cpu_has_feature(CPU_FTR_TM_COMP) && | |
644 | is_kvmppc_hv_enabled(kvm); | |
645 | break; | |
bbf45ba5 HB |
646 | default: |
647 | r = 0; | |
648 | break; | |
649 | } | |
650 | return r; | |
651 | ||
652 | } | |
653 | ||
654 | long kvm_arch_dev_ioctl(struct file *filp, | |
655 | unsigned int ioctl, unsigned long arg) | |
656 | { | |
657 | return -EINVAL; | |
658 | } | |
659 | ||
5587027c | 660 | void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, |
db3fe4eb TY |
661 | struct kvm_memory_slot *dont) |
662 | { | |
5587027c | 663 | kvmppc_core_free_memslot(kvm, free, dont); |
db3fe4eb TY |
664 | } |
665 | ||
5587027c AK |
666 | int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, |
667 | unsigned long npages) | |
db3fe4eb | 668 | { |
5587027c | 669 | return kvmppc_core_create_memslot(kvm, slot, npages); |
db3fe4eb TY |
670 | } |
671 | ||
f7784b8e | 672 | int kvm_arch_prepare_memory_region(struct kvm *kvm, |
462fce46 | 673 | struct kvm_memory_slot *memslot, |
09170a49 | 674 | const struct kvm_userspace_memory_region *mem, |
7b6195a9 | 675 | enum kvm_mr_change change) |
bbf45ba5 | 676 | { |
a66b48c3 | 677 | return kvmppc_core_prepare_memory_region(kvm, memslot, mem); |
bbf45ba5 HB |
678 | } |
679 | ||
f7784b8e | 680 | void kvm_arch_commit_memory_region(struct kvm *kvm, |
09170a49 | 681 | const struct kvm_userspace_memory_region *mem, |
8482644a | 682 | const struct kvm_memory_slot *old, |
f36f3f28 | 683 | const struct kvm_memory_slot *new, |
8482644a | 684 | enum kvm_mr_change change) |
f7784b8e | 685 | { |
f36f3f28 | 686 | kvmppc_core_commit_memory_region(kvm, mem, old, new); |
f7784b8e MT |
687 | } |
688 | ||
2df72e9b MT |
689 | void kvm_arch_flush_shadow_memslot(struct kvm *kvm, |
690 | struct kvm_memory_slot *slot) | |
34d4cb8f | 691 | { |
dfe49dbd | 692 | kvmppc_core_flush_memslot(kvm, slot); |
34d4cb8f MT |
693 | } |
694 | ||
bbf45ba5 HB |
695 | struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id) |
696 | { | |
73e75b41 HB |
697 | struct kvm_vcpu *vcpu; |
698 | vcpu = kvmppc_core_vcpu_create(kvm, id); | |
03cdab53 ME |
699 | if (!IS_ERR(vcpu)) { |
700 | vcpu->arch.wqp = &vcpu->wq; | |
06056bfb | 701 | kvmppc_create_vcpu_debugfs(vcpu, id); |
03cdab53 | 702 | } |
73e75b41 | 703 | return vcpu; |
bbf45ba5 HB |
704 | } |
705 | ||
31928aa5 | 706 | void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) |
42897d86 | 707 | { |
42897d86 MT |
708 | } |
709 | ||
bbf45ba5 HB |
710 | void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) |
711 | { | |
a595405d AG |
712 | /* Make sure we're not using the vcpu anymore */ |
713 | hrtimer_cancel(&vcpu->arch.dec_timer); | |
a595405d | 714 | |
73e75b41 | 715 | kvmppc_remove_vcpu_debugfs(vcpu); |
eb1e4f43 SW |
716 | |
717 | switch (vcpu->arch.irq_type) { | |
718 | case KVMPPC_IRQ_MPIC: | |
719 | kvmppc_mpic_disconnect_vcpu(vcpu->arch.mpic, vcpu); | |
720 | break; | |
bc5ad3f3 | 721 | case KVMPPC_IRQ_XICS: |
5af50993 BH |
722 | if (xive_enabled()) |
723 | kvmppc_xive_cleanup_vcpu(vcpu); | |
724 | else | |
725 | kvmppc_xics_free_icp(vcpu); | |
bc5ad3f3 | 726 | break; |
eb1e4f43 SW |
727 | } |
728 | ||
db93f574 | 729 | kvmppc_core_vcpu_free(vcpu); |
bbf45ba5 HB |
730 | } |
731 | ||
732 | void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) | |
733 | { | |
734 | kvm_arch_vcpu_free(vcpu); | |
735 | } | |
736 | ||
737 | int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu) | |
738 | { | |
9dd921cf | 739 | return kvmppc_core_pending_dec(vcpu); |
bbf45ba5 HB |
740 | } |
741 | ||
5358a963 | 742 | static enum hrtimer_restart kvmppc_decrementer_wakeup(struct hrtimer *timer) |
544c6761 AG |
743 | { |
744 | struct kvm_vcpu *vcpu; | |
745 | ||
746 | vcpu = container_of(timer, struct kvm_vcpu, arch.dec_timer); | |
d02d4d15 | 747 | kvmppc_decrementer_func(vcpu); |
544c6761 AG |
748 | |
749 | return HRTIMER_NORESTART; | |
750 | } | |
751 | ||
bbf45ba5 HB |
752 | int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) |
753 | { | |
f61c94bb BB |
754 | int ret; |
755 | ||
544c6761 | 756 | hrtimer_init(&vcpu->arch.dec_timer, CLOCK_REALTIME, HRTIMER_MODE_ABS); |
544c6761 | 757 | vcpu->arch.dec_timer.function = kvmppc_decrementer_wakeup; |
de56a948 | 758 | vcpu->arch.dec_expires = ~(u64)0; |
bbf45ba5 | 759 | |
09000adb BB |
760 | #ifdef CONFIG_KVM_EXIT_TIMING |
761 | mutex_init(&vcpu->arch.exit_timing_lock); | |
762 | #endif | |
f61c94bb BB |
763 | ret = kvmppc_subarch_vcpu_init(vcpu); |
764 | return ret; | |
bbf45ba5 HB |
765 | } |
766 | ||
767 | void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) | |
768 | { | |
ecc0981f | 769 | kvmppc_mmu_destroy(vcpu); |
f61c94bb | 770 | kvmppc_subarch_vcpu_uninit(vcpu); |
bbf45ba5 HB |
771 | } |
772 | ||
773 | void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) | |
774 | { | |
eab17672 SW |
775 | #ifdef CONFIG_BOOKE |
776 | /* | |
777 | * vrsave (formerly usprg0) isn't used by Linux, but may | |
778 | * be used by the guest. | |
779 | * | |
780 | * On non-booke this is associated with Altivec and | |
781 | * is handled by code in book3s.c. | |
782 | */ | |
783 | mtspr(SPRN_VRSAVE, vcpu->arch.vrsave); | |
784 | #endif | |
9dd921cf | 785 | kvmppc_core_vcpu_load(vcpu, cpu); |
bbf45ba5 HB |
786 | } |
787 | ||
788 | void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) | |
789 | { | |
9dd921cf | 790 | kvmppc_core_vcpu_put(vcpu); |
eab17672 SW |
791 | #ifdef CONFIG_BOOKE |
792 | vcpu->arch.vrsave = mfspr(SPRN_VRSAVE); | |
793 | #endif | |
bbf45ba5 HB |
794 | } |
795 | ||
9576730d SW |
796 | /* |
797 | * irq_bypass_add_producer and irq_bypass_del_producer are only | |
798 | * useful if the architecture supports PCI passthrough. | |
799 | * irq_bypass_stop and irq_bypass_start are not needed and so | |
800 | * kvm_ops are not defined for them. | |
801 | */ | |
802 | bool kvm_arch_has_irq_bypass(void) | |
803 | { | |
804 | return ((kvmppc_hv_ops && kvmppc_hv_ops->irq_bypass_add_producer) || | |
805 | (kvmppc_pr_ops && kvmppc_pr_ops->irq_bypass_add_producer)); | |
806 | } | |
807 | ||
808 | int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, | |
809 | struct irq_bypass_producer *prod) | |
810 | { | |
811 | struct kvm_kernel_irqfd *irqfd = | |
812 | container_of(cons, struct kvm_kernel_irqfd, consumer); | |
813 | struct kvm *kvm = irqfd->kvm; | |
814 | ||
815 | if (kvm->arch.kvm_ops->irq_bypass_add_producer) | |
816 | return kvm->arch.kvm_ops->irq_bypass_add_producer(cons, prod); | |
817 | ||
818 | return 0; | |
819 | } | |
820 | ||
821 | void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, | |
822 | struct irq_bypass_producer *prod) | |
823 | { | |
824 | struct kvm_kernel_irqfd *irqfd = | |
825 | container_of(cons, struct kvm_kernel_irqfd, consumer); | |
826 | struct kvm *kvm = irqfd->kvm; | |
827 | ||
828 | if (kvm->arch.kvm_ops->irq_bypass_del_producer) | |
829 | kvm->arch.kvm_ops->irq_bypass_del_producer(cons, prod); | |
830 | } | |
831 | ||
6f63e81b BL |
832 | #ifdef CONFIG_VSX |
833 | static inline int kvmppc_get_vsr_dword_offset(int index) | |
834 | { | |
835 | int offset; | |
836 | ||
837 | if ((index != 0) && (index != 1)) | |
838 | return -1; | |
839 | ||
840 | #ifdef __BIG_ENDIAN | |
841 | offset = index; | |
842 | #else | |
843 | offset = 1 - index; | |
844 | #endif | |
845 | ||
846 | return offset; | |
847 | } | |
848 | ||
849 | static inline int kvmppc_get_vsr_word_offset(int index) | |
850 | { | |
851 | int offset; | |
852 | ||
853 | if ((index > 3) || (index < 0)) | |
854 | return -1; | |
855 | ||
856 | #ifdef __BIG_ENDIAN | |
857 | offset = index; | |
858 | #else | |
859 | offset = 3 - index; | |
860 | #endif | |
861 | return offset; | |
862 | } | |
863 | ||
864 | static inline void kvmppc_set_vsr_dword(struct kvm_vcpu *vcpu, | |
865 | u64 gpr) | |
866 | { | |
867 | union kvmppc_one_reg val; | |
868 | int offset = kvmppc_get_vsr_dword_offset(vcpu->arch.mmio_vsx_offset); | |
869 | int index = vcpu->arch.io_gpr & KVM_MMIO_REG_MASK; | |
870 | ||
871 | if (offset == -1) | |
872 | return; | |
873 | ||
874 | if (vcpu->arch.mmio_vsx_tx_sx_enabled) { | |
875 | val.vval = VCPU_VSX_VR(vcpu, index); | |
876 | val.vsxval[offset] = gpr; | |
877 | VCPU_VSX_VR(vcpu, index) = val.vval; | |
878 | } else { | |
879 | VCPU_VSX_FPR(vcpu, index, offset) = gpr; | |
880 | } | |
881 | } | |
882 | ||
883 | static inline void kvmppc_set_vsr_dword_dump(struct kvm_vcpu *vcpu, | |
884 | u64 gpr) | |
885 | { | |
886 | union kvmppc_one_reg val; | |
887 | int index = vcpu->arch.io_gpr & KVM_MMIO_REG_MASK; | |
888 | ||
889 | if (vcpu->arch.mmio_vsx_tx_sx_enabled) { | |
890 | val.vval = VCPU_VSX_VR(vcpu, index); | |
891 | val.vsxval[0] = gpr; | |
892 | val.vsxval[1] = gpr; | |
893 | VCPU_VSX_VR(vcpu, index) = val.vval; | |
894 | } else { | |
895 | VCPU_VSX_FPR(vcpu, index, 0) = gpr; | |
896 | VCPU_VSX_FPR(vcpu, index, 1) = gpr; | |
897 | } | |
898 | } | |
899 | ||
900 | static inline void kvmppc_set_vsr_word(struct kvm_vcpu *vcpu, | |
901 | u32 gpr32) | |
902 | { | |
903 | union kvmppc_one_reg val; | |
904 | int offset = kvmppc_get_vsr_word_offset(vcpu->arch.mmio_vsx_offset); | |
905 | int index = vcpu->arch.io_gpr & KVM_MMIO_REG_MASK; | |
906 | int dword_offset, word_offset; | |
907 | ||
908 | if (offset == -1) | |
909 | return; | |
910 | ||
911 | if (vcpu->arch.mmio_vsx_tx_sx_enabled) { | |
912 | val.vval = VCPU_VSX_VR(vcpu, index); | |
913 | val.vsx32val[offset] = gpr32; | |
914 | VCPU_VSX_VR(vcpu, index) = val.vval; | |
915 | } else { | |
916 | dword_offset = offset / 2; | |
917 | word_offset = offset % 2; | |
918 | val.vsxval[0] = VCPU_VSX_FPR(vcpu, index, dword_offset); | |
919 | val.vsx32val[word_offset] = gpr32; | |
920 | VCPU_VSX_FPR(vcpu, index, dword_offset) = val.vsxval[0]; | |
921 | } | |
922 | } | |
923 | #endif /* CONFIG_VSX */ | |
924 | ||
925 | #ifdef CONFIG_PPC_FPU | |
926 | static inline u64 sp_to_dp(u32 fprs) | |
927 | { | |
928 | u64 fprd; | |
929 | ||
930 | preempt_disable(); | |
931 | enable_kernel_fp(); | |
932 | asm ("lfs%U1%X1 0,%1; stfd%U0%X0 0,%0" : "=m" (fprd) : "m" (fprs) | |
933 | : "fr0"); | |
934 | preempt_enable(); | |
935 | return fprd; | |
936 | } | |
937 | ||
938 | static inline u32 dp_to_sp(u64 fprd) | |
939 | { | |
940 | u32 fprs; | |
941 | ||
942 | preempt_disable(); | |
943 | enable_kernel_fp(); | |
944 | asm ("lfd%U1%X1 0,%1; stfs%U0%X0 0,%0" : "=m" (fprs) : "m" (fprd) | |
945 | : "fr0"); | |
946 | preempt_enable(); | |
947 | return fprs; | |
948 | } | |
949 | ||
950 | #else | |
951 | #define sp_to_dp(x) (x) | |
952 | #define dp_to_sp(x) (x) | |
953 | #endif /* CONFIG_PPC_FPU */ | |
954 | ||
bbf45ba5 HB |
955 | static void kvmppc_complete_mmio_load(struct kvm_vcpu *vcpu, |
956 | struct kvm_run *run) | |
957 | { | |
69b61833 | 958 | u64 uninitialized_var(gpr); |
bbf45ba5 | 959 | |
8e5b26b5 | 960 | if (run->mmio.len > sizeof(gpr)) { |
bbf45ba5 HB |
961 | printk(KERN_ERR "bad MMIO length: %d\n", run->mmio.len); |
962 | return; | |
963 | } | |
964 | ||
d078eed3 | 965 | if (!vcpu->arch.mmio_host_swabbed) { |
bbf45ba5 | 966 | switch (run->mmio.len) { |
b104d066 | 967 | case 8: gpr = *(u64 *)run->mmio.data; break; |
8e5b26b5 AG |
968 | case 4: gpr = *(u32 *)run->mmio.data; break; |
969 | case 2: gpr = *(u16 *)run->mmio.data; break; | |
970 | case 1: gpr = *(u8 *)run->mmio.data; break; | |
bbf45ba5 HB |
971 | } |
972 | } else { | |
bbf45ba5 | 973 | switch (run->mmio.len) { |
d078eed3 DG |
974 | case 8: gpr = swab64(*(u64 *)run->mmio.data); break; |
975 | case 4: gpr = swab32(*(u32 *)run->mmio.data); break; | |
976 | case 2: gpr = swab16(*(u16 *)run->mmio.data); break; | |
8e5b26b5 | 977 | case 1: gpr = *(u8 *)run->mmio.data; break; |
bbf45ba5 HB |
978 | } |
979 | } | |
8e5b26b5 | 980 | |
6f63e81b BL |
981 | /* conversion between single and double precision */ |
982 | if ((vcpu->arch.mmio_sp64_extend) && (run->mmio.len == 4)) | |
983 | gpr = sp_to_dp(gpr); | |
984 | ||
3587d534 AG |
985 | if (vcpu->arch.mmio_sign_extend) { |
986 | switch (run->mmio.len) { | |
987 | #ifdef CONFIG_PPC64 | |
988 | case 4: | |
989 | gpr = (s64)(s32)gpr; | |
990 | break; | |
991 | #endif | |
992 | case 2: | |
993 | gpr = (s64)(s16)gpr; | |
994 | break; | |
995 | case 1: | |
996 | gpr = (s64)(s8)gpr; | |
997 | break; | |
998 | } | |
999 | } | |
1000 | ||
b3c5d3c2 AG |
1001 | switch (vcpu->arch.io_gpr & KVM_MMIO_REG_EXT_MASK) { |
1002 | case KVM_MMIO_REG_GPR: | |
b104d066 AG |
1003 | kvmppc_set_gpr(vcpu, vcpu->arch.io_gpr, gpr); |
1004 | break; | |
b3c5d3c2 | 1005 | case KVM_MMIO_REG_FPR: |
efff1912 | 1006 | VCPU_FPR(vcpu, vcpu->arch.io_gpr & KVM_MMIO_REG_MASK) = gpr; |
b104d066 | 1007 | break; |
287d5611 | 1008 | #ifdef CONFIG_PPC_BOOK3S |
b3c5d3c2 AG |
1009 | case KVM_MMIO_REG_QPR: |
1010 | vcpu->arch.qpr[vcpu->arch.io_gpr & KVM_MMIO_REG_MASK] = gpr; | |
b104d066 | 1011 | break; |
b3c5d3c2 | 1012 | case KVM_MMIO_REG_FQPR: |
efff1912 | 1013 | VCPU_FPR(vcpu, vcpu->arch.io_gpr & KVM_MMIO_REG_MASK) = gpr; |
b3c5d3c2 | 1014 | vcpu->arch.qpr[vcpu->arch.io_gpr & KVM_MMIO_REG_MASK] = gpr; |
b104d066 | 1015 | break; |
6f63e81b BL |
1016 | #endif |
1017 | #ifdef CONFIG_VSX | |
1018 | case KVM_MMIO_REG_VSX: | |
1019 | if (vcpu->arch.mmio_vsx_copy_type == KVMPPC_VSX_COPY_DWORD) | |
1020 | kvmppc_set_vsr_dword(vcpu, gpr); | |
1021 | else if (vcpu->arch.mmio_vsx_copy_type == KVMPPC_VSX_COPY_WORD) | |
1022 | kvmppc_set_vsr_word(vcpu, gpr); | |
1023 | else if (vcpu->arch.mmio_vsx_copy_type == | |
1024 | KVMPPC_VSX_COPY_DWORD_LOAD_DUMP) | |
1025 | kvmppc_set_vsr_dword_dump(vcpu, gpr); | |
1026 | break; | |
287d5611 | 1027 | #endif |
b104d066 AG |
1028 | default: |
1029 | BUG(); | |
1030 | } | |
bbf45ba5 HB |
1031 | } |
1032 | ||
eb8b0560 PM |
1033 | static int __kvmppc_handle_load(struct kvm_run *run, struct kvm_vcpu *vcpu, |
1034 | unsigned int rt, unsigned int bytes, | |
1035 | int is_default_endian, int sign_extend) | |
bbf45ba5 | 1036 | { |
ed840ee9 | 1037 | int idx, ret; |
d078eed3 | 1038 | bool host_swabbed; |
73601775 | 1039 | |
d078eed3 | 1040 | /* Pity C doesn't have a logical XOR operator */ |
73601775 | 1041 | if (kvmppc_need_byteswap(vcpu)) { |
d078eed3 | 1042 | host_swabbed = is_default_endian; |
73601775 | 1043 | } else { |
d078eed3 | 1044 | host_swabbed = !is_default_endian; |
73601775 | 1045 | } |
ed840ee9 | 1046 | |
bbf45ba5 HB |
1047 | if (bytes > sizeof(run->mmio.data)) { |
1048 | printk(KERN_ERR "%s: bad MMIO length: %d\n", __func__, | |
1049 | run->mmio.len); | |
1050 | } | |
1051 | ||
1052 | run->mmio.phys_addr = vcpu->arch.paddr_accessed; | |
1053 | run->mmio.len = bytes; | |
1054 | run->mmio.is_write = 0; | |
1055 | ||
1056 | vcpu->arch.io_gpr = rt; | |
d078eed3 | 1057 | vcpu->arch.mmio_host_swabbed = host_swabbed; |
bbf45ba5 HB |
1058 | vcpu->mmio_needed = 1; |
1059 | vcpu->mmio_is_write = 0; | |
eb8b0560 | 1060 | vcpu->arch.mmio_sign_extend = sign_extend; |
bbf45ba5 | 1061 | |
ed840ee9 SW |
1062 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
1063 | ||
e32edf4f | 1064 | ret = kvm_io_bus_read(vcpu, KVM_MMIO_BUS, run->mmio.phys_addr, |
ed840ee9 SW |
1065 | bytes, &run->mmio.data); |
1066 | ||
1067 | srcu_read_unlock(&vcpu->kvm->srcu, idx); | |
1068 | ||
1069 | if (!ret) { | |
0e673fb6 AG |
1070 | kvmppc_complete_mmio_load(vcpu, run); |
1071 | vcpu->mmio_needed = 0; | |
1072 | return EMULATE_DONE; | |
1073 | } | |
1074 | ||
bbf45ba5 HB |
1075 | return EMULATE_DO_MMIO; |
1076 | } | |
eb8b0560 PM |
1077 | |
1078 | int kvmppc_handle_load(struct kvm_run *run, struct kvm_vcpu *vcpu, | |
1079 | unsigned int rt, unsigned int bytes, | |
1080 | int is_default_endian) | |
1081 | { | |
1082 | return __kvmppc_handle_load(run, vcpu, rt, bytes, is_default_endian, 0); | |
1083 | } | |
2ba9f0d8 | 1084 | EXPORT_SYMBOL_GPL(kvmppc_handle_load); |
bbf45ba5 | 1085 | |
3587d534 AG |
1086 | /* Same as above, but sign extends */ |
1087 | int kvmppc_handle_loads(struct kvm_run *run, struct kvm_vcpu *vcpu, | |
73601775 CLG |
1088 | unsigned int rt, unsigned int bytes, |
1089 | int is_default_endian) | |
3587d534 | 1090 | { |
eb8b0560 | 1091 | return __kvmppc_handle_load(run, vcpu, rt, bytes, is_default_endian, 1); |
3587d534 AG |
1092 | } |
1093 | ||
6f63e81b BL |
1094 | #ifdef CONFIG_VSX |
1095 | int kvmppc_handle_vsx_load(struct kvm_run *run, struct kvm_vcpu *vcpu, | |
1096 | unsigned int rt, unsigned int bytes, | |
1097 | int is_default_endian, int mmio_sign_extend) | |
1098 | { | |
1099 | enum emulation_result emulated = EMULATE_DONE; | |
1100 | ||
1101 | /* Currently, mmio_vsx_copy_nums only allowed to be less than 4 */ | |
1102 | if ( (vcpu->arch.mmio_vsx_copy_nums > 4) || | |
1103 | (vcpu->arch.mmio_vsx_copy_nums < 0) ) { | |
1104 | return EMULATE_FAIL; | |
1105 | } | |
1106 | ||
1107 | while (vcpu->arch.mmio_vsx_copy_nums) { | |
1108 | emulated = __kvmppc_handle_load(run, vcpu, rt, bytes, | |
1109 | is_default_endian, mmio_sign_extend); | |
1110 | ||
1111 | if (emulated != EMULATE_DONE) | |
1112 | break; | |
1113 | ||
1114 | vcpu->arch.paddr_accessed += run->mmio.len; | |
1115 | ||
1116 | vcpu->arch.mmio_vsx_copy_nums--; | |
1117 | vcpu->arch.mmio_vsx_offset++; | |
1118 | } | |
1119 | return emulated; | |
1120 | } | |
1121 | #endif /* CONFIG_VSX */ | |
1122 | ||
bbf45ba5 | 1123 | int kvmppc_handle_store(struct kvm_run *run, struct kvm_vcpu *vcpu, |
73601775 | 1124 | u64 val, unsigned int bytes, int is_default_endian) |
bbf45ba5 HB |
1125 | { |
1126 | void *data = run->mmio.data; | |
ed840ee9 | 1127 | int idx, ret; |
d078eed3 | 1128 | bool host_swabbed; |
73601775 | 1129 | |
d078eed3 | 1130 | /* Pity C doesn't have a logical XOR operator */ |
73601775 | 1131 | if (kvmppc_need_byteswap(vcpu)) { |
d078eed3 | 1132 | host_swabbed = is_default_endian; |
73601775 | 1133 | } else { |
d078eed3 | 1134 | host_swabbed = !is_default_endian; |
73601775 | 1135 | } |
bbf45ba5 HB |
1136 | |
1137 | if (bytes > sizeof(run->mmio.data)) { | |
1138 | printk(KERN_ERR "%s: bad MMIO length: %d\n", __func__, | |
1139 | run->mmio.len); | |
1140 | } | |
1141 | ||
1142 | run->mmio.phys_addr = vcpu->arch.paddr_accessed; | |
1143 | run->mmio.len = bytes; | |
1144 | run->mmio.is_write = 1; | |
1145 | vcpu->mmio_needed = 1; | |
1146 | vcpu->mmio_is_write = 1; | |
1147 | ||
6f63e81b BL |
1148 | if ((vcpu->arch.mmio_sp64_extend) && (bytes == 4)) |
1149 | val = dp_to_sp(val); | |
1150 | ||
bbf45ba5 | 1151 | /* Store the value at the lowest bytes in 'data'. */ |
d078eed3 | 1152 | if (!host_swabbed) { |
bbf45ba5 | 1153 | switch (bytes) { |
b104d066 | 1154 | case 8: *(u64 *)data = val; break; |
bbf45ba5 HB |
1155 | case 4: *(u32 *)data = val; break; |
1156 | case 2: *(u16 *)data = val; break; | |
1157 | case 1: *(u8 *)data = val; break; | |
1158 | } | |
1159 | } else { | |
bbf45ba5 | 1160 | switch (bytes) { |
d078eed3 DG |
1161 | case 8: *(u64 *)data = swab64(val); break; |
1162 | case 4: *(u32 *)data = swab32(val); break; | |
1163 | case 2: *(u16 *)data = swab16(val); break; | |
1164 | case 1: *(u8 *)data = val; break; | |
bbf45ba5 HB |
1165 | } |
1166 | } | |
1167 | ||
ed840ee9 SW |
1168 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
1169 | ||
e32edf4f | 1170 | ret = kvm_io_bus_write(vcpu, KVM_MMIO_BUS, run->mmio.phys_addr, |
ed840ee9 SW |
1171 | bytes, &run->mmio.data); |
1172 | ||
1173 | srcu_read_unlock(&vcpu->kvm->srcu, idx); | |
1174 | ||
1175 | if (!ret) { | |
0e673fb6 AG |
1176 | vcpu->mmio_needed = 0; |
1177 | return EMULATE_DONE; | |
1178 | } | |
1179 | ||
bbf45ba5 HB |
1180 | return EMULATE_DO_MMIO; |
1181 | } | |
2ba9f0d8 | 1182 | EXPORT_SYMBOL_GPL(kvmppc_handle_store); |
bbf45ba5 | 1183 | |
6f63e81b BL |
1184 | #ifdef CONFIG_VSX |
1185 | static inline int kvmppc_get_vsr_data(struct kvm_vcpu *vcpu, int rs, u64 *val) | |
1186 | { | |
1187 | u32 dword_offset, word_offset; | |
1188 | union kvmppc_one_reg reg; | |
1189 | int vsx_offset = 0; | |
1190 | int copy_type = vcpu->arch.mmio_vsx_copy_type; | |
1191 | int result = 0; | |
1192 | ||
1193 | switch (copy_type) { | |
1194 | case KVMPPC_VSX_COPY_DWORD: | |
1195 | vsx_offset = | |
1196 | kvmppc_get_vsr_dword_offset(vcpu->arch.mmio_vsx_offset); | |
1197 | ||
1198 | if (vsx_offset == -1) { | |
1199 | result = -1; | |
1200 | break; | |
1201 | } | |
1202 | ||
1203 | if (!vcpu->arch.mmio_vsx_tx_sx_enabled) { | |
1204 | *val = VCPU_VSX_FPR(vcpu, rs, vsx_offset); | |
1205 | } else { | |
1206 | reg.vval = VCPU_VSX_VR(vcpu, rs); | |
1207 | *val = reg.vsxval[vsx_offset]; | |
1208 | } | |
1209 | break; | |
1210 | ||
1211 | case KVMPPC_VSX_COPY_WORD: | |
1212 | vsx_offset = | |
1213 | kvmppc_get_vsr_word_offset(vcpu->arch.mmio_vsx_offset); | |
1214 | ||
1215 | if (vsx_offset == -1) { | |
1216 | result = -1; | |
1217 | break; | |
1218 | } | |
1219 | ||
1220 | if (!vcpu->arch.mmio_vsx_tx_sx_enabled) { | |
1221 | dword_offset = vsx_offset / 2; | |
1222 | word_offset = vsx_offset % 2; | |
1223 | reg.vsxval[0] = VCPU_VSX_FPR(vcpu, rs, dword_offset); | |
1224 | *val = reg.vsx32val[word_offset]; | |
1225 | } else { | |
1226 | reg.vval = VCPU_VSX_VR(vcpu, rs); | |
1227 | *val = reg.vsx32val[vsx_offset]; | |
1228 | } | |
1229 | break; | |
1230 | ||
1231 | default: | |
1232 | result = -1; | |
1233 | break; | |
1234 | } | |
1235 | ||
1236 | return result; | |
1237 | } | |
1238 | ||
1239 | int kvmppc_handle_vsx_store(struct kvm_run *run, struct kvm_vcpu *vcpu, | |
1240 | int rs, unsigned int bytes, int is_default_endian) | |
1241 | { | |
1242 | u64 val; | |
1243 | enum emulation_result emulated = EMULATE_DONE; | |
1244 | ||
1245 | vcpu->arch.io_gpr = rs; | |
1246 | ||
1247 | /* Currently, mmio_vsx_copy_nums only allowed to be less than 4 */ | |
1248 | if ( (vcpu->arch.mmio_vsx_copy_nums > 4) || | |
1249 | (vcpu->arch.mmio_vsx_copy_nums < 0) ) { | |
1250 | return EMULATE_FAIL; | |
1251 | } | |
1252 | ||
1253 | while (vcpu->arch.mmio_vsx_copy_nums) { | |
1254 | if (kvmppc_get_vsr_data(vcpu, rs, &val) == -1) | |
1255 | return EMULATE_FAIL; | |
1256 | ||
1257 | emulated = kvmppc_handle_store(run, vcpu, | |
1258 | val, bytes, is_default_endian); | |
1259 | ||
1260 | if (emulated != EMULATE_DONE) | |
1261 | break; | |
1262 | ||
1263 | vcpu->arch.paddr_accessed += run->mmio.len; | |
1264 | ||
1265 | vcpu->arch.mmio_vsx_copy_nums--; | |
1266 | vcpu->arch.mmio_vsx_offset++; | |
1267 | } | |
1268 | ||
1269 | return emulated; | |
1270 | } | |
1271 | ||
1272 | static int kvmppc_emulate_mmio_vsx_loadstore(struct kvm_vcpu *vcpu, | |
1273 | struct kvm_run *run) | |
1274 | { | |
1275 | enum emulation_result emulated = EMULATE_FAIL; | |
1276 | int r; | |
1277 | ||
1278 | vcpu->arch.paddr_accessed += run->mmio.len; | |
1279 | ||
1280 | if (!vcpu->mmio_is_write) { | |
1281 | emulated = kvmppc_handle_vsx_load(run, vcpu, vcpu->arch.io_gpr, | |
1282 | run->mmio.len, 1, vcpu->arch.mmio_sign_extend); | |
1283 | } else { | |
1284 | emulated = kvmppc_handle_vsx_store(run, vcpu, | |
1285 | vcpu->arch.io_gpr, run->mmio.len, 1); | |
1286 | } | |
1287 | ||
1288 | switch (emulated) { | |
1289 | case EMULATE_DO_MMIO: | |
1290 | run->exit_reason = KVM_EXIT_MMIO; | |
1291 | r = RESUME_HOST; | |
1292 | break; | |
1293 | case EMULATE_FAIL: | |
1294 | pr_info("KVM: MMIO emulation failed (VSX repeat)\n"); | |
1295 | run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
1296 | run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
1297 | r = RESUME_HOST; | |
1298 | break; | |
1299 | default: | |
1300 | r = RESUME_GUEST; | |
1301 | break; | |
1302 | } | |
1303 | return r; | |
1304 | } | |
1305 | #endif /* CONFIG_VSX */ | |
1306 | ||
8a41ea53 MC |
1307 | int kvm_vcpu_ioctl_get_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg) |
1308 | { | |
1309 | int r = 0; | |
1310 | union kvmppc_one_reg val; | |
1311 | int size; | |
1312 | ||
1313 | size = one_reg_size(reg->id); | |
1314 | if (size > sizeof(val)) | |
1315 | return -EINVAL; | |
1316 | ||
1317 | r = kvmppc_get_one_reg(vcpu, reg->id, &val); | |
1318 | if (r == -EINVAL) { | |
1319 | r = 0; | |
1320 | switch (reg->id) { | |
3840edc8 MC |
1321 | #ifdef CONFIG_ALTIVEC |
1322 | case KVM_REG_PPC_VR0 ... KVM_REG_PPC_VR31: | |
1323 | if (!cpu_has_feature(CPU_FTR_ALTIVEC)) { | |
1324 | r = -ENXIO; | |
1325 | break; | |
1326 | } | |
b4d7f161 | 1327 | val.vval = vcpu->arch.vr.vr[reg->id - KVM_REG_PPC_VR0]; |
3840edc8 MC |
1328 | break; |
1329 | case KVM_REG_PPC_VSCR: | |
1330 | if (!cpu_has_feature(CPU_FTR_ALTIVEC)) { | |
1331 | r = -ENXIO; | |
1332 | break; | |
1333 | } | |
b4d7f161 | 1334 | val = get_reg_val(reg->id, vcpu->arch.vr.vscr.u[3]); |
3840edc8 MC |
1335 | break; |
1336 | case KVM_REG_PPC_VRSAVE: | |
b4d7f161 | 1337 | val = get_reg_val(reg->id, vcpu->arch.vrsave); |
3840edc8 MC |
1338 | break; |
1339 | #endif /* CONFIG_ALTIVEC */ | |
8a41ea53 MC |
1340 | default: |
1341 | r = -EINVAL; | |
1342 | break; | |
1343 | } | |
1344 | } | |
1345 | ||
1346 | if (r) | |
1347 | return r; | |
1348 | ||
1349 | if (copy_to_user((char __user *)(unsigned long)reg->addr, &val, size)) | |
1350 | r = -EFAULT; | |
1351 | ||
1352 | return r; | |
1353 | } | |
1354 | ||
1355 | int kvm_vcpu_ioctl_set_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg) | |
1356 | { | |
1357 | int r; | |
1358 | union kvmppc_one_reg val; | |
1359 | int size; | |
1360 | ||
1361 | size = one_reg_size(reg->id); | |
1362 | if (size > sizeof(val)) | |
1363 | return -EINVAL; | |
1364 | ||
1365 | if (copy_from_user(&val, (char __user *)(unsigned long)reg->addr, size)) | |
1366 | return -EFAULT; | |
1367 | ||
1368 | r = kvmppc_set_one_reg(vcpu, reg->id, &val); | |
1369 | if (r == -EINVAL) { | |
1370 | r = 0; | |
1371 | switch (reg->id) { | |
3840edc8 MC |
1372 | #ifdef CONFIG_ALTIVEC |
1373 | case KVM_REG_PPC_VR0 ... KVM_REG_PPC_VR31: | |
1374 | if (!cpu_has_feature(CPU_FTR_ALTIVEC)) { | |
1375 | r = -ENXIO; | |
1376 | break; | |
1377 | } | |
b4d7f161 | 1378 | vcpu->arch.vr.vr[reg->id - KVM_REG_PPC_VR0] = val.vval; |
3840edc8 MC |
1379 | break; |
1380 | case KVM_REG_PPC_VSCR: | |
1381 | if (!cpu_has_feature(CPU_FTR_ALTIVEC)) { | |
1382 | r = -ENXIO; | |
1383 | break; | |
1384 | } | |
b4d7f161 | 1385 | vcpu->arch.vr.vscr.u[3] = set_reg_val(reg->id, val); |
3840edc8 MC |
1386 | break; |
1387 | case KVM_REG_PPC_VRSAVE: | |
b4d7f161 GK |
1388 | if (!cpu_has_feature(CPU_FTR_ALTIVEC)) { |
1389 | r = -ENXIO; | |
1390 | break; | |
1391 | } | |
1392 | vcpu->arch.vrsave = set_reg_val(reg->id, val); | |
3840edc8 MC |
1393 | break; |
1394 | #endif /* CONFIG_ALTIVEC */ | |
8a41ea53 MC |
1395 | default: |
1396 | r = -EINVAL; | |
1397 | break; | |
1398 | } | |
1399 | } | |
1400 | ||
1401 | return r; | |
1402 | } | |
1403 | ||
bbf45ba5 HB |
1404 | int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run) |
1405 | { | |
1406 | int r; | |
1407 | sigset_t sigsaved; | |
1408 | ||
bbf45ba5 | 1409 | if (vcpu->mmio_needed) { |
6f63e81b | 1410 | vcpu->mmio_needed = 0; |
bbf45ba5 HB |
1411 | if (!vcpu->mmio_is_write) |
1412 | kvmppc_complete_mmio_load(vcpu, run); | |
6f63e81b BL |
1413 | #ifdef CONFIG_VSX |
1414 | if (vcpu->arch.mmio_vsx_copy_nums > 0) { | |
1415 | vcpu->arch.mmio_vsx_copy_nums--; | |
1416 | vcpu->arch.mmio_vsx_offset++; | |
1417 | } | |
1418 | ||
1419 | if (vcpu->arch.mmio_vsx_copy_nums > 0) { | |
1420 | r = kvmppc_emulate_mmio_vsx_loadstore(vcpu, run); | |
1421 | if (r == RESUME_HOST) { | |
1422 | vcpu->mmio_needed = 1; | |
1423 | return r; | |
1424 | } | |
1425 | } | |
1426 | #endif | |
ad0a048b AG |
1427 | } else if (vcpu->arch.osi_needed) { |
1428 | u64 *gprs = run->osi.gprs; | |
1429 | int i; | |
1430 | ||
1431 | for (i = 0; i < 32; i++) | |
1432 | kvmppc_set_gpr(vcpu, i, gprs[i]); | |
1433 | vcpu->arch.osi_needed = 0; | |
de56a948 PM |
1434 | } else if (vcpu->arch.hcall_needed) { |
1435 | int i; | |
1436 | ||
1437 | kvmppc_set_gpr(vcpu, 3, run->papr_hcall.ret); | |
1438 | for (i = 0; i < 9; ++i) | |
1439 | kvmppc_set_gpr(vcpu, 4 + i, run->papr_hcall.args[i]); | |
1440 | vcpu->arch.hcall_needed = 0; | |
1c810636 AG |
1441 | #ifdef CONFIG_BOOKE |
1442 | } else if (vcpu->arch.epr_needed) { | |
1443 | kvmppc_set_epr(vcpu, run->epr.epr); | |
1444 | vcpu->arch.epr_needed = 0; | |
1445 | #endif | |
bbf45ba5 HB |
1446 | } |
1447 | ||
6f63e81b BL |
1448 | if (vcpu->sigset_active) |
1449 | sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); | |
1450 | ||
460df4c1 PB |
1451 | if (run->immediate_exit) |
1452 | r = -EINTR; | |
1453 | else | |
1454 | r = kvmppc_vcpu_run(run, vcpu); | |
bbf45ba5 HB |
1455 | |
1456 | if (vcpu->sigset_active) | |
1457 | sigprocmask(SIG_SETMASK, &sigsaved, NULL); | |
1458 | ||
1459 | return r; | |
1460 | } | |
1461 | ||
1462 | int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, struct kvm_interrupt *irq) | |
1463 | { | |
19ccb76a | 1464 | if (irq->irq == KVM_INTERRUPT_UNSET) { |
4fe27d2a | 1465 | kvmppc_core_dequeue_external(vcpu); |
19ccb76a PM |
1466 | return 0; |
1467 | } | |
1468 | ||
1469 | kvmppc_core_queue_external(vcpu, irq); | |
b6d33834 | 1470 | |
dfd4d47e | 1471 | kvm_vcpu_kick(vcpu); |
45c5eb67 | 1472 | |
bbf45ba5 HB |
1473 | return 0; |
1474 | } | |
1475 | ||
71fbfd5f AG |
1476 | static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, |
1477 | struct kvm_enable_cap *cap) | |
1478 | { | |
1479 | int r; | |
1480 | ||
1481 | if (cap->flags) | |
1482 | return -EINVAL; | |
1483 | ||
1484 | switch (cap->cap) { | |
ad0a048b AG |
1485 | case KVM_CAP_PPC_OSI: |
1486 | r = 0; | |
1487 | vcpu->arch.osi_enabled = true; | |
1488 | break; | |
930b412a AG |
1489 | case KVM_CAP_PPC_PAPR: |
1490 | r = 0; | |
1491 | vcpu->arch.papr_enabled = true; | |
1492 | break; | |
1c810636 AG |
1493 | case KVM_CAP_PPC_EPR: |
1494 | r = 0; | |
5df554ad SW |
1495 | if (cap->args[0]) |
1496 | vcpu->arch.epr_flags |= KVMPPC_EPR_USER; | |
1497 | else | |
1498 | vcpu->arch.epr_flags &= ~KVMPPC_EPR_USER; | |
1c810636 | 1499 | break; |
f61c94bb BB |
1500 | #ifdef CONFIG_BOOKE |
1501 | case KVM_CAP_PPC_BOOKE_WATCHDOG: | |
1502 | r = 0; | |
1503 | vcpu->arch.watchdog_enabled = true; | |
1504 | break; | |
1505 | #endif | |
bf7ca4bd | 1506 | #if defined(CONFIG_KVM_E500V2) || defined(CONFIG_KVM_E500MC) |
dc83b8bc SW |
1507 | case KVM_CAP_SW_TLB: { |
1508 | struct kvm_config_tlb cfg; | |
1509 | void __user *user_ptr = (void __user *)(uintptr_t)cap->args[0]; | |
1510 | ||
1511 | r = -EFAULT; | |
1512 | if (copy_from_user(&cfg, user_ptr, sizeof(cfg))) | |
1513 | break; | |
1514 | ||
1515 | r = kvm_vcpu_ioctl_config_tlb(vcpu, &cfg); | |
1516 | break; | |
eb1e4f43 SW |
1517 | } |
1518 | #endif | |
1519 | #ifdef CONFIG_KVM_MPIC | |
1520 | case KVM_CAP_IRQ_MPIC: { | |
70abaded | 1521 | struct fd f; |
eb1e4f43 SW |
1522 | struct kvm_device *dev; |
1523 | ||
1524 | r = -EBADF; | |
70abaded AV |
1525 | f = fdget(cap->args[0]); |
1526 | if (!f.file) | |
eb1e4f43 SW |
1527 | break; |
1528 | ||
1529 | r = -EPERM; | |
70abaded | 1530 | dev = kvm_device_from_filp(f.file); |
eb1e4f43 SW |
1531 | if (dev) |
1532 | r = kvmppc_mpic_connect_vcpu(dev, vcpu, cap->args[1]); | |
1533 | ||
70abaded | 1534 | fdput(f); |
eb1e4f43 | 1535 | break; |
dc83b8bc SW |
1536 | } |
1537 | #endif | |
5975a2e0 PM |
1538 | #ifdef CONFIG_KVM_XICS |
1539 | case KVM_CAP_IRQ_XICS: { | |
70abaded | 1540 | struct fd f; |
5975a2e0 PM |
1541 | struct kvm_device *dev; |
1542 | ||
1543 | r = -EBADF; | |
70abaded AV |
1544 | f = fdget(cap->args[0]); |
1545 | if (!f.file) | |
5975a2e0 PM |
1546 | break; |
1547 | ||
1548 | r = -EPERM; | |
70abaded | 1549 | dev = kvm_device_from_filp(f.file); |
5af50993 BH |
1550 | if (dev) { |
1551 | if (xive_enabled()) | |
1552 | r = kvmppc_xive_connect_vcpu(dev, vcpu, cap->args[1]); | |
1553 | else | |
1554 | r = kvmppc_xics_connect_vcpu(dev, vcpu, cap->args[1]); | |
1555 | } | |
5975a2e0 | 1556 | |
70abaded | 1557 | fdput(f); |
5975a2e0 PM |
1558 | break; |
1559 | } | |
1560 | #endif /* CONFIG_KVM_XICS */ | |
134764ed AP |
1561 | #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE |
1562 | case KVM_CAP_PPC_FWNMI: | |
1563 | r = -EINVAL; | |
1564 | if (!is_kvmppc_hv_enabled(vcpu->kvm)) | |
1565 | break; | |
1566 | r = 0; | |
1567 | vcpu->kvm->arch.fwnmi_enabled = true; | |
1568 | break; | |
1569 | #endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */ | |
71fbfd5f AG |
1570 | default: |
1571 | r = -EINVAL; | |
1572 | break; | |
1573 | } | |
1574 | ||
af8f38b3 AG |
1575 | if (!r) |
1576 | r = kvmppc_sanity_check(vcpu); | |
1577 | ||
71fbfd5f AG |
1578 | return r; |
1579 | } | |
1580 | ||
34a75b0f PM |
1581 | bool kvm_arch_intc_initialized(struct kvm *kvm) |
1582 | { | |
1583 | #ifdef CONFIG_KVM_MPIC | |
1584 | if (kvm->arch.mpic) | |
1585 | return true; | |
1586 | #endif | |
1587 | #ifdef CONFIG_KVM_XICS | |
5af50993 | 1588 | if (kvm->arch.xics || kvm->arch.xive) |
34a75b0f PM |
1589 | return true; |
1590 | #endif | |
1591 | return false; | |
1592 | } | |
1593 | ||
bbf45ba5 HB |
1594 | int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, |
1595 | struct kvm_mp_state *mp_state) | |
1596 | { | |
1597 | return -EINVAL; | |
1598 | } | |
1599 | ||
1600 | int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, | |
1601 | struct kvm_mp_state *mp_state) | |
1602 | { | |
1603 | return -EINVAL; | |
1604 | } | |
1605 | ||
1606 | long kvm_arch_vcpu_ioctl(struct file *filp, | |
1607 | unsigned int ioctl, unsigned long arg) | |
1608 | { | |
1609 | struct kvm_vcpu *vcpu = filp->private_data; | |
1610 | void __user *argp = (void __user *)arg; | |
1611 | long r; | |
1612 | ||
93736624 AK |
1613 | switch (ioctl) { |
1614 | case KVM_INTERRUPT: { | |
bbf45ba5 HB |
1615 | struct kvm_interrupt irq; |
1616 | r = -EFAULT; | |
1617 | if (copy_from_user(&irq, argp, sizeof(irq))) | |
93736624 | 1618 | goto out; |
bbf45ba5 | 1619 | r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); |
93736624 | 1620 | goto out; |
bbf45ba5 | 1621 | } |
19483d14 | 1622 | |
71fbfd5f AG |
1623 | case KVM_ENABLE_CAP: |
1624 | { | |
1625 | struct kvm_enable_cap cap; | |
1626 | r = -EFAULT; | |
1627 | if (copy_from_user(&cap, argp, sizeof(cap))) | |
1628 | goto out; | |
1629 | r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); | |
1630 | break; | |
1631 | } | |
dc83b8bc | 1632 | |
e24ed81f AG |
1633 | case KVM_SET_ONE_REG: |
1634 | case KVM_GET_ONE_REG: | |
1635 | { | |
1636 | struct kvm_one_reg reg; | |
1637 | r = -EFAULT; | |
1638 | if (copy_from_user(®, argp, sizeof(reg))) | |
1639 | goto out; | |
1640 | if (ioctl == KVM_SET_ONE_REG) | |
1641 | r = kvm_vcpu_ioctl_set_one_reg(vcpu, ®); | |
1642 | else | |
1643 | r = kvm_vcpu_ioctl_get_one_reg(vcpu, ®); | |
1644 | break; | |
1645 | } | |
1646 | ||
bf7ca4bd | 1647 | #if defined(CONFIG_KVM_E500V2) || defined(CONFIG_KVM_E500MC) |
dc83b8bc SW |
1648 | case KVM_DIRTY_TLB: { |
1649 | struct kvm_dirty_tlb dirty; | |
1650 | r = -EFAULT; | |
1651 | if (copy_from_user(&dirty, argp, sizeof(dirty))) | |
1652 | goto out; | |
1653 | r = kvm_vcpu_ioctl_dirty_tlb(vcpu, &dirty); | |
1654 | break; | |
1655 | } | |
1656 | #endif | |
bbf45ba5 HB |
1657 | default: |
1658 | r = -EINVAL; | |
1659 | } | |
1660 | ||
1661 | out: | |
1662 | return r; | |
1663 | } | |
1664 | ||
5b1c1493 CO |
1665 | int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) |
1666 | { | |
1667 | return VM_FAULT_SIGBUS; | |
1668 | } | |
1669 | ||
15711e9c AG |
1670 | static int kvm_vm_ioctl_get_pvinfo(struct kvm_ppc_pvinfo *pvinfo) |
1671 | { | |
784bafac SY |
1672 | u32 inst_nop = 0x60000000; |
1673 | #ifdef CONFIG_KVM_BOOKE_HV | |
1674 | u32 inst_sc1 = 0x44000022; | |
2743103f AG |
1675 | pvinfo->hcall[0] = cpu_to_be32(inst_sc1); |
1676 | pvinfo->hcall[1] = cpu_to_be32(inst_nop); | |
1677 | pvinfo->hcall[2] = cpu_to_be32(inst_nop); | |
1678 | pvinfo->hcall[3] = cpu_to_be32(inst_nop); | |
784bafac | 1679 | #else |
15711e9c AG |
1680 | u32 inst_lis = 0x3c000000; |
1681 | u32 inst_ori = 0x60000000; | |
15711e9c AG |
1682 | u32 inst_sc = 0x44000002; |
1683 | u32 inst_imm_mask = 0xffff; | |
1684 | ||
1685 | /* | |
1686 | * The hypercall to get into KVM from within guest context is as | |
1687 | * follows: | |
1688 | * | |
1689 | * lis r0, r0, KVM_SC_MAGIC_R0@h | |
1690 | * ori r0, KVM_SC_MAGIC_R0@l | |
1691 | * sc | |
1692 | * nop | |
1693 | */ | |
2743103f AG |
1694 | pvinfo->hcall[0] = cpu_to_be32(inst_lis | ((KVM_SC_MAGIC_R0 >> 16) & inst_imm_mask)); |
1695 | pvinfo->hcall[1] = cpu_to_be32(inst_ori | (KVM_SC_MAGIC_R0 & inst_imm_mask)); | |
1696 | pvinfo->hcall[2] = cpu_to_be32(inst_sc); | |
1697 | pvinfo->hcall[3] = cpu_to_be32(inst_nop); | |
784bafac | 1698 | #endif |
15711e9c | 1699 | |
9202e076 LYB |
1700 | pvinfo->flags = KVM_PPC_PVINFO_FLAGS_EV_IDLE; |
1701 | ||
15711e9c AG |
1702 | return 0; |
1703 | } | |
1704 | ||
5efdb4be AG |
1705 | int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, |
1706 | bool line_status) | |
1707 | { | |
1708 | if (!irqchip_in_kernel(kvm)) | |
1709 | return -ENXIO; | |
1710 | ||
1711 | irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, | |
1712 | irq_event->irq, irq_event->level, | |
1713 | line_status); | |
1714 | return 0; | |
1715 | } | |
1716 | ||
699a0ea0 PM |
1717 | |
1718 | static int kvm_vm_ioctl_enable_cap(struct kvm *kvm, | |
1719 | struct kvm_enable_cap *cap) | |
1720 | { | |
1721 | int r; | |
1722 | ||
1723 | if (cap->flags) | |
1724 | return -EINVAL; | |
1725 | ||
1726 | switch (cap->cap) { | |
1727 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER | |
1728 | case KVM_CAP_PPC_ENABLE_HCALL: { | |
1729 | unsigned long hcall = cap->args[0]; | |
1730 | ||
1731 | r = -EINVAL; | |
1732 | if (hcall > MAX_HCALL_OPCODE || (hcall & 3) || | |
1733 | cap->args[1] > 1) | |
1734 | break; | |
ae2113a4 PM |
1735 | if (!kvmppc_book3s_hcall_implemented(kvm, hcall)) |
1736 | break; | |
699a0ea0 PM |
1737 | if (cap->args[1]) |
1738 | set_bit(hcall / 4, kvm->arch.enabled_hcalls); | |
1739 | else | |
1740 | clear_bit(hcall / 4, kvm->arch.enabled_hcalls); | |
1741 | r = 0; | |
1742 | break; | |
1743 | } | |
3c313524 PM |
1744 | case KVM_CAP_PPC_SMT: { |
1745 | unsigned long mode = cap->args[0]; | |
1746 | unsigned long flags = cap->args[1]; | |
1747 | ||
1748 | r = -EINVAL; | |
1749 | if (kvm->arch.kvm_ops->set_smt_mode) | |
1750 | r = kvm->arch.kvm_ops->set_smt_mode(kvm, mode, flags); | |
1751 | break; | |
1752 | } | |
699a0ea0 PM |
1753 | #endif |
1754 | default: | |
1755 | r = -EINVAL; | |
1756 | break; | |
1757 | } | |
1758 | ||
1759 | return r; | |
1760 | } | |
1761 | ||
bbf45ba5 HB |
1762 | long kvm_arch_vm_ioctl(struct file *filp, |
1763 | unsigned int ioctl, unsigned long arg) | |
1764 | { | |
5df554ad | 1765 | struct kvm *kvm __maybe_unused = filp->private_data; |
15711e9c | 1766 | void __user *argp = (void __user *)arg; |
bbf45ba5 HB |
1767 | long r; |
1768 | ||
1769 | switch (ioctl) { | |
15711e9c AG |
1770 | case KVM_PPC_GET_PVINFO: { |
1771 | struct kvm_ppc_pvinfo pvinfo; | |
d8cdddcd | 1772 | memset(&pvinfo, 0, sizeof(pvinfo)); |
15711e9c AG |
1773 | r = kvm_vm_ioctl_get_pvinfo(&pvinfo); |
1774 | if (copy_to_user(argp, &pvinfo, sizeof(pvinfo))) { | |
1775 | r = -EFAULT; | |
1776 | goto out; | |
1777 | } | |
1778 | ||
1779 | break; | |
1780 | } | |
699a0ea0 PM |
1781 | case KVM_ENABLE_CAP: |
1782 | { | |
1783 | struct kvm_enable_cap cap; | |
1784 | r = -EFAULT; | |
1785 | if (copy_from_user(&cap, argp, sizeof(cap))) | |
1786 | goto out; | |
1787 | r = kvm_vm_ioctl_enable_cap(kvm, &cap); | |
1788 | break; | |
1789 | } | |
76d837a4 | 1790 | #ifdef CONFIG_SPAPR_TCE_IOMMU |
58ded420 AK |
1791 | case KVM_CREATE_SPAPR_TCE_64: { |
1792 | struct kvm_create_spapr_tce_64 create_tce_64; | |
1793 | ||
1794 | r = -EFAULT; | |
1795 | if (copy_from_user(&create_tce_64, argp, sizeof(create_tce_64))) | |
1796 | goto out; | |
1797 | if (create_tce_64.flags) { | |
1798 | r = -EINVAL; | |
1799 | goto out; | |
1800 | } | |
1801 | r = kvm_vm_ioctl_create_spapr_tce(kvm, &create_tce_64); | |
1802 | goto out; | |
1803 | } | |
54738c09 DG |
1804 | case KVM_CREATE_SPAPR_TCE: { |
1805 | struct kvm_create_spapr_tce create_tce; | |
58ded420 | 1806 | struct kvm_create_spapr_tce_64 create_tce_64; |
54738c09 DG |
1807 | |
1808 | r = -EFAULT; | |
1809 | if (copy_from_user(&create_tce, argp, sizeof(create_tce))) | |
1810 | goto out; | |
58ded420 AK |
1811 | |
1812 | create_tce_64.liobn = create_tce.liobn; | |
1813 | create_tce_64.page_shift = IOMMU_PAGE_SHIFT_4K; | |
1814 | create_tce_64.offset = 0; | |
1815 | create_tce_64.size = create_tce.window_size >> | |
1816 | IOMMU_PAGE_SHIFT_4K; | |
1817 | create_tce_64.flags = 0; | |
1818 | r = kvm_vm_ioctl_create_spapr_tce(kvm, &create_tce_64); | |
54738c09 DG |
1819 | goto out; |
1820 | } | |
76d837a4 PM |
1821 | #endif |
1822 | #ifdef CONFIG_PPC_BOOK3S_64 | |
5b74716e | 1823 | case KVM_PPC_GET_SMMU_INFO: { |
5b74716e | 1824 | struct kvm_ppc_smmu_info info; |
cbbc58d4 | 1825 | struct kvm *kvm = filp->private_data; |
5b74716e BH |
1826 | |
1827 | memset(&info, 0, sizeof(info)); | |
cbbc58d4 | 1828 | r = kvm->arch.kvm_ops->get_smmu_info(kvm, &info); |
5b74716e BH |
1829 | if (r >= 0 && copy_to_user(argp, &info, sizeof(info))) |
1830 | r = -EFAULT; | |
1831 | break; | |
1832 | } | |
8e591cb7 ME |
1833 | case KVM_PPC_RTAS_DEFINE_TOKEN: { |
1834 | struct kvm *kvm = filp->private_data; | |
1835 | ||
1836 | r = kvm_vm_ioctl_rtas_define_token(kvm, argp); | |
1837 | break; | |
1838 | } | |
c9270132 PM |
1839 | case KVM_PPC_CONFIGURE_V3_MMU: { |
1840 | struct kvm *kvm = filp->private_data; | |
1841 | struct kvm_ppc_mmuv3_cfg cfg; | |
1842 | ||
1843 | r = -EINVAL; | |
1844 | if (!kvm->arch.kvm_ops->configure_mmu) | |
1845 | goto out; | |
1846 | r = -EFAULT; | |
1847 | if (copy_from_user(&cfg, argp, sizeof(cfg))) | |
1848 | goto out; | |
1849 | r = kvm->arch.kvm_ops->configure_mmu(kvm, &cfg); | |
1850 | break; | |
1851 | } | |
1852 | case KVM_PPC_GET_RMMU_INFO: { | |
1853 | struct kvm *kvm = filp->private_data; | |
1854 | struct kvm_ppc_rmmu_info info; | |
1855 | ||
1856 | r = -EINVAL; | |
1857 | if (!kvm->arch.kvm_ops->get_rmmu_info) | |
1858 | goto out; | |
1859 | r = kvm->arch.kvm_ops->get_rmmu_info(kvm, &info); | |
1860 | if (r >= 0 && copy_to_user(argp, &info, sizeof(info))) | |
1861 | r = -EFAULT; | |
1862 | break; | |
1863 | } | |
cbbc58d4 AK |
1864 | default: { |
1865 | struct kvm *kvm = filp->private_data; | |
1866 | r = kvm->arch.kvm_ops->arch_vm_ioctl(filp, ioctl, arg); | |
1867 | } | |
3a167bea | 1868 | #else /* CONFIG_PPC_BOOK3S_64 */ |
bbf45ba5 | 1869 | default: |
367e1319 | 1870 | r = -ENOTTY; |
3a167bea | 1871 | #endif |
bbf45ba5 | 1872 | } |
15711e9c | 1873 | out: |
bbf45ba5 HB |
1874 | return r; |
1875 | } | |
1876 | ||
043cc4d7 SW |
1877 | static unsigned long lpid_inuse[BITS_TO_LONGS(KVMPPC_NR_LPIDS)]; |
1878 | static unsigned long nr_lpids; | |
1879 | ||
1880 | long kvmppc_alloc_lpid(void) | |
1881 | { | |
1882 | long lpid; | |
1883 | ||
1884 | do { | |
1885 | lpid = find_first_zero_bit(lpid_inuse, KVMPPC_NR_LPIDS); | |
1886 | if (lpid >= nr_lpids) { | |
1887 | pr_err("%s: No LPIDs free\n", __func__); | |
1888 | return -ENOMEM; | |
1889 | } | |
1890 | } while (test_and_set_bit(lpid, lpid_inuse)); | |
1891 | ||
1892 | return lpid; | |
1893 | } | |
2ba9f0d8 | 1894 | EXPORT_SYMBOL_GPL(kvmppc_alloc_lpid); |
043cc4d7 SW |
1895 | |
1896 | void kvmppc_claim_lpid(long lpid) | |
1897 | { | |
1898 | set_bit(lpid, lpid_inuse); | |
1899 | } | |
2ba9f0d8 | 1900 | EXPORT_SYMBOL_GPL(kvmppc_claim_lpid); |
043cc4d7 SW |
1901 | |
1902 | void kvmppc_free_lpid(long lpid) | |
1903 | { | |
1904 | clear_bit(lpid, lpid_inuse); | |
1905 | } | |
2ba9f0d8 | 1906 | EXPORT_SYMBOL_GPL(kvmppc_free_lpid); |
043cc4d7 SW |
1907 | |
1908 | void kvmppc_init_lpid(unsigned long nr_lpids_param) | |
1909 | { | |
1910 | nr_lpids = min_t(unsigned long, KVMPPC_NR_LPIDS, nr_lpids_param); | |
1911 | memset(lpid_inuse, 0, sizeof(lpid_inuse)); | |
1912 | } | |
2ba9f0d8 | 1913 | EXPORT_SYMBOL_GPL(kvmppc_init_lpid); |
043cc4d7 | 1914 | |
bbf45ba5 HB |
1915 | int kvm_arch_init(void *opaque) |
1916 | { | |
1917 | return 0; | |
1918 | } | |
1919 | ||
478d6686 | 1920 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ppc_instr); |