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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
1da177e4 LT |
2 | /* |
3 | * PowerPC64 port by Mike Corrigan and Dave Engebretsen | |
4 | * {mikejc|engebret}@us.ibm.com | |
5 | * | |
6 | * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com> | |
7 | * | |
8 | * SMP scalability work: | |
9 | * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM | |
10 | * | |
11 | * Module name: htab.c | |
12 | * | |
13 | * Description: | |
14 | * PowerPC Hashed Page Table functions | |
1da177e4 LT |
15 | */ |
16 | ||
17 | #undef DEBUG | |
3c726f8d | 18 | #undef DEBUG_LOW |
1da177e4 | 19 | |
7f142661 | 20 | #define pr_fmt(fmt) "hash-mmu: " fmt |
1da177e4 LT |
21 | #include <linux/spinlock.h> |
22 | #include <linux/errno.h> | |
589ee628 | 23 | #include <linux/sched/mm.h> |
1da177e4 LT |
24 | #include <linux/proc_fs.h> |
25 | #include <linux/stat.h> | |
26 | #include <linux/sysctl.h> | |
66b15db6 | 27 | #include <linux/export.h> |
1da177e4 LT |
28 | #include <linux/ctype.h> |
29 | #include <linux/cache.h> | |
30 | #include <linux/init.h> | |
31 | #include <linux/signal.h> | |
95f72d1e | 32 | #include <linux/memblock.h> |
ba12eede | 33 | #include <linux/context_tracking.h> |
5556ecf5 | 34 | #include <linux/libfdt.h> |
92e3da3c | 35 | #include <linux/pkeys.h> |
45d0ba52 | 36 | #include <linux/hugetlb.h> |
1da177e4 | 37 | |
7644d581 | 38 | #include <asm/debugfs.h> |
1da177e4 LT |
39 | #include <asm/processor.h> |
40 | #include <asm/pgtable.h> | |
41 | #include <asm/mmu.h> | |
42 | #include <asm/mmu_context.h> | |
43 | #include <asm/page.h> | |
44 | #include <asm/types.h> | |
7c0f6ba6 | 45 | #include <linux/uaccess.h> |
1da177e4 | 46 | #include <asm/machdep.h> |
d9b2b2a2 | 47 | #include <asm/prom.h> |
1da177e4 LT |
48 | #include <asm/io.h> |
49 | #include <asm/eeh.h> | |
50 | #include <asm/tlb.h> | |
51 | #include <asm/cacheflush.h> | |
52 | #include <asm/cputable.h> | |
1da177e4 | 53 | #include <asm/sections.h> |
be3ebfe8 | 54 | #include <asm/copro.h> |
aa39be09 | 55 | #include <asm/udbg.h> |
b68a70c4 | 56 | #include <asm/code-patching.h> |
3ccc00a7 | 57 | #include <asm/fadump.h> |
f5339277 | 58 | #include <asm/firmware.h> |
bc2a9408 | 59 | #include <asm/tm.h> |
cfcb3d80 | 60 | #include <asm/trace.h> |
166dd7d3 | 61 | #include <asm/ps3.h> |
94171b19 | 62 | #include <asm/pte-walk.h> |
eacbb218 | 63 | #include <asm/asm-prototypes.h> |
1da177e4 | 64 | |
e4dccf90 CL |
65 | #include <mm/mmu_decl.h> |
66 | ||
1da177e4 LT |
67 | #ifdef DEBUG |
68 | #define DBG(fmt...) udbg_printf(fmt) | |
69 | #else | |
70 | #define DBG(fmt...) | |
71 | #endif | |
72 | ||
3c726f8d BH |
73 | #ifdef DEBUG_LOW |
74 | #define DBG_LOW(fmt...) udbg_printf(fmt) | |
75 | #else | |
76 | #define DBG_LOW(fmt...) | |
77 | #endif | |
78 | ||
79 | #define KB (1024) | |
80 | #define MB (1024*KB) | |
658013e9 | 81 | #define GB (1024L*MB) |
3c726f8d | 82 | |
1da177e4 LT |
83 | /* |
84 | * Note: pte --> Linux PTE | |
85 | * HPTE --> PowerPC Hashed Page Table Entry | |
86 | * | |
87 | * Execution context: | |
88 | * htab_initialize is called with the MMU off (of course), but | |
89 | * the kernel has been copied down to zero so it can directly | |
90 | * reference global data. At this point it is very difficult | |
91 | * to print debug info. | |
92 | * | |
93 | */ | |
94 | ||
799d6046 PM |
95 | static unsigned long _SDR1; |
96 | struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; | |
e1802b06 | 97 | EXPORT_SYMBOL_GPL(mmu_psize_defs); |
799d6046 | 98 | |
0eeede0c PM |
99 | u8 hpte_page_sizes[1 << LP_BITS]; |
100 | EXPORT_SYMBOL_GPL(hpte_page_sizes); | |
101 | ||
8e561e7e | 102 | struct hash_pte *htab_address; |
337a7128 | 103 | unsigned long htab_size_bytes; |
96e28449 | 104 | unsigned long htab_hash_mask; |
4ab79aa8 | 105 | EXPORT_SYMBOL_GPL(htab_hash_mask); |
3c726f8d | 106 | int mmu_linear_psize = MMU_PAGE_4K; |
8ca7a82f | 107 | EXPORT_SYMBOL_GPL(mmu_linear_psize); |
3c726f8d | 108 | int mmu_virtual_psize = MMU_PAGE_4K; |
bf72aeba | 109 | int mmu_vmalloc_psize = MMU_PAGE_4K; |
cec08e7a BH |
110 | #ifdef CONFIG_SPARSEMEM_VMEMMAP |
111 | int mmu_vmemmap_psize = MMU_PAGE_4K; | |
112 | #endif | |
bf72aeba | 113 | int mmu_io_psize = MMU_PAGE_4K; |
1189be65 | 114 | int mmu_kernel_ssize = MMU_SEGSIZE_256M; |
8ca7a82f | 115 | EXPORT_SYMBOL_GPL(mmu_kernel_ssize); |
1189be65 | 116 | int mmu_highuser_ssize = MMU_SEGSIZE_256M; |
584f8b71 | 117 | u16 mmu_slb_size = 64; |
4ab79aa8 | 118 | EXPORT_SYMBOL_GPL(mmu_slb_size); |
bf72aeba PM |
119 | #ifdef CONFIG_PPC_64K_PAGES |
120 | int mmu_ci_restrictions; | |
121 | #endif | |
370a908d BH |
122 | #ifdef CONFIG_DEBUG_PAGEALLOC |
123 | static u8 *linear_map_hash_slots; | |
124 | static unsigned long linear_map_hash_count; | |
ed166692 | 125 | static DEFINE_SPINLOCK(linear_map_hash_lock); |
370a908d | 126 | #endif /* CONFIG_DEBUG_PAGEALLOC */ |
7025776e BH |
127 | struct mmu_hash_ops mmu_hash_ops; |
128 | EXPORT_SYMBOL(mmu_hash_ops); | |
1da177e4 | 129 | |
47d99948 CL |
130 | /* |
131 | * These are definitions of page sizes arrays to be used when none | |
3c726f8d BH |
132 | * is provided by the firmware. |
133 | */ | |
1da177e4 | 134 | |
471d7ff8 NP |
135 | /* |
136 | * Fallback (4k pages only) | |
3c726f8d | 137 | */ |
471d7ff8 | 138 | static struct mmu_psize_def mmu_psize_defaults[] = { |
3c726f8d BH |
139 | [MMU_PAGE_4K] = { |
140 | .shift = 12, | |
141 | .sllp = 0, | |
b1022fbd | 142 | .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1}, |
3c726f8d BH |
143 | .avpnm = 0, |
144 | .tlbiel = 0, | |
145 | }, | |
146 | }; | |
147 | ||
47d99948 CL |
148 | /* |
149 | * POWER4, GPUL, POWER5 | |
3c726f8d BH |
150 | * |
151 | * Support for 16Mb large pages | |
152 | */ | |
09de9ff8 | 153 | static struct mmu_psize_def mmu_psize_defaults_gp[] = { |
3c726f8d BH |
154 | [MMU_PAGE_4K] = { |
155 | .shift = 12, | |
156 | .sllp = 0, | |
b1022fbd | 157 | .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1}, |
3c726f8d BH |
158 | .avpnm = 0, |
159 | .tlbiel = 1, | |
160 | }, | |
161 | [MMU_PAGE_16M] = { | |
162 | .shift = 24, | |
163 | .sllp = SLB_VSID_L, | |
b1022fbd AK |
164 | .penc = {[0 ... MMU_PAGE_16M - 1] = -1, [MMU_PAGE_16M] = 0, |
165 | [MMU_PAGE_16M + 1 ... MMU_PAGE_COUNT - 1] = -1 }, | |
3c726f8d BH |
166 | .avpnm = 0x1UL, |
167 | .tlbiel = 0, | |
168 | }, | |
169 | }; | |
170 | ||
dc47c0c1 AK |
171 | /* |
172 | * 'R' and 'C' update notes: | |
173 | * - Under pHyp or KVM, the updatepp path will not set C, thus it *will* | |
174 | * create writeable HPTEs without C set, because the hcall H_PROTECT | |
175 | * that we use in that case will not update C | |
176 | * - The above is however not a problem, because we also don't do that | |
177 | * fancy "no flush" variant of eviction and we use H_REMOVE which will | |
178 | * do the right thing and thus we don't have the race I described earlier | |
179 | * | |
180 | * - Under bare metal, we do have the race, so we need R and C set | |
181 | * - We make sure R is always set and never lost | |
182 | * - C is _PAGE_DIRTY, and *should* always be set for a writeable mapping | |
183 | */ | |
c6a3c495 | 184 | unsigned long htab_convert_pte_flags(unsigned long pteflags) |
bc033b63 | 185 | { |
c6a3c495 | 186 | unsigned long rflags = 0; |
bc033b63 BH |
187 | |
188 | /* _PAGE_EXEC -> NOEXEC */ | |
189 | if ((pteflags & _PAGE_EXEC) == 0) | |
190 | rflags |= HPTE_R_N; | |
c6a3c495 | 191 | /* |
e58e87ad | 192 | * PPP bits: |
1ec3f937 | 193 | * Linux uses slb key 0 for kernel and 1 for user. |
e58e87ad AK |
194 | * kernel RW areas are mapped with PPP=0b000 |
195 | * User area is mapped with PPP=0b010 for read/write | |
196 | * or PPP=0b011 for read-only (including writeable but clean pages). | |
bc033b63 | 197 | */ |
e58e87ad AK |
198 | if (pteflags & _PAGE_PRIVILEGED) { |
199 | /* | |
200 | * Kernel read only mapped with ppp bits 0b110 | |
201 | */ | |
984d7a1e AK |
202 | if (!(pteflags & _PAGE_WRITE)) { |
203 | if (mmu_has_feature(MMU_FTR_KERNEL_RO)) | |
204 | rflags |= (HPTE_R_PP0 | 0x2); | |
205 | else | |
206 | rflags |= 0x3; | |
207 | } | |
e58e87ad | 208 | } else { |
c7d54842 AK |
209 | if (pteflags & _PAGE_RWX) |
210 | rflags |= 0x2; | |
211 | if (!((pteflags & _PAGE_WRITE) && (pteflags & _PAGE_DIRTY))) | |
c6a3c495 AK |
212 | rflags |= 0x1; |
213 | } | |
c8c06f5a | 214 | /* |
dc47c0c1 AK |
215 | * We can't allow hardware to update hpte bits. Hence always |
216 | * set 'R' bit and set 'C' if it is a write fault | |
c8c06f5a | 217 | */ |
e568006b | 218 | rflags |= HPTE_R_R; |
dc47c0c1 AK |
219 | |
220 | if (pteflags & _PAGE_DIRTY) | |
221 | rflags |= HPTE_R_C; | |
40e8550a AK |
222 | /* |
223 | * Add in WIG bits | |
224 | */ | |
30bda41a AK |
225 | |
226 | if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_TOLERANT) | |
40e8550a | 227 | rflags |= HPTE_R_I; |
e568006b | 228 | else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT) |
30bda41a | 229 | rflags |= (HPTE_R_I | HPTE_R_G); |
e568006b AK |
230 | else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_SAO) |
231 | rflags |= (HPTE_R_W | HPTE_R_I | HPTE_R_M); | |
232 | else | |
233 | /* | |
234 | * Add memory coherence if cache inhibited is not set | |
235 | */ | |
236 | rflags |= HPTE_R_M; | |
40e8550a | 237 | |
a6590ca5 | 238 | rflags |= pte_to_hpte_pkey_bits(pteflags); |
40e8550a | 239 | return rflags; |
bc033b63 | 240 | } |
3c726f8d BH |
241 | |
242 | int htab_bolt_mapping(unsigned long vstart, unsigned long vend, | |
bc033b63 | 243 | unsigned long pstart, unsigned long prot, |
1189be65 | 244 | int psize, int ssize) |
1da177e4 | 245 | { |
3c726f8d BH |
246 | unsigned long vaddr, paddr; |
247 | unsigned int step, shift; | |
3c726f8d | 248 | int ret = 0; |
1da177e4 | 249 | |
3c726f8d BH |
250 | shift = mmu_psize_defs[psize].shift; |
251 | step = 1 << shift; | |
1da177e4 | 252 | |
bc033b63 BH |
253 | prot = htab_convert_pte_flags(prot); |
254 | ||
255 | DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n", | |
256 | vstart, vend, pstart, prot, psize, ssize); | |
257 | ||
3c726f8d BH |
258 | for (vaddr = vstart, paddr = pstart; vaddr < vend; |
259 | vaddr += step, paddr += step) { | |
370a908d | 260 | unsigned long hash, hpteg; |
1189be65 | 261 | unsigned long vsid = get_kernel_vsid(vaddr, ssize); |
5524a27d | 262 | unsigned long vpn = hpt_vpn(vaddr, vsid, ssize); |
9e88ba4e PM |
263 | unsigned long tprot = prot; |
264 | ||
c60ac569 AK |
265 | /* |
266 | * If we hit a bad address return error. | |
267 | */ | |
268 | if (!vsid) | |
269 | return -1; | |
9e88ba4e | 270 | /* Make kernel text executable */ |
549e8152 | 271 | if (overlaps_kernel_text(vaddr, vaddr + step)) |
9e88ba4e | 272 | tprot &= ~HPTE_R_N; |
1da177e4 | 273 | |
b18db0b8 AG |
274 | /* Make kvm guest trampolines executable */ |
275 | if (overlaps_kvm_tmp(vaddr, vaddr + step)) | |
276 | tprot &= ~HPTE_R_N; | |
277 | ||
429d2e83 MS |
278 | /* |
279 | * If relocatable, check if it overlaps interrupt vectors that | |
280 | * are copied down to real 0. For relocatable kernel | |
281 | * (e.g. kdump case) we copy interrupt vectors down to real | |
282 | * address 0. Mark that region as executable. This is | |
283 | * because on p8 system with relocation on exception feature | |
284 | * enabled, exceptions are raised with MMU (IR=DR=1) ON. Hence | |
285 | * in order to execute the interrupt handlers in virtual | |
286 | * mode the vector region need to be marked as executable. | |
287 | */ | |
288 | if ((PHYSICAL_START > MEMORY_START) && | |
289 | overlaps_interrupt_vector_text(vaddr, vaddr + step)) | |
290 | tprot &= ~HPTE_R_N; | |
291 | ||
5524a27d | 292 | hash = hpt_hash(vpn, shift, ssize); |
1da177e4 LT |
293 | hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP); |
294 | ||
7025776e BH |
295 | BUG_ON(!mmu_hash_ops.hpte_insert); |
296 | ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot, | |
297 | HPTE_V_BOLTED, psize, psize, | |
298 | ssize); | |
c30a4df3 | 299 | |
3c726f8d BH |
300 | if (ret < 0) |
301 | break; | |
e7df0d88 | 302 | |
370a908d | 303 | #ifdef CONFIG_DEBUG_PAGEALLOC |
e7df0d88 JK |
304 | if (debug_pagealloc_enabled() && |
305 | (paddr >> PAGE_SHIFT) < linear_map_hash_count) | |
370a908d BH |
306 | linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80; |
307 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
3c726f8d BH |
308 | } |
309 | return ret < 0 ? ret : 0; | |
310 | } | |
1da177e4 | 311 | |
ed5694a8 | 312 | int htab_remove_mapping(unsigned long vstart, unsigned long vend, |
f8c8803b BP |
313 | int psize, int ssize) |
314 | { | |
315 | unsigned long vaddr; | |
316 | unsigned int step, shift; | |
27828f98 DG |
317 | int rc; |
318 | int ret = 0; | |
f8c8803b BP |
319 | |
320 | shift = mmu_psize_defs[psize].shift; | |
321 | step = 1 << shift; | |
322 | ||
7025776e | 323 | if (!mmu_hash_ops.hpte_removebolted) |
abd0a0e7 | 324 | return -ENODEV; |
f8c8803b | 325 | |
27828f98 | 326 | for (vaddr = vstart; vaddr < vend; vaddr += step) { |
7025776e | 327 | rc = mmu_hash_ops.hpte_removebolted(vaddr, psize, ssize); |
27828f98 DG |
328 | if (rc == -ENOENT) { |
329 | ret = -ENOENT; | |
330 | continue; | |
331 | } | |
332 | if (rc < 0) | |
333 | return rc; | |
334 | } | |
52db9b44 | 335 | |
27828f98 | 336 | return ret; |
f8c8803b BP |
337 | } |
338 | ||
faf78829 OH |
339 | static bool disable_1tb_segments = false; |
340 | ||
341 | static int __init parse_disable_1tb_segments(char *p) | |
342 | { | |
343 | disable_1tb_segments = true; | |
344 | return 0; | |
345 | } | |
346 | early_param("disable_1tb_segments", parse_disable_1tb_segments); | |
347 | ||
1189be65 PM |
348 | static int __init htab_dt_scan_seg_sizes(unsigned long node, |
349 | const char *uname, int depth, | |
350 | void *data) | |
351 | { | |
9d0c4dfe RH |
352 | const char *type = of_get_flat_dt_prop(node, "device_type", NULL); |
353 | const __be32 *prop; | |
354 | int size = 0; | |
1189be65 PM |
355 | |
356 | /* We are scanning "cpu" nodes only */ | |
357 | if (type == NULL || strcmp(type, "cpu") != 0) | |
358 | return 0; | |
359 | ||
12f04f2b | 360 | prop = of_get_flat_dt_prop(node, "ibm,processor-segment-sizes", &size); |
1189be65 PM |
361 | if (prop == NULL) |
362 | return 0; | |
363 | for (; size >= 4; size -= 4, ++prop) { | |
12f04f2b | 364 | if (be32_to_cpu(prop[0]) == 40) { |
1189be65 | 365 | DBG("1T segment support detected\n"); |
faf78829 OH |
366 | |
367 | if (disable_1tb_segments) { | |
368 | DBG("1T segments disabled by command line\n"); | |
369 | break; | |
370 | } | |
371 | ||
44ae3ab3 | 372 | cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT; |
f5534004 | 373 | return 1; |
1189be65 | 374 | } |
1189be65 | 375 | } |
44ae3ab3 | 376 | cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B; |
1189be65 PM |
377 | return 0; |
378 | } | |
379 | ||
b1022fbd AK |
380 | static int __init get_idx_from_shift(unsigned int shift) |
381 | { | |
382 | int idx = -1; | |
383 | ||
384 | switch (shift) { | |
385 | case 0xc: | |
386 | idx = MMU_PAGE_4K; | |
387 | break; | |
388 | case 0x10: | |
389 | idx = MMU_PAGE_64K; | |
390 | break; | |
391 | case 0x14: | |
392 | idx = MMU_PAGE_1M; | |
393 | break; | |
394 | case 0x18: | |
395 | idx = MMU_PAGE_16M; | |
396 | break; | |
397 | case 0x22: | |
398 | idx = MMU_PAGE_16G; | |
399 | break; | |
400 | } | |
401 | return idx; | |
402 | } | |
403 | ||
3c726f8d BH |
404 | static int __init htab_dt_scan_page_sizes(unsigned long node, |
405 | const char *uname, int depth, | |
406 | void *data) | |
407 | { | |
9d0c4dfe RH |
408 | const char *type = of_get_flat_dt_prop(node, "device_type", NULL); |
409 | const __be32 *prop; | |
410 | int size = 0; | |
3c726f8d BH |
411 | |
412 | /* We are scanning "cpu" nodes only */ | |
413 | if (type == NULL || strcmp(type, "cpu") != 0) | |
414 | return 0; | |
415 | ||
12f04f2b | 416 | prop = of_get_flat_dt_prop(node, "ibm,segment-page-sizes", &size); |
9e34992a ME |
417 | if (!prop) |
418 | return 0; | |
419 | ||
420 | pr_info("Page sizes from device-tree:\n"); | |
421 | size /= 4; | |
422 | cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE); | |
423 | while(size > 0) { | |
424 | unsigned int base_shift = be32_to_cpu(prop[0]); | |
425 | unsigned int slbenc = be32_to_cpu(prop[1]); | |
426 | unsigned int lpnum = be32_to_cpu(prop[2]); | |
427 | struct mmu_psize_def *def; | |
428 | int idx, base_idx; | |
429 | ||
430 | size -= 3; prop += 3; | |
431 | base_idx = get_idx_from_shift(base_shift); | |
432 | if (base_idx < 0) { | |
433 | /* skip the pte encoding also */ | |
434 | prop += lpnum * 2; size -= lpnum * 2; | |
435 | continue; | |
436 | } | |
437 | def = &mmu_psize_defs[base_idx]; | |
438 | if (base_idx == MMU_PAGE_16M) | |
439 | cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE; | |
440 | ||
441 | def->shift = base_shift; | |
442 | if (base_shift <= 23) | |
443 | def->avpnm = 0; | |
444 | else | |
445 | def->avpnm = (1 << (base_shift - 23)) - 1; | |
446 | def->sllp = slbenc; | |
447 | /* | |
448 | * We don't know for sure what's up with tlbiel, so | |
449 | * for now we only set it for 4K and 64K pages | |
450 | */ | |
451 | if (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K) | |
452 | def->tlbiel = 1; | |
453 | else | |
454 | def->tlbiel = 0; | |
455 | ||
456 | while (size > 0 && lpnum) { | |
457 | unsigned int shift = be32_to_cpu(prop[0]); | |
458 | int penc = be32_to_cpu(prop[1]); | |
459 | ||
460 | prop += 2; size -= 2; | |
461 | lpnum--; | |
462 | ||
463 | idx = get_idx_from_shift(shift); | |
464 | if (idx < 0) | |
b1022fbd | 465 | continue; |
9e34992a ME |
466 | |
467 | if (penc == -1) | |
468 | pr_err("Invalid penc for base_shift=%d " | |
469 | "shift=%d\n", base_shift, shift); | |
470 | ||
471 | def->penc[idx] = penc; | |
472 | pr_info("base_shift=%d: shift=%d, sllp=0x%04lx," | |
473 | " avpnm=0x%08lx, tlbiel=%d, penc=%d\n", | |
474 | base_shift, shift, def->sllp, | |
475 | def->avpnm, def->tlbiel, def->penc[idx]); | |
1da177e4 | 476 | } |
3c726f8d | 477 | } |
9e34992a ME |
478 | |
479 | return 1; | |
3c726f8d BH |
480 | } |
481 | ||
e16a9c09 | 482 | #ifdef CONFIG_HUGETLB_PAGE |
47d99948 CL |
483 | /* |
484 | * Scan for 16G memory blocks that have been set aside for huge pages | |
658013e9 JT |
485 | * and reserve those blocks for 16G huge pages. |
486 | */ | |
487 | static int __init htab_dt_scan_hugepage_blocks(unsigned long node, | |
488 | const char *uname, int depth, | |
489 | void *data) { | |
9d0c4dfe RH |
490 | const char *type = of_get_flat_dt_prop(node, "device_type", NULL); |
491 | const __be64 *addr_prop; | |
492 | const __be32 *page_count_prop; | |
658013e9 JT |
493 | unsigned int expected_pages; |
494 | long unsigned int phys_addr; | |
495 | long unsigned int block_size; | |
496 | ||
497 | /* We are scanning "memory" nodes only */ | |
498 | if (type == NULL || strcmp(type, "memory") != 0) | |
499 | return 0; | |
500 | ||
47d99948 CL |
501 | /* |
502 | * This property is the log base 2 of the number of virtual pages that | |
503 | * will represent this memory block. | |
504 | */ | |
658013e9 JT |
505 | page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL); |
506 | if (page_count_prop == NULL) | |
507 | return 0; | |
12f04f2b | 508 | expected_pages = (1 << be32_to_cpu(page_count_prop[0])); |
658013e9 JT |
509 | addr_prop = of_get_flat_dt_prop(node, "reg", NULL); |
510 | if (addr_prop == NULL) | |
511 | return 0; | |
12f04f2b AB |
512 | phys_addr = be64_to_cpu(addr_prop[0]); |
513 | block_size = be64_to_cpu(addr_prop[1]); | |
658013e9 JT |
514 | if (block_size != (16 * GB)) |
515 | return 0; | |
516 | printk(KERN_INFO "Huge page(16GB) memory: " | |
517 | "addr = 0x%lX size = 0x%lX pages = %d\n", | |
518 | phys_addr, block_size, expected_pages); | |
23493c12 | 519 | if (phys_addr + block_size * expected_pages <= memblock_end_of_DRAM()) { |
95f72d1e | 520 | memblock_reserve(phys_addr, block_size * expected_pages); |
79cc38de | 521 | pseries_add_gpage(phys_addr, block_size, expected_pages); |
4792adba | 522 | } |
658013e9 JT |
523 | return 0; |
524 | } | |
e16a9c09 | 525 | #endif /* CONFIG_HUGETLB_PAGE */ |
658013e9 | 526 | |
b1022fbd AK |
527 | static void mmu_psize_set_default_penc(void) |
528 | { | |
529 | int bpsize, apsize; | |
530 | for (bpsize = 0; bpsize < MMU_PAGE_COUNT; bpsize++) | |
531 | for (apsize = 0; apsize < MMU_PAGE_COUNT; apsize++) | |
532 | mmu_psize_defs[bpsize].penc[apsize] = -1; | |
533 | } | |
534 | ||
9048e648 AG |
535 | #ifdef CONFIG_PPC_64K_PAGES |
536 | ||
537 | static bool might_have_hea(void) | |
538 | { | |
539 | /* | |
540 | * The HEA ethernet adapter requires awareness of the | |
541 | * GX bus. Without that awareness we can easily assume | |
542 | * we will never see an HEA ethernet device. | |
543 | */ | |
544 | #ifdef CONFIG_IBMEBUS | |
2b4e3ad8 | 545 | return !cpu_has_feature(CPU_FTR_ARCH_207S) && |
08bf75ba | 546 | firmware_has_feature(FW_FEATURE_SPLPAR); |
9048e648 AG |
547 | #else |
548 | return false; | |
549 | #endif | |
550 | } | |
551 | ||
552 | #endif /* #ifdef CONFIG_PPC_64K_PAGES */ | |
553 | ||
bacf9cf8 | 554 | static void __init htab_scan_page_sizes(void) |
3c726f8d BH |
555 | { |
556 | int rc; | |
557 | ||
b1022fbd AK |
558 | /* se the invalid penc to -1 */ |
559 | mmu_psize_set_default_penc(); | |
560 | ||
3c726f8d | 561 | /* Default to 4K pages only */ |
471d7ff8 NP |
562 | memcpy(mmu_psize_defs, mmu_psize_defaults, |
563 | sizeof(mmu_psize_defaults)); | |
3c726f8d BH |
564 | |
565 | /* | |
566 | * Try to find the available page sizes in the device-tree | |
567 | */ | |
568 | rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL); | |
b8f1b4f8 | 569 | if (rc == 0 && early_mmu_has_feature(MMU_FTR_16M_PAGE)) { |
bacf9cf8 ME |
570 | /* |
571 | * Nothing in the device-tree, but the CPU supports 16M pages, | |
572 | * so let's fallback on a known size list for 16M capable CPUs. | |
573 | */ | |
3c726f8d BH |
574 | memcpy(mmu_psize_defs, mmu_psize_defaults_gp, |
575 | sizeof(mmu_psize_defaults_gp)); | |
bacf9cf8 ME |
576 | } |
577 | ||
578 | #ifdef CONFIG_HUGETLB_PAGE | |
85975387 HB |
579 | if (!hugetlb_disabled) { |
580 | /* Reserve 16G huge page memory sections for huge pages */ | |
581 | of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL); | |
582 | } | |
bacf9cf8 ME |
583 | #endif /* CONFIG_HUGETLB_PAGE */ |
584 | } | |
585 | ||
0eeede0c PM |
586 | /* |
587 | * Fill in the hpte_page_sizes[] array. | |
588 | * We go through the mmu_psize_defs[] array looking for all the | |
589 | * supported base/actual page size combinations. Each combination | |
590 | * has a unique pagesize encoding (penc) value in the low bits of | |
591 | * the LP field of the HPTE. For actual page sizes less than 1MB, | |
592 | * some of the upper LP bits are used for RPN bits, meaning that | |
593 | * we need to fill in several entries in hpte_page_sizes[]. | |
594 | * | |
595 | * In diagrammatic form, with r = RPN bits and z = page size bits: | |
596 | * PTE LP actual page size | |
597 | * rrrr rrrz >=8KB | |
598 | * rrrr rrzz >=16KB | |
599 | * rrrr rzzz >=32KB | |
600 | * rrrr zzzz >=64KB | |
601 | * ... | |
602 | * | |
603 | * The zzzz bits are implementation-specific but are chosen so that | |
604 | * no encoding for a larger page size uses the same value in its | |
605 | * low-order N bits as the encoding for the 2^(12+N) byte page size | |
606 | * (if it exists). | |
607 | */ | |
608 | static void init_hpte_page_sizes(void) | |
609 | { | |
610 | long int ap, bp; | |
611 | long int shift, penc; | |
612 | ||
613 | for (bp = 0; bp < MMU_PAGE_COUNT; ++bp) { | |
614 | if (!mmu_psize_defs[bp].shift) | |
615 | continue; /* not a supported page size */ | |
616 | for (ap = bp; ap < MMU_PAGE_COUNT; ++ap) { | |
617 | penc = mmu_psize_defs[bp].penc[ap]; | |
10527e80 | 618 | if (penc == -1 || !mmu_psize_defs[ap].shift) |
0eeede0c PM |
619 | continue; |
620 | shift = mmu_psize_defs[ap].shift - LP_SHIFT; | |
621 | if (shift <= 0) | |
622 | continue; /* should never happen */ | |
623 | /* | |
624 | * For page sizes less than 1MB, this loop | |
625 | * replicates the entry for all possible values | |
626 | * of the rrrr bits. | |
627 | */ | |
628 | while (penc < (1 << LP_BITS)) { | |
629 | hpte_page_sizes[penc] = (ap << 4) | bp; | |
630 | penc += 1 << shift; | |
631 | } | |
632 | } | |
633 | } | |
634 | } | |
635 | ||
bacf9cf8 ME |
636 | static void __init htab_init_page_sizes(void) |
637 | { | |
0eeede0c PM |
638 | init_hpte_page_sizes(); |
639 | ||
e7df0d88 JK |
640 | if (!debug_pagealloc_enabled()) { |
641 | /* | |
642 | * Pick a size for the linear mapping. Currently, we only | |
643 | * support 16M, 1M and 4K which is the default | |
644 | */ | |
645 | if (mmu_psize_defs[MMU_PAGE_16M].shift) | |
646 | mmu_linear_psize = MMU_PAGE_16M; | |
647 | else if (mmu_psize_defs[MMU_PAGE_1M].shift) | |
648 | mmu_linear_psize = MMU_PAGE_1M; | |
649 | } | |
3c726f8d | 650 | |
bf72aeba | 651 | #ifdef CONFIG_PPC_64K_PAGES |
3c726f8d BH |
652 | /* |
653 | * Pick a size for the ordinary pages. Default is 4K, we support | |
bf72aeba PM |
654 | * 64K for user mappings and vmalloc if supported by the processor. |
655 | * We only use 64k for ioremap if the processor | |
656 | * (and firmware) support cache-inhibited large pages. | |
657 | * If not, we use 4k and set mmu_ci_restrictions so that | |
658 | * hash_page knows to switch processes that use cache-inhibited | |
659 | * mappings to 4k pages. | |
3c726f8d | 660 | */ |
bf72aeba | 661 | if (mmu_psize_defs[MMU_PAGE_64K].shift) { |
3c726f8d | 662 | mmu_virtual_psize = MMU_PAGE_64K; |
bf72aeba | 663 | mmu_vmalloc_psize = MMU_PAGE_64K; |
370a908d BH |
664 | if (mmu_linear_psize == MMU_PAGE_4K) |
665 | mmu_linear_psize = MMU_PAGE_64K; | |
44ae3ab3 | 666 | if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) { |
cfe666b1 | 667 | /* |
9048e648 AG |
668 | * When running on pSeries using 64k pages for ioremap |
669 | * would stop us accessing the HEA ethernet. So if we | |
670 | * have the chance of ever seeing one, stay at 4k. | |
cfe666b1 | 671 | */ |
2b4e3ad8 | 672 | if (!might_have_hea()) |
cfe666b1 PM |
673 | mmu_io_psize = MMU_PAGE_64K; |
674 | } else | |
bf72aeba PM |
675 | mmu_ci_restrictions = 1; |
676 | } | |
370a908d | 677 | #endif /* CONFIG_PPC_64K_PAGES */ |
3c726f8d | 678 | |
cec08e7a | 679 | #ifdef CONFIG_SPARSEMEM_VMEMMAP |
47d99948 CL |
680 | /* |
681 | * We try to use 16M pages for vmemmap if that is supported | |
cec08e7a BH |
682 | * and we have at least 1G of RAM at boot |
683 | */ | |
684 | if (mmu_psize_defs[MMU_PAGE_16M].shift && | |
95f72d1e | 685 | memblock_phys_mem_size() >= 0x40000000) |
cec08e7a BH |
686 | mmu_vmemmap_psize = MMU_PAGE_16M; |
687 | else if (mmu_psize_defs[MMU_PAGE_64K].shift) | |
688 | mmu_vmemmap_psize = MMU_PAGE_64K; | |
689 | else | |
690 | mmu_vmemmap_psize = MMU_PAGE_4K; | |
691 | #endif /* CONFIG_SPARSEMEM_VMEMMAP */ | |
692 | ||
bf72aeba | 693 | printk(KERN_DEBUG "Page orders: linear mapping = %d, " |
cec08e7a BH |
694 | "virtual = %d, io = %d" |
695 | #ifdef CONFIG_SPARSEMEM_VMEMMAP | |
696 | ", vmemmap = %d" | |
697 | #endif | |
698 | "\n", | |
3c726f8d | 699 | mmu_psize_defs[mmu_linear_psize].shift, |
bf72aeba | 700 | mmu_psize_defs[mmu_virtual_psize].shift, |
cec08e7a BH |
701 | mmu_psize_defs[mmu_io_psize].shift |
702 | #ifdef CONFIG_SPARSEMEM_VMEMMAP | |
703 | ,mmu_psize_defs[mmu_vmemmap_psize].shift | |
704 | #endif | |
705 | ); | |
3c726f8d BH |
706 | } |
707 | ||
708 | static int __init htab_dt_scan_pftsize(unsigned long node, | |
709 | const char *uname, int depth, | |
710 | void *data) | |
711 | { | |
9d0c4dfe RH |
712 | const char *type = of_get_flat_dt_prop(node, "device_type", NULL); |
713 | const __be32 *prop; | |
3c726f8d BH |
714 | |
715 | /* We are scanning "cpu" nodes only */ | |
716 | if (type == NULL || strcmp(type, "cpu") != 0) | |
717 | return 0; | |
718 | ||
12f04f2b | 719 | prop = of_get_flat_dt_prop(node, "ibm,pft-size", NULL); |
3c726f8d BH |
720 | if (prop != NULL) { |
721 | /* pft_size[0] is the NUMA CEC cookie */ | |
12f04f2b | 722 | ppc64_pft_size = be32_to_cpu(prop[1]); |
3c726f8d | 723 | return 1; |
1da177e4 | 724 | } |
3c726f8d | 725 | return 0; |
1da177e4 LT |
726 | } |
727 | ||
5c3c7ede | 728 | unsigned htab_shift_for_mem_size(unsigned long mem_size) |
3eac8c69 | 729 | { |
5c3c7ede DG |
730 | unsigned memshift = __ilog2(mem_size); |
731 | unsigned pshift = mmu_psize_defs[mmu_virtual_psize].shift; | |
732 | unsigned pteg_shift; | |
733 | ||
734 | /* round mem_size up to next power of 2 */ | |
735 | if ((1UL << memshift) < mem_size) | |
736 | memshift += 1; | |
3eac8c69 | 737 | |
5c3c7ede DG |
738 | /* aim for 2 pages / pteg */ |
739 | pteg_shift = memshift - (pshift + 1); | |
3eac8c69 | 740 | |
5c3c7ede DG |
741 | /* |
742 | * 2^11 PTEGS of 128 bytes each, ie. 2^18 bytes is the minimum htab | |
743 | * size permitted by the architecture. | |
744 | */ | |
745 | return max(pteg_shift + 7, 18U); | |
746 | } | |
747 | ||
748 | static unsigned long __init htab_get_table_size(void) | |
749 | { | |
47d99948 CL |
750 | /* |
751 | * If hash size isn't already provided by the platform, we try to | |
943ffb58 | 752 | * retrieve it from the device-tree. If it's not there neither, we |
3c726f8d | 753 | * calculate it now based on the total RAM size |
3eac8c69 | 754 | */ |
3c726f8d BH |
755 | if (ppc64_pft_size == 0) |
756 | of_scan_flat_dt(htab_dt_scan_pftsize, NULL); | |
3eac8c69 PM |
757 | if (ppc64_pft_size) |
758 | return 1UL << ppc64_pft_size; | |
759 | ||
5c3c7ede | 760 | return 1UL << htab_shift_for_mem_size(memblock_phys_mem_size()); |
3eac8c69 PM |
761 | } |
762 | ||
54b79248 | 763 | #ifdef CONFIG_MEMORY_HOTPLUG |
f172acbf | 764 | int resize_hpt_for_hotplug(unsigned long new_mem_size) |
438cc81a DG |
765 | { |
766 | unsigned target_hpt_shift; | |
767 | ||
768 | if (!mmu_hash_ops.resize_hpt) | |
f172acbf | 769 | return 0; |
438cc81a DG |
770 | |
771 | target_hpt_shift = htab_shift_for_mem_size(new_mem_size); | |
772 | ||
773 | /* | |
774 | * To avoid lots of HPT resizes if memory size is fluctuating | |
775 | * across a boundary, we deliberately have some hysterisis | |
776 | * here: we immediately increase the HPT size if the target | |
777 | * shift exceeds the current shift, but we won't attempt to | |
778 | * reduce unless the target shift is at least 2 below the | |
779 | * current shift | |
780 | */ | |
f172acbf LV |
781 | if (target_hpt_shift > ppc64_pft_size || |
782 | target_hpt_shift < ppc64_pft_size - 1) | |
783 | return mmu_hash_ops.resize_hpt(target_hpt_shift); | |
784 | ||
785 | return 0; | |
438cc81a DG |
786 | } |
787 | ||
29ab6c47 | 788 | int hash__create_section_mapping(unsigned long start, unsigned long end, int nid) |
54b79248 | 789 | { |
e0909392 AK |
790 | int rc; |
791 | ||
792 | if (end >= H_VMALLOC_START) { | |
f341d897 | 793 | pr_warn("Outside the supported range\n"); |
e0909392 AK |
794 | return -1; |
795 | } | |
796 | ||
797 | rc = htab_bolt_mapping(start, end, __pa(start), | |
798 | pgprot_val(PAGE_KERNEL), mmu_linear_psize, | |
799 | mmu_kernel_ssize); | |
1dace6c6 DG |
800 | |
801 | if (rc < 0) { | |
802 | int rc2 = htab_remove_mapping(start, end, mmu_linear_psize, | |
803 | mmu_kernel_ssize); | |
804 | BUG_ON(rc2 && (rc2 != -ENOENT)); | |
805 | } | |
806 | return rc; | |
54b79248 | 807 | } |
f8c8803b | 808 | |
32b53c01 | 809 | int hash__remove_section_mapping(unsigned long start, unsigned long end) |
f8c8803b | 810 | { |
abd0a0e7 DG |
811 | int rc = htab_remove_mapping(start, end, mmu_linear_psize, |
812 | mmu_kernel_ssize); | |
813 | WARN_ON(rc < 0); | |
814 | return rc; | |
f8c8803b | 815 | } |
54b79248 MK |
816 | #endif /* CONFIG_MEMORY_HOTPLUG */ |
817 | ||
50de596d | 818 | static void __init hash_init_partition_table(phys_addr_t hash_table, |
4b7a3504 | 819 | unsigned long htab_size) |
50de596d | 820 | { |
9d661958 | 821 | mmu_partition_table_init(); |
50de596d AK |
822 | |
823 | /* | |
9d661958 PM |
824 | * PS field (VRMA page size) is not used for LPID 0, hence set to 0. |
825 | * For now, UPRT is 0 and we have no segment table. | |
50de596d | 826 | */ |
4b7a3504 | 827 | htab_size = __ilog2(htab_size) - 18; |
9d661958 | 828 | mmu_partition_table_set_entry(0, hash_table | htab_size, 0); |
56547411 | 829 | pr_info("Partition table %p\n", partition_tb); |
50de596d AK |
830 | } |
831 | ||
757c74d2 | 832 | static void __init htab_initialize(void) |
1da177e4 | 833 | { |
337a7128 | 834 | unsigned long table; |
1da177e4 | 835 | unsigned long pteg_count; |
9e88ba4e | 836 | unsigned long prot; |
5556ecf5 | 837 | unsigned long base = 0, size = 0; |
28be7072 | 838 | struct memblock_region *reg; |
3c726f8d | 839 | |
1da177e4 LT |
840 | DBG(" -> htab_initialize()\n"); |
841 | ||
44ae3ab3 | 842 | if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) { |
1189be65 PM |
843 | mmu_kernel_ssize = MMU_SEGSIZE_1T; |
844 | mmu_highuser_ssize = MMU_SEGSIZE_1T; | |
845 | printk(KERN_INFO "Using 1TB segments\n"); | |
846 | } | |
847 | ||
1da177e4 LT |
848 | /* |
849 | * Calculate the required size of the htab. We want the number of | |
850 | * PTEGs to equal one half the number of real pages. | |
851 | */ | |
3c726f8d | 852 | htab_size_bytes = htab_get_table_size(); |
1da177e4 LT |
853 | pteg_count = htab_size_bytes >> 7; |
854 | ||
1da177e4 LT |
855 | htab_hash_mask = pteg_count - 1; |
856 | ||
5556ecf5 BH |
857 | if (firmware_has_feature(FW_FEATURE_LPAR) || |
858 | firmware_has_feature(FW_FEATURE_PS3_LV1)) { | |
1da177e4 LT |
859 | /* Using a hypervisor which owns the htab */ |
860 | htab_address = NULL; | |
861 | _SDR1 = 0; | |
dbfcf3cb PM |
862 | /* |
863 | * On POWER9, we need to do a H_REGISTER_PROC_TBL hcall | |
864 | * to inform the hypervisor that we wish to use the HPT. | |
865 | */ | |
866 | if (cpu_has_feature(CPU_FTR_ARCH_300)) | |
867 | register_process_table(0, 0, 0); | |
3ccc00a7 MS |
868 | #ifdef CONFIG_FA_DUMP |
869 | /* | |
870 | * If firmware assisted dump is active firmware preserves | |
871 | * the contents of htab along with entire partition memory. | |
872 | * Clear the htab if firmware assisted dump is active so | |
873 | * that we dont end up using old mappings. | |
874 | */ | |
7025776e BH |
875 | if (is_fadump_active() && mmu_hash_ops.hpte_clear_all) |
876 | mmu_hash_ops.hpte_clear_all(); | |
3ccc00a7 | 877 | #endif |
1da177e4 | 878 | } else { |
5556ecf5 BH |
879 | unsigned long limit = MEMBLOCK_ALLOC_ANYWHERE; |
880 | ||
881 | #ifdef CONFIG_PPC_CELL | |
882 | /* | |
883 | * Cell may require the hash table down low when using the | |
884 | * Axon IOMMU in order to fit the dynamic region over it, see | |
885 | * comments in cell/iommu.c | |
1da177e4 | 886 | */ |
5556ecf5 | 887 | if (fdt_subnode_offset(initial_boot_params, 0, "axon") > 0) { |
31bf1119 | 888 | limit = 0x80000000; |
5556ecf5 BH |
889 | pr_info("Hash table forced below 2G for Axon IOMMU\n"); |
890 | } | |
891 | #endif /* CONFIG_PPC_CELL */ | |
41d824bf | 892 | |
0ba9e6ed MR |
893 | table = memblock_phys_alloc_range(htab_size_bytes, |
894 | htab_size_bytes, | |
895 | 0, limit); | |
896 | if (!table) | |
897 | panic("ERROR: Failed to allocate %pa bytes below %pa\n", | |
898 | &htab_size_bytes, &limit); | |
1da177e4 LT |
899 | |
900 | DBG("Hash table allocated at %lx, size: %lx\n", table, | |
901 | htab_size_bytes); | |
902 | ||
70267a7f | 903 | htab_address = __va(table); |
1da177e4 LT |
904 | |
905 | /* htab absolute addr + encoded htabsize */ | |
4b7a3504 | 906 | _SDR1 = table + __ilog2(htab_size_bytes) - 18; |
1da177e4 LT |
907 | |
908 | /* Initialize the HPT with no entries */ | |
909 | memset((void *)table, 0, htab_size_bytes); | |
799d6046 | 910 | |
50de596d AK |
911 | if (!cpu_has_feature(CPU_FTR_ARCH_300)) |
912 | /* Set SDR1 */ | |
913 | mtspr(SPRN_SDR1, _SDR1); | |
914 | else | |
4b7a3504 | 915 | hash_init_partition_table(table, htab_size_bytes); |
1da177e4 LT |
916 | } |
917 | ||
f5ea64dc | 918 | prot = pgprot_val(PAGE_KERNEL); |
1da177e4 | 919 | |
370a908d | 920 | #ifdef CONFIG_DEBUG_PAGEALLOC |
e7df0d88 JK |
921 | if (debug_pagealloc_enabled()) { |
922 | linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT; | |
f806714f MR |
923 | linear_map_hash_slots = memblock_alloc_try_nid( |
924 | linear_map_hash_count, 1, MEMBLOCK_LOW_LIMIT, | |
925 | ppc64_rma_size, NUMA_NO_NODE); | |
8a7f97b9 MR |
926 | if (!linear_map_hash_slots) |
927 | panic("%s: Failed to allocate %lu bytes max_addr=%pa\n", | |
928 | __func__, linear_map_hash_count, &ppc64_rma_size); | |
e7df0d88 | 929 | } |
370a908d BH |
930 | #endif /* CONFIG_DEBUG_PAGEALLOC */ |
931 | ||
1da177e4 | 932 | /* create bolted the linear mapping in the hash table */ |
28be7072 BH |
933 | for_each_memblock(memory, reg) { |
934 | base = (unsigned long)__va(reg->base); | |
935 | size = reg->size; | |
1da177e4 | 936 | |
5c339919 | 937 | DBG("creating mapping for region: %lx..%lx (prot: %lx)\n", |
9e88ba4e | 938 | base, size, prot); |
1da177e4 | 939 | |
e0909392 | 940 | if ((base + size) >= H_VMALLOC_START) { |
f341d897 | 941 | pr_warn("Outside the supported range\n"); |
e0909392 AK |
942 | continue; |
943 | } | |
944 | ||
caf80e57 | 945 | BUG_ON(htab_bolt_mapping(base, base + size, __pa(base), |
9e88ba4e | 946 | prot, mmu_linear_psize, mmu_kernel_ssize)); |
e63075a3 BH |
947 | } |
948 | memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE); | |
1da177e4 LT |
949 | |
950 | /* | |
951 | * If we have a memory_limit and we've allocated TCEs then we need to | |
952 | * explicitly map the TCE area at the top of RAM. We also cope with the | |
953 | * case that the TCEs start below memory_limit. | |
954 | * tce_alloc_start/end are 16MB aligned so the mapping should work | |
955 | * for either 4K or 16MB pages. | |
956 | */ | |
957 | if (tce_alloc_start) { | |
b5666f70 ME |
958 | tce_alloc_start = (unsigned long)__va(tce_alloc_start); |
959 | tce_alloc_end = (unsigned long)__va(tce_alloc_end); | |
1da177e4 LT |
960 | |
961 | if (base + size >= tce_alloc_start) | |
962 | tce_alloc_start = base + size + 1; | |
963 | ||
caf80e57 | 964 | BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end, |
bc033b63 | 965 | __pa(tce_alloc_start), prot, |
1189be65 | 966 | mmu_linear_psize, mmu_kernel_ssize)); |
1da177e4 LT |
967 | } |
968 | ||
7d0daae4 | 969 | |
1da177e4 LT |
970 | DBG(" <- htab_initialize()\n"); |
971 | } | |
972 | #undef KB | |
973 | #undef MB | |
1da177e4 | 974 | |
bacf9cf8 ME |
975 | void __init hash__early_init_devtree(void) |
976 | { | |
977 | /* Initialize segment sizes */ | |
978 | of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL); | |
979 | ||
980 | /* Initialize page sizes */ | |
981 | htab_scan_page_sizes(); | |
982 | } | |
983 | ||
70110186 | 984 | struct hash_mm_context init_hash_mm_context; |
756d08d1 | 985 | void __init hash__early_init_mmu(void) |
799d6046 | 986 | { |
9d2edb18 | 987 | #ifndef CONFIG_PPC_64K_PAGES |
6aa59f51 | 988 | /* |
9d2edb18 | 989 | * We have code in __hash_page_4K() and elsewhere, which assumes it can |
6aa59f51 AK |
990 | * do the following: |
991 | * new_pte |= (slot << H_PAGE_F_GIX_SHIFT) & (H_PAGE_F_SECOND | H_PAGE_F_GIX); | |
992 | * | |
993 | * Where the slot number is between 0-15, and values of 8-15 indicate | |
994 | * the secondary bucket. For that code to work H_PAGE_F_SECOND and | |
995 | * H_PAGE_F_GIX must occupy four contiguous bits in the PTE, and | |
996 | * H_PAGE_F_SECOND must be placed above H_PAGE_F_GIX. Assert that here | |
997 | * with a BUILD_BUG_ON(). | |
998 | */ | |
999 | BUILD_BUG_ON(H_PAGE_F_SECOND != (1ul << (H_PAGE_F_GIX_SHIFT + 3))); | |
9d2edb18 | 1000 | #endif /* CONFIG_PPC_64K_PAGES */ |
6aa59f51 | 1001 | |
bacf9cf8 ME |
1002 | htab_init_page_sizes(); |
1003 | ||
dd1842a2 AK |
1004 | /* |
1005 | * initialize page table size | |
1006 | */ | |
5ed7ecd0 AK |
1007 | __pte_frag_nr = H_PTE_FRAG_NR; |
1008 | __pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT; | |
8a6c697b AK |
1009 | __pmd_frag_nr = H_PMD_FRAG_NR; |
1010 | __pmd_frag_size_shift = H_PMD_FRAG_SIZE_SHIFT; | |
5ed7ecd0 | 1011 | |
dd1842a2 AK |
1012 | __pte_index_size = H_PTE_INDEX_SIZE; |
1013 | __pmd_index_size = H_PMD_INDEX_SIZE; | |
1014 | __pud_index_size = H_PUD_INDEX_SIZE; | |
1015 | __pgd_index_size = H_PGD_INDEX_SIZE; | |
fae22116 | 1016 | __pud_cache_index = H_PUD_CACHE_INDEX; |
dd1842a2 AK |
1017 | __pte_table_size = H_PTE_TABLE_SIZE; |
1018 | __pmd_table_size = H_PMD_TABLE_SIZE; | |
1019 | __pud_table_size = H_PUD_TABLE_SIZE; | |
1020 | __pgd_table_size = H_PGD_TABLE_SIZE; | |
a2f41eb9 AK |
1021 | /* |
1022 | * 4k use hugepd format, so for hash set then to | |
1023 | * zero | |
1024 | */ | |
da7ad366 AK |
1025 | __pmd_val_bits = HASH_PMD_VAL_BITS; |
1026 | __pud_val_bits = HASH_PUD_VAL_BITS; | |
1027 | __pgd_val_bits = HASH_PGD_VAL_BITS; | |
d6a9996e AK |
1028 | |
1029 | __kernel_virt_start = H_KERN_VIRT_START; | |
d6a9996e AK |
1030 | __vmalloc_start = H_VMALLOC_START; |
1031 | __vmalloc_end = H_VMALLOC_END; | |
63ee9b2f | 1032 | __kernel_io_start = H_KERN_IO_START; |
a35a3c6f | 1033 | __kernel_io_end = H_KERN_IO_END; |
0034d395 | 1034 | vmemmap = (struct page *)H_VMEMMAP_START; |
d6a9996e AK |
1035 | ioremap_bot = IOREMAP_BASE; |
1036 | ||
bfa37087 DS |
1037 | #ifdef CONFIG_PCI |
1038 | pci_io_base = ISA_IO_BASE; | |
1039 | #endif | |
1040 | ||
166dd7d3 BH |
1041 | /* Select appropriate backend */ |
1042 | if (firmware_has_feature(FW_FEATURE_PS3_LV1)) | |
1043 | ps3_early_mm_init(); | |
1044 | else if (firmware_has_feature(FW_FEATURE_LPAR)) | |
6364e84e | 1045 | hpte_init_pseries(); |
fbef66f0 | 1046 | else if (IS_ENABLED(CONFIG_PPC_NATIVE)) |
166dd7d3 BH |
1047 | hpte_init_native(); |
1048 | ||
7353644f ME |
1049 | if (!mmu_hash_ops.hpte_insert) |
1050 | panic("hash__early_init_mmu: No MMU hash ops defined!\n"); | |
1051 | ||
47d99948 CL |
1052 | /* |
1053 | * Initialize the MMU Hash table and create the linear mapping | |
376af594 ME |
1054 | * of memory. Has to be done before SLB initialization as this is |
1055 | * currently where the page size encoding is obtained. | |
757c74d2 BH |
1056 | */ |
1057 | htab_initialize(); | |
1058 | ||
70110186 | 1059 | init_mm.context.hash_context = &init_hash_mm_context; |
5953fb4f | 1060 | mm_ctx_set_slb_addr_limit(&init_mm.context, SLB_ADDR_LIMIT_DEFAULT); |
67fda38f | 1061 | |
56547411 | 1062 | pr_info("Initializing hash mmu with SLB\n"); |
376af594 | 1063 | /* Initialize SLB management */ |
13b3d13b | 1064 | slb_initialize(); |
d4748276 NP |
1065 | |
1066 | if (cpu_has_feature(CPU_FTR_ARCH_206) | |
1067 | && cpu_has_feature(CPU_FTR_HVMODE)) | |
1068 | tlbiel_all(); | |
757c74d2 BH |
1069 | } |
1070 | ||
1071 | #ifdef CONFIG_SMP | |
756d08d1 | 1072 | void hash__early_init_mmu_secondary(void) |
757c74d2 BH |
1073 | { |
1074 | /* Initialize hash table for that CPU */ | |
b5dcc609 | 1075 | if (!firmware_has_feature(FW_FEATURE_LPAR)) { |
cac4a185 | 1076 | |
b5dcc609 AK |
1077 | if (!cpu_has_feature(CPU_FTR_ARCH_300)) |
1078 | mtspr(SPRN_SDR1, _SDR1); | |
1079 | else | |
1080 | mtspr(SPRN_PTCR, | |
1081 | __pa(partition_tb) | (PATB_SIZE_SHIFT - 12)); | |
1082 | } | |
376af594 | 1083 | /* Initialize SLB */ |
13b3d13b | 1084 | slb_initialize(); |
d4748276 NP |
1085 | |
1086 | if (cpu_has_feature(CPU_FTR_ARCH_206) | |
1087 | && cpu_has_feature(CPU_FTR_HVMODE)) | |
1088 | tlbiel_all(); | |
799d6046 | 1089 | } |
757c74d2 | 1090 | #endif /* CONFIG_SMP */ |
799d6046 | 1091 | |
1da177e4 LT |
1092 | /* |
1093 | * Called by asm hashtable.S for doing lazy icache flush | |
1094 | */ | |
1095 | unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap) | |
1096 | { | |
1097 | struct page *page; | |
1098 | ||
76c8e25b BH |
1099 | if (!pfn_valid(pte_pfn(pte))) |
1100 | return pp; | |
1101 | ||
1da177e4 LT |
1102 | page = pte_page(pte); |
1103 | ||
1104 | /* page is dirty */ | |
1105 | if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) { | |
1106 | if (trap == 0x400) { | |
0895ecda | 1107 | flush_dcache_icache_page(page); |
1da177e4 LT |
1108 | set_bit(PG_arch_1, &page->flags); |
1109 | } else | |
3c726f8d | 1110 | pp |= HPTE_R_N; |
1da177e4 LT |
1111 | } |
1112 | return pp; | |
1113 | } | |
1114 | ||
3a8247cc | 1115 | #ifdef CONFIG_PPC_MM_SLICES |
54be0b9c | 1116 | static unsigned int get_paca_psize(unsigned long addr) |
3a8247cc | 1117 | { |
15472423 | 1118 | unsigned char *psizes; |
7aa0727f | 1119 | unsigned long index, mask_index; |
3a8247cc PM |
1120 | |
1121 | if (addr < SLICE_LOW_TOP) { | |
54be0b9c | 1122 | psizes = get_paca()->mm_ctx_low_slices_psize; |
3a8247cc | 1123 | index = GET_LOW_SLICE_INDEX(addr); |
15472423 | 1124 | } else { |
54be0b9c | 1125 | psizes = get_paca()->mm_ctx_high_slices_psize; |
15472423 | 1126 | index = GET_HIGH_SLICE_INDEX(addr); |
3a8247cc | 1127 | } |
7aa0727f | 1128 | mask_index = index & 0x1; |
15472423 | 1129 | return (psizes[index >> 1] >> (mask_index * 4)) & 0xF; |
3a8247cc PM |
1130 | } |
1131 | ||
1132 | #else | |
54be0b9c | 1133 | unsigned int get_paca_psize(unsigned long addr) |
3a8247cc | 1134 | { |
54be0b9c | 1135 | return get_paca()->mm_ctx_user_psize; |
3a8247cc PM |
1136 | } |
1137 | #endif | |
1138 | ||
721151d0 PM |
1139 | /* |
1140 | * Demote a segment to using 4k pages. | |
1141 | * For now this makes the whole process use 4k pages. | |
1142 | */ | |
721151d0 | 1143 | #ifdef CONFIG_PPC_64K_PAGES |
fa28237c | 1144 | void demote_segment_4k(struct mm_struct *mm, unsigned long addr) |
16f1c746 | 1145 | { |
54be0b9c | 1146 | if (get_slice_psize(mm, addr) == MMU_PAGE_4K) |
721151d0 | 1147 | return; |
3a8247cc | 1148 | slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K); |
be3ebfe8 | 1149 | copro_flush_all_slbs(mm); |
54be0b9c ME |
1150 | if ((get_paca_psize(addr) != MMU_PAGE_4K) && (current->mm == mm)) { |
1151 | ||
1152 | copy_mm_to_paca(mm); | |
94ee4272 | 1153 | slb_flush_and_restore_bolted(); |
54be0b9c | 1154 | } |
721151d0 | 1155 | } |
16f1c746 | 1156 | #endif /* CONFIG_PPC_64K_PAGES */ |
721151d0 | 1157 | |
fa28237c PM |
1158 | #ifdef CONFIG_PPC_SUBPAGE_PROT |
1159 | /* | |
1160 | * This looks up a 2-bit protection code for a 4k subpage of a 64k page. | |
1161 | * Userspace sets the subpage permissions using the subpage_prot system call. | |
1162 | * | |
1163 | * Result is 0: full permissions, _PAGE_RW: read-only, | |
73a1441a | 1164 | * _PAGE_RWX: no access. |
fa28237c | 1165 | */ |
d28513bc | 1166 | static int subpage_protection(struct mm_struct *mm, unsigned long ea) |
fa28237c | 1167 | { |
60458fba | 1168 | struct subpage_prot_table *spt = mm_ctx_subpage_prot(&mm->context); |
fa28237c PM |
1169 | u32 spp = 0; |
1170 | u32 **sbpm, *sbpp; | |
1171 | ||
ef629cc5 AK |
1172 | if (!spt) |
1173 | return 0; | |
1174 | ||
fa28237c PM |
1175 | if (ea >= spt->maxaddr) |
1176 | return 0; | |
b0d436c7 | 1177 | if (ea < 0x100000000UL) { |
fa28237c PM |
1178 | /* addresses below 4GB use spt->low_prot */ |
1179 | sbpm = spt->low_prot; | |
1180 | } else { | |
1181 | sbpm = spt->protptrs[ea >> SBP_L3_SHIFT]; | |
1182 | if (!sbpm) | |
1183 | return 0; | |
1184 | } | |
1185 | sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)]; | |
1186 | if (!sbpp) | |
1187 | return 0; | |
1188 | spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)]; | |
1189 | ||
1190 | /* extract 2-bit bitfield for this 4k subpage */ | |
1191 | spp >>= 30 - 2 * ((ea >> 12) & 0xf); | |
1192 | ||
73a1441a AK |
1193 | /* |
1194 | * 0 -> full premission | |
1195 | * 1 -> Read only | |
1196 | * 2 -> no access. | |
1197 | * We return the flag that need to be cleared. | |
1198 | */ | |
1199 | spp = ((spp & 2) ? _PAGE_RWX : 0) | ((spp & 1) ? _PAGE_WRITE : 0); | |
fa28237c PM |
1200 | return spp; |
1201 | } | |
1202 | ||
1203 | #else /* CONFIG_PPC_SUBPAGE_PROT */ | |
d28513bc | 1204 | static inline int subpage_protection(struct mm_struct *mm, unsigned long ea) |
fa28237c PM |
1205 | { |
1206 | return 0; | |
1207 | } | |
1208 | #endif | |
1209 | ||
4b8692c0 BH |
1210 | void hash_failure_debug(unsigned long ea, unsigned long access, |
1211 | unsigned long vsid, unsigned long trap, | |
d8139ebf | 1212 | int ssize, int psize, int lpsize, unsigned long pte) |
4b8692c0 BH |
1213 | { |
1214 | if (!printk_ratelimit()) | |
1215 | return; | |
1216 | pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n", | |
1217 | ea, access, current->comm); | |
d8139ebf AK |
1218 | pr_info(" trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n", |
1219 | trap, vsid, ssize, psize, lpsize, pte); | |
4b8692c0 BH |
1220 | } |
1221 | ||
54be0b9c ME |
1222 | static void check_paca_psize(unsigned long ea, struct mm_struct *mm, |
1223 | int psize, bool user_region) | |
1224 | { | |
1225 | if (user_region) { | |
1226 | if (psize != get_paca_psize(ea)) { | |
1227 | copy_mm_to_paca(mm); | |
94ee4272 | 1228 | slb_flush_and_restore_bolted(); |
54be0b9c ME |
1229 | } |
1230 | } else if (get_paca()->vmalloc_sllp != | |
1231 | mmu_psize_defs[mmu_vmalloc_psize].sllp) { | |
1232 | get_paca()->vmalloc_sllp = | |
1233 | mmu_psize_defs[mmu_vmalloc_psize].sllp; | |
1234 | slb_vmalloc_update(); | |
1235 | } | |
1236 | } | |
1237 | ||
47d99948 CL |
1238 | /* |
1239 | * Result code is: | |
1da177e4 LT |
1240 | * 0 - handled |
1241 | * 1 - normal page fault | |
1242 | * -1 - critical hash insertion error | |
fa28237c | 1243 | * -2 - access not permitted by subpage protection mechanism |
1da177e4 | 1244 | */ |
aefa5688 AK |
1245 | int hash_page_mm(struct mm_struct *mm, unsigned long ea, |
1246 | unsigned long access, unsigned long trap, | |
1247 | unsigned long flags) | |
1da177e4 | 1248 | { |
891121e6 | 1249 | bool is_thp; |
ba12eede | 1250 | enum ctx_state prev_state = exception_enter(); |
a1128f8f | 1251 | pgd_t *pgdir; |
1da177e4 | 1252 | unsigned long vsid; |
1da177e4 | 1253 | pte_t *ptep; |
a4fe3ce7 | 1254 | unsigned hugeshift; |
aefa5688 | 1255 | int rc, user_region = 0; |
1189be65 | 1256 | int psize, ssize; |
1da177e4 | 1257 | |
3c726f8d BH |
1258 | DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n", |
1259 | ea, access, trap); | |
cfcb3d80 | 1260 | trace_hash_fault(ea, access, trap); |
1f8d419e | 1261 | |
3c726f8d | 1262 | /* Get region & vsid */ |
0034d395 | 1263 | switch (get_region_id(ea)) { |
1da177e4 LT |
1264 | case USER_REGION_ID: |
1265 | user_region = 1; | |
3c726f8d BH |
1266 | if (! mm) { |
1267 | DBG_LOW(" user region with no mm !\n"); | |
ba12eede LZ |
1268 | rc = 1; |
1269 | goto bail; | |
3c726f8d | 1270 | } |
54be0b9c | 1271 | psize = get_slice_psize(mm, ea); |
1189be65 | 1272 | ssize = user_segment_size(ea); |
f384796c | 1273 | vsid = get_user_vsid(&mm->context, ea, ssize); |
1da177e4 | 1274 | break; |
1da177e4 | 1275 | case VMALLOC_REGION_ID: |
1189be65 | 1276 | vsid = get_kernel_vsid(ea, mmu_kernel_ssize); |
0034d395 AK |
1277 | psize = mmu_vmalloc_psize; |
1278 | ssize = mmu_kernel_ssize; | |
1279 | break; | |
1280 | ||
1281 | case IO_REGION_ID: | |
1282 | vsid = get_kernel_vsid(ea, mmu_kernel_ssize); | |
1283 | psize = mmu_io_psize; | |
1189be65 | 1284 | ssize = mmu_kernel_ssize; |
1da177e4 | 1285 | break; |
1da177e4 | 1286 | default: |
47d99948 CL |
1287 | /* |
1288 | * Not a valid range | |
1289 | * Send the problem up to do_page_fault() | |
1da177e4 | 1290 | */ |
ba12eede LZ |
1291 | rc = 1; |
1292 | goto bail; | |
1da177e4 | 1293 | } |
3c726f8d | 1294 | DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid); |
1da177e4 | 1295 | |
c60ac569 AK |
1296 | /* Bad address. */ |
1297 | if (!vsid) { | |
1298 | DBG_LOW("Bad address!\n"); | |
ba12eede LZ |
1299 | rc = 1; |
1300 | goto bail; | |
c60ac569 | 1301 | } |
3c726f8d | 1302 | /* Get pgdir */ |
1da177e4 | 1303 | pgdir = mm->pgd; |
ba12eede LZ |
1304 | if (pgdir == NULL) { |
1305 | rc = 1; | |
1306 | goto bail; | |
1307 | } | |
1da177e4 | 1308 | |
3c726f8d | 1309 | /* Check CPU locality */ |
b426e4bd | 1310 | if (user_region && mm_is_thread_local(mm)) |
aefa5688 | 1311 | flags |= HPTE_LOCAL_UPDATE; |
1da177e4 | 1312 | |
16c2d476 | 1313 | #ifndef CONFIG_PPC_64K_PAGES |
47d99948 CL |
1314 | /* |
1315 | * If we use 4K pages and our psize is not 4K, then we might | |
a4fe3ce7 DG |
1316 | * be hitting a special driver mapping, and need to align the |
1317 | * address before we fetch the PTE. | |
1318 | * | |
1319 | * It could also be a hugepage mapping, in which case this is | |
1320 | * not necessary, but it's not harmful, either. | |
16c2d476 BH |
1321 | */ |
1322 | if (psize != MMU_PAGE_4K) | |
1323 | ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1); | |
1324 | #endif /* CONFIG_PPC_64K_PAGES */ | |
1325 | ||
3c726f8d | 1326 | /* Get PTE and page size from page tables */ |
94171b19 | 1327 | ptep = find_linux_pte(pgdir, ea, &is_thp, &hugeshift); |
3c726f8d BH |
1328 | if (ptep == NULL || !pte_present(*ptep)) { |
1329 | DBG_LOW(" no PTE !\n"); | |
ba12eede LZ |
1330 | rc = 1; |
1331 | goto bail; | |
3c726f8d BH |
1332 | } |
1333 | ||
ca91e6c0 BH |
1334 | /* Add _PAGE_PRESENT to the required access perm */ |
1335 | access |= _PAGE_PRESENT; | |
1336 | ||
47d99948 CL |
1337 | /* |
1338 | * Pre-check access permissions (will be re-checked atomically | |
ca91e6c0 BH |
1339 | * in __hash_page_XX but this pre-check is a fast path |
1340 | */ | |
ac29c640 | 1341 | if (!check_pte_access(access, pte_val(*ptep))) { |
ca91e6c0 | 1342 | DBG_LOW(" no access !\n"); |
ba12eede LZ |
1343 | rc = 1; |
1344 | goto bail; | |
ca91e6c0 BH |
1345 | } |
1346 | ||
ba12eede | 1347 | if (hugeshift) { |
891121e6 | 1348 | if (is_thp) |
6d492ecc | 1349 | rc = __hash_page_thp(ea, access, vsid, (pmd_t *)ptep, |
aefa5688 | 1350 | trap, flags, ssize, psize); |
6d492ecc AK |
1351 | #ifdef CONFIG_HUGETLB_PAGE |
1352 | else | |
1353 | rc = __hash_page_huge(ea, access, vsid, ptep, trap, | |
aefa5688 | 1354 | flags, ssize, hugeshift, psize); |
6d492ecc AK |
1355 | #else |
1356 | else { | |
1357 | /* | |
1358 | * if we have hugeshift, and is not transhuge with | |
1359 | * hugetlb disabled, something is really wrong. | |
1360 | */ | |
1361 | rc = 1; | |
1362 | WARN_ON(1); | |
1363 | } | |
1364 | #endif | |
54be0b9c ME |
1365 | if (current->mm == mm) |
1366 | check_paca_psize(ea, mm, psize, user_region); | |
1367 | ||
ba12eede LZ |
1368 | goto bail; |
1369 | } | |
a4fe3ce7 | 1370 | |
3c726f8d BH |
1371 | #ifndef CONFIG_PPC_64K_PAGES |
1372 | DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep)); | |
1373 | #else | |
1374 | DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep), | |
1375 | pte_val(*(ptep + PTRS_PER_PTE))); | |
1376 | #endif | |
3c726f8d | 1377 | /* Do actual hashing */ |
16c2d476 | 1378 | #ifdef CONFIG_PPC_64K_PAGES |
945537df AK |
1379 | /* If H_PAGE_4K_PFN is set, make sure this is a 4k segment */ |
1380 | if ((pte_val(*ptep) & H_PAGE_4K_PFN) && psize == MMU_PAGE_64K) { | |
721151d0 PM |
1381 | demote_segment_4k(mm, ea); |
1382 | psize = MMU_PAGE_4K; | |
1383 | } | |
1384 | ||
47d99948 CL |
1385 | /* |
1386 | * If this PTE is non-cacheable and we have restrictions on | |
16f1c746 BH |
1387 | * using non cacheable large pages, then we switch to 4k |
1388 | */ | |
30bda41a | 1389 | if (mmu_ci_restrictions && psize == MMU_PAGE_64K && pte_ci(*ptep)) { |
16f1c746 BH |
1390 | if (user_region) { |
1391 | demote_segment_4k(mm, ea); | |
1392 | psize = MMU_PAGE_4K; | |
1393 | } else if (ea < VMALLOC_END) { | |
1394 | /* | |
1395 | * some driver did a non-cacheable mapping | |
1396 | * in vmalloc space, so switch vmalloc | |
1397 | * to 4k pages | |
1398 | */ | |
1399 | printk(KERN_ALERT "Reducing vmalloc segment " | |
1400 | "to 4kB pages because of " | |
1401 | "non-cacheable mapping\n"); | |
1402 | psize = mmu_vmalloc_psize = MMU_PAGE_4K; | |
be3ebfe8 | 1403 | copro_flush_all_slbs(mm); |
bf72aeba | 1404 | } |
16f1c746 | 1405 | } |
09567e7f | 1406 | |
0863d7f2 AK |
1407 | #endif /* CONFIG_PPC_64K_PAGES */ |
1408 | ||
54be0b9c ME |
1409 | if (current->mm == mm) |
1410 | check_paca_psize(ea, mm, psize, user_region); | |
1411 | ||
73b341ef | 1412 | #ifdef CONFIG_PPC_64K_PAGES |
bf72aeba | 1413 | if (psize == MMU_PAGE_64K) |
aefa5688 AK |
1414 | rc = __hash_page_64K(ea, access, vsid, ptep, trap, |
1415 | flags, ssize); | |
3c726f8d | 1416 | else |
73b341ef | 1417 | #endif /* CONFIG_PPC_64K_PAGES */ |
fa28237c | 1418 | { |
a1128f8f | 1419 | int spp = subpage_protection(mm, ea); |
fa28237c PM |
1420 | if (access & spp) |
1421 | rc = -2; | |
1422 | else | |
1423 | rc = __hash_page_4K(ea, access, vsid, ptep, trap, | |
aefa5688 | 1424 | flags, ssize, spp); |
fa28237c | 1425 | } |
3c726f8d | 1426 | |
47d99948 CL |
1427 | /* |
1428 | * Dump some info in case of hash insertion failure, they should | |
4b8692c0 BH |
1429 | * never happen so it is really useful to know if/when they do |
1430 | */ | |
1431 | if (rc == -1) | |
1432 | hash_failure_debug(ea, access, vsid, trap, ssize, psize, | |
d8139ebf | 1433 | psize, pte_val(*ptep)); |
3c726f8d BH |
1434 | #ifndef CONFIG_PPC_64K_PAGES |
1435 | DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep)); | |
1436 | #else | |
1437 | DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep), | |
1438 | pte_val(*(ptep + PTRS_PER_PTE))); | |
1439 | #endif | |
1440 | DBG_LOW(" -> rc=%d\n", rc); | |
ba12eede LZ |
1441 | |
1442 | bail: | |
1443 | exception_exit(prev_state); | |
3c726f8d | 1444 | return rc; |
1da177e4 | 1445 | } |
a1dca346 IM |
1446 | EXPORT_SYMBOL_GPL(hash_page_mm); |
1447 | ||
aefa5688 AK |
1448 | int hash_page(unsigned long ea, unsigned long access, unsigned long trap, |
1449 | unsigned long dsisr) | |
a1dca346 | 1450 | { |
aefa5688 | 1451 | unsigned long flags = 0; |
a1dca346 IM |
1452 | struct mm_struct *mm = current->mm; |
1453 | ||
0034d395 AK |
1454 | if ((get_region_id(ea) == VMALLOC_REGION_ID) || |
1455 | (get_region_id(ea) == IO_REGION_ID)) | |
a1dca346 IM |
1456 | mm = &init_mm; |
1457 | ||
aefa5688 AK |
1458 | if (dsisr & DSISR_NOHPTE) |
1459 | flags |= HPTE_NOHPTE_UPDATE; | |
1460 | ||
1461 | return hash_page_mm(mm, ea, access, trap, flags); | |
a1dca346 | 1462 | } |
67207b96 | 1463 | EXPORT_SYMBOL_GPL(hash_page); |
1da177e4 | 1464 | |
106713a1 AK |
1465 | int __hash_page(unsigned long ea, unsigned long msr, unsigned long trap, |
1466 | unsigned long dsisr) | |
1467 | { | |
c7d54842 | 1468 | unsigned long access = _PAGE_PRESENT | _PAGE_READ; |
106713a1 AK |
1469 | unsigned long flags = 0; |
1470 | struct mm_struct *mm = current->mm; | |
0034d395 | 1471 | unsigned int region_id = get_region_id(ea); |
106713a1 | 1472 | |
0034d395 | 1473 | if ((region_id == VMALLOC_REGION_ID) || (region_id == IO_REGION_ID)) |
106713a1 AK |
1474 | mm = &init_mm; |
1475 | ||
1476 | if (dsisr & DSISR_NOHPTE) | |
1477 | flags |= HPTE_NOHPTE_UPDATE; | |
1478 | ||
1479 | if (dsisr & DSISR_ISSTORE) | |
c7d54842 | 1480 | access |= _PAGE_WRITE; |
106713a1 | 1481 | /* |
ac29c640 AK |
1482 | * We set _PAGE_PRIVILEGED only when |
1483 | * kernel mode access kernel space. | |
1484 | * | |
1485 | * _PAGE_PRIVILEGED is NOT set | |
1486 | * 1) when kernel mode access user space | |
1487 | * 2) user space access kernel space. | |
106713a1 | 1488 | */ |
ac29c640 | 1489 | access |= _PAGE_PRIVILEGED; |
0034d395 | 1490 | if ((msr & MSR_PR) || (region_id == USER_REGION_ID)) |
ac29c640 | 1491 | access &= ~_PAGE_PRIVILEGED; |
106713a1 AK |
1492 | |
1493 | if (trap == 0x400) | |
1494 | access |= _PAGE_EXEC; | |
1495 | ||
1496 | return hash_page_mm(mm, ea, access, trap, flags); | |
1497 | } | |
1498 | ||
8bbc9b7b ME |
1499 | #ifdef CONFIG_PPC_MM_SLICES |
1500 | static bool should_hash_preload(struct mm_struct *mm, unsigned long ea) | |
1501 | { | |
54be0b9c | 1502 | int psize = get_slice_psize(mm, ea); |
aac55d75 | 1503 | |
8bbc9b7b | 1504 | /* We only prefault standard pages for now */ |
60458fba | 1505 | if (unlikely(psize != mm_ctx_user_psize(&mm->context))) |
aac55d75 ME |
1506 | return false; |
1507 | ||
1508 | /* | |
1509 | * Don't prefault if subpage protection is enabled for the EA. | |
1510 | */ | |
1511 | if (unlikely((psize == MMU_PAGE_4K) && subpage_protection(mm, ea))) | |
8bbc9b7b ME |
1512 | return false; |
1513 | ||
1514 | return true; | |
1515 | } | |
1516 | #else | |
1517 | static bool should_hash_preload(struct mm_struct *mm, unsigned long ea) | |
1518 | { | |
1519 | return true; | |
1520 | } | |
1521 | #endif | |
1522 | ||
3c726f8d | 1523 | void hash_preload(struct mm_struct *mm, unsigned long ea, |
34eb138e | 1524 | bool is_exec, unsigned long trap) |
1da177e4 | 1525 | { |
12bc9f6f | 1526 | int hugepage_shift; |
3c726f8d | 1527 | unsigned long vsid; |
0b97fee0 | 1528 | pgd_t *pgdir; |
3c726f8d | 1529 | pte_t *ptep; |
3c726f8d | 1530 | unsigned long flags; |
aefa5688 | 1531 | int rc, ssize, update_flags = 0; |
34eb138e | 1532 | unsigned long access = _PAGE_PRESENT | _PAGE_READ | (is_exec ? _PAGE_EXEC : 0); |
3c726f8d | 1533 | |
0034d395 | 1534 | BUG_ON(get_region_id(ea) != USER_REGION_ID); |
d0f13e3c | 1535 | |
8bbc9b7b | 1536 | if (!should_hash_preload(mm, ea)) |
3c726f8d BH |
1537 | return; |
1538 | ||
1539 | DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx," | |
1540 | " trap=%lx\n", mm, mm->pgd, ea, access, trap); | |
1da177e4 | 1541 | |
16f1c746 | 1542 | /* Get Linux PTE if available */ |
3c726f8d BH |
1543 | pgdir = mm->pgd; |
1544 | if (pgdir == NULL) | |
1545 | return; | |
0ac52dd7 AK |
1546 | |
1547 | /* Get VSID */ | |
1548 | ssize = user_segment_size(ea); | |
f384796c | 1549 | vsid = get_user_vsid(&mm->context, ea, ssize); |
0ac52dd7 AK |
1550 | if (!vsid) |
1551 | return; | |
1552 | /* | |
1553 | * Hash doesn't like irqs. Walking linux page table with irq disabled | |
1554 | * saves us from holding multiple locks. | |
1555 | */ | |
1556 | local_irq_save(flags); | |
1557 | ||
12bc9f6f AK |
1558 | /* |
1559 | * THP pages use update_mmu_cache_pmd. We don't do | |
1560 | * hash preload there. Hence can ignore THP here | |
1561 | */ | |
94171b19 | 1562 | ptep = find_current_mm_pte(pgdir, ea, NULL, &hugepage_shift); |
3c726f8d | 1563 | if (!ptep) |
0ac52dd7 | 1564 | goto out_exit; |
16f1c746 | 1565 | |
12bc9f6f | 1566 | WARN_ON(hugepage_shift); |
16f1c746 | 1567 | #ifdef CONFIG_PPC_64K_PAGES |
945537df | 1568 | /* If either H_PAGE_4K_PFN or cache inhibited is set (and we are on |
16f1c746 BH |
1569 | * a 64K kernel), then we don't preload, hash_page() will take |
1570 | * care of it once we actually try to access the page. | |
1571 | * That way we don't have to duplicate all of the logic for segment | |
1572 | * page size demotion here | |
1573 | */ | |
945537df | 1574 | if ((pte_val(*ptep) & H_PAGE_4K_PFN) || pte_ci(*ptep)) |
0ac52dd7 | 1575 | goto out_exit; |
16f1c746 BH |
1576 | #endif /* CONFIG_PPC_64K_PAGES */ |
1577 | ||
16c2d476 | 1578 | /* Is that local to this CPU ? */ |
b426e4bd | 1579 | if (mm_is_thread_local(mm)) |
aefa5688 | 1580 | update_flags |= HPTE_LOCAL_UPDATE; |
16c2d476 BH |
1581 | |
1582 | /* Hash it in */ | |
73b341ef | 1583 | #ifdef CONFIG_PPC_64K_PAGES |
60458fba | 1584 | if (mm_ctx_user_psize(&mm->context) == MMU_PAGE_64K) |
aefa5688 AK |
1585 | rc = __hash_page_64K(ea, access, vsid, ptep, trap, |
1586 | update_flags, ssize); | |
1da177e4 | 1587 | else |
73b341ef | 1588 | #endif /* CONFIG_PPC_64K_PAGES */ |
aefa5688 AK |
1589 | rc = __hash_page_4K(ea, access, vsid, ptep, trap, update_flags, |
1590 | ssize, subpage_protection(mm, ea)); | |
4b8692c0 BH |
1591 | |
1592 | /* Dump some info in case of hash insertion failure, they should | |
1593 | * never happen so it is really useful to know if/when they do | |
1594 | */ | |
1595 | if (rc == -1) | |
1596 | hash_failure_debug(ea, access, vsid, trap, ssize, | |
60458fba AK |
1597 | mm_ctx_user_psize(&mm->context), |
1598 | mm_ctx_user_psize(&mm->context), | |
d8139ebf | 1599 | pte_val(*ptep)); |
0ac52dd7 | 1600 | out_exit: |
3c726f8d BH |
1601 | local_irq_restore(flags); |
1602 | } | |
1603 | ||
087003e9 RP |
1604 | #ifdef CONFIG_PPC_MEM_KEYS |
1605 | /* | |
1606 | * Return the protection key associated with the given address and the | |
1607 | * mm_struct. | |
1608 | */ | |
1609 | u16 get_mm_addr_key(struct mm_struct *mm, unsigned long address) | |
1610 | { | |
1611 | pte_t *ptep; | |
1612 | u16 pkey = 0; | |
1613 | unsigned long flags; | |
1614 | ||
1615 | if (!mm || !mm->pgd) | |
1616 | return 0; | |
1617 | ||
1618 | local_irq_save(flags); | |
1619 | ptep = find_linux_pte(mm->pgd, address, NULL, NULL); | |
1620 | if (ptep) | |
1621 | pkey = pte_to_pkey_bits(pte_val(READ_ONCE(*ptep))); | |
1622 | local_irq_restore(flags); | |
1623 | ||
1624 | return pkey; | |
1625 | } | |
1626 | #endif /* CONFIG_PPC_MEM_KEYS */ | |
1627 | ||
f1a55ce0 RT |
1628 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1629 | static inline void tm_flush_hash_page(int local) | |
1630 | { | |
1631 | /* | |
1632 | * Transactions are not aborted by tlbiel, only tlbie. Without, syncing a | |
1633 | * page back to a block device w/PIO could pick up transactional data | |
1634 | * (bad!) so we force an abort here. Before the sync the page will be | |
1635 | * made read-only, which will flush_hash_page. BIG ISSUE here: if the | |
1636 | * kernel uses a page from userspace without unmapping it first, it may | |
1637 | * see the speculated version. | |
1638 | */ | |
1639 | if (local && cpu_has_feature(CPU_FTR_TM) && current->thread.regs && | |
1640 | MSR_TM_ACTIVE(current->thread.regs->msr)) { | |
1641 | tm_enable(); | |
1642 | tm_abort(TM_CAUSE_TLBI); | |
1643 | } | |
1644 | } | |
1645 | #else | |
1646 | static inline void tm_flush_hash_page(int local) | |
1647 | { | |
1648 | } | |
1649 | #endif | |
1650 | ||
318995b4 RP |
1651 | /* |
1652 | * Return the global hash slot, corresponding to the given PTE, which contains | |
1653 | * the HPTE. | |
1654 | */ | |
1655 | unsigned long pte_get_hash_gslot(unsigned long vpn, unsigned long shift, | |
1656 | int ssize, real_pte_t rpte, unsigned int subpg_index) | |
1657 | { | |
1658 | unsigned long hash, gslot, hidx; | |
1659 | ||
1660 | hash = hpt_hash(vpn, shift, ssize); | |
1661 | hidx = __rpte_to_hidx(rpte, subpg_index); | |
1662 | if (hidx & _PTEIDX_SECONDARY) | |
1663 | hash = ~hash; | |
1664 | gslot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
1665 | gslot += hidx & _PTEIDX_GROUP_IX; | |
1666 | return gslot; | |
1667 | } | |
1668 | ||
47d99948 CL |
1669 | /* |
1670 | * WARNING: This is called from hash_low_64.S, if you change this prototype, | |
f6ab0b92 BH |
1671 | * do not forget to update the assembly call site ! |
1672 | */ | |
5524a27d | 1673 | void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize, |
aefa5688 | 1674 | unsigned long flags) |
3c726f8d | 1675 | { |
a8548686 | 1676 | unsigned long index, shift, gslot; |
aefa5688 | 1677 | int local = flags & HPTE_LOCAL_UPDATE; |
3c726f8d | 1678 | |
5524a27d AK |
1679 | DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn); |
1680 | pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) { | |
a8548686 RP |
1681 | gslot = pte_get_hash_gslot(vpn, shift, ssize, pte, index); |
1682 | DBG_LOW(" sub %ld: gslot=%lx\n", index, gslot); | |
db3d8534 AK |
1683 | /* |
1684 | * We use same base page size and actual psize, because we don't | |
1685 | * use these functions for hugepage | |
1686 | */ | |
a8548686 | 1687 | mmu_hash_ops.hpte_invalidate(gslot, vpn, psize, psize, |
7025776e | 1688 | ssize, local); |
3c726f8d | 1689 | } pte_iterate_hashed_end(); |
bc2a9408 | 1690 | |
f1a55ce0 | 1691 | tm_flush_hash_page(local); |
1da177e4 LT |
1692 | } |
1693 | ||
f1581bf1 AK |
1694 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
1695 | void flush_hash_hugepage(unsigned long vsid, unsigned long addr, | |
aefa5688 AK |
1696 | pmd_t *pmdp, unsigned int psize, int ssize, |
1697 | unsigned long flags) | |
f1581bf1 AK |
1698 | { |
1699 | int i, max_hpte_count, valid; | |
1700 | unsigned long s_addr; | |
1701 | unsigned char *hpte_slot_array; | |
1702 | unsigned long hidx, shift, vpn, hash, slot; | |
aefa5688 | 1703 | int local = flags & HPTE_LOCAL_UPDATE; |
f1581bf1 AK |
1704 | |
1705 | s_addr = addr & HPAGE_PMD_MASK; | |
1706 | hpte_slot_array = get_hpte_slot_array(pmdp); | |
1707 | /* | |
1708 | * IF we try to do a HUGE PTE update after a withdraw is done. | |
1709 | * we will find the below NULL. This happens when we do | |
1710 | * split_huge_page_pmd | |
1711 | */ | |
1712 | if (!hpte_slot_array) | |
1713 | return; | |
1714 | ||
7025776e BH |
1715 | if (mmu_hash_ops.hugepage_invalidate) { |
1716 | mmu_hash_ops.hugepage_invalidate(vsid, s_addr, hpte_slot_array, | |
1717 | psize, ssize, local); | |
d557b098 AK |
1718 | goto tm_abort; |
1719 | } | |
f1581bf1 AK |
1720 | /* |
1721 | * No bluk hpte removal support, invalidate each entry | |
1722 | */ | |
1723 | shift = mmu_psize_defs[psize].shift; | |
1724 | max_hpte_count = HPAGE_PMD_SIZE >> shift; | |
1725 | for (i = 0; i < max_hpte_count; i++) { | |
1726 | /* | |
1727 | * 8 bits per each hpte entries | |
1728 | * 000| [ secondary group (one bit) | hidx (3 bits) | valid bit] | |
1729 | */ | |
1730 | valid = hpte_valid(hpte_slot_array, i); | |
1731 | if (!valid) | |
1732 | continue; | |
1733 | hidx = hpte_hash_index(hpte_slot_array, i); | |
1734 | ||
1735 | /* get the vpn */ | |
1736 | addr = s_addr + (i * (1ul << shift)); | |
1737 | vpn = hpt_vpn(addr, vsid, ssize); | |
1738 | hash = hpt_hash(vpn, shift, ssize); | |
1739 | if (hidx & _PTEIDX_SECONDARY) | |
1740 | hash = ~hash; | |
1741 | ||
1742 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
1743 | slot += hidx & _PTEIDX_GROUP_IX; | |
7025776e BH |
1744 | mmu_hash_ops.hpte_invalidate(slot, vpn, psize, |
1745 | MMU_PAGE_16M, ssize, local); | |
d557b098 AK |
1746 | } |
1747 | tm_abort: | |
f1a55ce0 | 1748 | tm_flush_hash_page(local); |
f1581bf1 AK |
1749 | } |
1750 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ | |
1751 | ||
61b1a942 | 1752 | void flush_hash_range(unsigned long number, int local) |
1da177e4 | 1753 | { |
7025776e BH |
1754 | if (mmu_hash_ops.flush_hash_range) |
1755 | mmu_hash_ops.flush_hash_range(number, local); | |
3c726f8d | 1756 | else { |
1da177e4 | 1757 | int i; |
61b1a942 | 1758 | struct ppc64_tlb_batch *batch = |
69111bac | 1759 | this_cpu_ptr(&ppc64_tlb_batch); |
1da177e4 LT |
1760 | |
1761 | for (i = 0; i < number; i++) | |
5524a27d | 1762 | flush_hash_page(batch->vpn[i], batch->pte[i], |
1189be65 | 1763 | batch->psize, batch->ssize, local); |
1da177e4 LT |
1764 | } |
1765 | } | |
1766 | ||
1da177e4 LT |
1767 | /* |
1768 | * low_hash_fault is called when we the low level hash code failed | |
1769 | * to instert a PTE due to an hypervisor error | |
1770 | */ | |
fa28237c | 1771 | void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc) |
1da177e4 | 1772 | { |
ba12eede LZ |
1773 | enum ctx_state prev_state = exception_enter(); |
1774 | ||
1da177e4 | 1775 | if (user_mode(regs)) { |
fa28237c PM |
1776 | #ifdef CONFIG_PPC_SUBPAGE_PROT |
1777 | if (rc == -2) | |
1778 | _exception(SIGSEGV, regs, SEGV_ACCERR, address); | |
1779 | else | |
1780 | #endif | |
1781 | _exception(SIGBUS, regs, BUS_ADRERR, address); | |
1782 | } else | |
1783 | bad_page_fault(regs, address, SIGBUS); | |
ba12eede LZ |
1784 | |
1785 | exception_exit(prev_state); | |
1da177e4 | 1786 | } |
370a908d | 1787 | |
b170bd3d LZ |
1788 | long hpte_insert_repeating(unsigned long hash, unsigned long vpn, |
1789 | unsigned long pa, unsigned long rflags, | |
1790 | unsigned long vflags, int psize, int ssize) | |
1791 | { | |
1792 | unsigned long hpte_group; | |
1793 | long slot; | |
1794 | ||
1795 | repeat: | |
1531cff4 | 1796 | hpte_group = (hash & htab_hash_mask) * HPTES_PER_GROUP; |
b170bd3d LZ |
1797 | |
1798 | /* Insert into the hash table, primary slot */ | |
7025776e BH |
1799 | slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags, vflags, |
1800 | psize, psize, ssize); | |
b170bd3d LZ |
1801 | |
1802 | /* Primary is full, try the secondary */ | |
1803 | if (unlikely(slot == -1)) { | |
1531cff4 | 1804 | hpte_group = (~hash & htab_hash_mask) * HPTES_PER_GROUP; |
7025776e BH |
1805 | slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags, |
1806 | vflags | HPTE_V_SECONDARY, | |
1807 | psize, psize, ssize); | |
b170bd3d LZ |
1808 | if (slot == -1) { |
1809 | if (mftb() & 0x1) | |
1531cff4 AK |
1810 | hpte_group = (hash & htab_hash_mask) * |
1811 | HPTES_PER_GROUP; | |
b170bd3d | 1812 | |
7025776e | 1813 | mmu_hash_ops.hpte_remove(hpte_group); |
b170bd3d LZ |
1814 | goto repeat; |
1815 | } | |
1816 | } | |
1817 | ||
1818 | return slot; | |
1819 | } | |
1820 | ||
370a908d BH |
1821 | #ifdef CONFIG_DEBUG_PAGEALLOC |
1822 | static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi) | |
1823 | { | |
016af59f | 1824 | unsigned long hash; |
1189be65 | 1825 | unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize); |
5524a27d | 1826 | unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize); |
09f3f326 | 1827 | unsigned long mode = htab_convert_pte_flags(pgprot_val(PAGE_KERNEL)); |
016af59f | 1828 | long ret; |
370a908d | 1829 | |
5524a27d | 1830 | hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize); |
370a908d | 1831 | |
c60ac569 AK |
1832 | /* Don't create HPTE entries for bad address */ |
1833 | if (!vsid) | |
1834 | return; | |
016af59f LZ |
1835 | |
1836 | ret = hpte_insert_repeating(hash, vpn, __pa(vaddr), mode, | |
1837 | HPTE_V_BOLTED, | |
1838 | mmu_linear_psize, mmu_kernel_ssize); | |
1839 | ||
370a908d BH |
1840 | BUG_ON (ret < 0); |
1841 | spin_lock(&linear_map_hash_lock); | |
1842 | BUG_ON(linear_map_hash_slots[lmi] & 0x80); | |
1843 | linear_map_hash_slots[lmi] = ret | 0x80; | |
1844 | spin_unlock(&linear_map_hash_lock); | |
1845 | } | |
1846 | ||
1847 | static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi) | |
1848 | { | |
1189be65 PM |
1849 | unsigned long hash, hidx, slot; |
1850 | unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize); | |
5524a27d | 1851 | unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize); |
370a908d | 1852 | |
5524a27d | 1853 | hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize); |
370a908d BH |
1854 | spin_lock(&linear_map_hash_lock); |
1855 | BUG_ON(!(linear_map_hash_slots[lmi] & 0x80)); | |
1856 | hidx = linear_map_hash_slots[lmi] & 0x7f; | |
1857 | linear_map_hash_slots[lmi] = 0; | |
1858 | spin_unlock(&linear_map_hash_lock); | |
1859 | if (hidx & _PTEIDX_SECONDARY) | |
1860 | hash = ~hash; | |
1861 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
1862 | slot += hidx & _PTEIDX_GROUP_IX; | |
7025776e BH |
1863 | mmu_hash_ops.hpte_invalidate(slot, vpn, mmu_linear_psize, |
1864 | mmu_linear_psize, | |
1865 | mmu_kernel_ssize, 0); | |
370a908d BH |
1866 | } |
1867 | ||
031bc574 | 1868 | void __kernel_map_pages(struct page *page, int numpages, int enable) |
370a908d BH |
1869 | { |
1870 | unsigned long flags, vaddr, lmi; | |
1871 | int i; | |
1872 | ||
1873 | local_irq_save(flags); | |
1874 | for (i = 0; i < numpages; i++, page++) { | |
1875 | vaddr = (unsigned long)page_address(page); | |
1876 | lmi = __pa(vaddr) >> PAGE_SHIFT; | |
1877 | if (lmi >= linear_map_hash_count) | |
1878 | continue; | |
1879 | if (enable) | |
1880 | kernel_map_linear_page(vaddr, lmi); | |
1881 | else | |
1882 | kernel_unmap_linear_page(vaddr, lmi); | |
1883 | } | |
1884 | local_irq_restore(flags); | |
1885 | } | |
1886 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
cd3db0c4 | 1887 | |
756d08d1 | 1888 | void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base, |
cd3db0c4 BH |
1889 | phys_addr_t first_memblock_size) |
1890 | { | |
47d99948 CL |
1891 | /* |
1892 | * We don't currently support the first MEMBLOCK not mapping 0 | |
cd3db0c4 BH |
1893 | * physical on those processors |
1894 | */ | |
1895 | BUG_ON(first_memblock_base != 0); | |
1896 | ||
1513c33d NP |
1897 | /* |
1898 | * On virtualized systems the first entry is our RMA region aka VRMA, | |
1899 | * non-virtualized 64-bit hash MMU systems don't have a limitation | |
1900 | * on real mode access. | |
1901 | * | |
c610d65c NP |
1902 | * For guests on platforms before POWER9, we clamp the it limit to 1G |
1903 | * to avoid some funky things such as RTAS bugs etc... | |
cd3db0c4 | 1904 | */ |
1513c33d | 1905 | if (!early_cpu_has_feature(CPU_FTR_HVMODE)) { |
c610d65c NP |
1906 | ppc64_rma_size = first_memblock_size; |
1907 | if (!early_cpu_has_feature(CPU_FTR_ARCH_300)) | |
1908 | ppc64_rma_size = min_t(u64, ppc64_rma_size, 0x40000000); | |
cd3db0c4 | 1909 | |
1513c33d NP |
1910 | /* Finally limit subsequent allocations */ |
1911 | memblock_set_current_limit(ppc64_rma_size); | |
1912 | } else { | |
1913 | ppc64_rma_size = ULONG_MAX; | |
1914 | } | |
cd3db0c4 | 1915 | } |
dbcf929c DG |
1916 | |
1917 | #ifdef CONFIG_DEBUG_FS | |
1918 | ||
1919 | static int hpt_order_get(void *data, u64 *val) | |
1920 | { | |
1921 | *val = ppc64_pft_size; | |
1922 | return 0; | |
1923 | } | |
1924 | ||
1925 | static int hpt_order_set(void *data, u64 val) | |
1926 | { | |
1927 | if (!mmu_hash_ops.resize_hpt) | |
1928 | return -ENODEV; | |
1929 | ||
1930 | return mmu_hash_ops.resize_hpt(val); | |
1931 | } | |
1932 | ||
7cd4774f | 1933 | DEFINE_DEBUGFS_ATTRIBUTE(fops_hpt_order, hpt_order_get, hpt_order_set, "%llu\n"); |
dbcf929c DG |
1934 | |
1935 | static int __init hash64_debugfs(void) | |
1936 | { | |
7cd4774f Y |
1937 | if (!debugfs_create_file_unsafe("hpt_order", 0600, powerpc_debugfs_root, |
1938 | NULL, &fops_hpt_order)) { | |
dbcf929c DG |
1939 | pr_err("lpar: unable to create hpt_order debugsfs file\n"); |
1940 | } | |
1941 | ||
1942 | return 0; | |
1943 | } | |
1944 | machine_device_initcall(pseries, hash64_debugfs); | |
dbcf929c | 1945 | #endif /* CONFIG_DEBUG_FS */ |
e4dccf90 CL |
1946 | |
1947 | void __init print_system_hash_info(void) | |
1948 | { | |
1949 | pr_info("ppc64_pft_size = 0x%llx\n", ppc64_pft_size); | |
1950 | ||
1951 | if (htab_hash_mask) | |
1952 | pr_info("htab_hash_mask = 0x%lx\n", htab_hash_mask); | |
1953 | pr_info("kernel vmalloc start = 0x%lx\n", KERN_VIRT_START); | |
1954 | pr_info("kernel IO start = 0x%lx\n", KERN_IO_START); | |
1955 | pr_info("kernel vmemmap start = 0x%lx\n", (unsigned long)vmemmap); | |
1956 | } |