[mirror_ubuntu-kernels.git] / arch / powerpc / mm / fsl_booke_mmu.c

/*
 * Modifications by Kumar Gala (galak@kernel.crashing.org) to support
 * E500 Book E processors.
 *
 * Copyright 2004 Freescale Semiconductor, Inc
 *
 * This file contains the routines for initializing the MMU
 * on the 4xx series of chips.
 *  -- paulus
 *
 *  Derived from arch/ppc/mm/init.c:
 *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
 *
 *  Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
 *  and Cort Dougan (PReP) (cort@cs.nmt.edu)
 *    Copyright (C) 1996 Paul Mackerras
 *
 *  Derived from "arch/i386/mm/init.c"
 *    Copyright (C) 1991, 1992, 1993, 1994  Linus Torvalds
 *
 *  This program is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU General Public License
 *  as published by the Free Software Foundation; either version
 *  2 of the License, or (at your option) any later version.
 *
 */

#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/types.h>
#include <linux/ptrace.h>
#include <linux/mman.h>
#include <linux/mm.h>
#include <linux/swap.h>
#include <linux/stddef.h>
#include <linux/vmalloc.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/highmem.h>

#include <asm/pgalloc.h>
#include <asm/prom.h>
#include <asm/io.h>
#include <asm/mmu_context.h>
#include <asm/pgtable.h>
#include <asm/mmu.h>
#include <asm/uaccess.h>
#include <asm/smp.h>
#include <asm/machdep.h>
#include <asm/setup.h>

#include "mmu_decl.h"

unsigned int tlbcam_index;

#define NUM_TLBCAMS	(64)

#if defined(CONFIG_LOWMEM_CAM_NUM_BOOL) && (CONFIG_LOWMEM_CAM_NUM >= NUM_TLBCAMS)
#error "LOWMEM_CAM_NUM must be less than NUM_TLBCAMS"
#endif

struct tlbcam {
	u32	MAS0;
	u32	MAS1;
	unsigned long	MAS2;
	u32	MAS3;
	u32	MAS7;
} TLBCAM[NUM_TLBCAMS];

struct tlbcamrange {
	unsigned long start;
	unsigned long limit;
	phys_addr_t phys;
} tlbcam_addrs[NUM_TLBCAMS];

extern unsigned int tlbcam_index;

unsigned long tlbcam_sz(int idx)
{
	return tlbcam_addrs[idx].limit - tlbcam_addrs[idx].start + 1;
}

/*
 * Return PA for this VA if it is mapped by a CAM, or 0
 */
phys_addr_t v_mapped_by_tlbcam(unsigned long va)
{
	int b;
	for (b = 0; b < tlbcam_index; ++b)
		if (va >= tlbcam_addrs[b].start && va < tlbcam_addrs[b].limit)
			return tlbcam_addrs[b].phys + (va - tlbcam_addrs[b].start);
	return 0;
}

/*
 * Return VA for a given PA or 0 if not mapped
 */
unsigned long p_mapped_by_tlbcam(phys_addr_t pa)
{
	int b;
	for (b = 0; b < tlbcam_index; ++b)
		if (pa >= tlbcam_addrs[b].phys
			&& pa < (tlbcam_addrs[b].limit-tlbcam_addrs[b].start)
		              +tlbcam_addrs[b].phys)
			return tlbcam_addrs[b].start+(pa-tlbcam_addrs[b].phys);
	return 0;
}

void loadcam_entry(int idx)
{
	mtspr(SPRN_MAS0, TLBCAM[idx].MAS0);
	mtspr(SPRN_MAS1, TLBCAM[idx].MAS1);
	mtspr(SPRN_MAS2, TLBCAM[idx].MAS2);
	mtspr(SPRN_MAS3, TLBCAM[idx].MAS3);

	if (cur_cpu_spec->cpu_features & MMU_FTR_BIG_PHYS)
		mtspr(SPRN_MAS7, TLBCAM[idx].MAS7);

	asm volatile("isync;tlbwe;isync" : : : "memory");
}

/*
 * Set up one of the I/D BAT (block address translation) register pairs.
 * The parameters are not checked; in particular size must be a power
 * of 4 between 4k and 256M.
 */
static void settlbcam(int index, unsigned long virt, phys_addr_t phys,
		unsigned long size, unsigned long flags, unsigned int pid)
{
	unsigned int tsize, lz;

	asm (PPC_CNTLZL "%0,%1" : "=r" (lz) : "r" (size));
	tsize = 21 - lz;

#ifdef CONFIG_SMP
	if ((flags & _PAGE_NO_CACHE) == 0)
		flags |= _PAGE_COHERENT;
#endif

	TLBCAM[index].MAS0 = MAS0_TLBSEL(1) | MAS0_ESEL(index) | MAS0_NV(index+1);
	TLBCAM[index].MAS1 = MAS1_VALID | MAS1_IPROT | MAS1_TSIZE(tsize) | MAS1_TID(pid);
	TLBCAM[index].MAS2 = virt & PAGE_MASK;

	TLBCAM[index].MAS2 |= (flags & _PAGE_WRITETHRU) ? MAS2_W : 0;
	TLBCAM[index].MAS2 |= (flags & _PAGE_NO_CACHE) ? MAS2_I : 0;
	TLBCAM[index].MAS2 |= (flags & _PAGE_COHERENT) ? MAS2_M : 0;
	TLBCAM[index].MAS2 |= (flags & _PAGE_GUARDED) ? MAS2_G : 0;
	TLBCAM[index].MAS2 |= (flags & _PAGE_ENDIAN) ? MAS2_E : 0;

	TLBCAM[index].MAS3 = (phys & MAS3_RPN) | MAS3_SX | MAS3_SR;
	TLBCAM[index].MAS3 |= ((flags & _PAGE_RW) ? MAS3_SW : 0);
	if (cur_cpu_spec->cpu_features & MMU_FTR_BIG_PHYS)
		TLBCAM[index].MAS7 = (u64)phys >> 32;

#ifndef CONFIG_KGDB /* want user access for breakpoints */
	if (flags & _PAGE_USER) {
	   TLBCAM[index].MAS3 |= MAS3_UX | MAS3_UR;
	   TLBCAM[index].MAS3 |= ((flags & _PAGE_RW) ? MAS3_UW : 0);
	}
#else
	TLBCAM[index].MAS3 |= MAS3_UX | MAS3_UR;
	TLBCAM[index].MAS3 |= ((flags & _PAGE_RW) ? MAS3_UW : 0);
#endif

	tlbcam_addrs[index].start = virt;
	tlbcam_addrs[index].limit = virt + size - 1;
	tlbcam_addrs[index].phys = phys;

	loadcam_entry(index);
}

unsigned long map_mem_in_cams(unsigned long ram, int max_cam_idx)
{
	int i;
	unsigned long virt = PAGE_OFFSET;
	phys_addr_t phys = memstart_addr;
	unsigned long amount_mapped = 0;
	unsigned long max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xf;

	/* Convert (4^max) kB to (2^max) bytes */
	max_cam = max_cam * 2 + 10;

	/* Calculate CAM values */
	for (i = 0; ram && i < max_cam_idx; i++) {
		unsigned int camsize = __ilog2(ram) & ~1U;
		unsigned int align = __ffs(virt | phys) & ~1U;
		unsigned long cam_sz;

		if (camsize > align)
			camsize = align;
		if (camsize > max_cam)
			camsize = max_cam;

		cam_sz = 1UL << camsize;
		settlbcam(i, virt, phys, cam_sz, PAGE_KERNEL_X, 0);

		ram -= cam_sz;
		amount_mapped += cam_sz;
		virt += cam_sz;
		phys += cam_sz;
	}
	tlbcam_index = i;

	return amount_mapped;
}

unsigned long __init mmu_mapin_ram(void)
{
	return tlbcam_addrs[tlbcam_index - 1].limit - PAGE_OFFSET + 1;
}

/*
 * MMU_init_hw does the chip-specific initialization of the MMU hardware.
 */
void __init MMU_init_hw(void)
{
	flush_instruction_cache();
}

void __init adjust_total_lowmem(void)
{
	unsigned long ram;
	int i;

	/* adjust lowmem size to __max_low_memory */
	ram = min((phys_addr_t)__max_low_memory, (phys_addr_t)total_lowmem);

	__max_low_memory = map_mem_in_cams(ram, CONFIG_LOWMEM_CAM_NUM);

	pr_info("Memory CAM mapping: ");
	for (i = 0; i < tlbcam_index - 1; i++)
		pr_cont("%lu/", tlbcam_sz(i) >> 20);
	pr_cont("%lu Mb, residual: %dMb\n", tlbcam_sz(tlbcam_index - 1) >> 20,
	        (unsigned int)((total_lowmem - __max_low_memory) >> 20));

	__initial_memory_limit_addr = memstart_addr + __max_low_memory;
}
Commit	Line	Data
14cf11af	1	/*
4c8d3d99	2	* Modifications by Kumar Gala (galak@kernel.crashing.org) to support
14cf11af PM	3	* E500 Book E processors.
	4	*
	5	* Copyright 2004 Freescale Semiconductor, Inc
	6	*
	7	* This file contains the routines for initializing the MMU
	8	* on the 4xx series of chips.
	9	* -- paulus
	10	*
	11	* Derived from arch/ppc/mm/init.c:
	12	* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
	13	*
	14	* Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
	15	* and Cort Dougan (PReP) (cort@cs.nmt.edu)
	16	* Copyright (C) 1996 Paul Mackerras
14cf11af PM	17	*
	18	* Derived from "arch/i386/mm/init.c"
	19	* Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
	20	*
	21	* This program is free software; you can redistribute it and/or
	22	* modify it under the terms of the GNU General Public License
	23	* as published by the Free Software Foundation; either version
	24	* 2 of the License, or (at your option) any later version.
	25	*
	26	*/
	27
14cf11af PM	28	#include <linux/signal.h>
	29	#include <linux/sched.h>
	30	#include <linux/kernel.h>
	31	#include <linux/errno.h>
	32	#include <linux/string.h>
	33	#include <linux/types.h>
	34	#include <linux/ptrace.h>
	35	#include <linux/mman.h>
	36	#include <linux/mm.h>
	37	#include <linux/swap.h>
	38	#include <linux/stddef.h>
	39	#include <linux/vmalloc.h>
	40	#include <linux/init.h>
	41	#include <linux/delay.h>
	42	#include <linux/highmem.h>
	43
	44	#include <asm/pgalloc.h>
	45	#include <asm/prom.h>
	46	#include <asm/io.h>
	47	#include <asm/mmu_context.h>
	48	#include <asm/pgtable.h>
	49	#include <asm/mmu.h>
	50	#include <asm/uaccess.h>
	51	#include <asm/smp.h>
14cf11af PM	52	#include <asm/machdep.h>
	53	#include <asm/setup.h>
	54
99c62dd7 KG	55	#include "mmu_decl.h"
99c62dd7 KG	56
14cf11af	57	unsigned int tlbcam_index;
14cf11af	58
8b27f0b6	59	#define NUM_TLBCAMS (64)
14cf11af	60
96051465 TP	61	#if defined(CONFIG_LOWMEM_CAM_NUM_BOOL) && (CONFIG_LOWMEM_CAM_NUM >= NUM_TLBCAMS)
	62	#error "LOWMEM_CAM_NUM must be less than NUM_TLBCAMS"
	63	#endif
	64
8b27f0b6 KG	65	struct tlbcam {
	66	u32 MAS0;
	67	u32 MAS1;
	68	unsigned long MAS2;
	69	u32 MAS3;
	70	u32 MAS7;
	71	} TLBCAM[NUM_TLBCAMS];
14cf11af PM	72
14cf11af PM	73	struct tlbcamrange {
8b27f0b6	74	unsigned long start;
14cf11af PM	75	unsigned long limit;
	76	phys_addr_t phys;
	77	} tlbcam_addrs[NUM_TLBCAMS];
	78
	79	extern unsigned int tlbcam_index;
	80
8b27f0b6 KG	81	unsigned long tlbcam_sz(int idx)
	82	{
	83	return tlbcam_addrs[idx].limit - tlbcam_addrs[idx].start + 1;
	84	}
	85
14cf11af PM	86	/*
	87	* Return PA for this VA if it is mapped by a CAM, or 0
	88	*/
6c24b174	89	phys_addr_t v_mapped_by_tlbcam(unsigned long va)
14cf11af PM	90	{
	91	int b;
	92	for (b = 0; b < tlbcam_index; ++b)
	93	if (va >= tlbcam_addrs[b].start && va < tlbcam_addrs[b].limit)
	94	return tlbcam_addrs[b].phys + (va - tlbcam_addrs[b].start);
	95	return 0;
	96	}
	97
	98	/*
	99	* Return VA for a given PA or 0 if not mapped
	100	*/
6c24b174	101	unsigned long p_mapped_by_tlbcam(phys_addr_t pa)
14cf11af PM	102	{
	103	int b;
	104	for (b = 0; b < tlbcam_index; ++b)
	105	if (pa >= tlbcam_addrs[b].phys
8b27f0b6	106	&& pa < (tlbcam_addrs[b].limit-tlbcam_addrs[b].start)
14cf11af PM	107	+tlbcam_addrs[b].phys)
	108	return tlbcam_addrs[b].start+(pa-tlbcam_addrs[b].phys);
	109	return 0;
	110	}
	111
8b27f0b6 KG	112	void loadcam_entry(int idx)
	113	{
	114	mtspr(SPRN_MAS0, TLBCAM[idx].MAS0);
	115	mtspr(SPRN_MAS1, TLBCAM[idx].MAS1);
	116	mtspr(SPRN_MAS2, TLBCAM[idx].MAS2);
	117	mtspr(SPRN_MAS3, TLBCAM[idx].MAS3);
	118
	119	if (cur_cpu_spec->cpu_features & MMU_FTR_BIG_PHYS)
	120	mtspr(SPRN_MAS7, TLBCAM[idx].MAS7);
	121
	122	asm volatile("isync;tlbwe;isync" : : : "memory");
	123	}
	124
14cf11af PM	125	/*
	126	* Set up one of the I/D BAT (block address translation) register pairs.
	127	* The parameters are not checked; in particular size must be a power
	128	* of 4 between 4k and 256M.
	129	*/
8b27f0b6 KG	130	static void settlbcam(int index, unsigned long virt, phys_addr_t phys,
8b27f0b6 KG	131	unsigned long size, unsigned long flags, unsigned int pid)
14cf11af PM	132	{
	133	unsigned int tsize, lz;
	134
8b27f0b6	135	asm (PPC_CNTLZL "%0,%1" : "=r" (lz) : "r" (size));
d66c82ea	136	tsize = 21 - lz;
14cf11af PM	137
	138	#ifdef CONFIG_SMP
	139	if ((flags & _PAGE_NO_CACHE) == 0)
	140	flags \|= _PAGE_COHERENT;
	141	#endif
	142
	143	TLBCAM[index].MAS0 = MAS0_TLBSEL(1) \| MAS0_ESEL(index) \| MAS0_NV(index+1);
	144	TLBCAM[index].MAS1 = MAS1_VALID \| MAS1_IPROT \| MAS1_TSIZE(tsize) \| MAS1_TID(pid);
	145	TLBCAM[index].MAS2 = virt & PAGE_MASK;
	146
	147	TLBCAM[index].MAS2 \|= (flags & _PAGE_WRITETHRU) ? MAS2_W : 0;
	148	TLBCAM[index].MAS2 \|= (flags & _PAGE_NO_CACHE) ? MAS2_I : 0;
	149	TLBCAM[index].MAS2 \|= (flags & _PAGE_COHERENT) ? MAS2_M : 0;
	150	TLBCAM[index].MAS2 \|= (flags & _PAGE_GUARDED) ? MAS2_G : 0;
	151	TLBCAM[index].MAS2 \|= (flags & _PAGE_ENDIAN) ? MAS2_E : 0;
	152
8b27f0b6	153	TLBCAM[index].MAS3 = (phys & MAS3_RPN) \| MAS3_SX \| MAS3_SR;
14cf11af	154	TLBCAM[index].MAS3 \|= ((flags & _PAGE_RW) ? MAS3_SW : 0);
8b27f0b6 KG	155	if (cur_cpu_spec->cpu_features & MMU_FTR_BIG_PHYS)
8b27f0b6 KG	156	TLBCAM[index].MAS7 = (u64)phys >> 32;
14cf11af PM	157
	158	#ifndef CONFIG_KGDB /* want user access for breakpoints */
	159	if (flags & _PAGE_USER) {
	160	TLBCAM[index].MAS3 \|= MAS3_UX \| MAS3_UR;
	161	TLBCAM[index].MAS3 \|= ((flags & _PAGE_RW) ? MAS3_UW : 0);
	162	}
	163	#else
	164	TLBCAM[index].MAS3 \|= MAS3_UX \| MAS3_UR;
	165	TLBCAM[index].MAS3 \|= ((flags & _PAGE_RW) ? MAS3_UW : 0);
	166	#endif
	167
	168	tlbcam_addrs[index].start = virt;
	169	tlbcam_addrs[index].limit = virt + size - 1;
	170	tlbcam_addrs[index].phys = phys;
	171
	172	loadcam_entry(index);
	173	}
	174
8b27f0b6	175	unsigned long map_mem_in_cams(unsigned long ram, int max_cam_idx)
14cf11af	176	{
8b27f0b6	177	int i;
f88747e7 TP	178	unsigned long virt = PAGE_OFFSET;
f88747e7 TP	179	phys_addr_t phys = memstart_addr;
8b27f0b6 KG	180	unsigned long amount_mapped = 0;
	181	unsigned long max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xf;
	182
	183	/* Convert (4^max) kB to (2^max) bytes */
	184	max_cam = max_cam * 2 + 10;
f88747e7	185
8b27f0b6 KG	186	/* Calculate CAM values */
	187	for (i = 0; ram && i < max_cam_idx; i++) {
	188	unsigned int camsize = __ilog2(ram) & ~1U;
	189	unsigned int align = __ffs(virt \| phys) & ~1U;
	190	unsigned long cam_sz;
	191
	192	if (camsize > align)
	193	camsize = align;
	194	if (camsize > max_cam)
	195	camsize = max_cam;
	196
	197	cam_sz = 1UL << camsize;
	198	settlbcam(i, virt, phys, cam_sz, PAGE_KERNEL_X, 0);
	199
	200	ram -= cam_sz;
	201	amount_mapped += cam_sz;
	202	virt += cam_sz;
	203	phys += cam_sz;
14cf11af	204	}
8b27f0b6 KG	205	tlbcam_index = i;
	206
	207	return amount_mapped;
	208	}
f88747e7	209
8b27f0b6 KG	210	unsigned long __init mmu_mapin_ram(void)
	211	{
	212	return tlbcam_addrs[tlbcam_index - 1].limit - PAGE_OFFSET + 1;
14cf11af PM	213	}
	214
	215	/*
	216	* MMU_init_hw does the chip-specific initialization of the MMU hardware.
	217	*/
	218	void __init MMU_init_hw(void)
	219	{
	220	flush_instruction_cache();
	221	}
	222
8b27f0b6	223	void __init adjust_total_lowmem(void)
14cf11af	224	{
8b27f0b6	225	unsigned long ram;
f88747e7	226	int i;
14cf11af	227
f88747e7 TP	228	/* adjust lowmem size to __max_low_memory */
f88747e7 TP	229	ram = min((phys_addr_t)__max_low_memory, (phys_addr_t)total_lowmem);
14cf11af	230
8b27f0b6	231	__max_low_memory = map_mem_in_cams(ram, CONFIG_LOWMEM_CAM_NUM);
c8f3570b	232
8b27f0b6 KG	233	pr_info("Memory CAM mapping: ");
	234	for (i = 0; i < tlbcam_index - 1; i++)
	235	pr_cont("%lu/", tlbcam_sz(i) >> 20);
	236	pr_cont("%lu Mb, residual: %dMb\n", tlbcam_sz(tlbcam_index - 1) >> 20,
96a8bac5	237	(unsigned int)((total_lowmem - __max_low_memory) >> 20));
8b27f0b6	238
09b5e63f	239	__initial_memory_limit_addr = memstart_addr + __max_low_memory;
14cf11af	240	}