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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * native hashtable management. | |
3 | * | |
4 | * SMP scalability work: | |
5 | * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version | |
10 | * 2 of the License, or (at your option) any later version. | |
11 | */ | |
3c726f8d BH |
12 | |
13 | #undef DEBUG_LOW | |
14 | ||
1da177e4 LT |
15 | #include <linux/spinlock.h> |
16 | #include <linux/bitops.h> | |
beacc6da | 17 | #include <linux/of.h> |
1da177e4 LT |
18 | #include <linux/threads.h> |
19 | #include <linux/smp.h> | |
20 | ||
1da177e4 LT |
21 | #include <asm/machdep.h> |
22 | #include <asm/mmu.h> | |
23 | #include <asm/mmu_context.h> | |
24 | #include <asm/pgtable.h> | |
25 | #include <asm/tlbflush.h> | |
26 | #include <asm/tlb.h> | |
27 | #include <asm/cputable.h> | |
3c726f8d | 28 | #include <asm/udbg.h> |
71bf08b6 | 29 | #include <asm/kexec.h> |
60dbf438 | 30 | #include <asm/ppc-opcode.h> |
3c726f8d BH |
31 | |
32 | #ifdef DEBUG_LOW | |
33 | #define DBG_LOW(fmt...) udbg_printf(fmt) | |
34 | #else | |
35 | #define DBG_LOW(fmt...) | |
36 | #endif | |
1da177e4 LT |
37 | |
38 | #define HPTE_LOCK_BIT 3 | |
39 | ||
9e368f29 | 40 | DEFINE_RAW_SPINLOCK(native_tlbie_lock); |
1da177e4 | 41 | |
5524a27d | 42 | static inline void __tlbie(unsigned long vpn, int psize, int ssize) |
3c726f8d | 43 | { |
5524a27d | 44 | unsigned long va; |
3c726f8d BH |
45 | unsigned int penc; |
46 | ||
5524a27d AK |
47 | /* |
48 | * We need 14 to 65 bits of va for a tlibe of 4K page | |
49 | * With vpn we ignore the lower VPN_SHIFT bits already. | |
50 | * And top two bits are already ignored because we can | |
51 | * only accomadate 76 bits in a 64 bit vpn with a VPN_SHIFT | |
52 | * of 12. | |
53 | */ | |
54 | va = vpn << VPN_SHIFT; | |
55 | /* | |
56 | * clear top 16 bits of 64bit va, non SLS segment | |
57 | * Older versions of the architecture (2.02 and earler) require the | |
58 | * masking of the top 16 bits. | |
59 | */ | |
3c726f8d BH |
60 | va &= ~(0xffffULL << 48); |
61 | ||
62 | switch (psize) { | |
63 | case MMU_PAGE_4K: | |
1189be65 | 64 | va |= ssize << 8; |
a32e252f | 65 | asm volatile(ASM_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0), %2) |
969391c5 | 66 | : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206) |
60dbf438 | 67 | : "memory"); |
3c726f8d BH |
68 | break; |
69 | default: | |
5524a27d | 70 | /* We need 14 to 14 + i bits of va */ |
3c726f8d BH |
71 | penc = mmu_psize_defs[psize].penc; |
72 | va &= ~((1ul << mmu_psize_defs[psize].shift) - 1); | |
19242b24 | 73 | va |= penc << 12; |
1189be65 | 74 | va |= ssize << 8; |
60dbf438 | 75 | va |= 1; /* L */ |
a32e252f | 76 | asm volatile(ASM_FTR_IFCLR("tlbie %0,1", PPC_TLBIE(%1,%0), %2) |
969391c5 | 77 | : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206) |
60dbf438 | 78 | : "memory"); |
3c726f8d BH |
79 | break; |
80 | } | |
81 | } | |
82 | ||
5524a27d | 83 | static inline void __tlbiel(unsigned long vpn, int psize, int ssize) |
3c726f8d | 84 | { |
5524a27d | 85 | unsigned long va; |
3c726f8d BH |
86 | unsigned int penc; |
87 | ||
5524a27d AK |
88 | /* VPN_SHIFT can be atmost 12 */ |
89 | va = vpn << VPN_SHIFT; | |
90 | /* | |
91 | * clear top 16 bits of 64 bit va, non SLS segment | |
92 | * Older versions of the architecture (2.02 and earler) require the | |
93 | * masking of the top 16 bits. | |
94 | */ | |
3c726f8d BH |
95 | va &= ~(0xffffULL << 48); |
96 | ||
97 | switch (psize) { | |
98 | case MMU_PAGE_4K: | |
1189be65 | 99 | va |= ssize << 8; |
3c726f8d BH |
100 | asm volatile(".long 0x7c000224 | (%0 << 11) | (0 << 21)" |
101 | : : "r"(va) : "memory"); | |
102 | break; | |
103 | default: | |
5524a27d | 104 | /* We need 14 to 14 + i bits of va */ |
3c726f8d BH |
105 | penc = mmu_psize_defs[psize].penc; |
106 | va &= ~((1ul << mmu_psize_defs[psize].shift) - 1); | |
19242b24 | 107 | va |= penc << 12; |
1189be65 | 108 | va |= ssize << 8; |
60dbf438 | 109 | va |= 1; /* L */ |
3c726f8d BH |
110 | asm volatile(".long 0x7c000224 | (%0 << 11) | (1 << 21)" |
111 | : : "r"(va) : "memory"); | |
112 | break; | |
113 | } | |
114 | ||
115 | } | |
116 | ||
5524a27d | 117 | static inline void tlbie(unsigned long vpn, int psize, int ssize, int local) |
3c726f8d | 118 | { |
44ae3ab3 ME |
119 | unsigned int use_local = local && mmu_has_feature(MMU_FTR_TLBIEL); |
120 | int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE); | |
3c726f8d BH |
121 | |
122 | if (use_local) | |
123 | use_local = mmu_psize_defs[psize].tlbiel; | |
124 | if (lock_tlbie && !use_local) | |
6b9c9b8a | 125 | raw_spin_lock(&native_tlbie_lock); |
3c726f8d BH |
126 | asm volatile("ptesync": : :"memory"); |
127 | if (use_local) { | |
5524a27d | 128 | __tlbiel(vpn, psize, ssize); |
3c726f8d BH |
129 | asm volatile("ptesync": : :"memory"); |
130 | } else { | |
5524a27d | 131 | __tlbie(vpn, psize, ssize); |
3c726f8d BH |
132 | asm volatile("eieio; tlbsync; ptesync": : :"memory"); |
133 | } | |
134 | if (lock_tlbie && !use_local) | |
6b9c9b8a | 135 | raw_spin_unlock(&native_tlbie_lock); |
3c726f8d BH |
136 | } |
137 | ||
8e561e7e | 138 | static inline void native_lock_hpte(struct hash_pte *hptep) |
1da177e4 | 139 | { |
96e28449 | 140 | unsigned long *word = &hptep->v; |
1da177e4 LT |
141 | |
142 | while (1) { | |
66d99b88 | 143 | if (!test_and_set_bit_lock(HPTE_LOCK_BIT, word)) |
1da177e4 LT |
144 | break; |
145 | while(test_bit(HPTE_LOCK_BIT, word)) | |
146 | cpu_relax(); | |
147 | } | |
148 | } | |
149 | ||
8e561e7e | 150 | static inline void native_unlock_hpte(struct hash_pte *hptep) |
1da177e4 | 151 | { |
96e28449 | 152 | unsigned long *word = &hptep->v; |
1da177e4 | 153 | |
66d99b88 | 154 | clear_bit_unlock(HPTE_LOCK_BIT, word); |
1da177e4 LT |
155 | } |
156 | ||
5524a27d | 157 | static long native_hpte_insert(unsigned long hpte_group, unsigned long vpn, |
3c726f8d | 158 | unsigned long pa, unsigned long rflags, |
1189be65 | 159 | unsigned long vflags, int psize, int ssize) |
1da177e4 | 160 | { |
8e561e7e | 161 | struct hash_pte *hptep = htab_address + hpte_group; |
96e28449 | 162 | unsigned long hpte_v, hpte_r; |
1da177e4 LT |
163 | int i; |
164 | ||
3c726f8d | 165 | if (!(vflags & HPTE_V_BOLTED)) { |
5524a27d | 166 | DBG_LOW(" insert(group=%lx, vpn=%016lx, pa=%016lx," |
3c726f8d | 167 | " rflags=%lx, vflags=%lx, psize=%d)\n", |
5524a27d | 168 | hpte_group, vpn, pa, rflags, vflags, psize); |
3c726f8d BH |
169 | } |
170 | ||
1da177e4 | 171 | for (i = 0; i < HPTES_PER_GROUP; i++) { |
96e28449 | 172 | if (! (hptep->v & HPTE_V_VALID)) { |
1da177e4 LT |
173 | /* retry with lock held */ |
174 | native_lock_hpte(hptep); | |
96e28449 | 175 | if (! (hptep->v & HPTE_V_VALID)) |
1da177e4 LT |
176 | break; |
177 | native_unlock_hpte(hptep); | |
178 | } | |
179 | ||
180 | hptep++; | |
181 | } | |
182 | ||
183 | if (i == HPTES_PER_GROUP) | |
184 | return -1; | |
185 | ||
5524a27d | 186 | hpte_v = hpte_encode_v(vpn, psize, ssize) | vflags | HPTE_V_VALID; |
3c726f8d BH |
187 | hpte_r = hpte_encode_r(pa, psize) | rflags; |
188 | ||
189 | if (!(vflags & HPTE_V_BOLTED)) { | |
190 | DBG_LOW(" i=%x hpte_v=%016lx, hpte_r=%016lx\n", | |
191 | i, hpte_v, hpte_r); | |
192 | } | |
1da177e4 | 193 | |
96e28449 | 194 | hptep->r = hpte_r; |
1da177e4 | 195 | /* Guarantee the second dword is visible before the valid bit */ |
74a0ba61 | 196 | eieio(); |
1da177e4 LT |
197 | /* |
198 | * Now set the first dword including the valid bit | |
199 | * NOTE: this also unlocks the hpte | |
200 | */ | |
96e28449 | 201 | hptep->v = hpte_v; |
1da177e4 LT |
202 | |
203 | __asm__ __volatile__ ("ptesync" : : : "memory"); | |
204 | ||
96e28449 | 205 | return i | (!!(vflags & HPTE_V_SECONDARY) << 3); |
1da177e4 LT |
206 | } |
207 | ||
208 | static long native_hpte_remove(unsigned long hpte_group) | |
209 | { | |
8e561e7e | 210 | struct hash_pte *hptep; |
1da177e4 LT |
211 | int i; |
212 | int slot_offset; | |
96e28449 | 213 | unsigned long hpte_v; |
1da177e4 | 214 | |
3c726f8d BH |
215 | DBG_LOW(" remove(group=%lx)\n", hpte_group); |
216 | ||
1da177e4 LT |
217 | /* pick a random entry to start at */ |
218 | slot_offset = mftb() & 0x7; | |
219 | ||
220 | for (i = 0; i < HPTES_PER_GROUP; i++) { | |
221 | hptep = htab_address + hpte_group + slot_offset; | |
96e28449 | 222 | hpte_v = hptep->v; |
1da177e4 | 223 | |
96e28449 | 224 | if ((hpte_v & HPTE_V_VALID) && !(hpte_v & HPTE_V_BOLTED)) { |
1da177e4 LT |
225 | /* retry with lock held */ |
226 | native_lock_hpte(hptep); | |
96e28449 DG |
227 | hpte_v = hptep->v; |
228 | if ((hpte_v & HPTE_V_VALID) | |
229 | && !(hpte_v & HPTE_V_BOLTED)) | |
1da177e4 LT |
230 | break; |
231 | native_unlock_hpte(hptep); | |
232 | } | |
233 | ||
234 | slot_offset++; | |
235 | slot_offset &= 0x7; | |
236 | } | |
237 | ||
238 | if (i == HPTES_PER_GROUP) | |
239 | return -1; | |
240 | ||
241 | /* Invalidate the hpte. NOTE: this also unlocks it */ | |
96e28449 | 242 | hptep->v = 0; |
1da177e4 LT |
243 | |
244 | return i; | |
245 | } | |
246 | ||
3c726f8d | 247 | static long native_hpte_updatepp(unsigned long slot, unsigned long newpp, |
5524a27d | 248 | unsigned long vpn, int psize, int ssize, |
1189be65 | 249 | int local) |
1da177e4 | 250 | { |
8e561e7e | 251 | struct hash_pte *hptep = htab_address + slot; |
3c726f8d BH |
252 | unsigned long hpte_v, want_v; |
253 | int ret = 0; | |
254 | ||
5524a27d | 255 | want_v = hpte_encode_v(vpn, psize, ssize); |
3c726f8d | 256 | |
5524a27d AK |
257 | DBG_LOW(" update(vpn=%016lx, avpnv=%016lx, group=%lx, newpp=%lx)", |
258 | vpn, want_v & HPTE_V_AVPN, slot, newpp); | |
3c726f8d BH |
259 | |
260 | native_lock_hpte(hptep); | |
261 | ||
262 | hpte_v = hptep->v; | |
263 | ||
264 | /* Even if we miss, we need to invalidate the TLB */ | |
265 | if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID)) { | |
266 | DBG_LOW(" -> miss\n"); | |
3c726f8d BH |
267 | ret = -1; |
268 | } else { | |
269 | DBG_LOW(" -> hit\n"); | |
270 | /* Update the HPTE */ | |
271 | hptep->r = (hptep->r & ~(HPTE_R_PP | HPTE_R_N)) | | |
c5cf0e30 | 272 | (newpp & (HPTE_R_PP | HPTE_R_N | HPTE_R_C)); |
3c726f8d | 273 | } |
3f1df7a2 | 274 | native_unlock_hpte(hptep); |
3c726f8d BH |
275 | |
276 | /* Ensure it is out of the tlb too. */ | |
5524a27d | 277 | tlbie(vpn, psize, ssize, local); |
3c726f8d BH |
278 | |
279 | return ret; | |
1da177e4 LT |
280 | } |
281 | ||
5524a27d | 282 | static long native_hpte_find(unsigned long vpn, int psize, int ssize) |
1da177e4 | 283 | { |
8e561e7e | 284 | struct hash_pte *hptep; |
1da177e4 | 285 | unsigned long hash; |
1189be65 | 286 | unsigned long i; |
1da177e4 | 287 | long slot; |
3c726f8d | 288 | unsigned long want_v, hpte_v; |
1da177e4 | 289 | |
5524a27d AK |
290 | hash = hpt_hash(vpn, mmu_psize_defs[psize].shift, ssize); |
291 | want_v = hpte_encode_v(vpn, psize, ssize); | |
1da177e4 | 292 | |
1189be65 PM |
293 | /* Bolted mappings are only ever in the primary group */ |
294 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
295 | for (i = 0; i < HPTES_PER_GROUP; i++) { | |
296 | hptep = htab_address + slot; | |
297 | hpte_v = hptep->v; | |
1da177e4 | 298 | |
1189be65 PM |
299 | if (HPTE_V_COMPARE(hpte_v, want_v) && (hpte_v & HPTE_V_VALID)) |
300 | /* HPTE matches */ | |
301 | return slot; | |
302 | ++slot; | |
1da177e4 LT |
303 | } |
304 | ||
305 | return -1; | |
306 | } | |
307 | ||
1da177e4 LT |
308 | /* |
309 | * Update the page protection bits. Intended to be used to create | |
310 | * guard pages for kernel data structures on pages which are bolted | |
311 | * in the HPT. Assumes pages being operated on will not be stolen. | |
1da177e4 LT |
312 | * |
313 | * No need to lock here because we should be the only user. | |
314 | */ | |
3c726f8d | 315 | static void native_hpte_updateboltedpp(unsigned long newpp, unsigned long ea, |
1189be65 | 316 | int psize, int ssize) |
1da177e4 | 317 | { |
5524a27d AK |
318 | unsigned long vpn; |
319 | unsigned long vsid; | |
1da177e4 | 320 | long slot; |
8e561e7e | 321 | struct hash_pte *hptep; |
1da177e4 | 322 | |
1189be65 | 323 | vsid = get_kernel_vsid(ea, ssize); |
5524a27d | 324 | vpn = hpt_vpn(ea, vsid, ssize); |
1da177e4 | 325 | |
5524a27d | 326 | slot = native_hpte_find(vpn, psize, ssize); |
1da177e4 LT |
327 | if (slot == -1) |
328 | panic("could not find page to bolt\n"); | |
329 | hptep = htab_address + slot; | |
330 | ||
3c726f8d BH |
331 | /* Update the HPTE */ |
332 | hptep->r = (hptep->r & ~(HPTE_R_PP | HPTE_R_N)) | | |
333 | (newpp & (HPTE_R_PP | HPTE_R_N)); | |
1da177e4 | 334 | |
3c726f8d | 335 | /* Ensure it is out of the tlb too. */ |
5524a27d | 336 | tlbie(vpn, psize, ssize, 0); |
1da177e4 LT |
337 | } |
338 | ||
5524a27d | 339 | static void native_hpte_invalidate(unsigned long slot, unsigned long vpn, |
1189be65 | 340 | int psize, int ssize, int local) |
1da177e4 | 341 | { |
8e561e7e | 342 | struct hash_pte *hptep = htab_address + slot; |
96e28449 | 343 | unsigned long hpte_v; |
3c726f8d | 344 | unsigned long want_v; |
1da177e4 | 345 | unsigned long flags; |
1da177e4 LT |
346 | |
347 | local_irq_save(flags); | |
1da177e4 | 348 | |
5524a27d | 349 | DBG_LOW(" invalidate(vpn=%016lx, hash: %lx)\n", vpn, slot); |
3c726f8d | 350 | |
5524a27d | 351 | want_v = hpte_encode_v(vpn, psize, ssize); |
3c726f8d | 352 | native_lock_hpte(hptep); |
96e28449 | 353 | hpte_v = hptep->v; |
1da177e4 LT |
354 | |
355 | /* Even if we miss, we need to invalidate the TLB */ | |
3c726f8d | 356 | if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID)) |
1da177e4 | 357 | native_unlock_hpte(hptep); |
3c726f8d | 358 | else |
1da177e4 | 359 | /* Invalidate the hpte. NOTE: this also unlocks it */ |
96e28449 | 360 | hptep->v = 0; |
1da177e4 | 361 | |
3c726f8d | 362 | /* Invalidate the TLB */ |
5524a27d | 363 | tlbie(vpn, psize, ssize, local); |
3c726f8d | 364 | |
1da177e4 LT |
365 | local_irq_restore(flags); |
366 | } | |
367 | ||
71bf08b6 LB |
368 | #define LP_SHIFT 12 |
369 | #define LP_BITS 8 | |
370 | #define LP_MASK(i) ((0xFF >> (i)) << LP_SHIFT) | |
3c726f8d | 371 | |
8e561e7e | 372 | static void hpte_decode(struct hash_pte *hpte, unsigned long slot, |
5524a27d | 373 | int *psize, int *ssize, unsigned long *vpn) |
71bf08b6 | 374 | { |
dcda287a | 375 | unsigned long avpn, pteg, vpi; |
71bf08b6 LB |
376 | unsigned long hpte_r = hpte->r; |
377 | unsigned long hpte_v = hpte->v; | |
dcda287a | 378 | unsigned long vsid, seg_off; |
8980ae86 | 379 | int i, size, shift, penc; |
71bf08b6 LB |
380 | |
381 | if (!(hpte_v & HPTE_V_LARGE)) | |
382 | size = MMU_PAGE_4K; | |
383 | else { | |
384 | for (i = 0; i < LP_BITS; i++) { | |
385 | if ((hpte_r & LP_MASK(i+1)) == LP_MASK(i+1)) | |
386 | break; | |
387 | } | |
388 | penc = LP_MASK(i+1) >> LP_SHIFT; | |
389 | for (size = 0; size < MMU_PAGE_COUNT; size++) { | |
3c726f8d | 390 | |
71bf08b6 LB |
391 | /* 4K pages are not represented by LP */ |
392 | if (size == MMU_PAGE_4K) | |
393 | continue; | |
3c726f8d | 394 | |
71bf08b6 LB |
395 | /* valid entries have a shift value */ |
396 | if (!mmu_psize_defs[size].shift) | |
397 | continue; | |
3c726f8d | 398 | |
71bf08b6 LB |
399 | if (penc == mmu_psize_defs[size].penc) |
400 | break; | |
401 | } | |
402 | } | |
3c726f8d | 403 | |
2454c7e9 | 404 | /* This works for all page sizes, and for 256M and 1T segments */ |
dcda287a | 405 | *ssize = hpte_v >> HPTE_V_SSIZE_SHIFT; |
71bf08b6 | 406 | shift = mmu_psize_defs[size].shift; |
71bf08b6 | 407 | |
dcda287a AK |
408 | avpn = (HPTE_V_AVPN_VAL(hpte_v) & ~mmu_psize_defs[size].avpnm); |
409 | pteg = slot / HPTES_PER_GROUP; | |
410 | if (hpte_v & HPTE_V_SECONDARY) | |
411 | pteg = ~pteg; | |
412 | ||
413 | switch (*ssize) { | |
414 | case MMU_SEGSIZE_256M: | |
415 | /* We only have 28 - 23 bits of seg_off in avpn */ | |
416 | seg_off = (avpn & 0x1f) << 23; | |
417 | vsid = avpn >> 5; | |
418 | /* We can find more bits from the pteg value */ | |
419 | if (shift < 23) { | |
420 | vpi = (vsid ^ pteg) & htab_hash_mask; | |
421 | seg_off |= vpi << shift; | |
422 | } | |
5524a27d | 423 | *vpn = vsid << (SID_SHIFT - VPN_SHIFT) | seg_off >> VPN_SHIFT; |
dcda287a AK |
424 | case MMU_SEGSIZE_1T: |
425 | /* We only have 40 - 23 bits of seg_off in avpn */ | |
426 | seg_off = (avpn & 0x1ffff) << 23; | |
427 | vsid = avpn >> 17; | |
428 | if (shift < 23) { | |
2454c7e9 | 429 | vpi = (vsid ^ (vsid << 25) ^ pteg) & htab_hash_mask; |
dcda287a | 430 | seg_off |= vpi << shift; |
71bf08b6 | 431 | } |
5524a27d | 432 | *vpn = vsid << (SID_SHIFT_1T - VPN_SHIFT) | seg_off >> VPN_SHIFT; |
dcda287a | 433 | default: |
5524a27d | 434 | *vpn = size = 0; |
3c726f8d | 435 | } |
71bf08b6 | 436 | *psize = size; |
3c726f8d BH |
437 | } |
438 | ||
f4c82d51 S |
439 | /* |
440 | * clear all mappings on kexec. All cpus are in real mode (or they will | |
441 | * be when they isi), and we are the only one left. We rely on our kernel | |
442 | * mapping being 0xC0's and the hardware ignoring those two real bits. | |
443 | * | |
444 | * TODO: add batching support when enabled. remember, no dynamic memory here, | |
445 | * athough there is the control page available... | |
446 | */ | |
447 | static void native_hpte_clear(void) | |
448 | { | |
5524a27d | 449 | unsigned long vpn = 0; |
f4c82d51 | 450 | unsigned long slot, slots, flags; |
8e561e7e | 451 | struct hash_pte *hptep = htab_address; |
5524a27d | 452 | unsigned long hpte_v; |
f4c82d51 | 453 | unsigned long pteg_count; |
1189be65 | 454 | int psize, ssize; |
f4c82d51 S |
455 | |
456 | pteg_count = htab_hash_mask + 1; | |
457 | ||
458 | local_irq_save(flags); | |
459 | ||
460 | /* we take the tlbie lock and hold it. Some hardware will | |
461 | * deadlock if we try to tlbie from two processors at once. | |
462 | */ | |
6b9c9b8a | 463 | raw_spin_lock(&native_tlbie_lock); |
f4c82d51 S |
464 | |
465 | slots = pteg_count * HPTES_PER_GROUP; | |
466 | ||
467 | for (slot = 0; slot < slots; slot++, hptep++) { | |
468 | /* | |
469 | * we could lock the pte here, but we are the only cpu | |
470 | * running, right? and for crash dump, we probably | |
471 | * don't want to wait for a maybe bad cpu. | |
472 | */ | |
96e28449 | 473 | hpte_v = hptep->v; |
f4c82d51 | 474 | |
47f78a49 S |
475 | /* |
476 | * Call __tlbie() here rather than tlbie() since we | |
477 | * already hold the native_tlbie_lock. | |
478 | */ | |
96e28449 | 479 | if (hpte_v & HPTE_V_VALID) { |
5524a27d | 480 | hpte_decode(hptep, slot, &psize, &ssize, &vpn); |
96e28449 | 481 | hptep->v = 0; |
5524a27d | 482 | __tlbie(vpn, psize, ssize); |
f4c82d51 S |
483 | } |
484 | } | |
485 | ||
47f78a49 | 486 | asm volatile("eieio; tlbsync; ptesync":::"memory"); |
6b9c9b8a | 487 | raw_spin_unlock(&native_tlbie_lock); |
f4c82d51 S |
488 | local_irq_restore(flags); |
489 | } | |
490 | ||
3c726f8d BH |
491 | /* |
492 | * Batched hash table flush, we batch the tlbie's to avoid taking/releasing | |
493 | * the lock all the time | |
494 | */ | |
61b1a942 | 495 | static void native_flush_hash_range(unsigned long number, int local) |
1da177e4 | 496 | { |
5524a27d AK |
497 | unsigned long vpn; |
498 | unsigned long hash, index, hidx, shift, slot; | |
8e561e7e | 499 | struct hash_pte *hptep; |
96e28449 | 500 | unsigned long hpte_v; |
3c726f8d BH |
501 | unsigned long want_v; |
502 | unsigned long flags; | |
503 | real_pte_t pte; | |
1da177e4 | 504 | struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch); |
3c726f8d | 505 | unsigned long psize = batch->psize; |
1189be65 | 506 | int ssize = batch->ssize; |
3c726f8d | 507 | int i; |
1da177e4 LT |
508 | |
509 | local_irq_save(flags); | |
510 | ||
1da177e4 | 511 | for (i = 0; i < number; i++) { |
5524a27d | 512 | vpn = batch->vpn[i]; |
3c726f8d BH |
513 | pte = batch->pte[i]; |
514 | ||
5524a27d AK |
515 | pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) { |
516 | hash = hpt_hash(vpn, shift, ssize); | |
3c726f8d BH |
517 | hidx = __rpte_to_hidx(pte, index); |
518 | if (hidx & _PTEIDX_SECONDARY) | |
519 | hash = ~hash; | |
520 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
521 | slot += hidx & _PTEIDX_GROUP_IX; | |
522 | hptep = htab_address + slot; | |
5524a27d | 523 | want_v = hpte_encode_v(vpn, psize, ssize); |
3c726f8d BH |
524 | native_lock_hpte(hptep); |
525 | hpte_v = hptep->v; | |
526 | if (!HPTE_V_COMPARE(hpte_v, want_v) || | |
527 | !(hpte_v & HPTE_V_VALID)) | |
528 | native_unlock_hpte(hptep); | |
529 | else | |
530 | hptep->v = 0; | |
531 | } pte_iterate_hashed_end(); | |
1da177e4 LT |
532 | } |
533 | ||
44ae3ab3 | 534 | if (mmu_has_feature(MMU_FTR_TLBIEL) && |
3c726f8d | 535 | mmu_psize_defs[psize].tlbiel && local) { |
1da177e4 | 536 | asm volatile("ptesync":::"memory"); |
3c726f8d | 537 | for (i = 0; i < number; i++) { |
5524a27d | 538 | vpn = batch->vpn[i]; |
3c726f8d BH |
539 | pte = batch->pte[i]; |
540 | ||
5524a27d AK |
541 | pte_iterate_hashed_subpages(pte, psize, |
542 | vpn, index, shift) { | |
543 | __tlbiel(vpn, psize, ssize); | |
3c726f8d BH |
544 | } pte_iterate_hashed_end(); |
545 | } | |
1da177e4 LT |
546 | asm volatile("ptesync":::"memory"); |
547 | } else { | |
44ae3ab3 | 548 | int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE); |
1da177e4 LT |
549 | |
550 | if (lock_tlbie) | |
6b9c9b8a | 551 | raw_spin_lock(&native_tlbie_lock); |
1da177e4 LT |
552 | |
553 | asm volatile("ptesync":::"memory"); | |
3c726f8d | 554 | for (i = 0; i < number; i++) { |
5524a27d | 555 | vpn = batch->vpn[i]; |
3c726f8d BH |
556 | pte = batch->pte[i]; |
557 | ||
5524a27d AK |
558 | pte_iterate_hashed_subpages(pte, psize, |
559 | vpn, index, shift) { | |
560 | __tlbie(vpn, psize, ssize); | |
3c726f8d BH |
561 | } pte_iterate_hashed_end(); |
562 | } | |
1da177e4 LT |
563 | asm volatile("eieio; tlbsync; ptesync":::"memory"); |
564 | ||
565 | if (lock_tlbie) | |
6b9c9b8a | 566 | raw_spin_unlock(&native_tlbie_lock); |
1da177e4 LT |
567 | } |
568 | ||
569 | local_irq_restore(flags); | |
570 | } | |
571 | ||
7d0daae4 | 572 | void __init hpte_init_native(void) |
1da177e4 LT |
573 | { |
574 | ppc_md.hpte_invalidate = native_hpte_invalidate; | |
575 | ppc_md.hpte_updatepp = native_hpte_updatepp; | |
576 | ppc_md.hpte_updateboltedpp = native_hpte_updateboltedpp; | |
577 | ppc_md.hpte_insert = native_hpte_insert; | |
f4c82d51 S |
578 | ppc_md.hpte_remove = native_hpte_remove; |
579 | ppc_md.hpte_clear_all = native_hpte_clear; | |
8e166991 | 580 | ppc_md.flush_hash_range = native_flush_hash_range; |
1da177e4 | 581 | } |