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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * native hashtable management. | |
3 | * | |
4 | * SMP scalability work: | |
5 | * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version | |
10 | * 2 of the License, or (at your option) any later version. | |
11 | */ | |
3c726f8d BH |
12 | |
13 | #undef DEBUG_LOW | |
14 | ||
1da177e4 LT |
15 | #include <linux/spinlock.h> |
16 | #include <linux/bitops.h> | |
17 | #include <linux/threads.h> | |
18 | #include <linux/smp.h> | |
19 | ||
20 | #include <asm/abs_addr.h> | |
21 | #include <asm/machdep.h> | |
22 | #include <asm/mmu.h> | |
23 | #include <asm/mmu_context.h> | |
24 | #include <asm/pgtable.h> | |
25 | #include <asm/tlbflush.h> | |
26 | #include <asm/tlb.h> | |
27 | #include <asm/cputable.h> | |
3c726f8d BH |
28 | #include <asm/udbg.h> |
29 | ||
30 | #ifdef DEBUG_LOW | |
31 | #define DBG_LOW(fmt...) udbg_printf(fmt) | |
32 | #else | |
33 | #define DBG_LOW(fmt...) | |
34 | #endif | |
1da177e4 LT |
35 | |
36 | #define HPTE_LOCK_BIT 3 | |
37 | ||
38 | static DEFINE_SPINLOCK(native_tlbie_lock); | |
39 | ||
3c726f8d BH |
40 | static inline void __tlbie(unsigned long va, unsigned int psize) |
41 | { | |
42 | unsigned int penc; | |
43 | ||
44 | /* clear top 16 bits, non SLS segment */ | |
45 | va &= ~(0xffffULL << 48); | |
46 | ||
47 | switch (psize) { | |
48 | case MMU_PAGE_4K: | |
49 | va &= ~0xffful; | |
50 | asm volatile("tlbie %0,0" : : "r" (va) : "memory"); | |
51 | break; | |
52 | default: | |
53 | penc = mmu_psize_defs[psize].penc; | |
54 | va &= ~((1ul << mmu_psize_defs[psize].shift) - 1); | |
19242b24 | 55 | va |= penc << 12; |
3c726f8d BH |
56 | asm volatile("tlbie %0,1" : : "r" (va) : "memory"); |
57 | break; | |
58 | } | |
59 | } | |
60 | ||
61 | static inline void __tlbiel(unsigned long va, unsigned int psize) | |
62 | { | |
63 | unsigned int penc; | |
64 | ||
65 | /* clear top 16 bits, non SLS segment */ | |
66 | va &= ~(0xffffULL << 48); | |
67 | ||
68 | switch (psize) { | |
69 | case MMU_PAGE_4K: | |
70 | va &= ~0xffful; | |
71 | asm volatile(".long 0x7c000224 | (%0 << 11) | (0 << 21)" | |
72 | : : "r"(va) : "memory"); | |
73 | break; | |
74 | default: | |
75 | penc = mmu_psize_defs[psize].penc; | |
76 | va &= ~((1ul << mmu_psize_defs[psize].shift) - 1); | |
19242b24 | 77 | va |= penc << 12; |
3c726f8d BH |
78 | asm volatile(".long 0x7c000224 | (%0 << 11) | (1 << 21)" |
79 | : : "r"(va) : "memory"); | |
80 | break; | |
81 | } | |
82 | ||
83 | } | |
84 | ||
85 | static inline void tlbie(unsigned long va, int psize, int local) | |
86 | { | |
87 | unsigned int use_local = local && cpu_has_feature(CPU_FTR_TLBIEL); | |
88 | int lock_tlbie = !cpu_has_feature(CPU_FTR_LOCKLESS_TLBIE); | |
89 | ||
90 | if (use_local) | |
91 | use_local = mmu_psize_defs[psize].tlbiel; | |
92 | if (lock_tlbie && !use_local) | |
93 | spin_lock(&native_tlbie_lock); | |
94 | asm volatile("ptesync": : :"memory"); | |
95 | if (use_local) { | |
96 | __tlbiel(va, psize); | |
97 | asm volatile("ptesync": : :"memory"); | |
98 | } else { | |
99 | __tlbie(va, psize); | |
100 | asm volatile("eieio; tlbsync; ptesync": : :"memory"); | |
101 | } | |
102 | if (lock_tlbie && !use_local) | |
103 | spin_unlock(&native_tlbie_lock); | |
104 | } | |
105 | ||
96e28449 | 106 | static inline void native_lock_hpte(hpte_t *hptep) |
1da177e4 | 107 | { |
96e28449 | 108 | unsigned long *word = &hptep->v; |
1da177e4 LT |
109 | |
110 | while (1) { | |
111 | if (!test_and_set_bit(HPTE_LOCK_BIT, word)) | |
112 | break; | |
113 | while(test_bit(HPTE_LOCK_BIT, word)) | |
114 | cpu_relax(); | |
115 | } | |
116 | } | |
117 | ||
96e28449 | 118 | static inline void native_unlock_hpte(hpte_t *hptep) |
1da177e4 | 119 | { |
96e28449 | 120 | unsigned long *word = &hptep->v; |
1da177e4 LT |
121 | |
122 | asm volatile("lwsync":::"memory"); | |
123 | clear_bit(HPTE_LOCK_BIT, word); | |
124 | } | |
125 | ||
035223fb | 126 | static long native_hpte_insert(unsigned long hpte_group, unsigned long va, |
3c726f8d BH |
127 | unsigned long pa, unsigned long rflags, |
128 | unsigned long vflags, int psize) | |
1da177e4 | 129 | { |
96e28449 DG |
130 | hpte_t *hptep = htab_address + hpte_group; |
131 | unsigned long hpte_v, hpte_r; | |
1da177e4 LT |
132 | int i; |
133 | ||
3c726f8d BH |
134 | if (!(vflags & HPTE_V_BOLTED)) { |
135 | DBG_LOW(" insert(group=%lx, va=%016lx, pa=%016lx," | |
136 | " rflags=%lx, vflags=%lx, psize=%d)\n", | |
137 | hpte_group, va, pa, rflags, vflags, psize); | |
138 | } | |
139 | ||
1da177e4 | 140 | for (i = 0; i < HPTES_PER_GROUP; i++) { |
96e28449 | 141 | if (! (hptep->v & HPTE_V_VALID)) { |
1da177e4 LT |
142 | /* retry with lock held */ |
143 | native_lock_hpte(hptep); | |
96e28449 | 144 | if (! (hptep->v & HPTE_V_VALID)) |
1da177e4 LT |
145 | break; |
146 | native_unlock_hpte(hptep); | |
147 | } | |
148 | ||
149 | hptep++; | |
150 | } | |
151 | ||
152 | if (i == HPTES_PER_GROUP) | |
153 | return -1; | |
154 | ||
3c726f8d BH |
155 | hpte_v = hpte_encode_v(va, psize) | vflags | HPTE_V_VALID; |
156 | hpte_r = hpte_encode_r(pa, psize) | rflags; | |
157 | ||
158 | if (!(vflags & HPTE_V_BOLTED)) { | |
159 | DBG_LOW(" i=%x hpte_v=%016lx, hpte_r=%016lx\n", | |
160 | i, hpte_v, hpte_r); | |
161 | } | |
1da177e4 | 162 | |
96e28449 | 163 | hptep->r = hpte_r; |
1da177e4 LT |
164 | /* Guarantee the second dword is visible before the valid bit */ |
165 | __asm__ __volatile__ ("eieio" : : : "memory"); | |
1da177e4 LT |
166 | /* |
167 | * Now set the first dword including the valid bit | |
168 | * NOTE: this also unlocks the hpte | |
169 | */ | |
96e28449 | 170 | hptep->v = hpte_v; |
1da177e4 LT |
171 | |
172 | __asm__ __volatile__ ("ptesync" : : : "memory"); | |
173 | ||
96e28449 | 174 | return i | (!!(vflags & HPTE_V_SECONDARY) << 3); |
1da177e4 LT |
175 | } |
176 | ||
177 | static long native_hpte_remove(unsigned long hpte_group) | |
178 | { | |
96e28449 | 179 | hpte_t *hptep; |
1da177e4 LT |
180 | int i; |
181 | int slot_offset; | |
96e28449 | 182 | unsigned long hpte_v; |
1da177e4 | 183 | |
3c726f8d BH |
184 | DBG_LOW(" remove(group=%lx)\n", hpte_group); |
185 | ||
1da177e4 LT |
186 | /* pick a random entry to start at */ |
187 | slot_offset = mftb() & 0x7; | |
188 | ||
189 | for (i = 0; i < HPTES_PER_GROUP; i++) { | |
190 | hptep = htab_address + hpte_group + slot_offset; | |
96e28449 | 191 | hpte_v = hptep->v; |
1da177e4 | 192 | |
96e28449 | 193 | if ((hpte_v & HPTE_V_VALID) && !(hpte_v & HPTE_V_BOLTED)) { |
1da177e4 LT |
194 | /* retry with lock held */ |
195 | native_lock_hpte(hptep); | |
96e28449 DG |
196 | hpte_v = hptep->v; |
197 | if ((hpte_v & HPTE_V_VALID) | |
198 | && !(hpte_v & HPTE_V_BOLTED)) | |
1da177e4 LT |
199 | break; |
200 | native_unlock_hpte(hptep); | |
201 | } | |
202 | ||
203 | slot_offset++; | |
204 | slot_offset &= 0x7; | |
205 | } | |
206 | ||
207 | if (i == HPTES_PER_GROUP) | |
208 | return -1; | |
209 | ||
210 | /* Invalidate the hpte. NOTE: this also unlocks it */ | |
96e28449 | 211 | hptep->v = 0; |
1da177e4 LT |
212 | |
213 | return i; | |
214 | } | |
215 | ||
3c726f8d BH |
216 | static long native_hpte_updatepp(unsigned long slot, unsigned long newpp, |
217 | unsigned long va, int psize, int local) | |
1da177e4 | 218 | { |
3c726f8d BH |
219 | hpte_t *hptep = htab_address + slot; |
220 | unsigned long hpte_v, want_v; | |
221 | int ret = 0; | |
222 | ||
223 | want_v = hpte_encode_v(va, psize); | |
224 | ||
225 | DBG_LOW(" update(va=%016lx, avpnv=%016lx, hash=%016lx, newpp=%x)", | |
226 | va, want_v & HPTE_V_AVPN, slot, newpp); | |
227 | ||
228 | native_lock_hpte(hptep); | |
229 | ||
230 | hpte_v = hptep->v; | |
231 | ||
232 | /* Even if we miss, we need to invalidate the TLB */ | |
233 | if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID)) { | |
234 | DBG_LOW(" -> miss\n"); | |
235 | native_unlock_hpte(hptep); | |
236 | ret = -1; | |
237 | } else { | |
238 | DBG_LOW(" -> hit\n"); | |
239 | /* Update the HPTE */ | |
240 | hptep->r = (hptep->r & ~(HPTE_R_PP | HPTE_R_N)) | | |
c5cf0e30 | 241 | (newpp & (HPTE_R_PP | HPTE_R_N | HPTE_R_C)); |
3c726f8d BH |
242 | native_unlock_hpte(hptep); |
243 | } | |
244 | ||
245 | /* Ensure it is out of the tlb too. */ | |
246 | tlbie(va, psize, local); | |
247 | ||
248 | return ret; | |
1da177e4 LT |
249 | } |
250 | ||
3c726f8d | 251 | static long native_hpte_find(unsigned long va, int psize) |
1da177e4 | 252 | { |
96e28449 | 253 | hpte_t *hptep; |
1da177e4 LT |
254 | unsigned long hash; |
255 | unsigned long i, j; | |
256 | long slot; | |
3c726f8d | 257 | unsigned long want_v, hpte_v; |
1da177e4 | 258 | |
3c726f8d BH |
259 | hash = hpt_hash(va, mmu_psize_defs[psize].shift); |
260 | want_v = hpte_encode_v(va, psize); | |
1da177e4 LT |
261 | |
262 | for (j = 0; j < 2; j++) { | |
263 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
264 | for (i = 0; i < HPTES_PER_GROUP; i++) { | |
265 | hptep = htab_address + slot; | |
96e28449 | 266 | hpte_v = hptep->v; |
1da177e4 | 267 | |
3c726f8d | 268 | if (HPTE_V_COMPARE(hpte_v, want_v) |
96e28449 DG |
269 | && (hpte_v & HPTE_V_VALID) |
270 | && ( !!(hpte_v & HPTE_V_SECONDARY) == j)) { | |
1da177e4 LT |
271 | /* HPTE matches */ |
272 | if (j) | |
273 | slot = -slot; | |
274 | return slot; | |
275 | } | |
276 | ++slot; | |
277 | } | |
278 | hash = ~hash; | |
279 | } | |
280 | ||
281 | return -1; | |
282 | } | |
283 | ||
1da177e4 LT |
284 | /* |
285 | * Update the page protection bits. Intended to be used to create | |
286 | * guard pages for kernel data structures on pages which are bolted | |
287 | * in the HPT. Assumes pages being operated on will not be stolen. | |
1da177e4 LT |
288 | * |
289 | * No need to lock here because we should be the only user. | |
290 | */ | |
3c726f8d BH |
291 | static void native_hpte_updateboltedpp(unsigned long newpp, unsigned long ea, |
292 | int psize) | |
1da177e4 | 293 | { |
3c726f8d | 294 | unsigned long vsid, va; |
1da177e4 | 295 | long slot; |
96e28449 | 296 | hpte_t *hptep; |
1da177e4 LT |
297 | |
298 | vsid = get_kernel_vsid(ea); | |
299 | va = (vsid << 28) | (ea & 0x0fffffff); | |
1da177e4 | 300 | |
3c726f8d | 301 | slot = native_hpte_find(va, psize); |
1da177e4 LT |
302 | if (slot == -1) |
303 | panic("could not find page to bolt\n"); | |
304 | hptep = htab_address + slot; | |
305 | ||
3c726f8d BH |
306 | /* Update the HPTE */ |
307 | hptep->r = (hptep->r & ~(HPTE_R_PP | HPTE_R_N)) | | |
308 | (newpp & (HPTE_R_PP | HPTE_R_N)); | |
1da177e4 | 309 | |
3c726f8d BH |
310 | /* Ensure it is out of the tlb too. */ |
311 | tlbie(va, psize, 0); | |
1da177e4 LT |
312 | } |
313 | ||
314 | static void native_hpte_invalidate(unsigned long slot, unsigned long va, | |
3c726f8d | 315 | int psize, int local) |
1da177e4 | 316 | { |
96e28449 DG |
317 | hpte_t *hptep = htab_address + slot; |
318 | unsigned long hpte_v; | |
3c726f8d | 319 | unsigned long want_v; |
1da177e4 | 320 | unsigned long flags; |
1da177e4 LT |
321 | |
322 | local_irq_save(flags); | |
1da177e4 | 323 | |
3c726f8d BH |
324 | DBG_LOW(" invalidate(va=%016lx, hash: %x)\n", va, slot); |
325 | ||
326 | want_v = hpte_encode_v(va, psize); | |
327 | native_lock_hpte(hptep); | |
96e28449 | 328 | hpte_v = hptep->v; |
1da177e4 LT |
329 | |
330 | /* Even if we miss, we need to invalidate the TLB */ | |
3c726f8d | 331 | if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID)) |
1da177e4 | 332 | native_unlock_hpte(hptep); |
3c726f8d | 333 | else |
1da177e4 | 334 | /* Invalidate the hpte. NOTE: this also unlocks it */ |
96e28449 | 335 | hptep->v = 0; |
1da177e4 | 336 | |
3c726f8d BH |
337 | /* Invalidate the TLB */ |
338 | tlbie(va, psize, local); | |
339 | ||
1da177e4 LT |
340 | local_irq_restore(flags); |
341 | } | |
342 | ||
3c726f8d BH |
343 | /* |
344 | * XXX This need fixing based on page size. It's only used by | |
345 | * native_hpte_clear() for now which needs fixing too so they | |
346 | * make a good pair... | |
347 | */ | |
348 | static unsigned long slot2va(unsigned long hpte_v, unsigned long slot) | |
349 | { | |
350 | unsigned long avpn = HPTE_V_AVPN_VAL(hpte_v); | |
351 | unsigned long va; | |
352 | ||
353 | va = avpn << 23; | |
354 | ||
355 | if (! (hpte_v & HPTE_V_LARGE)) { | |
356 | unsigned long vpi, pteg; | |
357 | ||
358 | pteg = slot / HPTES_PER_GROUP; | |
359 | if (hpte_v & HPTE_V_SECONDARY) | |
360 | pteg = ~pteg; | |
361 | ||
362 | vpi = ((va >> 28) ^ pteg) & htab_hash_mask; | |
363 | ||
364 | va |= vpi << PAGE_SHIFT; | |
365 | } | |
366 | ||
367 | return va; | |
368 | } | |
369 | ||
f4c82d51 S |
370 | /* |
371 | * clear all mappings on kexec. All cpus are in real mode (or they will | |
372 | * be when they isi), and we are the only one left. We rely on our kernel | |
373 | * mapping being 0xC0's and the hardware ignoring those two real bits. | |
374 | * | |
375 | * TODO: add batching support when enabled. remember, no dynamic memory here, | |
376 | * athough there is the control page available... | |
3c726f8d BH |
377 | * |
378 | * XXX FIXME: 4k only for now ! | |
f4c82d51 S |
379 | */ |
380 | static void native_hpte_clear(void) | |
381 | { | |
382 | unsigned long slot, slots, flags; | |
96e28449 DG |
383 | hpte_t *hptep = htab_address; |
384 | unsigned long hpte_v; | |
f4c82d51 S |
385 | unsigned long pteg_count; |
386 | ||
387 | pteg_count = htab_hash_mask + 1; | |
388 | ||
389 | local_irq_save(flags); | |
390 | ||
391 | /* we take the tlbie lock and hold it. Some hardware will | |
392 | * deadlock if we try to tlbie from two processors at once. | |
393 | */ | |
394 | spin_lock(&native_tlbie_lock); | |
395 | ||
396 | slots = pteg_count * HPTES_PER_GROUP; | |
397 | ||
398 | for (slot = 0; slot < slots; slot++, hptep++) { | |
399 | /* | |
400 | * we could lock the pte here, but we are the only cpu | |
401 | * running, right? and for crash dump, we probably | |
402 | * don't want to wait for a maybe bad cpu. | |
403 | */ | |
96e28449 | 404 | hpte_v = hptep->v; |
f4c82d51 | 405 | |
47f78a49 S |
406 | /* |
407 | * Call __tlbie() here rather than tlbie() since we | |
408 | * already hold the native_tlbie_lock. | |
409 | */ | |
96e28449 DG |
410 | if (hpte_v & HPTE_V_VALID) { |
411 | hptep->v = 0; | |
47f78a49 | 412 | __tlbie(slot2va(hpte_v, slot), MMU_PAGE_4K); |
f4c82d51 S |
413 | } |
414 | } | |
415 | ||
47f78a49 | 416 | asm volatile("eieio; tlbsync; ptesync":::"memory"); |
f4c82d51 S |
417 | spin_unlock(&native_tlbie_lock); |
418 | local_irq_restore(flags); | |
419 | } | |
420 | ||
3c726f8d BH |
421 | /* |
422 | * Batched hash table flush, we batch the tlbie's to avoid taking/releasing | |
423 | * the lock all the time | |
424 | */ | |
61b1a942 | 425 | static void native_flush_hash_range(unsigned long number, int local) |
1da177e4 | 426 | { |
3c726f8d | 427 | unsigned long va, hash, index, hidx, shift, slot; |
96e28449 DG |
428 | hpte_t *hptep; |
429 | unsigned long hpte_v; | |
3c726f8d BH |
430 | unsigned long want_v; |
431 | unsigned long flags; | |
432 | real_pte_t pte; | |
1da177e4 | 433 | struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch); |
3c726f8d BH |
434 | unsigned long psize = batch->psize; |
435 | int i; | |
1da177e4 LT |
436 | |
437 | local_irq_save(flags); | |
438 | ||
1da177e4 | 439 | for (i = 0; i < number; i++) { |
3c726f8d BH |
440 | va = batch->vaddr[i]; |
441 | pte = batch->pte[i]; | |
442 | ||
443 | pte_iterate_hashed_subpages(pte, psize, va, index, shift) { | |
444 | hash = hpt_hash(va, shift); | |
445 | hidx = __rpte_to_hidx(pte, index); | |
446 | if (hidx & _PTEIDX_SECONDARY) | |
447 | hash = ~hash; | |
448 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
449 | slot += hidx & _PTEIDX_GROUP_IX; | |
450 | hptep = htab_address + slot; | |
451 | want_v = hpte_encode_v(va, psize); | |
452 | native_lock_hpte(hptep); | |
453 | hpte_v = hptep->v; | |
454 | if (!HPTE_V_COMPARE(hpte_v, want_v) || | |
455 | !(hpte_v & HPTE_V_VALID)) | |
456 | native_unlock_hpte(hptep); | |
457 | else | |
458 | hptep->v = 0; | |
459 | } pte_iterate_hashed_end(); | |
1da177e4 LT |
460 | } |
461 | ||
3c726f8d BH |
462 | if (cpu_has_feature(CPU_FTR_TLBIEL) && |
463 | mmu_psize_defs[psize].tlbiel && local) { | |
1da177e4 | 464 | asm volatile("ptesync":::"memory"); |
3c726f8d BH |
465 | for (i = 0; i < number; i++) { |
466 | va = batch->vaddr[i]; | |
467 | pte = batch->pte[i]; | |
468 | ||
469 | pte_iterate_hashed_subpages(pte, psize, va, index, | |
470 | shift) { | |
471 | __tlbiel(va, psize); | |
472 | } pte_iterate_hashed_end(); | |
473 | } | |
1da177e4 LT |
474 | asm volatile("ptesync":::"memory"); |
475 | } else { | |
476 | int lock_tlbie = !cpu_has_feature(CPU_FTR_LOCKLESS_TLBIE); | |
477 | ||
478 | if (lock_tlbie) | |
479 | spin_lock(&native_tlbie_lock); | |
480 | ||
481 | asm volatile("ptesync":::"memory"); | |
3c726f8d BH |
482 | for (i = 0; i < number; i++) { |
483 | va = batch->vaddr[i]; | |
484 | pte = batch->pte[i]; | |
485 | ||
486 | pte_iterate_hashed_subpages(pte, psize, va, index, | |
487 | shift) { | |
488 | __tlbie(va, psize); | |
489 | } pte_iterate_hashed_end(); | |
490 | } | |
1da177e4 LT |
491 | asm volatile("eieio; tlbsync; ptesync":::"memory"); |
492 | ||
493 | if (lock_tlbie) | |
494 | spin_unlock(&native_tlbie_lock); | |
495 | } | |
496 | ||
497 | local_irq_restore(flags); | |
498 | } | |
499 | ||
500 | #ifdef CONFIG_PPC_PSERIES | |
501 | /* Disable TLB batching on nighthawk */ | |
502 | static inline int tlb_batching_enabled(void) | |
503 | { | |
504 | struct device_node *root = of_find_node_by_path("/"); | |
505 | int enabled = 1; | |
506 | ||
507 | if (root) { | |
e2eb6392 | 508 | const char *model = of_get_property(root, "model", NULL); |
1da177e4 LT |
509 | if (model && !strcmp(model, "IBM,9076-N81")) |
510 | enabled = 0; | |
511 | of_node_put(root); | |
512 | } | |
513 | ||
514 | return enabled; | |
515 | } | |
516 | #else | |
517 | static inline int tlb_batching_enabled(void) | |
518 | { | |
519 | return 1; | |
520 | } | |
521 | #endif | |
522 | ||
7d0daae4 | 523 | void __init hpte_init_native(void) |
1da177e4 LT |
524 | { |
525 | ppc_md.hpte_invalidate = native_hpte_invalidate; | |
526 | ppc_md.hpte_updatepp = native_hpte_updatepp; | |
527 | ppc_md.hpte_updateboltedpp = native_hpte_updateboltedpp; | |
528 | ppc_md.hpte_insert = native_hpte_insert; | |
f4c82d51 S |
529 | ppc_md.hpte_remove = native_hpte_remove; |
530 | ppc_md.hpte_clear_all = native_hpte_clear; | |
1da177e4 LT |
531 | if (tlb_batching_enabled()) |
532 | ppc_md.flush_hash_range = native_flush_hash_range; | |
1da177e4 | 533 | } |