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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * native hashtable management. | |
3 | * | |
4 | * SMP scalability work: | |
5 | * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version | |
10 | * 2 of the License, or (at your option) any later version. | |
11 | */ | |
3c726f8d BH |
12 | |
13 | #undef DEBUG_LOW | |
14 | ||
1da177e4 LT |
15 | #include <linux/spinlock.h> |
16 | #include <linux/bitops.h> | |
beacc6da | 17 | #include <linux/of.h> |
1da177e4 LT |
18 | #include <linux/threads.h> |
19 | #include <linux/smp.h> | |
20 | ||
1da177e4 LT |
21 | #include <asm/machdep.h> |
22 | #include <asm/mmu.h> | |
23 | #include <asm/mmu_context.h> | |
24 | #include <asm/pgtable.h> | |
25 | #include <asm/tlbflush.h> | |
26 | #include <asm/tlb.h> | |
27 | #include <asm/cputable.h> | |
3c726f8d | 28 | #include <asm/udbg.h> |
71bf08b6 | 29 | #include <asm/kexec.h> |
60dbf438 | 30 | #include <asm/ppc-opcode.h> |
3c726f8d BH |
31 | |
32 | #ifdef DEBUG_LOW | |
33 | #define DBG_LOW(fmt...) udbg_printf(fmt) | |
34 | #else | |
35 | #define DBG_LOW(fmt...) | |
36 | #endif | |
1da177e4 LT |
37 | |
38 | #define HPTE_LOCK_BIT 3 | |
39 | ||
9e368f29 | 40 | DEFINE_RAW_SPINLOCK(native_tlbie_lock); |
1da177e4 | 41 | |
b1022fbd | 42 | static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize) |
3c726f8d | 43 | { |
5524a27d | 44 | unsigned long va; |
3c726f8d | 45 | unsigned int penc; |
de640959 | 46 | unsigned long sllp; |
3c726f8d | 47 | |
5524a27d AK |
48 | /* |
49 | * We need 14 to 65 bits of va for a tlibe of 4K page | |
50 | * With vpn we ignore the lower VPN_SHIFT bits already. | |
51 | * And top two bits are already ignored because we can | |
52 | * only accomadate 76 bits in a 64 bit vpn with a VPN_SHIFT | |
53 | * of 12. | |
54 | */ | |
55 | va = vpn << VPN_SHIFT; | |
56 | /* | |
57 | * clear top 16 bits of 64bit va, non SLS segment | |
58 | * Older versions of the architecture (2.02 and earler) require the | |
59 | * masking of the top 16 bits. | |
60 | */ | |
3c726f8d BH |
61 | va &= ~(0xffffULL << 48); |
62 | ||
63 | switch (psize) { | |
64 | case MMU_PAGE_4K: | |
1f6aaacc AK |
65 | /* clear out bits after (52) [0....52.....63] */ |
66 | va &= ~((1ul << (64 - 52)) - 1); | |
1189be65 | 67 | va |= ssize << 8; |
de640959 AK |
68 | sllp = ((mmu_psize_defs[apsize].sllp & SLB_VSID_L) >> 6) | |
69 | ((mmu_psize_defs[apsize].sllp & SLB_VSID_LP) >> 4); | |
70 | va |= sllp << 5; | |
a32e252f | 71 | asm volatile(ASM_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0), %2) |
969391c5 | 72 | : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206) |
60dbf438 | 73 | : "memory"); |
3c726f8d BH |
74 | break; |
75 | default: | |
5524a27d | 76 | /* We need 14 to 14 + i bits of va */ |
b1022fbd | 77 | penc = mmu_psize_defs[psize].penc[apsize]; |
1f6aaacc | 78 | va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1); |
19242b24 | 79 | va |= penc << 12; |
1189be65 | 80 | va |= ssize << 8; |
1f6aaacc AK |
81 | /* Add AVAL part */ |
82 | if (psize != apsize) { | |
83 | /* | |
84 | * MPSS, 64K base page size and 16MB parge page size | |
85 | * We don't need all the bits, but rest of the bits | |
86 | * must be ignored by the processor. | |
87 | * vpn cover upto 65 bits of va. (0...65) and we need | |
88 | * 58..64 bits of va. | |
89 | */ | |
90 | va |= (vpn & 0xfe); | |
91 | } | |
60dbf438 | 92 | va |= 1; /* L */ |
a32e252f | 93 | asm volatile(ASM_FTR_IFCLR("tlbie %0,1", PPC_TLBIE(%1,%0), %2) |
969391c5 | 94 | : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206) |
60dbf438 | 95 | : "memory"); |
3c726f8d BH |
96 | break; |
97 | } | |
98 | } | |
99 | ||
b1022fbd | 100 | static inline void __tlbiel(unsigned long vpn, int psize, int apsize, int ssize) |
3c726f8d | 101 | { |
5524a27d | 102 | unsigned long va; |
3c726f8d | 103 | unsigned int penc; |
de640959 | 104 | unsigned long sllp; |
3c726f8d | 105 | |
5524a27d AK |
106 | /* VPN_SHIFT can be atmost 12 */ |
107 | va = vpn << VPN_SHIFT; | |
108 | /* | |
109 | * clear top 16 bits of 64 bit va, non SLS segment | |
110 | * Older versions of the architecture (2.02 and earler) require the | |
111 | * masking of the top 16 bits. | |
112 | */ | |
3c726f8d BH |
113 | va &= ~(0xffffULL << 48); |
114 | ||
115 | switch (psize) { | |
116 | case MMU_PAGE_4K: | |
1f6aaacc AK |
117 | /* clear out bits after(52) [0....52.....63] */ |
118 | va &= ~((1ul << (64 - 52)) - 1); | |
1189be65 | 119 | va |= ssize << 8; |
de640959 AK |
120 | sllp = ((mmu_psize_defs[apsize].sllp & SLB_VSID_L) >> 6) | |
121 | ((mmu_psize_defs[apsize].sllp & SLB_VSID_LP) >> 4); | |
122 | va |= sllp << 5; | |
3c726f8d BH |
123 | asm volatile(".long 0x7c000224 | (%0 << 11) | (0 << 21)" |
124 | : : "r"(va) : "memory"); | |
125 | break; | |
126 | default: | |
5524a27d | 127 | /* We need 14 to 14 + i bits of va */ |
b1022fbd | 128 | penc = mmu_psize_defs[psize].penc[apsize]; |
1f6aaacc | 129 | va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1); |
19242b24 | 130 | va |= penc << 12; |
1189be65 | 131 | va |= ssize << 8; |
1f6aaacc AK |
132 | /* Add AVAL part */ |
133 | if (psize != apsize) { | |
134 | /* | |
135 | * MPSS, 64K base page size and 16MB parge page size | |
136 | * We don't need all the bits, but rest of the bits | |
137 | * must be ignored by the processor. | |
138 | * vpn cover upto 65 bits of va. (0...65) and we need | |
139 | * 58..64 bits of va. | |
140 | */ | |
141 | va |= (vpn & 0xfe); | |
142 | } | |
60dbf438 | 143 | va |= 1; /* L */ |
3c726f8d BH |
144 | asm volatile(".long 0x7c000224 | (%0 << 11) | (1 << 21)" |
145 | : : "r"(va) : "memory"); | |
146 | break; | |
147 | } | |
148 | ||
149 | } | |
150 | ||
b1022fbd AK |
151 | static inline void tlbie(unsigned long vpn, int psize, int apsize, |
152 | int ssize, int local) | |
3c726f8d | 153 | { |
44ae3ab3 ME |
154 | unsigned int use_local = local && mmu_has_feature(MMU_FTR_TLBIEL); |
155 | int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE); | |
3c726f8d BH |
156 | |
157 | if (use_local) | |
158 | use_local = mmu_psize_defs[psize].tlbiel; | |
159 | if (lock_tlbie && !use_local) | |
6b9c9b8a | 160 | raw_spin_lock(&native_tlbie_lock); |
3c726f8d BH |
161 | asm volatile("ptesync": : :"memory"); |
162 | if (use_local) { | |
b1022fbd | 163 | __tlbiel(vpn, psize, apsize, ssize); |
3c726f8d BH |
164 | asm volatile("ptesync": : :"memory"); |
165 | } else { | |
b1022fbd | 166 | __tlbie(vpn, psize, apsize, ssize); |
3c726f8d BH |
167 | asm volatile("eieio; tlbsync; ptesync": : :"memory"); |
168 | } | |
169 | if (lock_tlbie && !use_local) | |
6b9c9b8a | 170 | raw_spin_unlock(&native_tlbie_lock); |
3c726f8d BH |
171 | } |
172 | ||
8e561e7e | 173 | static inline void native_lock_hpte(struct hash_pte *hptep) |
1da177e4 | 174 | { |
96e28449 | 175 | unsigned long *word = &hptep->v; |
1da177e4 LT |
176 | |
177 | while (1) { | |
66d99b88 | 178 | if (!test_and_set_bit_lock(HPTE_LOCK_BIT, word)) |
1da177e4 LT |
179 | break; |
180 | while(test_bit(HPTE_LOCK_BIT, word)) | |
181 | cpu_relax(); | |
182 | } | |
183 | } | |
184 | ||
8e561e7e | 185 | static inline void native_unlock_hpte(struct hash_pte *hptep) |
1da177e4 | 186 | { |
96e28449 | 187 | unsigned long *word = &hptep->v; |
1da177e4 | 188 | |
66d99b88 | 189 | clear_bit_unlock(HPTE_LOCK_BIT, word); |
1da177e4 LT |
190 | } |
191 | ||
5524a27d | 192 | static long native_hpte_insert(unsigned long hpte_group, unsigned long vpn, |
3c726f8d | 193 | unsigned long pa, unsigned long rflags, |
b1022fbd | 194 | unsigned long vflags, int psize, int apsize, int ssize) |
1da177e4 | 195 | { |
8e561e7e | 196 | struct hash_pte *hptep = htab_address + hpte_group; |
96e28449 | 197 | unsigned long hpte_v, hpte_r; |
1da177e4 LT |
198 | int i; |
199 | ||
3c726f8d | 200 | if (!(vflags & HPTE_V_BOLTED)) { |
5524a27d | 201 | DBG_LOW(" insert(group=%lx, vpn=%016lx, pa=%016lx," |
3c726f8d | 202 | " rflags=%lx, vflags=%lx, psize=%d)\n", |
5524a27d | 203 | hpte_group, vpn, pa, rflags, vflags, psize); |
3c726f8d BH |
204 | } |
205 | ||
1da177e4 | 206 | for (i = 0; i < HPTES_PER_GROUP; i++) { |
96e28449 | 207 | if (! (hptep->v & HPTE_V_VALID)) { |
1da177e4 LT |
208 | /* retry with lock held */ |
209 | native_lock_hpte(hptep); | |
96e28449 | 210 | if (! (hptep->v & HPTE_V_VALID)) |
1da177e4 LT |
211 | break; |
212 | native_unlock_hpte(hptep); | |
213 | } | |
214 | ||
215 | hptep++; | |
216 | } | |
217 | ||
218 | if (i == HPTES_PER_GROUP) | |
219 | return -1; | |
220 | ||
b1022fbd AK |
221 | hpte_v = hpte_encode_v(vpn, psize, apsize, ssize) | vflags | HPTE_V_VALID; |
222 | hpte_r = hpte_encode_r(pa, psize, apsize) | rflags; | |
3c726f8d BH |
223 | |
224 | if (!(vflags & HPTE_V_BOLTED)) { | |
225 | DBG_LOW(" i=%x hpte_v=%016lx, hpte_r=%016lx\n", | |
226 | i, hpte_v, hpte_r); | |
227 | } | |
1da177e4 | 228 | |
96e28449 | 229 | hptep->r = hpte_r; |
1da177e4 | 230 | /* Guarantee the second dword is visible before the valid bit */ |
74a0ba61 | 231 | eieio(); |
1da177e4 LT |
232 | /* |
233 | * Now set the first dword including the valid bit | |
234 | * NOTE: this also unlocks the hpte | |
235 | */ | |
96e28449 | 236 | hptep->v = hpte_v; |
1da177e4 LT |
237 | |
238 | __asm__ __volatile__ ("ptesync" : : : "memory"); | |
239 | ||
96e28449 | 240 | return i | (!!(vflags & HPTE_V_SECONDARY) << 3); |
1da177e4 LT |
241 | } |
242 | ||
243 | static long native_hpte_remove(unsigned long hpte_group) | |
244 | { | |
8e561e7e | 245 | struct hash_pte *hptep; |
1da177e4 LT |
246 | int i; |
247 | int slot_offset; | |
96e28449 | 248 | unsigned long hpte_v; |
1da177e4 | 249 | |
3c726f8d BH |
250 | DBG_LOW(" remove(group=%lx)\n", hpte_group); |
251 | ||
1da177e4 LT |
252 | /* pick a random entry to start at */ |
253 | slot_offset = mftb() & 0x7; | |
254 | ||
255 | for (i = 0; i < HPTES_PER_GROUP; i++) { | |
256 | hptep = htab_address + hpte_group + slot_offset; | |
96e28449 | 257 | hpte_v = hptep->v; |
1da177e4 | 258 | |
96e28449 | 259 | if ((hpte_v & HPTE_V_VALID) && !(hpte_v & HPTE_V_BOLTED)) { |
1da177e4 LT |
260 | /* retry with lock held */ |
261 | native_lock_hpte(hptep); | |
96e28449 DG |
262 | hpte_v = hptep->v; |
263 | if ((hpte_v & HPTE_V_VALID) | |
264 | && !(hpte_v & HPTE_V_BOLTED)) | |
1da177e4 LT |
265 | break; |
266 | native_unlock_hpte(hptep); | |
267 | } | |
268 | ||
269 | slot_offset++; | |
270 | slot_offset &= 0x7; | |
271 | } | |
272 | ||
273 | if (i == HPTES_PER_GROUP) | |
274 | return -1; | |
275 | ||
276 | /* Invalidate the hpte. NOTE: this also unlocks it */ | |
96e28449 | 277 | hptep->v = 0; |
1da177e4 LT |
278 | |
279 | return i; | |
280 | } | |
281 | ||
3c726f8d | 282 | static long native_hpte_updatepp(unsigned long slot, unsigned long newpp, |
db3d8534 AK |
283 | unsigned long vpn, int bpsize, |
284 | int apsize, int ssize, int local) | |
1da177e4 | 285 | { |
8e561e7e | 286 | struct hash_pte *hptep = htab_address + slot; |
3c726f8d BH |
287 | unsigned long hpte_v, want_v; |
288 | int ret = 0; | |
289 | ||
db3d8534 | 290 | want_v = hpte_encode_avpn(vpn, bpsize, ssize); |
3c726f8d | 291 | |
5524a27d AK |
292 | DBG_LOW(" update(vpn=%016lx, avpnv=%016lx, group=%lx, newpp=%lx)", |
293 | vpn, want_v & HPTE_V_AVPN, slot, newpp); | |
3c726f8d BH |
294 | |
295 | native_lock_hpte(hptep); | |
296 | ||
297 | hpte_v = hptep->v; | |
0608d692 AK |
298 | /* |
299 | * We need to invalidate the TLB always because hpte_remove doesn't do | |
300 | * a tlb invalidate. If a hash bucket gets full, we "evict" a more/less | |
301 | * random entry from it. When we do that we don't invalidate the TLB | |
302 | * (hpte_remove) because we assume the old translation is still | |
303 | * technically "valid". | |
304 | */ | |
db3d8534 | 305 | if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID)) { |
3c726f8d | 306 | DBG_LOW(" -> miss\n"); |
3c726f8d BH |
307 | ret = -1; |
308 | } else { | |
309 | DBG_LOW(" -> hit\n"); | |
310 | /* Update the HPTE */ | |
311 | hptep->r = (hptep->r & ~(HPTE_R_PP | HPTE_R_N)) | | |
c5cf0e30 | 312 | (newpp & (HPTE_R_PP | HPTE_R_N | HPTE_R_C)); |
3c726f8d | 313 | } |
3f1df7a2 | 314 | native_unlock_hpte(hptep); |
3c726f8d BH |
315 | |
316 | /* Ensure it is out of the tlb too. */ | |
db3d8534 | 317 | tlbie(vpn, bpsize, apsize, ssize, local); |
3c726f8d BH |
318 | |
319 | return ret; | |
1da177e4 LT |
320 | } |
321 | ||
5524a27d | 322 | static long native_hpte_find(unsigned long vpn, int psize, int ssize) |
1da177e4 | 323 | { |
8e561e7e | 324 | struct hash_pte *hptep; |
1da177e4 | 325 | unsigned long hash; |
1189be65 | 326 | unsigned long i; |
1da177e4 | 327 | long slot; |
3c726f8d | 328 | unsigned long want_v, hpte_v; |
1da177e4 | 329 | |
5524a27d | 330 | hash = hpt_hash(vpn, mmu_psize_defs[psize].shift, ssize); |
74f227b2 | 331 | want_v = hpte_encode_avpn(vpn, psize, ssize); |
1da177e4 | 332 | |
1189be65 PM |
333 | /* Bolted mappings are only ever in the primary group */ |
334 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
335 | for (i = 0; i < HPTES_PER_GROUP; i++) { | |
336 | hptep = htab_address + slot; | |
337 | hpte_v = hptep->v; | |
1da177e4 | 338 | |
1189be65 PM |
339 | if (HPTE_V_COMPARE(hpte_v, want_v) && (hpte_v & HPTE_V_VALID)) |
340 | /* HPTE matches */ | |
341 | return slot; | |
342 | ++slot; | |
1da177e4 LT |
343 | } |
344 | ||
345 | return -1; | |
346 | } | |
347 | ||
1da177e4 LT |
348 | /* |
349 | * Update the page protection bits. Intended to be used to create | |
350 | * guard pages for kernel data structures on pages which are bolted | |
351 | * in the HPT. Assumes pages being operated on will not be stolen. | |
1da177e4 LT |
352 | * |
353 | * No need to lock here because we should be the only user. | |
354 | */ | |
3c726f8d | 355 | static void native_hpte_updateboltedpp(unsigned long newpp, unsigned long ea, |
1189be65 | 356 | int psize, int ssize) |
1da177e4 | 357 | { |
5524a27d AK |
358 | unsigned long vpn; |
359 | unsigned long vsid; | |
1da177e4 | 360 | long slot; |
8e561e7e | 361 | struct hash_pte *hptep; |
1da177e4 | 362 | |
1189be65 | 363 | vsid = get_kernel_vsid(ea, ssize); |
5524a27d | 364 | vpn = hpt_vpn(ea, vsid, ssize); |
1da177e4 | 365 | |
5524a27d | 366 | slot = native_hpte_find(vpn, psize, ssize); |
1da177e4 LT |
367 | if (slot == -1) |
368 | panic("could not find page to bolt\n"); | |
369 | hptep = htab_address + slot; | |
370 | ||
3c726f8d BH |
371 | /* Update the HPTE */ |
372 | hptep->r = (hptep->r & ~(HPTE_R_PP | HPTE_R_N)) | | |
373 | (newpp & (HPTE_R_PP | HPTE_R_N)); | |
db3d8534 AK |
374 | /* |
375 | * Ensure it is out of the tlb too. Bolted entries base and | |
376 | * actual page size will be same. | |
377 | */ | |
378 | tlbie(vpn, psize, psize, ssize, 0); | |
1da177e4 LT |
379 | } |
380 | ||
5524a27d | 381 | static void native_hpte_invalidate(unsigned long slot, unsigned long vpn, |
db3d8534 | 382 | int bpsize, int apsize, int ssize, int local) |
1da177e4 | 383 | { |
8e561e7e | 384 | struct hash_pte *hptep = htab_address + slot; |
96e28449 | 385 | unsigned long hpte_v; |
3c726f8d | 386 | unsigned long want_v; |
1da177e4 | 387 | unsigned long flags; |
1da177e4 LT |
388 | |
389 | local_irq_save(flags); | |
1da177e4 | 390 | |
5524a27d | 391 | DBG_LOW(" invalidate(vpn=%016lx, hash: %lx)\n", vpn, slot); |
3c726f8d | 392 | |
db3d8534 | 393 | want_v = hpte_encode_avpn(vpn, bpsize, ssize); |
3c726f8d | 394 | native_lock_hpte(hptep); |
96e28449 | 395 | hpte_v = hptep->v; |
1da177e4 | 396 | |
0608d692 AK |
397 | /* |
398 | * We need to invalidate the TLB always because hpte_remove doesn't do | |
399 | * a tlb invalidate. If a hash bucket gets full, we "evict" a more/less | |
400 | * random entry from it. When we do that we don't invalidate the TLB | |
401 | * (hpte_remove) because we assume the old translation is still | |
402 | * technically "valid". | |
403 | */ | |
db3d8534 | 404 | if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID)) |
1da177e4 | 405 | native_unlock_hpte(hptep); |
3c726f8d | 406 | else |
1da177e4 | 407 | /* Invalidate the hpte. NOTE: this also unlocks it */ |
96e28449 | 408 | hptep->v = 0; |
1da177e4 | 409 | |
3c726f8d | 410 | /* Invalidate the TLB */ |
db3d8534 AK |
411 | tlbie(vpn, bpsize, apsize, ssize, local); |
412 | ||
1da177e4 LT |
413 | local_irq_restore(flags); |
414 | } | |
415 | ||
1a527286 AK |
416 | static void native_hugepage_invalidate(struct mm_struct *mm, |
417 | unsigned char *hpte_slot_array, | |
418 | unsigned long addr, int psize) | |
419 | { | |
420 | int ssize = 0, i; | |
421 | int lock_tlbie; | |
422 | struct hash_pte *hptep; | |
423 | int actual_psize = MMU_PAGE_16M; | |
424 | unsigned int max_hpte_count, valid; | |
425 | unsigned long flags, s_addr = addr; | |
426 | unsigned long hpte_v, want_v, shift; | |
427 | unsigned long hidx, vpn = 0, vsid, hash, slot; | |
428 | ||
429 | shift = mmu_psize_defs[psize].shift; | |
430 | max_hpte_count = 1U << (PMD_SHIFT - shift); | |
431 | ||
432 | local_irq_save(flags); | |
433 | for (i = 0; i < max_hpte_count; i++) { | |
434 | valid = hpte_valid(hpte_slot_array, i); | |
435 | if (!valid) | |
436 | continue; | |
437 | hidx = hpte_hash_index(hpte_slot_array, i); | |
438 | ||
439 | /* get the vpn */ | |
440 | addr = s_addr + (i * (1ul << shift)); | |
441 | if (!is_kernel_addr(addr)) { | |
442 | ssize = user_segment_size(addr); | |
443 | vsid = get_vsid(mm->context.id, addr, ssize); | |
444 | WARN_ON(vsid == 0); | |
445 | } else { | |
446 | vsid = get_kernel_vsid(addr, mmu_kernel_ssize); | |
447 | ssize = mmu_kernel_ssize; | |
448 | } | |
449 | ||
450 | vpn = hpt_vpn(addr, vsid, ssize); | |
451 | hash = hpt_hash(vpn, shift, ssize); | |
452 | if (hidx & _PTEIDX_SECONDARY) | |
453 | hash = ~hash; | |
454 | ||
455 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
456 | slot += hidx & _PTEIDX_GROUP_IX; | |
457 | ||
458 | hptep = htab_address + slot; | |
459 | want_v = hpte_encode_avpn(vpn, psize, ssize); | |
460 | native_lock_hpte(hptep); | |
461 | hpte_v = hptep->v; | |
462 | ||
463 | /* Even if we miss, we need to invalidate the TLB */ | |
464 | if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID)) | |
465 | native_unlock_hpte(hptep); | |
466 | else | |
467 | /* Invalidate the hpte. NOTE: this also unlocks it */ | |
468 | hptep->v = 0; | |
469 | } | |
470 | /* | |
471 | * Since this is a hugepage, we just need a single tlbie. | |
472 | * use the last vpn. | |
473 | */ | |
474 | lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE); | |
475 | if (lock_tlbie) | |
476 | raw_spin_lock(&native_tlbie_lock); | |
477 | ||
478 | asm volatile("ptesync":::"memory"); | |
479 | __tlbie(vpn, psize, actual_psize, ssize); | |
480 | asm volatile("eieio; tlbsync; ptesync":::"memory"); | |
481 | ||
482 | if (lock_tlbie) | |
483 | raw_spin_unlock(&native_tlbie_lock); | |
484 | ||
485 | local_irq_restore(flags); | |
486 | } | |
487 | ||
db3d8534 AK |
488 | static inline int __hpte_actual_psize(unsigned int lp, int psize) |
489 | { | |
490 | int i, shift; | |
491 | unsigned int mask; | |
492 | ||
493 | /* start from 1 ignoring MMU_PAGE_4K */ | |
494 | for (i = 1; i < MMU_PAGE_COUNT; i++) { | |
495 | ||
496 | /* invalid penc */ | |
497 | if (mmu_psize_defs[psize].penc[i] == -1) | |
498 | continue; | |
499 | /* | |
500 | * encoding bits per actual page size | |
501 | * PTE LP actual page size | |
502 | * rrrr rrrz >=8KB | |
503 | * rrrr rrzz >=16KB | |
504 | * rrrr rzzz >=32KB | |
505 | * rrrr zzzz >=64KB | |
506 | * ....... | |
507 | */ | |
508 | shift = mmu_psize_defs[i].shift - LP_SHIFT; | |
509 | if (shift > LP_BITS) | |
510 | shift = LP_BITS; | |
511 | mask = (1 << shift) - 1; | |
512 | if ((lp & mask) == mmu_psize_defs[psize].penc[i]) | |
513 | return i; | |
514 | } | |
515 | return -1; | |
516 | } | |
517 | ||
8e561e7e | 518 | static void hpte_decode(struct hash_pte *hpte, unsigned long slot, |
b1022fbd | 519 | int *psize, int *apsize, int *ssize, unsigned long *vpn) |
71bf08b6 | 520 | { |
dcda287a | 521 | unsigned long avpn, pteg, vpi; |
71bf08b6 | 522 | unsigned long hpte_v = hpte->v; |
dcda287a | 523 | unsigned long vsid, seg_off; |
7e74c392 AK |
524 | int size, a_size, shift; |
525 | /* Look at the 8 bit LP value */ | |
526 | unsigned int lp = (hpte->r >> LP_SHIFT) & ((1 << LP_BITS) - 1); | |
71bf08b6 | 527 | |
b1022fbd AK |
528 | if (!(hpte_v & HPTE_V_LARGE)) { |
529 | size = MMU_PAGE_4K; | |
530 | a_size = MMU_PAGE_4K; | |
531 | } else { | |
71bf08b6 | 532 | for (size = 0; size < MMU_PAGE_COUNT; size++) { |
3c726f8d | 533 | |
71bf08b6 LB |
534 | /* valid entries have a shift value */ |
535 | if (!mmu_psize_defs[size].shift) | |
536 | continue; | |
b1022fbd | 537 | |
7e74c392 AK |
538 | a_size = __hpte_actual_psize(lp, size); |
539 | if (a_size != -1) | |
540 | break; | |
71bf08b6 LB |
541 | } |
542 | } | |
2454c7e9 | 543 | /* This works for all page sizes, and for 256M and 1T segments */ |
dcda287a | 544 | *ssize = hpte_v >> HPTE_V_SSIZE_SHIFT; |
71bf08b6 | 545 | shift = mmu_psize_defs[size].shift; |
71bf08b6 | 546 | |
dcda287a AK |
547 | avpn = (HPTE_V_AVPN_VAL(hpte_v) & ~mmu_psize_defs[size].avpnm); |
548 | pteg = slot / HPTES_PER_GROUP; | |
549 | if (hpte_v & HPTE_V_SECONDARY) | |
550 | pteg = ~pteg; | |
551 | ||
552 | switch (*ssize) { | |
553 | case MMU_SEGSIZE_256M: | |
554 | /* We only have 28 - 23 bits of seg_off in avpn */ | |
555 | seg_off = (avpn & 0x1f) << 23; | |
556 | vsid = avpn >> 5; | |
557 | /* We can find more bits from the pteg value */ | |
558 | if (shift < 23) { | |
559 | vpi = (vsid ^ pteg) & htab_hash_mask; | |
560 | seg_off |= vpi << shift; | |
561 | } | |
5524a27d | 562 | *vpn = vsid << (SID_SHIFT - VPN_SHIFT) | seg_off >> VPN_SHIFT; |
83383b73 | 563 | break; |
dcda287a AK |
564 | case MMU_SEGSIZE_1T: |
565 | /* We only have 40 - 23 bits of seg_off in avpn */ | |
566 | seg_off = (avpn & 0x1ffff) << 23; | |
567 | vsid = avpn >> 17; | |
568 | if (shift < 23) { | |
2454c7e9 | 569 | vpi = (vsid ^ (vsid << 25) ^ pteg) & htab_hash_mask; |
dcda287a | 570 | seg_off |= vpi << shift; |
71bf08b6 | 571 | } |
5524a27d | 572 | *vpn = vsid << (SID_SHIFT_1T - VPN_SHIFT) | seg_off >> VPN_SHIFT; |
83383b73 | 573 | break; |
dcda287a | 574 | default: |
5524a27d | 575 | *vpn = size = 0; |
3c726f8d | 576 | } |
b1022fbd AK |
577 | *psize = size; |
578 | *apsize = a_size; | |
3c726f8d BH |
579 | } |
580 | ||
f4c82d51 S |
581 | /* |
582 | * clear all mappings on kexec. All cpus are in real mode (or they will | |
583 | * be when they isi), and we are the only one left. We rely on our kernel | |
584 | * mapping being 0xC0's and the hardware ignoring those two real bits. | |
585 | * | |
586 | * TODO: add batching support when enabled. remember, no dynamic memory here, | |
587 | * athough there is the control page available... | |
588 | */ | |
589 | static void native_hpte_clear(void) | |
590 | { | |
5524a27d | 591 | unsigned long vpn = 0; |
f4c82d51 | 592 | unsigned long slot, slots, flags; |
8e561e7e | 593 | struct hash_pte *hptep = htab_address; |
5524a27d | 594 | unsigned long hpte_v; |
f4c82d51 | 595 | unsigned long pteg_count; |
b1022fbd | 596 | int psize, apsize, ssize; |
f4c82d51 S |
597 | |
598 | pteg_count = htab_hash_mask + 1; | |
599 | ||
600 | local_irq_save(flags); | |
601 | ||
602 | /* we take the tlbie lock and hold it. Some hardware will | |
603 | * deadlock if we try to tlbie from two processors at once. | |
604 | */ | |
6b9c9b8a | 605 | raw_spin_lock(&native_tlbie_lock); |
f4c82d51 S |
606 | |
607 | slots = pteg_count * HPTES_PER_GROUP; | |
608 | ||
609 | for (slot = 0; slot < slots; slot++, hptep++) { | |
610 | /* | |
611 | * we could lock the pte here, but we are the only cpu | |
612 | * running, right? and for crash dump, we probably | |
613 | * don't want to wait for a maybe bad cpu. | |
614 | */ | |
96e28449 | 615 | hpte_v = hptep->v; |
f4c82d51 | 616 | |
47f78a49 S |
617 | /* |
618 | * Call __tlbie() here rather than tlbie() since we | |
619 | * already hold the native_tlbie_lock. | |
620 | */ | |
96e28449 | 621 | if (hpte_v & HPTE_V_VALID) { |
b1022fbd | 622 | hpte_decode(hptep, slot, &psize, &apsize, &ssize, &vpn); |
96e28449 | 623 | hptep->v = 0; |
b1022fbd | 624 | __tlbie(vpn, psize, apsize, ssize); |
f4c82d51 S |
625 | } |
626 | } | |
627 | ||
47f78a49 | 628 | asm volatile("eieio; tlbsync; ptesync":::"memory"); |
6b9c9b8a | 629 | raw_spin_unlock(&native_tlbie_lock); |
f4c82d51 S |
630 | local_irq_restore(flags); |
631 | } | |
632 | ||
3c726f8d BH |
633 | /* |
634 | * Batched hash table flush, we batch the tlbie's to avoid taking/releasing | |
635 | * the lock all the time | |
636 | */ | |
61b1a942 | 637 | static void native_flush_hash_range(unsigned long number, int local) |
1da177e4 | 638 | { |
5524a27d AK |
639 | unsigned long vpn; |
640 | unsigned long hash, index, hidx, shift, slot; | |
8e561e7e | 641 | struct hash_pte *hptep; |
96e28449 | 642 | unsigned long hpte_v; |
3c726f8d BH |
643 | unsigned long want_v; |
644 | unsigned long flags; | |
645 | real_pte_t pte; | |
1da177e4 | 646 | struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch); |
3c726f8d | 647 | unsigned long psize = batch->psize; |
1189be65 | 648 | int ssize = batch->ssize; |
3c726f8d | 649 | int i; |
1da177e4 LT |
650 | |
651 | local_irq_save(flags); | |
652 | ||
1da177e4 | 653 | for (i = 0; i < number; i++) { |
5524a27d | 654 | vpn = batch->vpn[i]; |
3c726f8d BH |
655 | pte = batch->pte[i]; |
656 | ||
5524a27d AK |
657 | pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) { |
658 | hash = hpt_hash(vpn, shift, ssize); | |
3c726f8d BH |
659 | hidx = __rpte_to_hidx(pte, index); |
660 | if (hidx & _PTEIDX_SECONDARY) | |
661 | hash = ~hash; | |
662 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
663 | slot += hidx & _PTEIDX_GROUP_IX; | |
664 | hptep = htab_address + slot; | |
74f227b2 | 665 | want_v = hpte_encode_avpn(vpn, psize, ssize); |
3c726f8d BH |
666 | native_lock_hpte(hptep); |
667 | hpte_v = hptep->v; | |
668 | if (!HPTE_V_COMPARE(hpte_v, want_v) || | |
669 | !(hpte_v & HPTE_V_VALID)) | |
670 | native_unlock_hpte(hptep); | |
671 | else | |
672 | hptep->v = 0; | |
673 | } pte_iterate_hashed_end(); | |
1da177e4 LT |
674 | } |
675 | ||
44ae3ab3 | 676 | if (mmu_has_feature(MMU_FTR_TLBIEL) && |
3c726f8d | 677 | mmu_psize_defs[psize].tlbiel && local) { |
1da177e4 | 678 | asm volatile("ptesync":::"memory"); |
3c726f8d | 679 | for (i = 0; i < number; i++) { |
5524a27d | 680 | vpn = batch->vpn[i]; |
3c726f8d BH |
681 | pte = batch->pte[i]; |
682 | ||
5524a27d AK |
683 | pte_iterate_hashed_subpages(pte, psize, |
684 | vpn, index, shift) { | |
b1022fbd | 685 | __tlbiel(vpn, psize, psize, ssize); |
3c726f8d BH |
686 | } pte_iterate_hashed_end(); |
687 | } | |
1da177e4 LT |
688 | asm volatile("ptesync":::"memory"); |
689 | } else { | |
44ae3ab3 | 690 | int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE); |
1da177e4 LT |
691 | |
692 | if (lock_tlbie) | |
6b9c9b8a | 693 | raw_spin_lock(&native_tlbie_lock); |
1da177e4 LT |
694 | |
695 | asm volatile("ptesync":::"memory"); | |
3c726f8d | 696 | for (i = 0; i < number; i++) { |
5524a27d | 697 | vpn = batch->vpn[i]; |
3c726f8d BH |
698 | pte = batch->pte[i]; |
699 | ||
5524a27d AK |
700 | pte_iterate_hashed_subpages(pte, psize, |
701 | vpn, index, shift) { | |
b1022fbd | 702 | __tlbie(vpn, psize, psize, ssize); |
3c726f8d BH |
703 | } pte_iterate_hashed_end(); |
704 | } | |
1da177e4 LT |
705 | asm volatile("eieio; tlbsync; ptesync":::"memory"); |
706 | ||
707 | if (lock_tlbie) | |
6b9c9b8a | 708 | raw_spin_unlock(&native_tlbie_lock); |
1da177e4 LT |
709 | } |
710 | ||
711 | local_irq_restore(flags); | |
712 | } | |
713 | ||
7d0daae4 | 714 | void __init hpte_init_native(void) |
1da177e4 LT |
715 | { |
716 | ppc_md.hpte_invalidate = native_hpte_invalidate; | |
717 | ppc_md.hpte_updatepp = native_hpte_updatepp; | |
718 | ppc_md.hpte_updateboltedpp = native_hpte_updateboltedpp; | |
719 | ppc_md.hpte_insert = native_hpte_insert; | |
f4c82d51 S |
720 | ppc_md.hpte_remove = native_hpte_remove; |
721 | ppc_md.hpte_clear_all = native_hpte_clear; | |
8e166991 | 722 | ppc_md.flush_hash_range = native_flush_hash_range; |
1a527286 | 723 | ppc_md.hugepage_invalidate = native_hugepage_invalidate; |
1da177e4 | 724 | } |