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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * native hashtable management. | |
3 | * | |
4 | * SMP scalability work: | |
5 | * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version | |
10 | * 2 of the License, or (at your option) any later version. | |
11 | */ | |
3c726f8d BH |
12 | |
13 | #undef DEBUG_LOW | |
14 | ||
1da177e4 LT |
15 | #include <linux/spinlock.h> |
16 | #include <linux/bitops.h> | |
beacc6da | 17 | #include <linux/of.h> |
1da177e4 LT |
18 | #include <linux/threads.h> |
19 | #include <linux/smp.h> | |
20 | ||
1da177e4 LT |
21 | #include <asm/machdep.h> |
22 | #include <asm/mmu.h> | |
23 | #include <asm/mmu_context.h> | |
24 | #include <asm/pgtable.h> | |
25 | #include <asm/tlbflush.h> | |
26 | #include <asm/tlb.h> | |
27 | #include <asm/cputable.h> | |
3c726f8d | 28 | #include <asm/udbg.h> |
71bf08b6 | 29 | #include <asm/kexec.h> |
60dbf438 | 30 | #include <asm/ppc-opcode.h> |
3c726f8d | 31 | |
4c6d9acc IM |
32 | #include <misc/cxl.h> |
33 | ||
3c726f8d BH |
34 | #ifdef DEBUG_LOW |
35 | #define DBG_LOW(fmt...) udbg_printf(fmt) | |
36 | #else | |
37 | #define DBG_LOW(fmt...) | |
38 | #endif | |
1da177e4 | 39 | |
12f04f2b | 40 | #ifdef __BIG_ENDIAN__ |
1da177e4 | 41 | #define HPTE_LOCK_BIT 3 |
12f04f2b AB |
42 | #else |
43 | #define HPTE_LOCK_BIT (56+3) | |
44 | #endif | |
1da177e4 | 45 | |
9e368f29 | 46 | DEFINE_RAW_SPINLOCK(native_tlbie_lock); |
1da177e4 | 47 | |
b1022fbd | 48 | static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize) |
3c726f8d | 49 | { |
5524a27d | 50 | unsigned long va; |
3c726f8d | 51 | unsigned int penc; |
de640959 | 52 | unsigned long sllp; |
3c726f8d | 53 | |
5524a27d AK |
54 | /* |
55 | * We need 14 to 65 bits of va for a tlibe of 4K page | |
56 | * With vpn we ignore the lower VPN_SHIFT bits already. | |
57 | * And top two bits are already ignored because we can | |
58 | * only accomadate 76 bits in a 64 bit vpn with a VPN_SHIFT | |
59 | * of 12. | |
60 | */ | |
61 | va = vpn << VPN_SHIFT; | |
62 | /* | |
63 | * clear top 16 bits of 64bit va, non SLS segment | |
64 | * Older versions of the architecture (2.02 and earler) require the | |
65 | * masking of the top 16 bits. | |
66 | */ | |
3c726f8d BH |
67 | va &= ~(0xffffULL << 48); |
68 | ||
69 | switch (psize) { | |
70 | case MMU_PAGE_4K: | |
1f6aaacc AK |
71 | /* clear out bits after (52) [0....52.....63] */ |
72 | va &= ~((1ul << (64 - 52)) - 1); | |
1189be65 | 73 | va |= ssize << 8; |
de640959 AK |
74 | sllp = ((mmu_psize_defs[apsize].sllp & SLB_VSID_L) >> 6) | |
75 | ((mmu_psize_defs[apsize].sllp & SLB_VSID_LP) >> 4); | |
76 | va |= sllp << 5; | |
a32e252f | 77 | asm volatile(ASM_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0), %2) |
969391c5 | 78 | : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206) |
60dbf438 | 79 | : "memory"); |
3c726f8d BH |
80 | break; |
81 | default: | |
5524a27d | 82 | /* We need 14 to 14 + i bits of va */ |
b1022fbd | 83 | penc = mmu_psize_defs[psize].penc[apsize]; |
1f6aaacc | 84 | va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1); |
19242b24 | 85 | va |= penc << 12; |
1189be65 | 86 | va |= ssize << 8; |
29ef7a3e AK |
87 | /* |
88 | * AVAL bits: | |
89 | * We don't need all the bits, but rest of the bits | |
90 | * must be ignored by the processor. | |
91 | * vpn cover upto 65 bits of va. (0...65) and we need | |
92 | * 58..64 bits of va. | |
93 | */ | |
94 | va |= (vpn & 0xfe); /* AVAL */ | |
60dbf438 | 95 | va |= 1; /* L */ |
a32e252f | 96 | asm volatile(ASM_FTR_IFCLR("tlbie %0,1", PPC_TLBIE(%1,%0), %2) |
969391c5 | 97 | : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206) |
60dbf438 | 98 | : "memory"); |
3c726f8d BH |
99 | break; |
100 | } | |
101 | } | |
102 | ||
b1022fbd | 103 | static inline void __tlbiel(unsigned long vpn, int psize, int apsize, int ssize) |
3c726f8d | 104 | { |
5524a27d | 105 | unsigned long va; |
3c726f8d | 106 | unsigned int penc; |
de640959 | 107 | unsigned long sllp; |
3c726f8d | 108 | |
5524a27d AK |
109 | /* VPN_SHIFT can be atmost 12 */ |
110 | va = vpn << VPN_SHIFT; | |
111 | /* | |
112 | * clear top 16 bits of 64 bit va, non SLS segment | |
113 | * Older versions of the architecture (2.02 and earler) require the | |
114 | * masking of the top 16 bits. | |
115 | */ | |
3c726f8d BH |
116 | va &= ~(0xffffULL << 48); |
117 | ||
118 | switch (psize) { | |
119 | case MMU_PAGE_4K: | |
1f6aaacc AK |
120 | /* clear out bits after(52) [0....52.....63] */ |
121 | va &= ~((1ul << (64 - 52)) - 1); | |
1189be65 | 122 | va |= ssize << 8; |
de640959 AK |
123 | sllp = ((mmu_psize_defs[apsize].sllp & SLB_VSID_L) >> 6) | |
124 | ((mmu_psize_defs[apsize].sllp & SLB_VSID_LP) >> 4); | |
125 | va |= sllp << 5; | |
3c726f8d BH |
126 | asm volatile(".long 0x7c000224 | (%0 << 11) | (0 << 21)" |
127 | : : "r"(va) : "memory"); | |
128 | break; | |
129 | default: | |
5524a27d | 130 | /* We need 14 to 14 + i bits of va */ |
b1022fbd | 131 | penc = mmu_psize_defs[psize].penc[apsize]; |
1f6aaacc | 132 | va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1); |
19242b24 | 133 | va |= penc << 12; |
1189be65 | 134 | va |= ssize << 8; |
29ef7a3e AK |
135 | /* |
136 | * AVAL bits: | |
137 | * We don't need all the bits, but rest of the bits | |
138 | * must be ignored by the processor. | |
139 | * vpn cover upto 65 bits of va. (0...65) and we need | |
140 | * 58..64 bits of va. | |
141 | */ | |
142 | va |= (vpn & 0xfe); | |
60dbf438 | 143 | va |= 1; /* L */ |
3c726f8d BH |
144 | asm volatile(".long 0x7c000224 | (%0 << 11) | (1 << 21)" |
145 | : : "r"(va) : "memory"); | |
146 | break; | |
147 | } | |
148 | ||
149 | } | |
150 | ||
b1022fbd AK |
151 | static inline void tlbie(unsigned long vpn, int psize, int apsize, |
152 | int ssize, int local) | |
3c726f8d | 153 | { |
4c6d9acc | 154 | unsigned int use_local; |
44ae3ab3 | 155 | int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE); |
3c726f8d | 156 | |
4c6d9acc IM |
157 | use_local = local && mmu_has_feature(MMU_FTR_TLBIEL) && !cxl_ctx_in_use(); |
158 | ||
3c726f8d BH |
159 | if (use_local) |
160 | use_local = mmu_psize_defs[psize].tlbiel; | |
161 | if (lock_tlbie && !use_local) | |
6b9c9b8a | 162 | raw_spin_lock(&native_tlbie_lock); |
3c726f8d BH |
163 | asm volatile("ptesync": : :"memory"); |
164 | if (use_local) { | |
b1022fbd | 165 | __tlbiel(vpn, psize, apsize, ssize); |
3c726f8d BH |
166 | asm volatile("ptesync": : :"memory"); |
167 | } else { | |
b1022fbd | 168 | __tlbie(vpn, psize, apsize, ssize); |
3c726f8d BH |
169 | asm volatile("eieio; tlbsync; ptesync": : :"memory"); |
170 | } | |
171 | if (lock_tlbie && !use_local) | |
6b9c9b8a | 172 | raw_spin_unlock(&native_tlbie_lock); |
3c726f8d BH |
173 | } |
174 | ||
8e561e7e | 175 | static inline void native_lock_hpte(struct hash_pte *hptep) |
1da177e4 | 176 | { |
12f04f2b | 177 | unsigned long *word = (unsigned long *)&hptep->v; |
1da177e4 LT |
178 | |
179 | while (1) { | |
66d99b88 | 180 | if (!test_and_set_bit_lock(HPTE_LOCK_BIT, word)) |
1da177e4 LT |
181 | break; |
182 | while(test_bit(HPTE_LOCK_BIT, word)) | |
183 | cpu_relax(); | |
184 | } | |
185 | } | |
186 | ||
8e561e7e | 187 | static inline void native_unlock_hpte(struct hash_pte *hptep) |
1da177e4 | 188 | { |
12f04f2b | 189 | unsigned long *word = (unsigned long *)&hptep->v; |
1da177e4 | 190 | |
66d99b88 | 191 | clear_bit_unlock(HPTE_LOCK_BIT, word); |
1da177e4 LT |
192 | } |
193 | ||
5524a27d | 194 | static long native_hpte_insert(unsigned long hpte_group, unsigned long vpn, |
3c726f8d | 195 | unsigned long pa, unsigned long rflags, |
b1022fbd | 196 | unsigned long vflags, int psize, int apsize, int ssize) |
1da177e4 | 197 | { |
8e561e7e | 198 | struct hash_pte *hptep = htab_address + hpte_group; |
96e28449 | 199 | unsigned long hpte_v, hpte_r; |
1da177e4 LT |
200 | int i; |
201 | ||
3c726f8d | 202 | if (!(vflags & HPTE_V_BOLTED)) { |
5524a27d | 203 | DBG_LOW(" insert(group=%lx, vpn=%016lx, pa=%016lx," |
3c726f8d | 204 | " rflags=%lx, vflags=%lx, psize=%d)\n", |
5524a27d | 205 | hpte_group, vpn, pa, rflags, vflags, psize); |
3c726f8d BH |
206 | } |
207 | ||
1da177e4 | 208 | for (i = 0; i < HPTES_PER_GROUP; i++) { |
12f04f2b | 209 | if (! (be64_to_cpu(hptep->v) & HPTE_V_VALID)) { |
1da177e4 LT |
210 | /* retry with lock held */ |
211 | native_lock_hpte(hptep); | |
12f04f2b | 212 | if (! (be64_to_cpu(hptep->v) & HPTE_V_VALID)) |
1da177e4 LT |
213 | break; |
214 | native_unlock_hpte(hptep); | |
215 | } | |
216 | ||
217 | hptep++; | |
218 | } | |
219 | ||
220 | if (i == HPTES_PER_GROUP) | |
221 | return -1; | |
222 | ||
b1022fbd AK |
223 | hpte_v = hpte_encode_v(vpn, psize, apsize, ssize) | vflags | HPTE_V_VALID; |
224 | hpte_r = hpte_encode_r(pa, psize, apsize) | rflags; | |
3c726f8d BH |
225 | |
226 | if (!(vflags & HPTE_V_BOLTED)) { | |
227 | DBG_LOW(" i=%x hpte_v=%016lx, hpte_r=%016lx\n", | |
228 | i, hpte_v, hpte_r); | |
229 | } | |
1da177e4 | 230 | |
12f04f2b | 231 | hptep->r = cpu_to_be64(hpte_r); |
1da177e4 | 232 | /* Guarantee the second dword is visible before the valid bit */ |
74a0ba61 | 233 | eieio(); |
1da177e4 LT |
234 | /* |
235 | * Now set the first dword including the valid bit | |
236 | * NOTE: this also unlocks the hpte | |
237 | */ | |
12f04f2b | 238 | hptep->v = cpu_to_be64(hpte_v); |
1da177e4 LT |
239 | |
240 | __asm__ __volatile__ ("ptesync" : : : "memory"); | |
241 | ||
96e28449 | 242 | return i | (!!(vflags & HPTE_V_SECONDARY) << 3); |
1da177e4 LT |
243 | } |
244 | ||
245 | static long native_hpte_remove(unsigned long hpte_group) | |
246 | { | |
8e561e7e | 247 | struct hash_pte *hptep; |
1da177e4 LT |
248 | int i; |
249 | int slot_offset; | |
96e28449 | 250 | unsigned long hpte_v; |
1da177e4 | 251 | |
3c726f8d BH |
252 | DBG_LOW(" remove(group=%lx)\n", hpte_group); |
253 | ||
1da177e4 LT |
254 | /* pick a random entry to start at */ |
255 | slot_offset = mftb() & 0x7; | |
256 | ||
257 | for (i = 0; i < HPTES_PER_GROUP; i++) { | |
258 | hptep = htab_address + hpte_group + slot_offset; | |
12f04f2b | 259 | hpte_v = be64_to_cpu(hptep->v); |
1da177e4 | 260 | |
96e28449 | 261 | if ((hpte_v & HPTE_V_VALID) && !(hpte_v & HPTE_V_BOLTED)) { |
1da177e4 LT |
262 | /* retry with lock held */ |
263 | native_lock_hpte(hptep); | |
12f04f2b | 264 | hpte_v = be64_to_cpu(hptep->v); |
96e28449 DG |
265 | if ((hpte_v & HPTE_V_VALID) |
266 | && !(hpte_v & HPTE_V_BOLTED)) | |
1da177e4 LT |
267 | break; |
268 | native_unlock_hpte(hptep); | |
269 | } | |
270 | ||
271 | slot_offset++; | |
272 | slot_offset &= 0x7; | |
273 | } | |
274 | ||
275 | if (i == HPTES_PER_GROUP) | |
276 | return -1; | |
277 | ||
278 | /* Invalidate the hpte. NOTE: this also unlocks it */ | |
96e28449 | 279 | hptep->v = 0; |
1da177e4 LT |
280 | |
281 | return i; | |
282 | } | |
283 | ||
3c726f8d | 284 | static long native_hpte_updatepp(unsigned long slot, unsigned long newpp, |
db3d8534 AK |
285 | unsigned long vpn, int bpsize, |
286 | int apsize, int ssize, int local) | |
1da177e4 | 287 | { |
8e561e7e | 288 | struct hash_pte *hptep = htab_address + slot; |
3c726f8d BH |
289 | unsigned long hpte_v, want_v; |
290 | int ret = 0; | |
291 | ||
db3d8534 | 292 | want_v = hpte_encode_avpn(vpn, bpsize, ssize); |
3c726f8d | 293 | |
5524a27d AK |
294 | DBG_LOW(" update(vpn=%016lx, avpnv=%016lx, group=%lx, newpp=%lx)", |
295 | vpn, want_v & HPTE_V_AVPN, slot, newpp); | |
3c726f8d | 296 | |
12f04f2b | 297 | hpte_v = be64_to_cpu(hptep->v); |
0608d692 AK |
298 | /* |
299 | * We need to invalidate the TLB always because hpte_remove doesn't do | |
300 | * a tlb invalidate. If a hash bucket gets full, we "evict" a more/less | |
301 | * random entry from it. When we do that we don't invalidate the TLB | |
302 | * (hpte_remove) because we assume the old translation is still | |
303 | * technically "valid". | |
304 | */ | |
db3d8534 | 305 | if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID)) { |
3c726f8d | 306 | DBG_LOW(" -> miss\n"); |
3c726f8d BH |
307 | ret = -1; |
308 | } else { | |
0ec2698f AK |
309 | native_lock_hpte(hptep); |
310 | /* recheck with locks held */ | |
311 | hpte_v = be64_to_cpu(hptep->v); | |
312 | if (unlikely(!HPTE_V_COMPARE(hpte_v, want_v) || | |
313 | !(hpte_v & HPTE_V_VALID))) { | |
314 | ret = -1; | |
315 | } else { | |
316 | DBG_LOW(" -> hit\n"); | |
317 | /* Update the HPTE */ | |
318 | hptep->r = cpu_to_be64((be64_to_cpu(hptep->r) & | |
319 | ~(HPTE_R_PP | HPTE_R_N)) | | |
320 | (newpp & (HPTE_R_PP | HPTE_R_N | | |
321 | HPTE_R_C))); | |
322 | } | |
323 | native_unlock_hpte(hptep); | |
3c726f8d | 324 | } |
3c726f8d | 325 | /* Ensure it is out of the tlb too. */ |
db3d8534 | 326 | tlbie(vpn, bpsize, apsize, ssize, local); |
3c726f8d | 327 | return ret; |
1da177e4 LT |
328 | } |
329 | ||
5524a27d | 330 | static long native_hpte_find(unsigned long vpn, int psize, int ssize) |
1da177e4 | 331 | { |
8e561e7e | 332 | struct hash_pte *hptep; |
1da177e4 | 333 | unsigned long hash; |
1189be65 | 334 | unsigned long i; |
1da177e4 | 335 | long slot; |
3c726f8d | 336 | unsigned long want_v, hpte_v; |
1da177e4 | 337 | |
5524a27d | 338 | hash = hpt_hash(vpn, mmu_psize_defs[psize].shift, ssize); |
74f227b2 | 339 | want_v = hpte_encode_avpn(vpn, psize, ssize); |
1da177e4 | 340 | |
1189be65 PM |
341 | /* Bolted mappings are only ever in the primary group */ |
342 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
343 | for (i = 0; i < HPTES_PER_GROUP; i++) { | |
344 | hptep = htab_address + slot; | |
12f04f2b | 345 | hpte_v = be64_to_cpu(hptep->v); |
1da177e4 | 346 | |
1189be65 PM |
347 | if (HPTE_V_COMPARE(hpte_v, want_v) && (hpte_v & HPTE_V_VALID)) |
348 | /* HPTE matches */ | |
349 | return slot; | |
350 | ++slot; | |
1da177e4 LT |
351 | } |
352 | ||
353 | return -1; | |
354 | } | |
355 | ||
1da177e4 LT |
356 | /* |
357 | * Update the page protection bits. Intended to be used to create | |
358 | * guard pages for kernel data structures on pages which are bolted | |
359 | * in the HPT. Assumes pages being operated on will not be stolen. | |
1da177e4 LT |
360 | * |
361 | * No need to lock here because we should be the only user. | |
362 | */ | |
3c726f8d | 363 | static void native_hpte_updateboltedpp(unsigned long newpp, unsigned long ea, |
1189be65 | 364 | int psize, int ssize) |
1da177e4 | 365 | { |
5524a27d AK |
366 | unsigned long vpn; |
367 | unsigned long vsid; | |
1da177e4 | 368 | long slot; |
8e561e7e | 369 | struct hash_pte *hptep; |
1da177e4 | 370 | |
1189be65 | 371 | vsid = get_kernel_vsid(ea, ssize); |
5524a27d | 372 | vpn = hpt_vpn(ea, vsid, ssize); |
1da177e4 | 373 | |
5524a27d | 374 | slot = native_hpte_find(vpn, psize, ssize); |
1da177e4 LT |
375 | if (slot == -1) |
376 | panic("could not find page to bolt\n"); | |
377 | hptep = htab_address + slot; | |
378 | ||
3c726f8d | 379 | /* Update the HPTE */ |
12f04f2b AB |
380 | hptep->r = cpu_to_be64((be64_to_cpu(hptep->r) & |
381 | ~(HPTE_R_PP | HPTE_R_N)) | | |
382 | (newpp & (HPTE_R_PP | HPTE_R_N))); | |
db3d8534 AK |
383 | /* |
384 | * Ensure it is out of the tlb too. Bolted entries base and | |
385 | * actual page size will be same. | |
386 | */ | |
387 | tlbie(vpn, psize, psize, ssize, 0); | |
1da177e4 LT |
388 | } |
389 | ||
5524a27d | 390 | static void native_hpte_invalidate(unsigned long slot, unsigned long vpn, |
db3d8534 | 391 | int bpsize, int apsize, int ssize, int local) |
1da177e4 | 392 | { |
8e561e7e | 393 | struct hash_pte *hptep = htab_address + slot; |
96e28449 | 394 | unsigned long hpte_v; |
3c726f8d | 395 | unsigned long want_v; |
1da177e4 | 396 | unsigned long flags; |
1da177e4 LT |
397 | |
398 | local_irq_save(flags); | |
1da177e4 | 399 | |
5524a27d | 400 | DBG_LOW(" invalidate(vpn=%016lx, hash: %lx)\n", vpn, slot); |
3c726f8d | 401 | |
db3d8534 | 402 | want_v = hpte_encode_avpn(vpn, bpsize, ssize); |
3c726f8d | 403 | native_lock_hpte(hptep); |
12f04f2b | 404 | hpte_v = be64_to_cpu(hptep->v); |
1da177e4 | 405 | |
0608d692 AK |
406 | /* |
407 | * We need to invalidate the TLB always because hpte_remove doesn't do | |
408 | * a tlb invalidate. If a hash bucket gets full, we "evict" a more/less | |
409 | * random entry from it. When we do that we don't invalidate the TLB | |
410 | * (hpte_remove) because we assume the old translation is still | |
411 | * technically "valid". | |
412 | */ | |
db3d8534 | 413 | if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID)) |
1da177e4 | 414 | native_unlock_hpte(hptep); |
3c726f8d | 415 | else |
1da177e4 | 416 | /* Invalidate the hpte. NOTE: this also unlocks it */ |
96e28449 | 417 | hptep->v = 0; |
1da177e4 | 418 | |
3c726f8d | 419 | /* Invalidate the TLB */ |
db3d8534 AK |
420 | tlbie(vpn, bpsize, apsize, ssize, local); |
421 | ||
1da177e4 LT |
422 | local_irq_restore(flags); |
423 | } | |
424 | ||
fa1f8ae8 AK |
425 | static void native_hugepage_invalidate(unsigned long vsid, |
426 | unsigned long addr, | |
1a527286 | 427 | unsigned char *hpte_slot_array, |
fa1f8ae8 | 428 | int psize, int ssize) |
1a527286 | 429 | { |
969b7b20 | 430 | int i; |
1a527286 AK |
431 | struct hash_pte *hptep; |
432 | int actual_psize = MMU_PAGE_16M; | |
433 | unsigned int max_hpte_count, valid; | |
434 | unsigned long flags, s_addr = addr; | |
435 | unsigned long hpte_v, want_v, shift; | |
fa1f8ae8 | 436 | unsigned long hidx, vpn = 0, hash, slot; |
1a527286 AK |
437 | |
438 | shift = mmu_psize_defs[psize].shift; | |
439 | max_hpte_count = 1U << (PMD_SHIFT - shift); | |
440 | ||
441 | local_irq_save(flags); | |
442 | for (i = 0; i < max_hpte_count; i++) { | |
443 | valid = hpte_valid(hpte_slot_array, i); | |
444 | if (!valid) | |
445 | continue; | |
446 | hidx = hpte_hash_index(hpte_slot_array, i); | |
447 | ||
448 | /* get the vpn */ | |
449 | addr = s_addr + (i * (1ul << shift)); | |
1a527286 AK |
450 | vpn = hpt_vpn(addr, vsid, ssize); |
451 | hash = hpt_hash(vpn, shift, ssize); | |
452 | if (hidx & _PTEIDX_SECONDARY) | |
453 | hash = ~hash; | |
454 | ||
455 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
456 | slot += hidx & _PTEIDX_GROUP_IX; | |
457 | ||
458 | hptep = htab_address + slot; | |
459 | want_v = hpte_encode_avpn(vpn, psize, ssize); | |
460 | native_lock_hpte(hptep); | |
12f04f2b | 461 | hpte_v = be64_to_cpu(hptep->v); |
1a527286 AK |
462 | |
463 | /* Even if we miss, we need to invalidate the TLB */ | |
464 | if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID)) | |
465 | native_unlock_hpte(hptep); | |
466 | else | |
467 | /* Invalidate the hpte. NOTE: this also unlocks it */ | |
468 | hptep->v = 0; | |
969b7b20 AK |
469 | /* |
470 | * We need to do tlb invalidate for all the address, tlbie | |
471 | * instruction compares entry_VA in tlb with the VA specified | |
472 | * here | |
473 | */ | |
474 | tlbie(vpn, psize, actual_psize, ssize, 0); | |
1a527286 | 475 | } |
1a527286 AK |
476 | local_irq_restore(flags); |
477 | } | |
478 | ||
db3d8534 AK |
479 | static inline int __hpte_actual_psize(unsigned int lp, int psize) |
480 | { | |
481 | int i, shift; | |
482 | unsigned int mask; | |
483 | ||
484 | /* start from 1 ignoring MMU_PAGE_4K */ | |
485 | for (i = 1; i < MMU_PAGE_COUNT; i++) { | |
486 | ||
487 | /* invalid penc */ | |
488 | if (mmu_psize_defs[psize].penc[i] == -1) | |
489 | continue; | |
490 | /* | |
491 | * encoding bits per actual page size | |
492 | * PTE LP actual page size | |
493 | * rrrr rrrz >=8KB | |
494 | * rrrr rrzz >=16KB | |
495 | * rrrr rzzz >=32KB | |
496 | * rrrr zzzz >=64KB | |
497 | * ....... | |
498 | */ | |
499 | shift = mmu_psize_defs[i].shift - LP_SHIFT; | |
500 | if (shift > LP_BITS) | |
501 | shift = LP_BITS; | |
502 | mask = (1 << shift) - 1; | |
503 | if ((lp & mask) == mmu_psize_defs[psize].penc[i]) | |
504 | return i; | |
505 | } | |
506 | return -1; | |
507 | } | |
508 | ||
8e561e7e | 509 | static void hpte_decode(struct hash_pte *hpte, unsigned long slot, |
b1022fbd | 510 | int *psize, int *apsize, int *ssize, unsigned long *vpn) |
71bf08b6 | 511 | { |
dcda287a | 512 | unsigned long avpn, pteg, vpi; |
12f04f2b AB |
513 | unsigned long hpte_v = be64_to_cpu(hpte->v); |
514 | unsigned long hpte_r = be64_to_cpu(hpte->r); | |
dcda287a | 515 | unsigned long vsid, seg_off; |
7e74c392 AK |
516 | int size, a_size, shift; |
517 | /* Look at the 8 bit LP value */ | |
12f04f2b | 518 | unsigned int lp = (hpte_r >> LP_SHIFT) & ((1 << LP_BITS) - 1); |
71bf08b6 | 519 | |
b1022fbd AK |
520 | if (!(hpte_v & HPTE_V_LARGE)) { |
521 | size = MMU_PAGE_4K; | |
522 | a_size = MMU_PAGE_4K; | |
523 | } else { | |
71bf08b6 | 524 | for (size = 0; size < MMU_PAGE_COUNT; size++) { |
3c726f8d | 525 | |
71bf08b6 LB |
526 | /* valid entries have a shift value */ |
527 | if (!mmu_psize_defs[size].shift) | |
528 | continue; | |
b1022fbd | 529 | |
7e74c392 AK |
530 | a_size = __hpte_actual_psize(lp, size); |
531 | if (a_size != -1) | |
532 | break; | |
71bf08b6 LB |
533 | } |
534 | } | |
2454c7e9 | 535 | /* This works for all page sizes, and for 256M and 1T segments */ |
dcda287a | 536 | *ssize = hpte_v >> HPTE_V_SSIZE_SHIFT; |
71bf08b6 | 537 | shift = mmu_psize_defs[size].shift; |
71bf08b6 | 538 | |
dcda287a AK |
539 | avpn = (HPTE_V_AVPN_VAL(hpte_v) & ~mmu_psize_defs[size].avpnm); |
540 | pteg = slot / HPTES_PER_GROUP; | |
541 | if (hpte_v & HPTE_V_SECONDARY) | |
542 | pteg = ~pteg; | |
543 | ||
544 | switch (*ssize) { | |
545 | case MMU_SEGSIZE_256M: | |
546 | /* We only have 28 - 23 bits of seg_off in avpn */ | |
547 | seg_off = (avpn & 0x1f) << 23; | |
548 | vsid = avpn >> 5; | |
549 | /* We can find more bits from the pteg value */ | |
550 | if (shift < 23) { | |
551 | vpi = (vsid ^ pteg) & htab_hash_mask; | |
552 | seg_off |= vpi << shift; | |
553 | } | |
5524a27d | 554 | *vpn = vsid << (SID_SHIFT - VPN_SHIFT) | seg_off >> VPN_SHIFT; |
83383b73 | 555 | break; |
dcda287a AK |
556 | case MMU_SEGSIZE_1T: |
557 | /* We only have 40 - 23 bits of seg_off in avpn */ | |
558 | seg_off = (avpn & 0x1ffff) << 23; | |
559 | vsid = avpn >> 17; | |
560 | if (shift < 23) { | |
2454c7e9 | 561 | vpi = (vsid ^ (vsid << 25) ^ pteg) & htab_hash_mask; |
dcda287a | 562 | seg_off |= vpi << shift; |
71bf08b6 | 563 | } |
5524a27d | 564 | *vpn = vsid << (SID_SHIFT_1T - VPN_SHIFT) | seg_off >> VPN_SHIFT; |
83383b73 | 565 | break; |
dcda287a | 566 | default: |
5524a27d | 567 | *vpn = size = 0; |
3c726f8d | 568 | } |
b1022fbd AK |
569 | *psize = size; |
570 | *apsize = a_size; | |
3c726f8d BH |
571 | } |
572 | ||
f4c82d51 S |
573 | /* |
574 | * clear all mappings on kexec. All cpus are in real mode (or they will | |
575 | * be when they isi), and we are the only one left. We rely on our kernel | |
576 | * mapping being 0xC0's and the hardware ignoring those two real bits. | |
577 | * | |
578 | * TODO: add batching support when enabled. remember, no dynamic memory here, | |
579 | * athough there is the control page available... | |
580 | */ | |
581 | static void native_hpte_clear(void) | |
582 | { | |
5524a27d | 583 | unsigned long vpn = 0; |
f4c82d51 | 584 | unsigned long slot, slots, flags; |
8e561e7e | 585 | struct hash_pte *hptep = htab_address; |
5524a27d | 586 | unsigned long hpte_v; |
f4c82d51 | 587 | unsigned long pteg_count; |
b1022fbd | 588 | int psize, apsize, ssize; |
f4c82d51 S |
589 | |
590 | pteg_count = htab_hash_mask + 1; | |
591 | ||
592 | local_irq_save(flags); | |
593 | ||
594 | /* we take the tlbie lock and hold it. Some hardware will | |
595 | * deadlock if we try to tlbie from two processors at once. | |
596 | */ | |
6b9c9b8a | 597 | raw_spin_lock(&native_tlbie_lock); |
f4c82d51 S |
598 | |
599 | slots = pteg_count * HPTES_PER_GROUP; | |
600 | ||
601 | for (slot = 0; slot < slots; slot++, hptep++) { | |
602 | /* | |
603 | * we could lock the pte here, but we are the only cpu | |
604 | * running, right? and for crash dump, we probably | |
605 | * don't want to wait for a maybe bad cpu. | |
606 | */ | |
12f04f2b | 607 | hpte_v = be64_to_cpu(hptep->v); |
f4c82d51 | 608 | |
47f78a49 S |
609 | /* |
610 | * Call __tlbie() here rather than tlbie() since we | |
611 | * already hold the native_tlbie_lock. | |
612 | */ | |
96e28449 | 613 | if (hpte_v & HPTE_V_VALID) { |
b1022fbd | 614 | hpte_decode(hptep, slot, &psize, &apsize, &ssize, &vpn); |
96e28449 | 615 | hptep->v = 0; |
b1022fbd | 616 | __tlbie(vpn, psize, apsize, ssize); |
f4c82d51 S |
617 | } |
618 | } | |
619 | ||
47f78a49 | 620 | asm volatile("eieio; tlbsync; ptesync":::"memory"); |
6b9c9b8a | 621 | raw_spin_unlock(&native_tlbie_lock); |
f4c82d51 S |
622 | local_irq_restore(flags); |
623 | } | |
624 | ||
3c726f8d BH |
625 | /* |
626 | * Batched hash table flush, we batch the tlbie's to avoid taking/releasing | |
627 | * the lock all the time | |
628 | */ | |
61b1a942 | 629 | static void native_flush_hash_range(unsigned long number, int local) |
1da177e4 | 630 | { |
5524a27d AK |
631 | unsigned long vpn; |
632 | unsigned long hash, index, hidx, shift, slot; | |
8e561e7e | 633 | struct hash_pte *hptep; |
96e28449 | 634 | unsigned long hpte_v; |
3c726f8d BH |
635 | unsigned long want_v; |
636 | unsigned long flags; | |
637 | real_pte_t pte; | |
69111bac | 638 | struct ppc64_tlb_batch *batch = this_cpu_ptr(&ppc64_tlb_batch); |
3c726f8d | 639 | unsigned long psize = batch->psize; |
1189be65 | 640 | int ssize = batch->ssize; |
3c726f8d | 641 | int i; |
1da177e4 LT |
642 | |
643 | local_irq_save(flags); | |
644 | ||
1da177e4 | 645 | for (i = 0; i < number; i++) { |
5524a27d | 646 | vpn = batch->vpn[i]; |
3c726f8d BH |
647 | pte = batch->pte[i]; |
648 | ||
5524a27d AK |
649 | pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) { |
650 | hash = hpt_hash(vpn, shift, ssize); | |
3c726f8d BH |
651 | hidx = __rpte_to_hidx(pte, index); |
652 | if (hidx & _PTEIDX_SECONDARY) | |
653 | hash = ~hash; | |
654 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
655 | slot += hidx & _PTEIDX_GROUP_IX; | |
656 | hptep = htab_address + slot; | |
74f227b2 | 657 | want_v = hpte_encode_avpn(vpn, psize, ssize); |
3c726f8d | 658 | native_lock_hpte(hptep); |
12f04f2b | 659 | hpte_v = be64_to_cpu(hptep->v); |
3c726f8d BH |
660 | if (!HPTE_V_COMPARE(hpte_v, want_v) || |
661 | !(hpte_v & HPTE_V_VALID)) | |
662 | native_unlock_hpte(hptep); | |
663 | else | |
664 | hptep->v = 0; | |
665 | } pte_iterate_hashed_end(); | |
1da177e4 LT |
666 | } |
667 | ||
44ae3ab3 | 668 | if (mmu_has_feature(MMU_FTR_TLBIEL) && |
3c726f8d | 669 | mmu_psize_defs[psize].tlbiel && local) { |
1da177e4 | 670 | asm volatile("ptesync":::"memory"); |
3c726f8d | 671 | for (i = 0; i < number; i++) { |
5524a27d | 672 | vpn = batch->vpn[i]; |
3c726f8d BH |
673 | pte = batch->pte[i]; |
674 | ||
5524a27d AK |
675 | pte_iterate_hashed_subpages(pte, psize, |
676 | vpn, index, shift) { | |
b1022fbd | 677 | __tlbiel(vpn, psize, psize, ssize); |
3c726f8d BH |
678 | } pte_iterate_hashed_end(); |
679 | } | |
1da177e4 LT |
680 | asm volatile("ptesync":::"memory"); |
681 | } else { | |
44ae3ab3 | 682 | int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE); |
1da177e4 LT |
683 | |
684 | if (lock_tlbie) | |
6b9c9b8a | 685 | raw_spin_lock(&native_tlbie_lock); |
1da177e4 LT |
686 | |
687 | asm volatile("ptesync":::"memory"); | |
3c726f8d | 688 | for (i = 0; i < number; i++) { |
5524a27d | 689 | vpn = batch->vpn[i]; |
3c726f8d BH |
690 | pte = batch->pte[i]; |
691 | ||
5524a27d AK |
692 | pte_iterate_hashed_subpages(pte, psize, |
693 | vpn, index, shift) { | |
b1022fbd | 694 | __tlbie(vpn, psize, psize, ssize); |
3c726f8d BH |
695 | } pte_iterate_hashed_end(); |
696 | } | |
1da177e4 LT |
697 | asm volatile("eieio; tlbsync; ptesync":::"memory"); |
698 | ||
699 | if (lock_tlbie) | |
6b9c9b8a | 700 | raw_spin_unlock(&native_tlbie_lock); |
1da177e4 LT |
701 | } |
702 | ||
703 | local_irq_restore(flags); | |
704 | } | |
705 | ||
7d0daae4 | 706 | void __init hpte_init_native(void) |
1da177e4 LT |
707 | { |
708 | ppc_md.hpte_invalidate = native_hpte_invalidate; | |
709 | ppc_md.hpte_updatepp = native_hpte_updatepp; | |
710 | ppc_md.hpte_updateboltedpp = native_hpte_updateboltedpp; | |
711 | ppc_md.hpte_insert = native_hpte_insert; | |
f4c82d51 S |
712 | ppc_md.hpte_remove = native_hpte_remove; |
713 | ppc_md.hpte_clear_all = native_hpte_clear; | |
8e166991 | 714 | ppc_md.flush_hash_range = native_flush_hash_range; |
1a527286 | 715 | ppc_md.hugepage_invalidate = native_hugepage_invalidate; |
1da177e4 | 716 | } |