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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * PowerPC64 port by Mike Corrigan and Dave Engebretsen | |
3 | * {mikejc|engebret}@us.ibm.com | |
4 | * | |
5 | * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com> | |
6 | * | |
7 | * SMP scalability work: | |
8 | * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM | |
9 | * | |
10 | * Module name: htab.c | |
11 | * | |
12 | * Description: | |
13 | * PowerPC Hashed Page Table functions | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License | |
17 | * as published by the Free Software Foundation; either version | |
18 | * 2 of the License, or (at your option) any later version. | |
19 | */ | |
20 | ||
21 | #undef DEBUG | |
3c726f8d | 22 | #undef DEBUG_LOW |
1da177e4 | 23 | |
1da177e4 LT |
24 | #include <linux/spinlock.h> |
25 | #include <linux/errno.h> | |
26 | #include <linux/sched.h> | |
27 | #include <linux/proc_fs.h> | |
28 | #include <linux/stat.h> | |
29 | #include <linux/sysctl.h> | |
66b15db6 | 30 | #include <linux/export.h> |
1da177e4 LT |
31 | #include <linux/ctype.h> |
32 | #include <linux/cache.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/signal.h> | |
95f72d1e | 35 | #include <linux/memblock.h> |
ba12eede | 36 | #include <linux/context_tracking.h> |
5556ecf5 | 37 | #include <linux/libfdt.h> |
1da177e4 | 38 | |
1da177e4 LT |
39 | #include <asm/processor.h> |
40 | #include <asm/pgtable.h> | |
41 | #include <asm/mmu.h> | |
42 | #include <asm/mmu_context.h> | |
43 | #include <asm/page.h> | |
44 | #include <asm/types.h> | |
1da177e4 LT |
45 | #include <asm/uaccess.h> |
46 | #include <asm/machdep.h> | |
d9b2b2a2 | 47 | #include <asm/prom.h> |
1da177e4 LT |
48 | #include <asm/tlbflush.h> |
49 | #include <asm/io.h> | |
50 | #include <asm/eeh.h> | |
51 | #include <asm/tlb.h> | |
52 | #include <asm/cacheflush.h> | |
53 | #include <asm/cputable.h> | |
1da177e4 | 54 | #include <asm/sections.h> |
be3ebfe8 | 55 | #include <asm/copro.h> |
aa39be09 | 56 | #include <asm/udbg.h> |
b68a70c4 | 57 | #include <asm/code-patching.h> |
3ccc00a7 | 58 | #include <asm/fadump.h> |
f5339277 | 59 | #include <asm/firmware.h> |
bc2a9408 | 60 | #include <asm/tm.h> |
cfcb3d80 | 61 | #include <asm/trace.h> |
166dd7d3 | 62 | #include <asm/ps3.h> |
1da177e4 LT |
63 | |
64 | #ifdef DEBUG | |
65 | #define DBG(fmt...) udbg_printf(fmt) | |
66 | #else | |
67 | #define DBG(fmt...) | |
68 | #endif | |
69 | ||
3c726f8d BH |
70 | #ifdef DEBUG_LOW |
71 | #define DBG_LOW(fmt...) udbg_printf(fmt) | |
72 | #else | |
73 | #define DBG_LOW(fmt...) | |
74 | #endif | |
75 | ||
76 | #define KB (1024) | |
77 | #define MB (1024*KB) | |
658013e9 | 78 | #define GB (1024L*MB) |
3c726f8d | 79 | |
1da177e4 LT |
80 | /* |
81 | * Note: pte --> Linux PTE | |
82 | * HPTE --> PowerPC Hashed Page Table Entry | |
83 | * | |
84 | * Execution context: | |
85 | * htab_initialize is called with the MMU off (of course), but | |
86 | * the kernel has been copied down to zero so it can directly | |
87 | * reference global data. At this point it is very difficult | |
88 | * to print debug info. | |
89 | * | |
90 | */ | |
91 | ||
799d6046 PM |
92 | static unsigned long _SDR1; |
93 | struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; | |
e1802b06 | 94 | EXPORT_SYMBOL_GPL(mmu_psize_defs); |
799d6046 | 95 | |
0eeede0c PM |
96 | u8 hpte_page_sizes[1 << LP_BITS]; |
97 | EXPORT_SYMBOL_GPL(hpte_page_sizes); | |
98 | ||
8e561e7e | 99 | struct hash_pte *htab_address; |
337a7128 | 100 | unsigned long htab_size_bytes; |
96e28449 | 101 | unsigned long htab_hash_mask; |
4ab79aa8 | 102 | EXPORT_SYMBOL_GPL(htab_hash_mask); |
3c726f8d | 103 | int mmu_linear_psize = MMU_PAGE_4K; |
8ca7a82f | 104 | EXPORT_SYMBOL_GPL(mmu_linear_psize); |
3c726f8d | 105 | int mmu_virtual_psize = MMU_PAGE_4K; |
bf72aeba | 106 | int mmu_vmalloc_psize = MMU_PAGE_4K; |
cec08e7a BH |
107 | #ifdef CONFIG_SPARSEMEM_VMEMMAP |
108 | int mmu_vmemmap_psize = MMU_PAGE_4K; | |
109 | #endif | |
bf72aeba | 110 | int mmu_io_psize = MMU_PAGE_4K; |
1189be65 | 111 | int mmu_kernel_ssize = MMU_SEGSIZE_256M; |
8ca7a82f | 112 | EXPORT_SYMBOL_GPL(mmu_kernel_ssize); |
1189be65 | 113 | int mmu_highuser_ssize = MMU_SEGSIZE_256M; |
584f8b71 | 114 | u16 mmu_slb_size = 64; |
4ab79aa8 | 115 | EXPORT_SYMBOL_GPL(mmu_slb_size); |
bf72aeba PM |
116 | #ifdef CONFIG_PPC_64K_PAGES |
117 | int mmu_ci_restrictions; | |
118 | #endif | |
370a908d BH |
119 | #ifdef CONFIG_DEBUG_PAGEALLOC |
120 | static u8 *linear_map_hash_slots; | |
121 | static unsigned long linear_map_hash_count; | |
ed166692 | 122 | static DEFINE_SPINLOCK(linear_map_hash_lock); |
370a908d | 123 | #endif /* CONFIG_DEBUG_PAGEALLOC */ |
7025776e BH |
124 | struct mmu_hash_ops mmu_hash_ops; |
125 | EXPORT_SYMBOL(mmu_hash_ops); | |
1da177e4 | 126 | |
3c726f8d BH |
127 | /* There are definitions of page sizes arrays to be used when none |
128 | * is provided by the firmware. | |
129 | */ | |
1da177e4 | 130 | |
3c726f8d BH |
131 | /* Pre-POWER4 CPUs (4k pages only) |
132 | */ | |
09de9ff8 | 133 | static struct mmu_psize_def mmu_psize_defaults_old[] = { |
3c726f8d BH |
134 | [MMU_PAGE_4K] = { |
135 | .shift = 12, | |
136 | .sllp = 0, | |
b1022fbd | 137 | .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1}, |
3c726f8d BH |
138 | .avpnm = 0, |
139 | .tlbiel = 0, | |
140 | }, | |
141 | }; | |
142 | ||
143 | /* POWER4, GPUL, POWER5 | |
144 | * | |
145 | * Support for 16Mb large pages | |
146 | */ | |
09de9ff8 | 147 | static struct mmu_psize_def mmu_psize_defaults_gp[] = { |
3c726f8d BH |
148 | [MMU_PAGE_4K] = { |
149 | .shift = 12, | |
150 | .sllp = 0, | |
b1022fbd | 151 | .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1}, |
3c726f8d BH |
152 | .avpnm = 0, |
153 | .tlbiel = 1, | |
154 | }, | |
155 | [MMU_PAGE_16M] = { | |
156 | .shift = 24, | |
157 | .sllp = SLB_VSID_L, | |
b1022fbd AK |
158 | .penc = {[0 ... MMU_PAGE_16M - 1] = -1, [MMU_PAGE_16M] = 0, |
159 | [MMU_PAGE_16M + 1 ... MMU_PAGE_COUNT - 1] = -1 }, | |
3c726f8d BH |
160 | .avpnm = 0x1UL, |
161 | .tlbiel = 0, | |
162 | }, | |
163 | }; | |
164 | ||
dc47c0c1 AK |
165 | /* |
166 | * 'R' and 'C' update notes: | |
167 | * - Under pHyp or KVM, the updatepp path will not set C, thus it *will* | |
168 | * create writeable HPTEs without C set, because the hcall H_PROTECT | |
169 | * that we use in that case will not update C | |
170 | * - The above is however not a problem, because we also don't do that | |
171 | * fancy "no flush" variant of eviction and we use H_REMOVE which will | |
172 | * do the right thing and thus we don't have the race I described earlier | |
173 | * | |
174 | * - Under bare metal, we do have the race, so we need R and C set | |
175 | * - We make sure R is always set and never lost | |
176 | * - C is _PAGE_DIRTY, and *should* always be set for a writeable mapping | |
177 | */ | |
c6a3c495 | 178 | unsigned long htab_convert_pte_flags(unsigned long pteflags) |
bc033b63 | 179 | { |
c6a3c495 | 180 | unsigned long rflags = 0; |
bc033b63 BH |
181 | |
182 | /* _PAGE_EXEC -> NOEXEC */ | |
183 | if ((pteflags & _PAGE_EXEC) == 0) | |
184 | rflags |= HPTE_R_N; | |
c6a3c495 | 185 | /* |
e58e87ad | 186 | * PPP bits: |
1ec3f937 | 187 | * Linux uses slb key 0 for kernel and 1 for user. |
e58e87ad AK |
188 | * kernel RW areas are mapped with PPP=0b000 |
189 | * User area is mapped with PPP=0b010 for read/write | |
190 | * or PPP=0b011 for read-only (including writeable but clean pages). | |
bc033b63 | 191 | */ |
e58e87ad AK |
192 | if (pteflags & _PAGE_PRIVILEGED) { |
193 | /* | |
194 | * Kernel read only mapped with ppp bits 0b110 | |
195 | */ | |
196 | if (!(pteflags & _PAGE_WRITE)) | |
197 | rflags |= (HPTE_R_PP0 | 0x2); | |
198 | } else { | |
c7d54842 AK |
199 | if (pteflags & _PAGE_RWX) |
200 | rflags |= 0x2; | |
201 | if (!((pteflags & _PAGE_WRITE) && (pteflags & _PAGE_DIRTY))) | |
c6a3c495 AK |
202 | rflags |= 0x1; |
203 | } | |
c8c06f5a | 204 | /* |
dc47c0c1 AK |
205 | * We can't allow hardware to update hpte bits. Hence always |
206 | * set 'R' bit and set 'C' if it is a write fault | |
c8c06f5a | 207 | */ |
e568006b | 208 | rflags |= HPTE_R_R; |
dc47c0c1 AK |
209 | |
210 | if (pteflags & _PAGE_DIRTY) | |
211 | rflags |= HPTE_R_C; | |
40e8550a AK |
212 | /* |
213 | * Add in WIG bits | |
214 | */ | |
30bda41a AK |
215 | |
216 | if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_TOLERANT) | |
40e8550a | 217 | rflags |= HPTE_R_I; |
e568006b | 218 | else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT) |
30bda41a | 219 | rflags |= (HPTE_R_I | HPTE_R_G); |
e568006b AK |
220 | else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_SAO) |
221 | rflags |= (HPTE_R_W | HPTE_R_I | HPTE_R_M); | |
222 | else | |
223 | /* | |
224 | * Add memory coherence if cache inhibited is not set | |
225 | */ | |
226 | rflags |= HPTE_R_M; | |
40e8550a AK |
227 | |
228 | return rflags; | |
bc033b63 | 229 | } |
3c726f8d BH |
230 | |
231 | int htab_bolt_mapping(unsigned long vstart, unsigned long vend, | |
bc033b63 | 232 | unsigned long pstart, unsigned long prot, |
1189be65 | 233 | int psize, int ssize) |
1da177e4 | 234 | { |
3c726f8d BH |
235 | unsigned long vaddr, paddr; |
236 | unsigned int step, shift; | |
3c726f8d | 237 | int ret = 0; |
1da177e4 | 238 | |
3c726f8d BH |
239 | shift = mmu_psize_defs[psize].shift; |
240 | step = 1 << shift; | |
1da177e4 | 241 | |
bc033b63 BH |
242 | prot = htab_convert_pte_flags(prot); |
243 | ||
244 | DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n", | |
245 | vstart, vend, pstart, prot, psize, ssize); | |
246 | ||
3c726f8d BH |
247 | for (vaddr = vstart, paddr = pstart; vaddr < vend; |
248 | vaddr += step, paddr += step) { | |
370a908d | 249 | unsigned long hash, hpteg; |
1189be65 | 250 | unsigned long vsid = get_kernel_vsid(vaddr, ssize); |
5524a27d | 251 | unsigned long vpn = hpt_vpn(vaddr, vsid, ssize); |
9e88ba4e PM |
252 | unsigned long tprot = prot; |
253 | ||
c60ac569 AK |
254 | /* |
255 | * If we hit a bad address return error. | |
256 | */ | |
257 | if (!vsid) | |
258 | return -1; | |
9e88ba4e | 259 | /* Make kernel text executable */ |
549e8152 | 260 | if (overlaps_kernel_text(vaddr, vaddr + step)) |
9e88ba4e | 261 | tprot &= ~HPTE_R_N; |
1da177e4 | 262 | |
b18db0b8 AG |
263 | /* Make kvm guest trampolines executable */ |
264 | if (overlaps_kvm_tmp(vaddr, vaddr + step)) | |
265 | tprot &= ~HPTE_R_N; | |
266 | ||
429d2e83 MS |
267 | /* |
268 | * If relocatable, check if it overlaps interrupt vectors that | |
269 | * are copied down to real 0. For relocatable kernel | |
270 | * (e.g. kdump case) we copy interrupt vectors down to real | |
271 | * address 0. Mark that region as executable. This is | |
272 | * because on p8 system with relocation on exception feature | |
273 | * enabled, exceptions are raised with MMU (IR=DR=1) ON. Hence | |
274 | * in order to execute the interrupt handlers in virtual | |
275 | * mode the vector region need to be marked as executable. | |
276 | */ | |
277 | if ((PHYSICAL_START > MEMORY_START) && | |
278 | overlaps_interrupt_vector_text(vaddr, vaddr + step)) | |
279 | tprot &= ~HPTE_R_N; | |
280 | ||
5524a27d | 281 | hash = hpt_hash(vpn, shift, ssize); |
1da177e4 LT |
282 | hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP); |
283 | ||
7025776e BH |
284 | BUG_ON(!mmu_hash_ops.hpte_insert); |
285 | ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot, | |
286 | HPTE_V_BOLTED, psize, psize, | |
287 | ssize); | |
c30a4df3 | 288 | |
3c726f8d BH |
289 | if (ret < 0) |
290 | break; | |
e7df0d88 | 291 | |
370a908d | 292 | #ifdef CONFIG_DEBUG_PAGEALLOC |
e7df0d88 JK |
293 | if (debug_pagealloc_enabled() && |
294 | (paddr >> PAGE_SHIFT) < linear_map_hash_count) | |
370a908d BH |
295 | linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80; |
296 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
3c726f8d BH |
297 | } |
298 | return ret < 0 ? ret : 0; | |
299 | } | |
1da177e4 | 300 | |
ed5694a8 | 301 | int htab_remove_mapping(unsigned long vstart, unsigned long vend, |
f8c8803b BP |
302 | int psize, int ssize) |
303 | { | |
304 | unsigned long vaddr; | |
305 | unsigned int step, shift; | |
27828f98 DG |
306 | int rc; |
307 | int ret = 0; | |
f8c8803b BP |
308 | |
309 | shift = mmu_psize_defs[psize].shift; | |
310 | step = 1 << shift; | |
311 | ||
7025776e | 312 | if (!mmu_hash_ops.hpte_removebolted) |
abd0a0e7 | 313 | return -ENODEV; |
f8c8803b | 314 | |
27828f98 | 315 | for (vaddr = vstart; vaddr < vend; vaddr += step) { |
7025776e | 316 | rc = mmu_hash_ops.hpte_removebolted(vaddr, psize, ssize); |
27828f98 DG |
317 | if (rc == -ENOENT) { |
318 | ret = -ENOENT; | |
319 | continue; | |
320 | } | |
321 | if (rc < 0) | |
322 | return rc; | |
323 | } | |
52db9b44 | 324 | |
27828f98 | 325 | return ret; |
f8c8803b BP |
326 | } |
327 | ||
faf78829 OH |
328 | static bool disable_1tb_segments = false; |
329 | ||
330 | static int __init parse_disable_1tb_segments(char *p) | |
331 | { | |
332 | disable_1tb_segments = true; | |
333 | return 0; | |
334 | } | |
335 | early_param("disable_1tb_segments", parse_disable_1tb_segments); | |
336 | ||
1189be65 PM |
337 | static int __init htab_dt_scan_seg_sizes(unsigned long node, |
338 | const char *uname, int depth, | |
339 | void *data) | |
340 | { | |
9d0c4dfe RH |
341 | const char *type = of_get_flat_dt_prop(node, "device_type", NULL); |
342 | const __be32 *prop; | |
343 | int size = 0; | |
1189be65 PM |
344 | |
345 | /* We are scanning "cpu" nodes only */ | |
346 | if (type == NULL || strcmp(type, "cpu") != 0) | |
347 | return 0; | |
348 | ||
12f04f2b | 349 | prop = of_get_flat_dt_prop(node, "ibm,processor-segment-sizes", &size); |
1189be65 PM |
350 | if (prop == NULL) |
351 | return 0; | |
352 | for (; size >= 4; size -= 4, ++prop) { | |
12f04f2b | 353 | if (be32_to_cpu(prop[0]) == 40) { |
1189be65 | 354 | DBG("1T segment support detected\n"); |
faf78829 OH |
355 | |
356 | if (disable_1tb_segments) { | |
357 | DBG("1T segments disabled by command line\n"); | |
358 | break; | |
359 | } | |
360 | ||
44ae3ab3 | 361 | cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT; |
f5534004 | 362 | return 1; |
1189be65 | 363 | } |
1189be65 | 364 | } |
44ae3ab3 | 365 | cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B; |
1189be65 PM |
366 | return 0; |
367 | } | |
368 | ||
b1022fbd AK |
369 | static int __init get_idx_from_shift(unsigned int shift) |
370 | { | |
371 | int idx = -1; | |
372 | ||
373 | switch (shift) { | |
374 | case 0xc: | |
375 | idx = MMU_PAGE_4K; | |
376 | break; | |
377 | case 0x10: | |
378 | idx = MMU_PAGE_64K; | |
379 | break; | |
380 | case 0x14: | |
381 | idx = MMU_PAGE_1M; | |
382 | break; | |
383 | case 0x18: | |
384 | idx = MMU_PAGE_16M; | |
385 | break; | |
386 | case 0x22: | |
387 | idx = MMU_PAGE_16G; | |
388 | break; | |
389 | } | |
390 | return idx; | |
391 | } | |
392 | ||
3c726f8d BH |
393 | static int __init htab_dt_scan_page_sizes(unsigned long node, |
394 | const char *uname, int depth, | |
395 | void *data) | |
396 | { | |
9d0c4dfe RH |
397 | const char *type = of_get_flat_dt_prop(node, "device_type", NULL); |
398 | const __be32 *prop; | |
399 | int size = 0; | |
3c726f8d BH |
400 | |
401 | /* We are scanning "cpu" nodes only */ | |
402 | if (type == NULL || strcmp(type, "cpu") != 0) | |
403 | return 0; | |
404 | ||
12f04f2b | 405 | prop = of_get_flat_dt_prop(node, "ibm,segment-page-sizes", &size); |
9e34992a ME |
406 | if (!prop) |
407 | return 0; | |
408 | ||
409 | pr_info("Page sizes from device-tree:\n"); | |
410 | size /= 4; | |
411 | cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE); | |
412 | while(size > 0) { | |
413 | unsigned int base_shift = be32_to_cpu(prop[0]); | |
414 | unsigned int slbenc = be32_to_cpu(prop[1]); | |
415 | unsigned int lpnum = be32_to_cpu(prop[2]); | |
416 | struct mmu_psize_def *def; | |
417 | int idx, base_idx; | |
418 | ||
419 | size -= 3; prop += 3; | |
420 | base_idx = get_idx_from_shift(base_shift); | |
421 | if (base_idx < 0) { | |
422 | /* skip the pte encoding also */ | |
423 | prop += lpnum * 2; size -= lpnum * 2; | |
424 | continue; | |
425 | } | |
426 | def = &mmu_psize_defs[base_idx]; | |
427 | if (base_idx == MMU_PAGE_16M) | |
428 | cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE; | |
429 | ||
430 | def->shift = base_shift; | |
431 | if (base_shift <= 23) | |
432 | def->avpnm = 0; | |
433 | else | |
434 | def->avpnm = (1 << (base_shift - 23)) - 1; | |
435 | def->sllp = slbenc; | |
436 | /* | |
437 | * We don't know for sure what's up with tlbiel, so | |
438 | * for now we only set it for 4K and 64K pages | |
439 | */ | |
440 | if (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K) | |
441 | def->tlbiel = 1; | |
442 | else | |
443 | def->tlbiel = 0; | |
444 | ||
445 | while (size > 0 && lpnum) { | |
446 | unsigned int shift = be32_to_cpu(prop[0]); | |
447 | int penc = be32_to_cpu(prop[1]); | |
448 | ||
449 | prop += 2; size -= 2; | |
450 | lpnum--; | |
451 | ||
452 | idx = get_idx_from_shift(shift); | |
453 | if (idx < 0) | |
b1022fbd | 454 | continue; |
9e34992a ME |
455 | |
456 | if (penc == -1) | |
457 | pr_err("Invalid penc for base_shift=%d " | |
458 | "shift=%d\n", base_shift, shift); | |
459 | ||
460 | def->penc[idx] = penc; | |
461 | pr_info("base_shift=%d: shift=%d, sllp=0x%04lx," | |
462 | " avpnm=0x%08lx, tlbiel=%d, penc=%d\n", | |
463 | base_shift, shift, def->sllp, | |
464 | def->avpnm, def->tlbiel, def->penc[idx]); | |
1da177e4 | 465 | } |
3c726f8d | 466 | } |
9e34992a ME |
467 | |
468 | return 1; | |
3c726f8d BH |
469 | } |
470 | ||
e16a9c09 | 471 | #ifdef CONFIG_HUGETLB_PAGE |
658013e9 JT |
472 | /* Scan for 16G memory blocks that have been set aside for huge pages |
473 | * and reserve those blocks for 16G huge pages. | |
474 | */ | |
475 | static int __init htab_dt_scan_hugepage_blocks(unsigned long node, | |
476 | const char *uname, int depth, | |
477 | void *data) { | |
9d0c4dfe RH |
478 | const char *type = of_get_flat_dt_prop(node, "device_type", NULL); |
479 | const __be64 *addr_prop; | |
480 | const __be32 *page_count_prop; | |
658013e9 JT |
481 | unsigned int expected_pages; |
482 | long unsigned int phys_addr; | |
483 | long unsigned int block_size; | |
484 | ||
485 | /* We are scanning "memory" nodes only */ | |
486 | if (type == NULL || strcmp(type, "memory") != 0) | |
487 | return 0; | |
488 | ||
489 | /* This property is the log base 2 of the number of virtual pages that | |
490 | * will represent this memory block. */ | |
491 | page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL); | |
492 | if (page_count_prop == NULL) | |
493 | return 0; | |
12f04f2b | 494 | expected_pages = (1 << be32_to_cpu(page_count_prop[0])); |
658013e9 JT |
495 | addr_prop = of_get_flat_dt_prop(node, "reg", NULL); |
496 | if (addr_prop == NULL) | |
497 | return 0; | |
12f04f2b AB |
498 | phys_addr = be64_to_cpu(addr_prop[0]); |
499 | block_size = be64_to_cpu(addr_prop[1]); | |
658013e9 JT |
500 | if (block_size != (16 * GB)) |
501 | return 0; | |
502 | printk(KERN_INFO "Huge page(16GB) memory: " | |
503 | "addr = 0x%lX size = 0x%lX pages = %d\n", | |
504 | phys_addr, block_size, expected_pages); | |
95f72d1e YL |
505 | if (phys_addr + (16 * GB) <= memblock_end_of_DRAM()) { |
506 | memblock_reserve(phys_addr, block_size * expected_pages); | |
4792adba JT |
507 | add_gpage(phys_addr, block_size, expected_pages); |
508 | } | |
658013e9 JT |
509 | return 0; |
510 | } | |
e16a9c09 | 511 | #endif /* CONFIG_HUGETLB_PAGE */ |
658013e9 | 512 | |
b1022fbd AK |
513 | static void mmu_psize_set_default_penc(void) |
514 | { | |
515 | int bpsize, apsize; | |
516 | for (bpsize = 0; bpsize < MMU_PAGE_COUNT; bpsize++) | |
517 | for (apsize = 0; apsize < MMU_PAGE_COUNT; apsize++) | |
518 | mmu_psize_defs[bpsize].penc[apsize] = -1; | |
519 | } | |
520 | ||
9048e648 AG |
521 | #ifdef CONFIG_PPC_64K_PAGES |
522 | ||
523 | static bool might_have_hea(void) | |
524 | { | |
525 | /* | |
526 | * The HEA ethernet adapter requires awareness of the | |
527 | * GX bus. Without that awareness we can easily assume | |
528 | * we will never see an HEA ethernet device. | |
529 | */ | |
530 | #ifdef CONFIG_IBMEBUS | |
2b4e3ad8 | 531 | return !cpu_has_feature(CPU_FTR_ARCH_207S) && |
08bf75ba | 532 | firmware_has_feature(FW_FEATURE_SPLPAR); |
9048e648 AG |
533 | #else |
534 | return false; | |
535 | #endif | |
536 | } | |
537 | ||
538 | #endif /* #ifdef CONFIG_PPC_64K_PAGES */ | |
539 | ||
bacf9cf8 | 540 | static void __init htab_scan_page_sizes(void) |
3c726f8d BH |
541 | { |
542 | int rc; | |
543 | ||
b1022fbd AK |
544 | /* se the invalid penc to -1 */ |
545 | mmu_psize_set_default_penc(); | |
546 | ||
3c726f8d BH |
547 | /* Default to 4K pages only */ |
548 | memcpy(mmu_psize_defs, mmu_psize_defaults_old, | |
549 | sizeof(mmu_psize_defaults_old)); | |
550 | ||
551 | /* | |
552 | * Try to find the available page sizes in the device-tree | |
553 | */ | |
554 | rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL); | |
b8f1b4f8 | 555 | if (rc == 0 && early_mmu_has_feature(MMU_FTR_16M_PAGE)) { |
bacf9cf8 ME |
556 | /* |
557 | * Nothing in the device-tree, but the CPU supports 16M pages, | |
558 | * so let's fallback on a known size list for 16M capable CPUs. | |
559 | */ | |
3c726f8d BH |
560 | memcpy(mmu_psize_defs, mmu_psize_defaults_gp, |
561 | sizeof(mmu_psize_defaults_gp)); | |
bacf9cf8 ME |
562 | } |
563 | ||
564 | #ifdef CONFIG_HUGETLB_PAGE | |
565 | /* Reserve 16G huge page memory sections for huge pages */ | |
566 | of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL); | |
567 | #endif /* CONFIG_HUGETLB_PAGE */ | |
568 | } | |
569 | ||
0eeede0c PM |
570 | /* |
571 | * Fill in the hpte_page_sizes[] array. | |
572 | * We go through the mmu_psize_defs[] array looking for all the | |
573 | * supported base/actual page size combinations. Each combination | |
574 | * has a unique pagesize encoding (penc) value in the low bits of | |
575 | * the LP field of the HPTE. For actual page sizes less than 1MB, | |
576 | * some of the upper LP bits are used for RPN bits, meaning that | |
577 | * we need to fill in several entries in hpte_page_sizes[]. | |
578 | * | |
579 | * In diagrammatic form, with r = RPN bits and z = page size bits: | |
580 | * PTE LP actual page size | |
581 | * rrrr rrrz >=8KB | |
582 | * rrrr rrzz >=16KB | |
583 | * rrrr rzzz >=32KB | |
584 | * rrrr zzzz >=64KB | |
585 | * ... | |
586 | * | |
587 | * The zzzz bits are implementation-specific but are chosen so that | |
588 | * no encoding for a larger page size uses the same value in its | |
589 | * low-order N bits as the encoding for the 2^(12+N) byte page size | |
590 | * (if it exists). | |
591 | */ | |
592 | static void init_hpte_page_sizes(void) | |
593 | { | |
594 | long int ap, bp; | |
595 | long int shift, penc; | |
596 | ||
597 | for (bp = 0; bp < MMU_PAGE_COUNT; ++bp) { | |
598 | if (!mmu_psize_defs[bp].shift) | |
599 | continue; /* not a supported page size */ | |
600 | for (ap = bp; ap < MMU_PAGE_COUNT; ++ap) { | |
601 | penc = mmu_psize_defs[bp].penc[ap]; | |
602 | if (penc == -1) | |
603 | continue; | |
604 | shift = mmu_psize_defs[ap].shift - LP_SHIFT; | |
605 | if (shift <= 0) | |
606 | continue; /* should never happen */ | |
607 | /* | |
608 | * For page sizes less than 1MB, this loop | |
609 | * replicates the entry for all possible values | |
610 | * of the rrrr bits. | |
611 | */ | |
612 | while (penc < (1 << LP_BITS)) { | |
613 | hpte_page_sizes[penc] = (ap << 4) | bp; | |
614 | penc += 1 << shift; | |
615 | } | |
616 | } | |
617 | } | |
618 | } | |
619 | ||
bacf9cf8 ME |
620 | static void __init htab_init_page_sizes(void) |
621 | { | |
0eeede0c PM |
622 | init_hpte_page_sizes(); |
623 | ||
e7df0d88 JK |
624 | if (!debug_pagealloc_enabled()) { |
625 | /* | |
626 | * Pick a size for the linear mapping. Currently, we only | |
627 | * support 16M, 1M and 4K which is the default | |
628 | */ | |
629 | if (mmu_psize_defs[MMU_PAGE_16M].shift) | |
630 | mmu_linear_psize = MMU_PAGE_16M; | |
631 | else if (mmu_psize_defs[MMU_PAGE_1M].shift) | |
632 | mmu_linear_psize = MMU_PAGE_1M; | |
633 | } | |
3c726f8d | 634 | |
bf72aeba | 635 | #ifdef CONFIG_PPC_64K_PAGES |
3c726f8d BH |
636 | /* |
637 | * Pick a size for the ordinary pages. Default is 4K, we support | |
bf72aeba PM |
638 | * 64K for user mappings and vmalloc if supported by the processor. |
639 | * We only use 64k for ioremap if the processor | |
640 | * (and firmware) support cache-inhibited large pages. | |
641 | * If not, we use 4k and set mmu_ci_restrictions so that | |
642 | * hash_page knows to switch processes that use cache-inhibited | |
643 | * mappings to 4k pages. | |
3c726f8d | 644 | */ |
bf72aeba | 645 | if (mmu_psize_defs[MMU_PAGE_64K].shift) { |
3c726f8d | 646 | mmu_virtual_psize = MMU_PAGE_64K; |
bf72aeba | 647 | mmu_vmalloc_psize = MMU_PAGE_64K; |
370a908d BH |
648 | if (mmu_linear_psize == MMU_PAGE_4K) |
649 | mmu_linear_psize = MMU_PAGE_64K; | |
44ae3ab3 | 650 | if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) { |
cfe666b1 | 651 | /* |
9048e648 AG |
652 | * When running on pSeries using 64k pages for ioremap |
653 | * would stop us accessing the HEA ethernet. So if we | |
654 | * have the chance of ever seeing one, stay at 4k. | |
cfe666b1 | 655 | */ |
2b4e3ad8 | 656 | if (!might_have_hea()) |
cfe666b1 PM |
657 | mmu_io_psize = MMU_PAGE_64K; |
658 | } else | |
bf72aeba PM |
659 | mmu_ci_restrictions = 1; |
660 | } | |
370a908d | 661 | #endif /* CONFIG_PPC_64K_PAGES */ |
3c726f8d | 662 | |
cec08e7a BH |
663 | #ifdef CONFIG_SPARSEMEM_VMEMMAP |
664 | /* We try to use 16M pages for vmemmap if that is supported | |
665 | * and we have at least 1G of RAM at boot | |
666 | */ | |
667 | if (mmu_psize_defs[MMU_PAGE_16M].shift && | |
95f72d1e | 668 | memblock_phys_mem_size() >= 0x40000000) |
cec08e7a BH |
669 | mmu_vmemmap_psize = MMU_PAGE_16M; |
670 | else if (mmu_psize_defs[MMU_PAGE_64K].shift) | |
671 | mmu_vmemmap_psize = MMU_PAGE_64K; | |
672 | else | |
673 | mmu_vmemmap_psize = MMU_PAGE_4K; | |
674 | #endif /* CONFIG_SPARSEMEM_VMEMMAP */ | |
675 | ||
bf72aeba | 676 | printk(KERN_DEBUG "Page orders: linear mapping = %d, " |
cec08e7a BH |
677 | "virtual = %d, io = %d" |
678 | #ifdef CONFIG_SPARSEMEM_VMEMMAP | |
679 | ", vmemmap = %d" | |
680 | #endif | |
681 | "\n", | |
3c726f8d | 682 | mmu_psize_defs[mmu_linear_psize].shift, |
bf72aeba | 683 | mmu_psize_defs[mmu_virtual_psize].shift, |
cec08e7a BH |
684 | mmu_psize_defs[mmu_io_psize].shift |
685 | #ifdef CONFIG_SPARSEMEM_VMEMMAP | |
686 | ,mmu_psize_defs[mmu_vmemmap_psize].shift | |
687 | #endif | |
688 | ); | |
3c726f8d BH |
689 | } |
690 | ||
691 | static int __init htab_dt_scan_pftsize(unsigned long node, | |
692 | const char *uname, int depth, | |
693 | void *data) | |
694 | { | |
9d0c4dfe RH |
695 | const char *type = of_get_flat_dt_prop(node, "device_type", NULL); |
696 | const __be32 *prop; | |
3c726f8d BH |
697 | |
698 | /* We are scanning "cpu" nodes only */ | |
699 | if (type == NULL || strcmp(type, "cpu") != 0) | |
700 | return 0; | |
701 | ||
12f04f2b | 702 | prop = of_get_flat_dt_prop(node, "ibm,pft-size", NULL); |
3c726f8d BH |
703 | if (prop != NULL) { |
704 | /* pft_size[0] is the NUMA CEC cookie */ | |
12f04f2b | 705 | ppc64_pft_size = be32_to_cpu(prop[1]); |
3c726f8d | 706 | return 1; |
1da177e4 | 707 | } |
3c726f8d | 708 | return 0; |
1da177e4 LT |
709 | } |
710 | ||
5c3c7ede | 711 | unsigned htab_shift_for_mem_size(unsigned long mem_size) |
3eac8c69 | 712 | { |
5c3c7ede DG |
713 | unsigned memshift = __ilog2(mem_size); |
714 | unsigned pshift = mmu_psize_defs[mmu_virtual_psize].shift; | |
715 | unsigned pteg_shift; | |
716 | ||
717 | /* round mem_size up to next power of 2 */ | |
718 | if ((1UL << memshift) < mem_size) | |
719 | memshift += 1; | |
3eac8c69 | 720 | |
5c3c7ede DG |
721 | /* aim for 2 pages / pteg */ |
722 | pteg_shift = memshift - (pshift + 1); | |
3eac8c69 | 723 | |
5c3c7ede DG |
724 | /* |
725 | * 2^11 PTEGS of 128 bytes each, ie. 2^18 bytes is the minimum htab | |
726 | * size permitted by the architecture. | |
727 | */ | |
728 | return max(pteg_shift + 7, 18U); | |
729 | } | |
730 | ||
731 | static unsigned long __init htab_get_table_size(void) | |
732 | { | |
3c726f8d | 733 | /* If hash size isn't already provided by the platform, we try to |
943ffb58 | 734 | * retrieve it from the device-tree. If it's not there neither, we |
3c726f8d | 735 | * calculate it now based on the total RAM size |
3eac8c69 | 736 | */ |
3c726f8d BH |
737 | if (ppc64_pft_size == 0) |
738 | of_scan_flat_dt(htab_dt_scan_pftsize, NULL); | |
3eac8c69 PM |
739 | if (ppc64_pft_size) |
740 | return 1UL << ppc64_pft_size; | |
741 | ||
5c3c7ede | 742 | return 1UL << htab_shift_for_mem_size(memblock_phys_mem_size()); |
3eac8c69 PM |
743 | } |
744 | ||
54b79248 | 745 | #ifdef CONFIG_MEMORY_HOTPLUG |
a1194097 | 746 | int create_section_mapping(unsigned long start, unsigned long end) |
54b79248 | 747 | { |
1dace6c6 DG |
748 | int rc = htab_bolt_mapping(start, end, __pa(start), |
749 | pgprot_val(PAGE_KERNEL), mmu_linear_psize, | |
750 | mmu_kernel_ssize); | |
751 | ||
752 | if (rc < 0) { | |
753 | int rc2 = htab_remove_mapping(start, end, mmu_linear_psize, | |
754 | mmu_kernel_ssize); | |
755 | BUG_ON(rc2 && (rc2 != -ENOENT)); | |
756 | } | |
757 | return rc; | |
54b79248 | 758 | } |
f8c8803b | 759 | |
52db9b44 | 760 | int remove_section_mapping(unsigned long start, unsigned long end) |
f8c8803b | 761 | { |
abd0a0e7 DG |
762 | int rc = htab_remove_mapping(start, end, mmu_linear_psize, |
763 | mmu_kernel_ssize); | |
764 | WARN_ON(rc < 0); | |
765 | return rc; | |
f8c8803b | 766 | } |
54b79248 MK |
767 | #endif /* CONFIG_MEMORY_HOTPLUG */ |
768 | ||
ad410674 AK |
769 | static void update_hid_for_hash(void) |
770 | { | |
771 | unsigned long hid0; | |
772 | unsigned long rb = 3UL << PPC_BITLSHIFT(53); /* IS = 3 */ | |
773 | ||
774 | asm volatile("ptesync": : :"memory"); | |
775 | /* prs = 0, ric = 2, rs = 0, r = 1 is = 3 */ | |
776 | asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1) | |
777 | : : "r"(rb), "i"(0), "i"(0), "i"(2), "r"(0) : "memory"); | |
778 | asm volatile("eieio; tlbsync; ptesync; isync; slbia": : :"memory"); | |
779 | /* | |
780 | * now switch the HID | |
781 | */ | |
782 | hid0 = mfspr(SPRN_HID0); | |
783 | hid0 &= ~HID0_POWER9_RADIX; | |
784 | mtspr(SPRN_HID0, hid0); | |
785 | asm volatile("isync": : :"memory"); | |
786 | ||
787 | /* Wait for it to happen */ | |
788 | while ((mfspr(SPRN_HID0) & HID0_POWER9_RADIX)) | |
789 | cpu_relax(); | |
790 | } | |
791 | ||
50de596d | 792 | static void __init hash_init_partition_table(phys_addr_t hash_table, |
4b7a3504 | 793 | unsigned long htab_size) |
50de596d AK |
794 | { |
795 | unsigned long ps_field; | |
50de596d AK |
796 | unsigned long patb_size = 1UL << PATB_SIZE_SHIFT; |
797 | ||
798 | /* | |
799 | * slb llp encoding for the page size used in VPM real mode. | |
800 | * We can ignore that for lpid 0 | |
801 | */ | |
802 | ps_field = 0; | |
4b7a3504 | 803 | htab_size = __ilog2(htab_size) - 18; |
50de596d AK |
804 | |
805 | BUILD_BUG_ON_MSG((PATB_SIZE_SHIFT > 24), "Partition table size too large."); | |
806 | partition_tb = __va(memblock_alloc_base(patb_size, patb_size, | |
807 | MEMBLOCK_ALLOC_ANYWHERE)); | |
808 | ||
809 | /* Initialize the Partition Table with no entries */ | |
810 | memset((void *)partition_tb, 0, patb_size); | |
811 | partition_tb->patb0 = cpu_to_be64(ps_field | hash_table | htab_size); | |
812 | /* | |
813 | * FIXME!! This should be done via update_partition table | |
814 | * For now UPRT is 0 for us. | |
815 | */ | |
816 | partition_tb->patb1 = 0; | |
56547411 | 817 | pr_info("Partition table %p\n", partition_tb); |
ad410674 AK |
818 | if (cpu_has_feature(CPU_FTR_POWER9_DD1)) |
819 | update_hid_for_hash(); | |
50de596d AK |
820 | /* |
821 | * update partition table control register, | |
822 | * 64 K size. | |
823 | */ | |
824 | mtspr(SPRN_PTCR, __pa(partition_tb) | (PATB_SIZE_SHIFT - 12)); | |
825 | ||
826 | } | |
827 | ||
757c74d2 | 828 | static void __init htab_initialize(void) |
1da177e4 | 829 | { |
337a7128 | 830 | unsigned long table; |
1da177e4 | 831 | unsigned long pteg_count; |
9e88ba4e | 832 | unsigned long prot; |
5556ecf5 | 833 | unsigned long base = 0, size = 0; |
28be7072 | 834 | struct memblock_region *reg; |
3c726f8d | 835 | |
1da177e4 LT |
836 | DBG(" -> htab_initialize()\n"); |
837 | ||
44ae3ab3 | 838 | if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) { |
1189be65 PM |
839 | mmu_kernel_ssize = MMU_SEGSIZE_1T; |
840 | mmu_highuser_ssize = MMU_SEGSIZE_1T; | |
841 | printk(KERN_INFO "Using 1TB segments\n"); | |
842 | } | |
843 | ||
1da177e4 LT |
844 | /* |
845 | * Calculate the required size of the htab. We want the number of | |
846 | * PTEGs to equal one half the number of real pages. | |
847 | */ | |
3c726f8d | 848 | htab_size_bytes = htab_get_table_size(); |
1da177e4 LT |
849 | pteg_count = htab_size_bytes >> 7; |
850 | ||
1da177e4 LT |
851 | htab_hash_mask = pteg_count - 1; |
852 | ||
5556ecf5 BH |
853 | if (firmware_has_feature(FW_FEATURE_LPAR) || |
854 | firmware_has_feature(FW_FEATURE_PS3_LV1)) { | |
1da177e4 LT |
855 | /* Using a hypervisor which owns the htab */ |
856 | htab_address = NULL; | |
857 | _SDR1 = 0; | |
3ccc00a7 MS |
858 | #ifdef CONFIG_FA_DUMP |
859 | /* | |
860 | * If firmware assisted dump is active firmware preserves | |
861 | * the contents of htab along with entire partition memory. | |
862 | * Clear the htab if firmware assisted dump is active so | |
863 | * that we dont end up using old mappings. | |
864 | */ | |
7025776e BH |
865 | if (is_fadump_active() && mmu_hash_ops.hpte_clear_all) |
866 | mmu_hash_ops.hpte_clear_all(); | |
3ccc00a7 | 867 | #endif |
1da177e4 | 868 | } else { |
5556ecf5 BH |
869 | unsigned long limit = MEMBLOCK_ALLOC_ANYWHERE; |
870 | ||
871 | #ifdef CONFIG_PPC_CELL | |
872 | /* | |
873 | * Cell may require the hash table down low when using the | |
874 | * Axon IOMMU in order to fit the dynamic region over it, see | |
875 | * comments in cell/iommu.c | |
1da177e4 | 876 | */ |
5556ecf5 | 877 | if (fdt_subnode_offset(initial_boot_params, 0, "axon") > 0) { |
31bf1119 | 878 | limit = 0x80000000; |
5556ecf5 BH |
879 | pr_info("Hash table forced below 2G for Axon IOMMU\n"); |
880 | } | |
881 | #endif /* CONFIG_PPC_CELL */ | |
41d824bf | 882 | |
5556ecf5 BH |
883 | table = memblock_alloc_base(htab_size_bytes, htab_size_bytes, |
884 | limit); | |
1da177e4 LT |
885 | |
886 | DBG("Hash table allocated at %lx, size: %lx\n", table, | |
887 | htab_size_bytes); | |
888 | ||
70267a7f | 889 | htab_address = __va(table); |
1da177e4 LT |
890 | |
891 | /* htab absolute addr + encoded htabsize */ | |
4b7a3504 | 892 | _SDR1 = table + __ilog2(htab_size_bytes) - 18; |
1da177e4 LT |
893 | |
894 | /* Initialize the HPT with no entries */ | |
895 | memset((void *)table, 0, htab_size_bytes); | |
799d6046 | 896 | |
50de596d AK |
897 | if (!cpu_has_feature(CPU_FTR_ARCH_300)) |
898 | /* Set SDR1 */ | |
899 | mtspr(SPRN_SDR1, _SDR1); | |
900 | else | |
4b7a3504 | 901 | hash_init_partition_table(table, htab_size_bytes); |
1da177e4 LT |
902 | } |
903 | ||
f5ea64dc | 904 | prot = pgprot_val(PAGE_KERNEL); |
1da177e4 | 905 | |
370a908d | 906 | #ifdef CONFIG_DEBUG_PAGEALLOC |
e7df0d88 JK |
907 | if (debug_pagealloc_enabled()) { |
908 | linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT; | |
909 | linear_map_hash_slots = __va(memblock_alloc_base( | |
910 | linear_map_hash_count, 1, ppc64_rma_size)); | |
911 | memset(linear_map_hash_slots, 0, linear_map_hash_count); | |
912 | } | |
370a908d BH |
913 | #endif /* CONFIG_DEBUG_PAGEALLOC */ |
914 | ||
1da177e4 LT |
915 | /* On U3 based machines, we need to reserve the DART area and |
916 | * _NOT_ map it to avoid cache paradoxes as it's remapped non | |
917 | * cacheable later on | |
918 | */ | |
1da177e4 LT |
919 | |
920 | /* create bolted the linear mapping in the hash table */ | |
28be7072 BH |
921 | for_each_memblock(memory, reg) { |
922 | base = (unsigned long)__va(reg->base); | |
923 | size = reg->size; | |
1da177e4 | 924 | |
5c339919 | 925 | DBG("creating mapping for region: %lx..%lx (prot: %lx)\n", |
9e88ba4e | 926 | base, size, prot); |
1da177e4 | 927 | |
caf80e57 | 928 | BUG_ON(htab_bolt_mapping(base, base + size, __pa(base), |
9e88ba4e | 929 | prot, mmu_linear_psize, mmu_kernel_ssize)); |
e63075a3 BH |
930 | } |
931 | memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE); | |
1da177e4 LT |
932 | |
933 | /* | |
934 | * If we have a memory_limit and we've allocated TCEs then we need to | |
935 | * explicitly map the TCE area at the top of RAM. We also cope with the | |
936 | * case that the TCEs start below memory_limit. | |
937 | * tce_alloc_start/end are 16MB aligned so the mapping should work | |
938 | * for either 4K or 16MB pages. | |
939 | */ | |
940 | if (tce_alloc_start) { | |
b5666f70 ME |
941 | tce_alloc_start = (unsigned long)__va(tce_alloc_start); |
942 | tce_alloc_end = (unsigned long)__va(tce_alloc_end); | |
1da177e4 LT |
943 | |
944 | if (base + size >= tce_alloc_start) | |
945 | tce_alloc_start = base + size + 1; | |
946 | ||
caf80e57 | 947 | BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end, |
bc033b63 | 948 | __pa(tce_alloc_start), prot, |
1189be65 | 949 | mmu_linear_psize, mmu_kernel_ssize)); |
1da177e4 LT |
950 | } |
951 | ||
7d0daae4 | 952 | |
1da177e4 LT |
953 | DBG(" <- htab_initialize()\n"); |
954 | } | |
955 | #undef KB | |
956 | #undef MB | |
1da177e4 | 957 | |
bacf9cf8 ME |
958 | void __init hash__early_init_devtree(void) |
959 | { | |
960 | /* Initialize segment sizes */ | |
961 | of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL); | |
962 | ||
963 | /* Initialize page sizes */ | |
964 | htab_scan_page_sizes(); | |
965 | } | |
966 | ||
756d08d1 | 967 | void __init hash__early_init_mmu(void) |
799d6046 | 968 | { |
bacf9cf8 ME |
969 | htab_init_page_sizes(); |
970 | ||
dd1842a2 AK |
971 | /* |
972 | * initialize page table size | |
973 | */ | |
5ed7ecd0 AK |
974 | __pte_frag_nr = H_PTE_FRAG_NR; |
975 | __pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT; | |
976 | ||
dd1842a2 AK |
977 | __pte_index_size = H_PTE_INDEX_SIZE; |
978 | __pmd_index_size = H_PMD_INDEX_SIZE; | |
979 | __pud_index_size = H_PUD_INDEX_SIZE; | |
980 | __pgd_index_size = H_PGD_INDEX_SIZE; | |
981 | __pmd_cache_index = H_PMD_CACHE_INDEX; | |
982 | __pte_table_size = H_PTE_TABLE_SIZE; | |
983 | __pmd_table_size = H_PMD_TABLE_SIZE; | |
984 | __pud_table_size = H_PUD_TABLE_SIZE; | |
985 | __pgd_table_size = H_PGD_TABLE_SIZE; | |
a2f41eb9 AK |
986 | /* |
987 | * 4k use hugepd format, so for hash set then to | |
988 | * zero | |
989 | */ | |
990 | __pmd_val_bits = 0; | |
991 | __pud_val_bits = 0; | |
992 | __pgd_val_bits = 0; | |
d6a9996e AK |
993 | |
994 | __kernel_virt_start = H_KERN_VIRT_START; | |
995 | __kernel_virt_size = H_KERN_VIRT_SIZE; | |
996 | __vmalloc_start = H_VMALLOC_START; | |
997 | __vmalloc_end = H_VMALLOC_END; | |
998 | vmemmap = (struct page *)H_VMEMMAP_BASE; | |
999 | ioremap_bot = IOREMAP_BASE; | |
1000 | ||
bfa37087 DS |
1001 | #ifdef CONFIG_PCI |
1002 | pci_io_base = ISA_IO_BASE; | |
1003 | #endif | |
1004 | ||
166dd7d3 BH |
1005 | /* Select appropriate backend */ |
1006 | if (firmware_has_feature(FW_FEATURE_PS3_LV1)) | |
1007 | ps3_early_mm_init(); | |
1008 | else if (firmware_has_feature(FW_FEATURE_LPAR)) | |
6364e84e | 1009 | hpte_init_pseries(); |
fbef66f0 | 1010 | else if (IS_ENABLED(CONFIG_PPC_NATIVE)) |
166dd7d3 BH |
1011 | hpte_init_native(); |
1012 | ||
7353644f ME |
1013 | if (!mmu_hash_ops.hpte_insert) |
1014 | panic("hash__early_init_mmu: No MMU hash ops defined!\n"); | |
1015 | ||
757c74d2 | 1016 | /* Initialize the MMU Hash table and create the linear mapping |
376af594 ME |
1017 | * of memory. Has to be done before SLB initialization as this is |
1018 | * currently where the page size encoding is obtained. | |
757c74d2 BH |
1019 | */ |
1020 | htab_initialize(); | |
1021 | ||
56547411 | 1022 | pr_info("Initializing hash mmu with SLB\n"); |
376af594 | 1023 | /* Initialize SLB management */ |
13b3d13b | 1024 | slb_initialize(); |
757c74d2 BH |
1025 | } |
1026 | ||
1027 | #ifdef CONFIG_SMP | |
756d08d1 | 1028 | void hash__early_init_mmu_secondary(void) |
757c74d2 BH |
1029 | { |
1030 | /* Initialize hash table for that CPU */ | |
b5dcc609 | 1031 | if (!firmware_has_feature(FW_FEATURE_LPAR)) { |
cac4a185 AK |
1032 | |
1033 | if (cpu_has_feature(CPU_FTR_POWER9_DD1)) | |
1034 | update_hid_for_hash(); | |
1035 | ||
b5dcc609 AK |
1036 | if (!cpu_has_feature(CPU_FTR_ARCH_300)) |
1037 | mtspr(SPRN_SDR1, _SDR1); | |
1038 | else | |
1039 | mtspr(SPRN_PTCR, | |
1040 | __pa(partition_tb) | (PATB_SIZE_SHIFT - 12)); | |
1041 | } | |
376af594 | 1042 | /* Initialize SLB */ |
13b3d13b | 1043 | slb_initialize(); |
799d6046 | 1044 | } |
757c74d2 | 1045 | #endif /* CONFIG_SMP */ |
799d6046 | 1046 | |
1da177e4 LT |
1047 | /* |
1048 | * Called by asm hashtable.S for doing lazy icache flush | |
1049 | */ | |
1050 | unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap) | |
1051 | { | |
1052 | struct page *page; | |
1053 | ||
76c8e25b BH |
1054 | if (!pfn_valid(pte_pfn(pte))) |
1055 | return pp; | |
1056 | ||
1da177e4 LT |
1057 | page = pte_page(pte); |
1058 | ||
1059 | /* page is dirty */ | |
1060 | if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) { | |
1061 | if (trap == 0x400) { | |
0895ecda | 1062 | flush_dcache_icache_page(page); |
1da177e4 LT |
1063 | set_bit(PG_arch_1, &page->flags); |
1064 | } else | |
3c726f8d | 1065 | pp |= HPTE_R_N; |
1da177e4 LT |
1066 | } |
1067 | return pp; | |
1068 | } | |
1069 | ||
3a8247cc | 1070 | #ifdef CONFIG_PPC_MM_SLICES |
e51df2c1 | 1071 | static unsigned int get_paca_psize(unsigned long addr) |
3a8247cc | 1072 | { |
7aa0727f AK |
1073 | u64 lpsizes; |
1074 | unsigned char *hpsizes; | |
1075 | unsigned long index, mask_index; | |
3a8247cc PM |
1076 | |
1077 | if (addr < SLICE_LOW_TOP) { | |
2fc251a8 | 1078 | lpsizes = get_paca()->mm_ctx_low_slices_psize; |
3a8247cc | 1079 | index = GET_LOW_SLICE_INDEX(addr); |
7aa0727f | 1080 | return (lpsizes >> (index * 4)) & 0xF; |
3a8247cc | 1081 | } |
2fc251a8 | 1082 | hpsizes = get_paca()->mm_ctx_high_slices_psize; |
7aa0727f AK |
1083 | index = GET_HIGH_SLICE_INDEX(addr); |
1084 | mask_index = index & 0x1; | |
1085 | return (hpsizes[index >> 1] >> (mask_index * 4)) & 0xF; | |
3a8247cc PM |
1086 | } |
1087 | ||
1088 | #else | |
1089 | unsigned int get_paca_psize(unsigned long addr) | |
1090 | { | |
c33e54fa | 1091 | return get_paca()->mm_ctx_user_psize; |
3a8247cc PM |
1092 | } |
1093 | #endif | |
1094 | ||
721151d0 PM |
1095 | /* |
1096 | * Demote a segment to using 4k pages. | |
1097 | * For now this makes the whole process use 4k pages. | |
1098 | */ | |
721151d0 | 1099 | #ifdef CONFIG_PPC_64K_PAGES |
fa28237c | 1100 | void demote_segment_4k(struct mm_struct *mm, unsigned long addr) |
16f1c746 | 1101 | { |
3a8247cc | 1102 | if (get_slice_psize(mm, addr) == MMU_PAGE_4K) |
721151d0 | 1103 | return; |
3a8247cc | 1104 | slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K); |
be3ebfe8 | 1105 | copro_flush_all_slbs(mm); |
a1dca346 | 1106 | if ((get_paca_psize(addr) != MMU_PAGE_4K) && (current->mm == mm)) { |
c395465d MN |
1107 | |
1108 | copy_mm_to_paca(&mm->context); | |
fa28237c PM |
1109 | slb_flush_and_rebolt(); |
1110 | } | |
721151d0 | 1111 | } |
16f1c746 | 1112 | #endif /* CONFIG_PPC_64K_PAGES */ |
721151d0 | 1113 | |
fa28237c PM |
1114 | #ifdef CONFIG_PPC_SUBPAGE_PROT |
1115 | /* | |
1116 | * This looks up a 2-bit protection code for a 4k subpage of a 64k page. | |
1117 | * Userspace sets the subpage permissions using the subpage_prot system call. | |
1118 | * | |
1119 | * Result is 0: full permissions, _PAGE_RW: read-only, | |
73a1441a | 1120 | * _PAGE_RWX: no access. |
fa28237c | 1121 | */ |
d28513bc | 1122 | static int subpage_protection(struct mm_struct *mm, unsigned long ea) |
fa28237c | 1123 | { |
d28513bc | 1124 | struct subpage_prot_table *spt = &mm->context.spt; |
fa28237c PM |
1125 | u32 spp = 0; |
1126 | u32 **sbpm, *sbpp; | |
1127 | ||
1128 | if (ea >= spt->maxaddr) | |
1129 | return 0; | |
b0d436c7 | 1130 | if (ea < 0x100000000UL) { |
fa28237c PM |
1131 | /* addresses below 4GB use spt->low_prot */ |
1132 | sbpm = spt->low_prot; | |
1133 | } else { | |
1134 | sbpm = spt->protptrs[ea >> SBP_L3_SHIFT]; | |
1135 | if (!sbpm) | |
1136 | return 0; | |
1137 | } | |
1138 | sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)]; | |
1139 | if (!sbpp) | |
1140 | return 0; | |
1141 | spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)]; | |
1142 | ||
1143 | /* extract 2-bit bitfield for this 4k subpage */ | |
1144 | spp >>= 30 - 2 * ((ea >> 12) & 0xf); | |
1145 | ||
73a1441a AK |
1146 | /* |
1147 | * 0 -> full premission | |
1148 | * 1 -> Read only | |
1149 | * 2 -> no access. | |
1150 | * We return the flag that need to be cleared. | |
1151 | */ | |
1152 | spp = ((spp & 2) ? _PAGE_RWX : 0) | ((spp & 1) ? _PAGE_WRITE : 0); | |
fa28237c PM |
1153 | return spp; |
1154 | } | |
1155 | ||
1156 | #else /* CONFIG_PPC_SUBPAGE_PROT */ | |
d28513bc | 1157 | static inline int subpage_protection(struct mm_struct *mm, unsigned long ea) |
fa28237c PM |
1158 | { |
1159 | return 0; | |
1160 | } | |
1161 | #endif | |
1162 | ||
4b8692c0 BH |
1163 | void hash_failure_debug(unsigned long ea, unsigned long access, |
1164 | unsigned long vsid, unsigned long trap, | |
d8139ebf | 1165 | int ssize, int psize, int lpsize, unsigned long pte) |
4b8692c0 BH |
1166 | { |
1167 | if (!printk_ratelimit()) | |
1168 | return; | |
1169 | pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n", | |
1170 | ea, access, current->comm); | |
d8139ebf AK |
1171 | pr_info(" trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n", |
1172 | trap, vsid, ssize, psize, lpsize, pte); | |
4b8692c0 BH |
1173 | } |
1174 | ||
09567e7f ME |
1175 | static void check_paca_psize(unsigned long ea, struct mm_struct *mm, |
1176 | int psize, bool user_region) | |
1177 | { | |
1178 | if (user_region) { | |
1179 | if (psize != get_paca_psize(ea)) { | |
c395465d | 1180 | copy_mm_to_paca(&mm->context); |
09567e7f ME |
1181 | slb_flush_and_rebolt(); |
1182 | } | |
1183 | } else if (get_paca()->vmalloc_sllp != | |
1184 | mmu_psize_defs[mmu_vmalloc_psize].sllp) { | |
1185 | get_paca()->vmalloc_sllp = | |
1186 | mmu_psize_defs[mmu_vmalloc_psize].sllp; | |
1187 | slb_vmalloc_update(); | |
1188 | } | |
1189 | } | |
1190 | ||
1da177e4 LT |
1191 | /* Result code is: |
1192 | * 0 - handled | |
1193 | * 1 - normal page fault | |
1194 | * -1 - critical hash insertion error | |
fa28237c | 1195 | * -2 - access not permitted by subpage protection mechanism |
1da177e4 | 1196 | */ |
aefa5688 AK |
1197 | int hash_page_mm(struct mm_struct *mm, unsigned long ea, |
1198 | unsigned long access, unsigned long trap, | |
1199 | unsigned long flags) | |
1da177e4 | 1200 | { |
891121e6 | 1201 | bool is_thp; |
ba12eede | 1202 | enum ctx_state prev_state = exception_enter(); |
a1128f8f | 1203 | pgd_t *pgdir; |
1da177e4 | 1204 | unsigned long vsid; |
1da177e4 | 1205 | pte_t *ptep; |
a4fe3ce7 | 1206 | unsigned hugeshift; |
56aa4129 | 1207 | const struct cpumask *tmp; |
aefa5688 | 1208 | int rc, user_region = 0; |
1189be65 | 1209 | int psize, ssize; |
1da177e4 | 1210 | |
3c726f8d BH |
1211 | DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n", |
1212 | ea, access, trap); | |
cfcb3d80 | 1213 | trace_hash_fault(ea, access, trap); |
1f8d419e | 1214 | |
3c726f8d | 1215 | /* Get region & vsid */ |
1da177e4 LT |
1216 | switch (REGION_ID(ea)) { |
1217 | case USER_REGION_ID: | |
1218 | user_region = 1; | |
3c726f8d BH |
1219 | if (! mm) { |
1220 | DBG_LOW(" user region with no mm !\n"); | |
ba12eede LZ |
1221 | rc = 1; |
1222 | goto bail; | |
3c726f8d | 1223 | } |
16c2d476 | 1224 | psize = get_slice_psize(mm, ea); |
1189be65 PM |
1225 | ssize = user_segment_size(ea); |
1226 | vsid = get_vsid(mm->context.id, ea, ssize); | |
1da177e4 | 1227 | break; |
1da177e4 | 1228 | case VMALLOC_REGION_ID: |
1189be65 | 1229 | vsid = get_kernel_vsid(ea, mmu_kernel_ssize); |
bf72aeba PM |
1230 | if (ea < VMALLOC_END) |
1231 | psize = mmu_vmalloc_psize; | |
1232 | else | |
1233 | psize = mmu_io_psize; | |
1189be65 | 1234 | ssize = mmu_kernel_ssize; |
1da177e4 | 1235 | break; |
1da177e4 LT |
1236 | default: |
1237 | /* Not a valid range | |
1238 | * Send the problem up to do_page_fault | |
1239 | */ | |
ba12eede LZ |
1240 | rc = 1; |
1241 | goto bail; | |
1da177e4 | 1242 | } |
3c726f8d | 1243 | DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid); |
1da177e4 | 1244 | |
c60ac569 AK |
1245 | /* Bad address. */ |
1246 | if (!vsid) { | |
1247 | DBG_LOW("Bad address!\n"); | |
ba12eede LZ |
1248 | rc = 1; |
1249 | goto bail; | |
c60ac569 | 1250 | } |
3c726f8d | 1251 | /* Get pgdir */ |
1da177e4 | 1252 | pgdir = mm->pgd; |
ba12eede LZ |
1253 | if (pgdir == NULL) { |
1254 | rc = 1; | |
1255 | goto bail; | |
1256 | } | |
1da177e4 | 1257 | |
3c726f8d | 1258 | /* Check CPU locality */ |
56aa4129 RR |
1259 | tmp = cpumask_of(smp_processor_id()); |
1260 | if (user_region && cpumask_equal(mm_cpumask(mm), tmp)) | |
aefa5688 | 1261 | flags |= HPTE_LOCAL_UPDATE; |
1da177e4 | 1262 | |
16c2d476 | 1263 | #ifndef CONFIG_PPC_64K_PAGES |
a4fe3ce7 DG |
1264 | /* If we use 4K pages and our psize is not 4K, then we might |
1265 | * be hitting a special driver mapping, and need to align the | |
1266 | * address before we fetch the PTE. | |
1267 | * | |
1268 | * It could also be a hugepage mapping, in which case this is | |
1269 | * not necessary, but it's not harmful, either. | |
16c2d476 BH |
1270 | */ |
1271 | if (psize != MMU_PAGE_4K) | |
1272 | ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1); | |
1273 | #endif /* CONFIG_PPC_64K_PAGES */ | |
1274 | ||
3c726f8d | 1275 | /* Get PTE and page size from page tables */ |
891121e6 | 1276 | ptep = __find_linux_pte_or_hugepte(pgdir, ea, &is_thp, &hugeshift); |
3c726f8d BH |
1277 | if (ptep == NULL || !pte_present(*ptep)) { |
1278 | DBG_LOW(" no PTE !\n"); | |
ba12eede LZ |
1279 | rc = 1; |
1280 | goto bail; | |
3c726f8d BH |
1281 | } |
1282 | ||
ca91e6c0 BH |
1283 | /* Add _PAGE_PRESENT to the required access perm */ |
1284 | access |= _PAGE_PRESENT; | |
1285 | ||
1286 | /* Pre-check access permissions (will be re-checked atomically | |
1287 | * in __hash_page_XX but this pre-check is a fast path | |
1288 | */ | |
ac29c640 | 1289 | if (!check_pte_access(access, pte_val(*ptep))) { |
ca91e6c0 | 1290 | DBG_LOW(" no access !\n"); |
ba12eede LZ |
1291 | rc = 1; |
1292 | goto bail; | |
ca91e6c0 BH |
1293 | } |
1294 | ||
ba12eede | 1295 | if (hugeshift) { |
891121e6 | 1296 | if (is_thp) |
6d492ecc | 1297 | rc = __hash_page_thp(ea, access, vsid, (pmd_t *)ptep, |
aefa5688 | 1298 | trap, flags, ssize, psize); |
6d492ecc AK |
1299 | #ifdef CONFIG_HUGETLB_PAGE |
1300 | else | |
1301 | rc = __hash_page_huge(ea, access, vsid, ptep, trap, | |
aefa5688 | 1302 | flags, ssize, hugeshift, psize); |
6d492ecc AK |
1303 | #else |
1304 | else { | |
1305 | /* | |
1306 | * if we have hugeshift, and is not transhuge with | |
1307 | * hugetlb disabled, something is really wrong. | |
1308 | */ | |
1309 | rc = 1; | |
1310 | WARN_ON(1); | |
1311 | } | |
1312 | #endif | |
a1dca346 IM |
1313 | if (current->mm == mm) |
1314 | check_paca_psize(ea, mm, psize, user_region); | |
09567e7f | 1315 | |
ba12eede LZ |
1316 | goto bail; |
1317 | } | |
a4fe3ce7 | 1318 | |
3c726f8d BH |
1319 | #ifndef CONFIG_PPC_64K_PAGES |
1320 | DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep)); | |
1321 | #else | |
1322 | DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep), | |
1323 | pte_val(*(ptep + PTRS_PER_PTE))); | |
1324 | #endif | |
3c726f8d | 1325 | /* Do actual hashing */ |
16c2d476 | 1326 | #ifdef CONFIG_PPC_64K_PAGES |
945537df AK |
1327 | /* If H_PAGE_4K_PFN is set, make sure this is a 4k segment */ |
1328 | if ((pte_val(*ptep) & H_PAGE_4K_PFN) && psize == MMU_PAGE_64K) { | |
721151d0 PM |
1329 | demote_segment_4k(mm, ea); |
1330 | psize = MMU_PAGE_4K; | |
1331 | } | |
1332 | ||
16f1c746 BH |
1333 | /* If this PTE is non-cacheable and we have restrictions on |
1334 | * using non cacheable large pages, then we switch to 4k | |
1335 | */ | |
30bda41a | 1336 | if (mmu_ci_restrictions && psize == MMU_PAGE_64K && pte_ci(*ptep)) { |
16f1c746 BH |
1337 | if (user_region) { |
1338 | demote_segment_4k(mm, ea); | |
1339 | psize = MMU_PAGE_4K; | |
1340 | } else if (ea < VMALLOC_END) { | |
1341 | /* | |
1342 | * some driver did a non-cacheable mapping | |
1343 | * in vmalloc space, so switch vmalloc | |
1344 | * to 4k pages | |
1345 | */ | |
1346 | printk(KERN_ALERT "Reducing vmalloc segment " | |
1347 | "to 4kB pages because of " | |
1348 | "non-cacheable mapping\n"); | |
1349 | psize = mmu_vmalloc_psize = MMU_PAGE_4K; | |
be3ebfe8 | 1350 | copro_flush_all_slbs(mm); |
bf72aeba | 1351 | } |
16f1c746 | 1352 | } |
09567e7f | 1353 | |
0863d7f2 AK |
1354 | #endif /* CONFIG_PPC_64K_PAGES */ |
1355 | ||
a1dca346 IM |
1356 | if (current->mm == mm) |
1357 | check_paca_psize(ea, mm, psize, user_region); | |
16f1c746 | 1358 | |
73b341ef | 1359 | #ifdef CONFIG_PPC_64K_PAGES |
bf72aeba | 1360 | if (psize == MMU_PAGE_64K) |
aefa5688 AK |
1361 | rc = __hash_page_64K(ea, access, vsid, ptep, trap, |
1362 | flags, ssize); | |
3c726f8d | 1363 | else |
73b341ef | 1364 | #endif /* CONFIG_PPC_64K_PAGES */ |
fa28237c | 1365 | { |
a1128f8f | 1366 | int spp = subpage_protection(mm, ea); |
fa28237c PM |
1367 | if (access & spp) |
1368 | rc = -2; | |
1369 | else | |
1370 | rc = __hash_page_4K(ea, access, vsid, ptep, trap, | |
aefa5688 | 1371 | flags, ssize, spp); |
fa28237c | 1372 | } |
3c726f8d | 1373 | |
4b8692c0 BH |
1374 | /* Dump some info in case of hash insertion failure, they should |
1375 | * never happen so it is really useful to know if/when they do | |
1376 | */ | |
1377 | if (rc == -1) | |
1378 | hash_failure_debug(ea, access, vsid, trap, ssize, psize, | |
d8139ebf | 1379 | psize, pte_val(*ptep)); |
3c726f8d BH |
1380 | #ifndef CONFIG_PPC_64K_PAGES |
1381 | DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep)); | |
1382 | #else | |
1383 | DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep), | |
1384 | pte_val(*(ptep + PTRS_PER_PTE))); | |
1385 | #endif | |
1386 | DBG_LOW(" -> rc=%d\n", rc); | |
ba12eede LZ |
1387 | |
1388 | bail: | |
1389 | exception_exit(prev_state); | |
3c726f8d | 1390 | return rc; |
1da177e4 | 1391 | } |
a1dca346 IM |
1392 | EXPORT_SYMBOL_GPL(hash_page_mm); |
1393 | ||
aefa5688 AK |
1394 | int hash_page(unsigned long ea, unsigned long access, unsigned long trap, |
1395 | unsigned long dsisr) | |
a1dca346 | 1396 | { |
aefa5688 | 1397 | unsigned long flags = 0; |
a1dca346 IM |
1398 | struct mm_struct *mm = current->mm; |
1399 | ||
1400 | if (REGION_ID(ea) == VMALLOC_REGION_ID) | |
1401 | mm = &init_mm; | |
1402 | ||
aefa5688 AK |
1403 | if (dsisr & DSISR_NOHPTE) |
1404 | flags |= HPTE_NOHPTE_UPDATE; | |
1405 | ||
1406 | return hash_page_mm(mm, ea, access, trap, flags); | |
a1dca346 | 1407 | } |
67207b96 | 1408 | EXPORT_SYMBOL_GPL(hash_page); |
1da177e4 | 1409 | |
106713a1 AK |
1410 | int __hash_page(unsigned long ea, unsigned long msr, unsigned long trap, |
1411 | unsigned long dsisr) | |
1412 | { | |
c7d54842 | 1413 | unsigned long access = _PAGE_PRESENT | _PAGE_READ; |
106713a1 AK |
1414 | unsigned long flags = 0; |
1415 | struct mm_struct *mm = current->mm; | |
1416 | ||
1417 | if (REGION_ID(ea) == VMALLOC_REGION_ID) | |
1418 | mm = &init_mm; | |
1419 | ||
1420 | if (dsisr & DSISR_NOHPTE) | |
1421 | flags |= HPTE_NOHPTE_UPDATE; | |
1422 | ||
1423 | if (dsisr & DSISR_ISSTORE) | |
c7d54842 | 1424 | access |= _PAGE_WRITE; |
106713a1 | 1425 | /* |
ac29c640 AK |
1426 | * We set _PAGE_PRIVILEGED only when |
1427 | * kernel mode access kernel space. | |
1428 | * | |
1429 | * _PAGE_PRIVILEGED is NOT set | |
1430 | * 1) when kernel mode access user space | |
1431 | * 2) user space access kernel space. | |
106713a1 | 1432 | */ |
ac29c640 | 1433 | access |= _PAGE_PRIVILEGED; |
106713a1 | 1434 | if ((msr & MSR_PR) || (REGION_ID(ea) == USER_REGION_ID)) |
ac29c640 | 1435 | access &= ~_PAGE_PRIVILEGED; |
106713a1 AK |
1436 | |
1437 | if (trap == 0x400) | |
1438 | access |= _PAGE_EXEC; | |
1439 | ||
1440 | return hash_page_mm(mm, ea, access, trap, flags); | |
1441 | } | |
1442 | ||
8bbc9b7b ME |
1443 | #ifdef CONFIG_PPC_MM_SLICES |
1444 | static bool should_hash_preload(struct mm_struct *mm, unsigned long ea) | |
1445 | { | |
aac55d75 ME |
1446 | int psize = get_slice_psize(mm, ea); |
1447 | ||
8bbc9b7b | 1448 | /* We only prefault standard pages for now */ |
aac55d75 ME |
1449 | if (unlikely(psize != mm->context.user_psize)) |
1450 | return false; | |
1451 | ||
1452 | /* | |
1453 | * Don't prefault if subpage protection is enabled for the EA. | |
1454 | */ | |
1455 | if (unlikely((psize == MMU_PAGE_4K) && subpage_protection(mm, ea))) | |
8bbc9b7b ME |
1456 | return false; |
1457 | ||
1458 | return true; | |
1459 | } | |
1460 | #else | |
1461 | static bool should_hash_preload(struct mm_struct *mm, unsigned long ea) | |
1462 | { | |
1463 | return true; | |
1464 | } | |
1465 | #endif | |
1466 | ||
3c726f8d BH |
1467 | void hash_preload(struct mm_struct *mm, unsigned long ea, |
1468 | unsigned long access, unsigned long trap) | |
1da177e4 | 1469 | { |
12bc9f6f | 1470 | int hugepage_shift; |
3c726f8d | 1471 | unsigned long vsid; |
0b97fee0 | 1472 | pgd_t *pgdir; |
3c726f8d | 1473 | pte_t *ptep; |
3c726f8d | 1474 | unsigned long flags; |
aefa5688 | 1475 | int rc, ssize, update_flags = 0; |
3c726f8d | 1476 | |
d0f13e3c BH |
1477 | BUG_ON(REGION_ID(ea) != USER_REGION_ID); |
1478 | ||
8bbc9b7b | 1479 | if (!should_hash_preload(mm, ea)) |
3c726f8d BH |
1480 | return; |
1481 | ||
1482 | DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx," | |
1483 | " trap=%lx\n", mm, mm->pgd, ea, access, trap); | |
1da177e4 | 1484 | |
16f1c746 | 1485 | /* Get Linux PTE if available */ |
3c726f8d BH |
1486 | pgdir = mm->pgd; |
1487 | if (pgdir == NULL) | |
1488 | return; | |
0ac52dd7 AK |
1489 | |
1490 | /* Get VSID */ | |
1491 | ssize = user_segment_size(ea); | |
1492 | vsid = get_vsid(mm->context.id, ea, ssize); | |
1493 | if (!vsid) | |
1494 | return; | |
1495 | /* | |
1496 | * Hash doesn't like irqs. Walking linux page table with irq disabled | |
1497 | * saves us from holding multiple locks. | |
1498 | */ | |
1499 | local_irq_save(flags); | |
1500 | ||
12bc9f6f AK |
1501 | /* |
1502 | * THP pages use update_mmu_cache_pmd. We don't do | |
1503 | * hash preload there. Hence can ignore THP here | |
1504 | */ | |
891121e6 | 1505 | ptep = find_linux_pte_or_hugepte(pgdir, ea, NULL, &hugepage_shift); |
3c726f8d | 1506 | if (!ptep) |
0ac52dd7 | 1507 | goto out_exit; |
16f1c746 | 1508 | |
12bc9f6f | 1509 | WARN_ON(hugepage_shift); |
16f1c746 | 1510 | #ifdef CONFIG_PPC_64K_PAGES |
945537df | 1511 | /* If either H_PAGE_4K_PFN or cache inhibited is set (and we are on |
16f1c746 BH |
1512 | * a 64K kernel), then we don't preload, hash_page() will take |
1513 | * care of it once we actually try to access the page. | |
1514 | * That way we don't have to duplicate all of the logic for segment | |
1515 | * page size demotion here | |
1516 | */ | |
945537df | 1517 | if ((pte_val(*ptep) & H_PAGE_4K_PFN) || pte_ci(*ptep)) |
0ac52dd7 | 1518 | goto out_exit; |
16f1c746 BH |
1519 | #endif /* CONFIG_PPC_64K_PAGES */ |
1520 | ||
16c2d476 | 1521 | /* Is that local to this CPU ? */ |
56aa4129 | 1522 | if (cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id()))) |
aefa5688 | 1523 | update_flags |= HPTE_LOCAL_UPDATE; |
16c2d476 BH |
1524 | |
1525 | /* Hash it in */ | |
73b341ef | 1526 | #ifdef CONFIG_PPC_64K_PAGES |
bf72aeba | 1527 | if (mm->context.user_psize == MMU_PAGE_64K) |
aefa5688 AK |
1528 | rc = __hash_page_64K(ea, access, vsid, ptep, trap, |
1529 | update_flags, ssize); | |
1da177e4 | 1530 | else |
73b341ef | 1531 | #endif /* CONFIG_PPC_64K_PAGES */ |
aefa5688 AK |
1532 | rc = __hash_page_4K(ea, access, vsid, ptep, trap, update_flags, |
1533 | ssize, subpage_protection(mm, ea)); | |
4b8692c0 BH |
1534 | |
1535 | /* Dump some info in case of hash insertion failure, they should | |
1536 | * never happen so it is really useful to know if/when they do | |
1537 | */ | |
1538 | if (rc == -1) | |
1539 | hash_failure_debug(ea, access, vsid, trap, ssize, | |
d8139ebf AK |
1540 | mm->context.user_psize, |
1541 | mm->context.user_psize, | |
1542 | pte_val(*ptep)); | |
0ac52dd7 | 1543 | out_exit: |
3c726f8d BH |
1544 | local_irq_restore(flags); |
1545 | } | |
1546 | ||
f1a55ce0 RT |
1547 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1548 | static inline void tm_flush_hash_page(int local) | |
1549 | { | |
1550 | /* | |
1551 | * Transactions are not aborted by tlbiel, only tlbie. Without, syncing a | |
1552 | * page back to a block device w/PIO could pick up transactional data | |
1553 | * (bad!) so we force an abort here. Before the sync the page will be | |
1554 | * made read-only, which will flush_hash_page. BIG ISSUE here: if the | |
1555 | * kernel uses a page from userspace without unmapping it first, it may | |
1556 | * see the speculated version. | |
1557 | */ | |
1558 | if (local && cpu_has_feature(CPU_FTR_TM) && current->thread.regs && | |
1559 | MSR_TM_ACTIVE(current->thread.regs->msr)) { | |
1560 | tm_enable(); | |
1561 | tm_abort(TM_CAUSE_TLBI); | |
1562 | } | |
1563 | } | |
1564 | #else | |
1565 | static inline void tm_flush_hash_page(int local) | |
1566 | { | |
1567 | } | |
1568 | #endif | |
1569 | ||
f6ab0b92 BH |
1570 | /* WARNING: This is called from hash_low_64.S, if you change this prototype, |
1571 | * do not forget to update the assembly call site ! | |
1572 | */ | |
5524a27d | 1573 | void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize, |
aefa5688 | 1574 | unsigned long flags) |
3c726f8d BH |
1575 | { |
1576 | unsigned long hash, index, shift, hidx, slot; | |
aefa5688 | 1577 | int local = flags & HPTE_LOCAL_UPDATE; |
3c726f8d | 1578 | |
5524a27d AK |
1579 | DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn); |
1580 | pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) { | |
1581 | hash = hpt_hash(vpn, shift, ssize); | |
3c726f8d BH |
1582 | hidx = __rpte_to_hidx(pte, index); |
1583 | if (hidx & _PTEIDX_SECONDARY) | |
1584 | hash = ~hash; | |
1585 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
1586 | slot += hidx & _PTEIDX_GROUP_IX; | |
5c339919 | 1587 | DBG_LOW(" sub %ld: hash=%lx, hidx=%lx\n", index, slot, hidx); |
db3d8534 AK |
1588 | /* |
1589 | * We use same base page size and actual psize, because we don't | |
1590 | * use these functions for hugepage | |
1591 | */ | |
7025776e BH |
1592 | mmu_hash_ops.hpte_invalidate(slot, vpn, psize, psize, |
1593 | ssize, local); | |
3c726f8d | 1594 | } pte_iterate_hashed_end(); |
bc2a9408 | 1595 | |
f1a55ce0 | 1596 | tm_flush_hash_page(local); |
1da177e4 LT |
1597 | } |
1598 | ||
f1581bf1 AK |
1599 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
1600 | void flush_hash_hugepage(unsigned long vsid, unsigned long addr, | |
aefa5688 AK |
1601 | pmd_t *pmdp, unsigned int psize, int ssize, |
1602 | unsigned long flags) | |
f1581bf1 AK |
1603 | { |
1604 | int i, max_hpte_count, valid; | |
1605 | unsigned long s_addr; | |
1606 | unsigned char *hpte_slot_array; | |
1607 | unsigned long hidx, shift, vpn, hash, slot; | |
aefa5688 | 1608 | int local = flags & HPTE_LOCAL_UPDATE; |
f1581bf1 AK |
1609 | |
1610 | s_addr = addr & HPAGE_PMD_MASK; | |
1611 | hpte_slot_array = get_hpte_slot_array(pmdp); | |
1612 | /* | |
1613 | * IF we try to do a HUGE PTE update after a withdraw is done. | |
1614 | * we will find the below NULL. This happens when we do | |
1615 | * split_huge_page_pmd | |
1616 | */ | |
1617 | if (!hpte_slot_array) | |
1618 | return; | |
1619 | ||
7025776e BH |
1620 | if (mmu_hash_ops.hugepage_invalidate) { |
1621 | mmu_hash_ops.hugepage_invalidate(vsid, s_addr, hpte_slot_array, | |
1622 | psize, ssize, local); | |
d557b098 AK |
1623 | goto tm_abort; |
1624 | } | |
f1581bf1 AK |
1625 | /* |
1626 | * No bluk hpte removal support, invalidate each entry | |
1627 | */ | |
1628 | shift = mmu_psize_defs[psize].shift; | |
1629 | max_hpte_count = HPAGE_PMD_SIZE >> shift; | |
1630 | for (i = 0; i < max_hpte_count; i++) { | |
1631 | /* | |
1632 | * 8 bits per each hpte entries | |
1633 | * 000| [ secondary group (one bit) | hidx (3 bits) | valid bit] | |
1634 | */ | |
1635 | valid = hpte_valid(hpte_slot_array, i); | |
1636 | if (!valid) | |
1637 | continue; | |
1638 | hidx = hpte_hash_index(hpte_slot_array, i); | |
1639 | ||
1640 | /* get the vpn */ | |
1641 | addr = s_addr + (i * (1ul << shift)); | |
1642 | vpn = hpt_vpn(addr, vsid, ssize); | |
1643 | hash = hpt_hash(vpn, shift, ssize); | |
1644 | if (hidx & _PTEIDX_SECONDARY) | |
1645 | hash = ~hash; | |
1646 | ||
1647 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
1648 | slot += hidx & _PTEIDX_GROUP_IX; | |
7025776e BH |
1649 | mmu_hash_ops.hpte_invalidate(slot, vpn, psize, |
1650 | MMU_PAGE_16M, ssize, local); | |
d557b098 AK |
1651 | } |
1652 | tm_abort: | |
f1a55ce0 | 1653 | tm_flush_hash_page(local); |
f1581bf1 AK |
1654 | } |
1655 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ | |
1656 | ||
61b1a942 | 1657 | void flush_hash_range(unsigned long number, int local) |
1da177e4 | 1658 | { |
7025776e BH |
1659 | if (mmu_hash_ops.flush_hash_range) |
1660 | mmu_hash_ops.flush_hash_range(number, local); | |
3c726f8d | 1661 | else { |
1da177e4 | 1662 | int i; |
61b1a942 | 1663 | struct ppc64_tlb_batch *batch = |
69111bac | 1664 | this_cpu_ptr(&ppc64_tlb_batch); |
1da177e4 LT |
1665 | |
1666 | for (i = 0; i < number; i++) | |
5524a27d | 1667 | flush_hash_page(batch->vpn[i], batch->pte[i], |
1189be65 | 1668 | batch->psize, batch->ssize, local); |
1da177e4 LT |
1669 | } |
1670 | } | |
1671 | ||
1da177e4 LT |
1672 | /* |
1673 | * low_hash_fault is called when we the low level hash code failed | |
1674 | * to instert a PTE due to an hypervisor error | |
1675 | */ | |
fa28237c | 1676 | void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc) |
1da177e4 | 1677 | { |
ba12eede LZ |
1678 | enum ctx_state prev_state = exception_enter(); |
1679 | ||
1da177e4 | 1680 | if (user_mode(regs)) { |
fa28237c PM |
1681 | #ifdef CONFIG_PPC_SUBPAGE_PROT |
1682 | if (rc == -2) | |
1683 | _exception(SIGSEGV, regs, SEGV_ACCERR, address); | |
1684 | else | |
1685 | #endif | |
1686 | _exception(SIGBUS, regs, BUS_ADRERR, address); | |
1687 | } else | |
1688 | bad_page_fault(regs, address, SIGBUS); | |
ba12eede LZ |
1689 | |
1690 | exception_exit(prev_state); | |
1da177e4 | 1691 | } |
370a908d | 1692 | |
b170bd3d LZ |
1693 | long hpte_insert_repeating(unsigned long hash, unsigned long vpn, |
1694 | unsigned long pa, unsigned long rflags, | |
1695 | unsigned long vflags, int psize, int ssize) | |
1696 | { | |
1697 | unsigned long hpte_group; | |
1698 | long slot; | |
1699 | ||
1700 | repeat: | |
1701 | hpte_group = ((hash & htab_hash_mask) * | |
1702 | HPTES_PER_GROUP) & ~0x7UL; | |
1703 | ||
1704 | /* Insert into the hash table, primary slot */ | |
7025776e BH |
1705 | slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags, vflags, |
1706 | psize, psize, ssize); | |
b170bd3d LZ |
1707 | |
1708 | /* Primary is full, try the secondary */ | |
1709 | if (unlikely(slot == -1)) { | |
1710 | hpte_group = ((~hash & htab_hash_mask) * | |
1711 | HPTES_PER_GROUP) & ~0x7UL; | |
7025776e BH |
1712 | slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags, |
1713 | vflags | HPTE_V_SECONDARY, | |
1714 | psize, psize, ssize); | |
b170bd3d LZ |
1715 | if (slot == -1) { |
1716 | if (mftb() & 0x1) | |
1717 | hpte_group = ((hash & htab_hash_mask) * | |
1718 | HPTES_PER_GROUP)&~0x7UL; | |
1719 | ||
7025776e | 1720 | mmu_hash_ops.hpte_remove(hpte_group); |
b170bd3d LZ |
1721 | goto repeat; |
1722 | } | |
1723 | } | |
1724 | ||
1725 | return slot; | |
1726 | } | |
1727 | ||
370a908d BH |
1728 | #ifdef CONFIG_DEBUG_PAGEALLOC |
1729 | static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi) | |
1730 | { | |
016af59f | 1731 | unsigned long hash; |
1189be65 | 1732 | unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize); |
5524a27d | 1733 | unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize); |
09f3f326 | 1734 | unsigned long mode = htab_convert_pte_flags(pgprot_val(PAGE_KERNEL)); |
016af59f | 1735 | long ret; |
370a908d | 1736 | |
5524a27d | 1737 | hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize); |
370a908d | 1738 | |
c60ac569 AK |
1739 | /* Don't create HPTE entries for bad address */ |
1740 | if (!vsid) | |
1741 | return; | |
016af59f LZ |
1742 | |
1743 | ret = hpte_insert_repeating(hash, vpn, __pa(vaddr), mode, | |
1744 | HPTE_V_BOLTED, | |
1745 | mmu_linear_psize, mmu_kernel_ssize); | |
1746 | ||
370a908d BH |
1747 | BUG_ON (ret < 0); |
1748 | spin_lock(&linear_map_hash_lock); | |
1749 | BUG_ON(linear_map_hash_slots[lmi] & 0x80); | |
1750 | linear_map_hash_slots[lmi] = ret | 0x80; | |
1751 | spin_unlock(&linear_map_hash_lock); | |
1752 | } | |
1753 | ||
1754 | static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi) | |
1755 | { | |
1189be65 PM |
1756 | unsigned long hash, hidx, slot; |
1757 | unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize); | |
5524a27d | 1758 | unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize); |
370a908d | 1759 | |
5524a27d | 1760 | hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize); |
370a908d BH |
1761 | spin_lock(&linear_map_hash_lock); |
1762 | BUG_ON(!(linear_map_hash_slots[lmi] & 0x80)); | |
1763 | hidx = linear_map_hash_slots[lmi] & 0x7f; | |
1764 | linear_map_hash_slots[lmi] = 0; | |
1765 | spin_unlock(&linear_map_hash_lock); | |
1766 | if (hidx & _PTEIDX_SECONDARY) | |
1767 | hash = ~hash; | |
1768 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
1769 | slot += hidx & _PTEIDX_GROUP_IX; | |
7025776e BH |
1770 | mmu_hash_ops.hpte_invalidate(slot, vpn, mmu_linear_psize, |
1771 | mmu_linear_psize, | |
1772 | mmu_kernel_ssize, 0); | |
370a908d BH |
1773 | } |
1774 | ||
031bc574 | 1775 | void __kernel_map_pages(struct page *page, int numpages, int enable) |
370a908d BH |
1776 | { |
1777 | unsigned long flags, vaddr, lmi; | |
1778 | int i; | |
1779 | ||
1780 | local_irq_save(flags); | |
1781 | for (i = 0; i < numpages; i++, page++) { | |
1782 | vaddr = (unsigned long)page_address(page); | |
1783 | lmi = __pa(vaddr) >> PAGE_SHIFT; | |
1784 | if (lmi >= linear_map_hash_count) | |
1785 | continue; | |
1786 | if (enable) | |
1787 | kernel_map_linear_page(vaddr, lmi); | |
1788 | else | |
1789 | kernel_unmap_linear_page(vaddr, lmi); | |
1790 | } | |
1791 | local_irq_restore(flags); | |
1792 | } | |
1793 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
cd3db0c4 | 1794 | |
756d08d1 | 1795 | void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base, |
cd3db0c4 BH |
1796 | phys_addr_t first_memblock_size) |
1797 | { | |
1798 | /* We don't currently support the first MEMBLOCK not mapping 0 | |
1799 | * physical on those processors | |
1800 | */ | |
1801 | BUG_ON(first_memblock_base != 0); | |
1802 | ||
1803 | /* On LPAR systems, the first entry is our RMA region, | |
1804 | * non-LPAR 64-bit hash MMU systems don't have a limitation | |
1805 | * on real mode access, but using the first entry works well | |
1806 | * enough. We also clamp it to 1G to avoid some funky things | |
1807 | * such as RTAS bugs etc... | |
1808 | */ | |
1809 | ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000); | |
1810 | ||
1811 | /* Finally limit subsequent allocations */ | |
1812 | memblock_set_current_limit(ppc64_rma_size); | |
1813 | } |