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2874c5fd 1/* SPDX-License-Identifier: GPL-2.0-or-later */
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2/*
3 * Declarations of procedures and variables shared between files
4 * in arch/ppc/mm/.
5 *
6 * Derived from arch/ppc/mm/init.c:
7 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
8 *
9 * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
10 * and Cort Dougan (PReP) (cort@cs.nmt.edu)
11 * Copyright (C) 1996 Paul Mackerras
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12 *
13 * Derived from "arch/i386/mm/init.c"
14 * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
14cf11af 15 */
62102307 16#include <linux/mm.h>
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17#include <asm/mmu.h>
18
2a4aca11 19#ifdef CONFIG_PPC_MMU_NOHASH
cf4a6085 20#include <asm/trace.h>
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21
22/*
23 * On 40x and 8xx, we directly inline tlbia and tlbivax
24 */
968159c0 25#if defined(CONFIG_40x) || defined(CONFIG_PPC_8xx)
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26static inline void _tlbil_all(void)
27{
4a082682 28 asm volatile ("sync; tlbia; isync" : : : "memory");
8114c36e 29 trace_tlbia(MMU_NO_CONTEXT);
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30}
31static inline void _tlbil_pid(unsigned int pid)
32{
4a082682 33 asm volatile ("sync; tlbia; isync" : : : "memory");
8114c36e 34 trace_tlbia(pid);
2a4aca11 35}
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36#define _tlbil_pid_noind(pid) _tlbil_pid(pid)
37
968159c0 38#else /* CONFIG_40x || CONFIG_PPC_8xx */
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39extern void _tlbil_all(void);
40extern void _tlbil_pid(unsigned int pid);
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41#ifdef CONFIG_PPC_BOOK3E
42extern void _tlbil_pid_noind(unsigned int pid);
43#else
d4e167da 44#define _tlbil_pid_noind(pid) _tlbil_pid(pid)
25d21ad6 45#endif
968159c0 46#endif /* !(CONFIG_40x || CONFIG_PPC_8xx) */
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47
48/*
49 * On 8xx, we directly inline tlbie, on others, it's extern
50 */
968159c0 51#ifdef CONFIG_PPC_8xx
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52static inline void _tlbil_va(unsigned long address, unsigned int pid,
53 unsigned int tsize, unsigned int ind)
2a4aca11 54{
4a082682 55 asm volatile ("tlbie %0; sync" : : "r" (address) : "memory");
cf4a6085 56 trace_tlbie(0, 0, address, pid, 0, 0, 0);
2a4aca11 57}
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58#elif defined(CONFIG_PPC_BOOK3E)
59extern void _tlbil_va(unsigned long address, unsigned int pid,
60 unsigned int tsize, unsigned int ind);
61#else
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62extern void __tlbil_va(unsigned long address, unsigned int pid);
63static inline void _tlbil_va(unsigned long address, unsigned int pid,
64 unsigned int tsize, unsigned int ind)
65{
66 __tlbil_va(address, pid);
67}
968159c0 68#endif /* CONFIG_PPC_8xx */
2a4aca11 69
e7f75ad0 70#if defined(CONFIG_PPC_BOOK3E) || defined(CONFIG_PPC_47x)
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71extern void _tlbivax_bcast(unsigned long address, unsigned int pid,
72 unsigned int tsize, unsigned int ind);
73#else
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74static inline void _tlbivax_bcast(unsigned long address, unsigned int pid,
75 unsigned int tsize, unsigned int ind)
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76{
77 BUG();
78}
25d21ad6 79#endif
2a4aca11 80
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81static inline void print_system_hash_info(void) {}
82
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83#else /* CONFIG_PPC_MMU_NOHASH */
84
ee4f2ea4 85extern void hash_preload(struct mm_struct *mm, unsigned long ea,
34eb138e 86 bool is_exec, unsigned long trap);
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87
88
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89extern void _tlbie(unsigned long address);
90extern void _tlbia(void);
91
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92void print_system_hash_info(void);
93
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94#endif /* CONFIG_PPC_MMU_NOHASH */
95
ab1f9dac 96#ifdef CONFIG_PPC32
19f5465e 97
14cf11af 98extern void mapin_ram(void);
7c5c4325 99extern void setbat(int index, unsigned long virt, phys_addr_t phys,
5dd4e4f6 100 unsigned int size, pgprot_t prot);
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101
102extern int __map_without_bats;
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103extern unsigned int rtas_data, rtas_size;
104
8e561e7e 105struct hash_pte;
57e0491b 106extern struct hash_pte *Hash;
215b8237 107extern u8 early_hash[];
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108
109#endif /* CONFIG_PPC32 */
110
800fc3ee 111extern unsigned long ioremap_bot;
ab1f9dac 112extern unsigned long __max_low_memory;
09b5e63f 113extern phys_addr_t __initial_memory_limit_addr;
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114extern phys_addr_t total_memory;
115extern phys_addr_t total_lowmem;
99c62dd7 116extern phys_addr_t memstart_addr;
d7917ba7 117extern phys_addr_t lowmem_end_addr;
14cf11af 118
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119#ifdef CONFIG_WII
120extern unsigned long wii_hole_start;
121extern unsigned long wii_hole_size;
122
123extern unsigned long wii_mmu_mapin_mem2(unsigned long top);
124extern void wii_memory_fixups(void);
125#endif
126
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127/* ...and now those things that may be slightly different between processor
128 * architectures. -- Dan
129 */
a372acfa 130#ifdef CONFIG_PPC32
14cf11af 131extern void MMU_init_hw(void);
72f208c6 132void MMU_init_hw_patch(void);
14e609d6 133unsigned long mmu_mapin_ram(unsigned long base, unsigned long top);
a372acfa 134#endif
14cf11af 135
a372acfa 136#ifdef CONFIG_PPC_FSL_BOOK3E
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137extern unsigned long map_mem_in_cams(unsigned long ram, int max_cam_idx,
138 bool dryrun);
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139extern unsigned long calc_cam_sz(unsigned long ram, unsigned long virt,
140 phys_addr_t phys);
55fd766b 141#ifdef CONFIG_PPC32
14cf11af 142extern void adjust_total_lowmem(void);
78a235ef 143extern int switch_to_as1(void);
0be7d969 144extern void restore_to_as0(int esel, int offset, void *dt_ptr, int bootcpu);
55fd766b 145#endif
78f62237 146extern void loadcam_entry(unsigned int index);
d9e1831a 147extern void loadcam_multi(int first_idx, int num, int tmp_idx);
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148
149struct tlbcam {
150 u32 MAS0;
151 u32 MAS1;
152 unsigned long MAS2;
153 u32 MAS3;
154 u32 MAS7;
155};
14cf11af 156#endif
3084cdb7 157
d7cceda9 158#if defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_FSL_BOOKE) || defined(CONFIG_PPC_8xx)
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159/* 6xx have BATS */
160/* FSL_BOOKE have TLBCAM */
4badd43a 161/* 8xx have LTLB */
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162phys_addr_t v_block_mapped(unsigned long va);
163unsigned long p_block_mapped(phys_addr_t pa);
164#else
165static inline phys_addr_t v_block_mapped(unsigned long va) { return 0; }
166static inline unsigned long p_block_mapped(phys_addr_t pa) { return 0; }
167#endif
63b2bc61 168
d5f17ee9 169#if defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_PPC_8xx)
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170void mmu_mark_initmem_nx(void);
171void mmu_mark_rodata_ro(void);
172#else
173static inline void mmu_mark_initmem_nx(void) { }
174static inline void mmu_mark_rodata_ro(void) { }
175#endif