]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - arch/powerpc/mm/mmu_decl.h
powerpc/8xx: Map IMMR area with 512k page at a fixed address
[mirror_ubuntu-artful-kernel.git] / arch / powerpc / mm / mmu_decl.h
CommitLineData
14cf11af
PM
1/*
2 * Declarations of procedures and variables shared between files
3 * in arch/ppc/mm/.
4 *
5 * Derived from arch/ppc/mm/init.c:
6 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
7 *
8 * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
9 * and Cort Dougan (PReP) (cort@cs.nmt.edu)
10 * Copyright (C) 1996 Paul Mackerras
14cf11af
PM
11 *
12 * Derived from "arch/i386/mm/init.c"
13 * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
19 *
20 */
62102307 21#include <linux/mm.h>
14cf11af
PM
22#include <asm/tlbflush.h>
23#include <asm/mmu.h>
24
2a4aca11
BH
25#ifdef CONFIG_PPC_MMU_NOHASH
26
27/*
28 * On 40x and 8xx, we directly inline tlbia and tlbivax
29 */
30#if defined(CONFIG_40x) || defined(CONFIG_8xx)
31static inline void _tlbil_all(void)
32{
4a082682 33 asm volatile ("sync; tlbia; isync" : : : "memory");
2a4aca11
BH
34}
35static inline void _tlbil_pid(unsigned int pid)
36{
4a082682 37 asm volatile ("sync; tlbia; isync" : : : "memory");
2a4aca11 38}
d4e167da
BH
39#define _tlbil_pid_noind(pid) _tlbil_pid(pid)
40
2a4aca11
BH
41#else /* CONFIG_40x || CONFIG_8xx */
42extern void _tlbil_all(void);
43extern void _tlbil_pid(unsigned int pid);
25d21ad6
BH
44#ifdef CONFIG_PPC_BOOK3E
45extern void _tlbil_pid_noind(unsigned int pid);
46#else
d4e167da 47#define _tlbil_pid_noind(pid) _tlbil_pid(pid)
25d21ad6 48#endif
2a4aca11
BH
49#endif /* !(CONFIG_40x || CONFIG_8xx) */
50
51/*
52 * On 8xx, we directly inline tlbie, on others, it's extern
53 */
54#ifdef CONFIG_8xx
d4e167da
BH
55static inline void _tlbil_va(unsigned long address, unsigned int pid,
56 unsigned int tsize, unsigned int ind)
2a4aca11 57{
4a082682 58 asm volatile ("tlbie %0; sync" : : "r" (address) : "memory");
2a4aca11 59}
25d21ad6
BH
60#elif defined(CONFIG_PPC_BOOK3E)
61extern void _tlbil_va(unsigned long address, unsigned int pid,
62 unsigned int tsize, unsigned int ind);
63#else
d4e167da
BH
64extern void __tlbil_va(unsigned long address, unsigned int pid);
65static inline void _tlbil_va(unsigned long address, unsigned int pid,
66 unsigned int tsize, unsigned int ind)
67{
68 __tlbil_va(address, pid);
69}
b823982c 70#endif /* CONFIG_8xx */
2a4aca11 71
e7f75ad0 72#if defined(CONFIG_PPC_BOOK3E) || defined(CONFIG_PPC_47x)
25d21ad6
BH
73extern void _tlbivax_bcast(unsigned long address, unsigned int pid,
74 unsigned int tsize, unsigned int ind);
75#else
d4e167da
BH
76static inline void _tlbivax_bcast(unsigned long address, unsigned int pid,
77 unsigned int tsize, unsigned int ind)
2a4aca11
BH
78{
79 BUG();
80}
25d21ad6 81#endif
2a4aca11
BH
82
83#else /* CONFIG_PPC_MMU_NOHASH */
84
ee4f2ea4
BH
85extern void hash_preload(struct mm_struct *mm, unsigned long ea,
86 unsigned long access, unsigned long trap);
87
88
2a4aca11
BH
89extern void _tlbie(unsigned long address);
90extern void _tlbia(void);
91
92#endif /* CONFIG_PPC_MMU_NOHASH */
93
ab1f9dac 94#ifdef CONFIG_PPC32
19f5465e 95
14cf11af
PM
96extern void mapin_ram(void);
97extern int map_page(unsigned long va, phys_addr_t pa, int flags);
7c5c4325 98extern void setbat(int index, unsigned long virt, phys_addr_t phys,
5dd4e4f6 99 unsigned int size, pgprot_t prot);
14cf11af
PM
100
101extern int __map_without_bats;
c5df7f77 102extern int __allow_ioremap_reserved;
14cf11af
PM
103extern unsigned int rtas_data, rtas_size;
104
8e561e7e
DG
105struct hash_pte;
106extern struct hash_pte *Hash, *Hash_end;
14cf11af 107extern unsigned long Hash_size, Hash_mask;
32a74949
BH
108
109#endif /* CONFIG_PPC32 */
110
800fc3ee 111extern unsigned long ioremap_bot;
ab1f9dac 112extern unsigned long __max_low_memory;
09b5e63f 113extern phys_addr_t __initial_memory_limit_addr;
2bf3016f
SR
114extern phys_addr_t total_memory;
115extern phys_addr_t total_lowmem;
99c62dd7 116extern phys_addr_t memstart_addr;
d7917ba7 117extern phys_addr_t lowmem_end_addr;
14cf11af 118
de32400d
AH
119#ifdef CONFIG_WII
120extern unsigned long wii_hole_start;
121extern unsigned long wii_hole_size;
122
123extern unsigned long wii_mmu_mapin_mem2(unsigned long top);
124extern void wii_memory_fixups(void);
125#endif
126
14cf11af
PM
127/* ...and now those things that may be slightly different between processor
128 * architectures. -- Dan
129 */
a372acfa 130#ifdef CONFIG_PPC32
14cf11af 131extern void MMU_init_hw(void);
ae4cec47 132extern unsigned long mmu_mapin_ram(unsigned long top);
a372acfa 133#endif
14cf11af 134
a372acfa 135#ifdef CONFIG_PPC_FSL_BOOK3E
eba5de8d
SW
136extern unsigned long map_mem_in_cams(unsigned long ram, int max_cam_idx,
137 bool dryrun);
1dc91c3e
KG
138extern unsigned long calc_cam_sz(unsigned long ram, unsigned long virt,
139 phys_addr_t phys);
55fd766b 140#ifdef CONFIG_PPC32
14cf11af 141extern void adjust_total_lowmem(void);
78a235ef 142extern int switch_to_as1(void);
0be7d969 143extern void restore_to_as0(int esel, int offset, void *dt_ptr, int bootcpu);
55fd766b 144#endif
78f62237 145extern void loadcam_entry(unsigned int index);
d9e1831a 146extern void loadcam_multi(int first_idx, int num, int tmp_idx);
78f62237
KG
147
148struct tlbcam {
149 u32 MAS0;
150 u32 MAS1;
151 unsigned long MAS2;
152 u32 MAS3;
153 u32 MAS7;
154};
14cf11af 155#endif
3084cdb7 156
4badd43a 157#if defined(CONFIG_6xx) || defined(CONFIG_FSL_BOOKE) || defined(CONFIG_PPC_8xx)
3084cdb7
CL
158/* 6xx have BATS */
159/* FSL_BOOKE have TLBCAM */
4badd43a 160/* 8xx have LTLB */
3084cdb7
CL
161phys_addr_t v_block_mapped(unsigned long va);
162unsigned long p_block_mapped(phys_addr_t pa);
163#else
164static inline phys_addr_t v_block_mapped(unsigned long va) { return 0; }
165static inline unsigned long p_block_mapped(phys_addr_t pa) { return 0; }
166#endif