]> git.proxmox.com Git - mirror_ubuntu-eoan-kernel.git/blame - arch/powerpc/mm/mmu_decl.h
powerpc/44x: break out cpu init code into stand-alone function
[mirror_ubuntu-eoan-kernel.git] / arch / powerpc / mm / mmu_decl.h
CommitLineData
14cf11af
PM
1/*
2 * Declarations of procedures and variables shared between files
3 * in arch/ppc/mm/.
4 *
5 * Derived from arch/ppc/mm/init.c:
6 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
7 *
8 * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
9 * and Cort Dougan (PReP) (cort@cs.nmt.edu)
10 * Copyright (C) 1996 Paul Mackerras
14cf11af
PM
11 *
12 * Derived from "arch/i386/mm/init.c"
13 * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
19 *
20 */
62102307 21#include <linux/mm.h>
14cf11af
PM
22#include <asm/tlbflush.h>
23#include <asm/mmu.h>
24
2a4aca11
BH
25#ifdef CONFIG_PPC_MMU_NOHASH
26
27/*
28 * On 40x and 8xx, we directly inline tlbia and tlbivax
29 */
30#if defined(CONFIG_40x) || defined(CONFIG_8xx)
31static inline void _tlbil_all(void)
32{
4a082682 33 asm volatile ("sync; tlbia; isync" : : : "memory");
2a4aca11
BH
34}
35static inline void _tlbil_pid(unsigned int pid)
36{
4a082682 37 asm volatile ("sync; tlbia; isync" : : : "memory");
2a4aca11 38}
d4e167da
BH
39#define _tlbil_pid_noind(pid) _tlbil_pid(pid)
40
2a4aca11
BH
41#else /* CONFIG_40x || CONFIG_8xx */
42extern void _tlbil_all(void);
43extern void _tlbil_pid(unsigned int pid);
25d21ad6
BH
44#ifdef CONFIG_PPC_BOOK3E
45extern void _tlbil_pid_noind(unsigned int pid);
46#else
d4e167da 47#define _tlbil_pid_noind(pid) _tlbil_pid(pid)
25d21ad6 48#endif
2a4aca11
BH
49#endif /* !(CONFIG_40x || CONFIG_8xx) */
50
51/*
52 * On 8xx, we directly inline tlbie, on others, it's extern
53 */
54#ifdef CONFIG_8xx
d4e167da
BH
55static inline void _tlbil_va(unsigned long address, unsigned int pid,
56 unsigned int tsize, unsigned int ind)
2a4aca11 57{
4a082682 58 asm volatile ("tlbie %0; sync" : : "r" (address) : "memory");
2a4aca11 59}
25d21ad6
BH
60#elif defined(CONFIG_PPC_BOOK3E)
61extern void _tlbil_va(unsigned long address, unsigned int pid,
62 unsigned int tsize, unsigned int ind);
63#else
d4e167da
BH
64extern void __tlbil_va(unsigned long address, unsigned int pid);
65static inline void _tlbil_va(unsigned long address, unsigned int pid,
66 unsigned int tsize, unsigned int ind)
67{
68 __tlbil_va(address, pid);
69}
2a4aca11
BH
70#endif /* CONIFG_8xx */
71
72/*
73 * As of today, we don't support tlbivax broadcast on any
74 * implementation. When that becomes the case, this will be
75 * an extern.
76 */
25d21ad6
BH
77#ifdef CONFIG_PPC_BOOK3E
78extern void _tlbivax_bcast(unsigned long address, unsigned int pid,
79 unsigned int tsize, unsigned int ind);
80#else
d4e167da
BH
81static inline void _tlbivax_bcast(unsigned long address, unsigned int pid,
82 unsigned int tsize, unsigned int ind)
2a4aca11
BH
83{
84 BUG();
85}
25d21ad6 86#endif
2a4aca11
BH
87
88#else /* CONFIG_PPC_MMU_NOHASH */
89
ee4f2ea4
BH
90extern void hash_preload(struct mm_struct *mm, unsigned long ea,
91 unsigned long access, unsigned long trap);
92
93
2a4aca11
BH
94extern void _tlbie(unsigned long address);
95extern void _tlbia(void);
96
97#endif /* CONFIG_PPC_MMU_NOHASH */
98
ab1f9dac 99#ifdef CONFIG_PPC32
19f5465e 100
14cf11af
PM
101extern void mapin_ram(void);
102extern int map_page(unsigned long va, phys_addr_t pa, int flags);
7c5c4325 103extern void setbat(int index, unsigned long virt, phys_addr_t phys,
14cf11af 104 unsigned int size, int flags);
14cf11af
PM
105
106extern int __map_without_bats;
c5df7f77 107extern int __allow_ioremap_reserved;
14cf11af 108extern unsigned long ioremap_base;
14cf11af
PM
109extern unsigned int rtas_data, rtas_size;
110
8e561e7e
DG
111struct hash_pte;
112extern struct hash_pte *Hash, *Hash_end;
14cf11af 113extern unsigned long Hash_size, Hash_mask;
32a74949
BH
114
115#endif /* CONFIG_PPC32 */
116
117#ifdef CONFIG_PPC64
118extern int map_kernel_page(unsigned long ea, unsigned long pa, int flags);
119#endif /* CONFIG_PPC64 */
ab1f9dac 120
800fc3ee 121extern unsigned long ioremap_bot;
ab1f9dac 122extern unsigned long __max_low_memory;
09b5e63f 123extern phys_addr_t __initial_memory_limit_addr;
2bf3016f
SR
124extern phys_addr_t total_memory;
125extern phys_addr_t total_lowmem;
99c62dd7 126extern phys_addr_t memstart_addr;
d7917ba7 127extern phys_addr_t lowmem_end_addr;
14cf11af 128
de32400d
AH
129#ifdef CONFIG_WII
130extern unsigned long wii_hole_start;
131extern unsigned long wii_hole_size;
132
133extern unsigned long wii_mmu_mapin_mem2(unsigned long top);
134extern void wii_memory_fixups(void);
135#endif
136
14cf11af
PM
137/* ...and now those things that may be slightly different between processor
138 * architectures. -- Dan
139 */
140#if defined(CONFIG_8xx)
14cf11af 141#define MMU_init_hw() do { } while(0)
ae4cec47 142#define mmu_mapin_ram(top) (0UL)
14cf11af
PM
143
144#elif defined(CONFIG_4xx)
14cf11af 145extern void MMU_init_hw(void);
ae4cec47 146extern unsigned long mmu_mapin_ram(unsigned long top);
14cf11af
PM
147
148#elif defined(CONFIG_FSL_BOOKE)
14cf11af 149extern void MMU_init_hw(void);
ae4cec47 150extern unsigned long mmu_mapin_ram(unsigned long top);
14cf11af
PM
151extern void adjust_total_lowmem(void);
152
ab1f9dac
PM
153#elif defined(CONFIG_PPC32)
154/* anything 32-bit except 4xx or 8xx */
14cf11af 155extern void MMU_init_hw(void);
de32400d 156extern unsigned long mmu_mapin_ram(unsigned long top);
14cf11af 157#endif