[mirror_ubuntu-bionic-kernel.git] / arch / powerpc / mm / pgtable-radix.c

/*
 * Page table handling routines for radix page table.
 *
 * Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */
#include <linux/sched.h>
#include <linux/memblock.h>
#include <linux/of_fdt.h>

#include <asm/pgtable.h>
#include <asm/pgalloc.h>
#include <asm/dma.h>
#include <asm/machdep.h>
#include <asm/mmu.h>
#include <asm/firmware.h>

#include <trace/events/thp.h>

static int native_update_partition_table(u64 patb1)
{
	partition_tb->patb1 = cpu_to_be64(patb1);
	return 0;
}

static __ref void *early_alloc_pgtable(unsigned long size)
{
	void *pt;

	pt = __va(memblock_alloc_base(size, size, MEMBLOCK_ALLOC_ANYWHERE));
	memset(pt, 0, size);

	return pt;
}

int radix__map_kernel_page(unsigned long ea, unsigned long pa,
			  pgprot_t flags,
			  unsigned int map_page_size)
{
	pgd_t *pgdp;
	pud_t *pudp;
	pmd_t *pmdp;
	pte_t *ptep;
	/*
	 * Make sure task size is correct as per the max adddr
	 */
	BUILD_BUG_ON(TASK_SIZE_USER64 > RADIX_PGTABLE_RANGE);
	if (slab_is_available()) {
		pgdp = pgd_offset_k(ea);
		pudp = pud_alloc(&init_mm, pgdp, ea);
		if (!pudp)
			return -ENOMEM;
		if (map_page_size == PUD_SIZE) {
			ptep = (pte_t *)pudp;
			goto set_the_pte;
		}
		pmdp = pmd_alloc(&init_mm, pudp, ea);
		if (!pmdp)
			return -ENOMEM;
		if (map_page_size == PMD_SIZE) {
			ptep = (pte_t *)pudp;
			goto set_the_pte;
		}
		ptep = pte_alloc_kernel(pmdp, ea);
		if (!ptep)
			return -ENOMEM;
	} else {
		pgdp = pgd_offset_k(ea);
		if (pgd_none(*pgdp)) {
			pudp = early_alloc_pgtable(PUD_TABLE_SIZE);
			BUG_ON(pudp == NULL);
			pgd_populate(&init_mm, pgdp, pudp);
		}
		pudp = pud_offset(pgdp, ea);
		if (map_page_size == PUD_SIZE) {
			ptep = (pte_t *)pudp;
			goto set_the_pte;
		}
		if (pud_none(*pudp)) {
			pmdp = early_alloc_pgtable(PMD_TABLE_SIZE);
			BUG_ON(pmdp == NULL);
			pud_populate(&init_mm, pudp, pmdp);
		}
		pmdp = pmd_offset(pudp, ea);
		if (map_page_size == PMD_SIZE) {
			ptep = (pte_t *)pudp;
			goto set_the_pte;
		}
		if (!pmd_present(*pmdp)) {
			ptep = early_alloc_pgtable(PAGE_SIZE);
			BUG_ON(ptep == NULL);
			pmd_populate_kernel(&init_mm, pmdp, ptep);
		}
		ptep = pte_offset_kernel(pmdp, ea);
	}

set_the_pte:
	set_pte_at(&init_mm, ea, ptep, pfn_pte(pa >> PAGE_SHIFT, flags));
	smp_wmb();
	return 0;
}

static void __init radix_init_pgtable(void)
{
	int loop_count;
	u64 base, end, start_addr;
	unsigned long rts_field;
	struct memblock_region *reg;
	unsigned long linear_page_size;

	/* We don't support slb for radix */
	mmu_slb_size = 0;
	/*
	 * Create the linear mapping, using standard page size for now
	 */
	loop_count = 0;
	for_each_memblock(memory, reg) {

		start_addr = reg->base;

redo:
		if (loop_count < 1 && mmu_psize_defs[MMU_PAGE_1G].shift)
			linear_page_size = PUD_SIZE;
		else if (loop_count < 2 && mmu_psize_defs[MMU_PAGE_2M].shift)
			linear_page_size = PMD_SIZE;
		else
			linear_page_size = PAGE_SIZE;

		base = _ALIGN_UP(start_addr, linear_page_size);
		end = _ALIGN_DOWN(reg->base + reg->size, linear_page_size);

		pr_info("Mapping range 0x%lx - 0x%lx with 0x%lx\n",
			(unsigned long)base, (unsigned long)end,
			linear_page_size);

		while (base < end) {
			radix__map_kernel_page((unsigned long)__va(base),
					      base, PAGE_KERNEL_X,
					      linear_page_size);
			base += linear_page_size;
		}
		/*
		 * map the rest using lower page size
		 */
		if (end < reg->base + reg->size) {
			start_addr = end;
			loop_count++;
			goto redo;
		}
	}
	/*
	 * Allocate Partition table and process table for the
	 * host.
	 */
	BUILD_BUG_ON_MSG((PRTB_SIZE_SHIFT > 23), "Process table size too large.");
	process_tb = early_alloc_pgtable(1UL << PRTB_SIZE_SHIFT);
	/*
	 * Fill in the process table.
	 */
	rts_field = radix__get_tree_size();
	process_tb->prtb0 = cpu_to_be64(rts_field | __pa(init_mm.pgd) | RADIX_PGD_INDEX_SIZE);
	/*
	 * Fill in the partition table. We are suppose to use effective address
	 * of process table here. But our linear mapping also enable us to use
	 * physical address here.
	 */
	ppc_md.update_partition_table(__pa(process_tb) | (PRTB_SIZE_SHIFT - 12) | PATB_GR);
	pr_info("Process table %p and radix root for kernel: %p\n", process_tb, init_mm.pgd);
}

static void __init radix_init_partition_table(void)
{
	unsigned long rts_field;

	rts_field = radix__get_tree_size();

	BUILD_BUG_ON_MSG((PATB_SIZE_SHIFT > 24), "Partition table size too large.");
	partition_tb = early_alloc_pgtable(1UL << PATB_SIZE_SHIFT);
	partition_tb->patb0 = cpu_to_be64(rts_field | __pa(init_mm.pgd) |
					  RADIX_PGD_INDEX_SIZE | PATB_HR);
	pr_info("Initializing Radix MMU\n");
	pr_info("Partition table %p\n", partition_tb);

	memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
	/*
	 * update partition table control register,
	 * 64 K size.
	 */
	mtspr(SPRN_PTCR, __pa(partition_tb) | (PATB_SIZE_SHIFT - 12));
}

void __init radix_init_native(void)
{
	ppc_md.update_partition_table = native_update_partition_table;
}

static int __init get_idx_from_shift(unsigned int shift)
{
	int idx = -1;

	switch (shift) {
	case 0xc:
		idx = MMU_PAGE_4K;
		break;
	case 0x10:
		idx = MMU_PAGE_64K;
		break;
	case 0x15:
		idx = MMU_PAGE_2M;
		break;
	case 0x1e:
		idx = MMU_PAGE_1G;
		break;
	}
	return idx;
}

static int __init radix_dt_scan_page_sizes(unsigned long node,
					   const char *uname, int depth,
					   void *data)
{
	int size = 0;
	int shift, idx;
	unsigned int ap;
	const __be32 *prop;
	const char *type = of_get_flat_dt_prop(node, "device_type", NULL);

	/* We are scanning "cpu" nodes only */
	if (type == NULL || strcmp(type, "cpu") != 0)
		return 0;

	prop = of_get_flat_dt_prop(node, "ibm,processor-radix-AP-encodings", &size);
	if (!prop)
		return 0;

	pr_info("Page sizes from device-tree:\n");
	for (; size >= 4; size -= 4, ++prop) {

		struct mmu_psize_def *def;

		/* top 3 bit is AP encoding */
		shift = be32_to_cpu(prop[0]) & ~(0xe << 28);
		ap = be32_to_cpu(prop[0]) >> 29;
		pr_info("Page size sift = %d AP=0x%x\n", shift, ap);

		idx = get_idx_from_shift(shift);
		if (idx < 0)
			continue;

		def = &mmu_psize_defs[idx];
		def->shift = shift;
		def->ap  = ap;
	}

	/* needed ? */
	cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
	return 1;
}

static void __init radix_init_page_sizes(void)
{
	int rc;

	/*
	 * Try to find the available page sizes in the device-tree
	 */
	rc = of_scan_flat_dt(radix_dt_scan_page_sizes, NULL);
	if (rc != 0)  /* Found */
		goto found;
	/*
	 * let's assume we have page 4k and 64k support
	 */
	mmu_psize_defs[MMU_PAGE_4K].shift = 12;
	mmu_psize_defs[MMU_PAGE_4K].ap = 0x0;

	mmu_psize_defs[MMU_PAGE_64K].shift = 16;
	mmu_psize_defs[MMU_PAGE_64K].ap = 0x5;
found:
#ifdef CONFIG_SPARSEMEM_VMEMMAP
	if (mmu_psize_defs[MMU_PAGE_2M].shift) {
		/*
		 * map vmemmap using 2M if available
		 */
		mmu_vmemmap_psize = MMU_PAGE_2M;
	}
#endif /* CONFIG_SPARSEMEM_VMEMMAP */
	return;
}

void __init radix__early_init_mmu(void)
{
	unsigned long lpcr;

#ifdef CONFIG_PPC_64K_PAGES
	/* PAGE_SIZE mappings */
	mmu_virtual_psize = MMU_PAGE_64K;
#else
	mmu_virtual_psize = MMU_PAGE_4K;
#endif

#ifdef CONFIG_SPARSEMEM_VMEMMAP
	/* vmemmap mapping */
	mmu_vmemmap_psize = mmu_virtual_psize;
#endif
	/*
	 * initialize page table size
	 */
	__pte_index_size = RADIX_PTE_INDEX_SIZE;
	__pmd_index_size = RADIX_PMD_INDEX_SIZE;
	__pud_index_size = RADIX_PUD_INDEX_SIZE;
	__pgd_index_size = RADIX_PGD_INDEX_SIZE;
	__pmd_cache_index = RADIX_PMD_INDEX_SIZE;
	__pte_table_size = RADIX_PTE_TABLE_SIZE;
	__pmd_table_size = RADIX_PMD_TABLE_SIZE;
	__pud_table_size = RADIX_PUD_TABLE_SIZE;
	__pgd_table_size = RADIX_PGD_TABLE_SIZE;

	__pmd_val_bits = RADIX_PMD_VAL_BITS;
	__pud_val_bits = RADIX_PUD_VAL_BITS;
	__pgd_val_bits = RADIX_PGD_VAL_BITS;

	__kernel_virt_start = RADIX_KERN_VIRT_START;
	__kernel_virt_size = RADIX_KERN_VIRT_SIZE;
	__vmalloc_start = RADIX_VMALLOC_START;
	__vmalloc_end = RADIX_VMALLOC_END;
	vmemmap = (struct page *)RADIX_VMEMMAP_BASE;
	ioremap_bot = IOREMAP_BASE;

#ifdef CONFIG_PCI
	pci_io_base = ISA_IO_BASE;
#endif

	/*
	 * For now radix also use the same frag size
	 */
	__pte_frag_nr = H_PTE_FRAG_NR;
	__pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT;

	radix_init_page_sizes();
	if (!firmware_has_feature(FW_FEATURE_LPAR)) {
		lpcr = mfspr(SPRN_LPCR);
		mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
		radix_init_partition_table();
	}

	radix_init_pgtable();
}

void radix__early_init_mmu_secondary(void)
{
	unsigned long lpcr;
	/*
	 * update partition table control register and UPRT
	 */
	if (!firmware_has_feature(FW_FEATURE_LPAR)) {
		lpcr = mfspr(SPRN_LPCR);
		mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);

		mtspr(SPRN_PTCR,
		      __pa(partition_tb) | (PATB_SIZE_SHIFT - 12));
	}
}

void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base,
				phys_addr_t first_memblock_size)
{
	/* We don't currently support the first MEMBLOCK not mapping 0
	 * physical on those processors
	 */
	BUG_ON(first_memblock_base != 0);
	/*
	 * We limit the allocation that depend on ppc64_rma_size
	 * to first_memblock_size. We also clamp it to 1GB to
	 * avoid some funky things such as RTAS bugs.
	 *
	 * On radix config we really don't have a limitation
	 * on real mode access. But keeping it as above works
	 * well enough.
	 */
	ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000);
	/*
	 * Finally limit subsequent allocations. We really don't want
	 * to limit the memblock allocations to rma_size. FIXME!! should
	 * we even limit at all ?
	 */
	memblock_set_current_limit(first_memblock_base + first_memblock_size);
}

#ifdef CONFIG_SPARSEMEM_VMEMMAP
int __meminit radix__vmemmap_create_mapping(unsigned long start,
				      unsigned long page_size,
				      unsigned long phys)
{
	/* Create a PTE encoding */
	unsigned long flags = _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_KERNEL_RW;

	BUG_ON(radix__map_kernel_page(start, phys, __pgprot(flags), page_size));
	return 0;
}

#ifdef CONFIG_MEMORY_HOTPLUG
void radix__vmemmap_remove_mapping(unsigned long start, unsigned long page_size)
{
	/* FIXME!! intel does more. We should free page tables mapping vmemmap ? */
}
#endif
#endif

#ifdef CONFIG_TRANSPARENT_HUGEPAGE

unsigned long radix__pmd_hugepage_update(struct mm_struct *mm, unsigned long addr,
				  pmd_t *pmdp, unsigned long clr,
				  unsigned long set)
{
	unsigned long old;

#ifdef CONFIG_DEBUG_VM
	WARN_ON(!radix__pmd_trans_huge(*pmdp));
	assert_spin_locked(&mm->page_table_lock);
#endif

	old = radix__pte_update(mm, addr, (pte_t *)pmdp, clr, set, 1);
	trace_hugepage_update(addr, old, clr, set);

	return old;
}

pmd_t radix__pmdp_collapse_flush(struct vm_area_struct *vma, unsigned long address,
			pmd_t *pmdp)

{
	pmd_t pmd;

	VM_BUG_ON(address & ~HPAGE_PMD_MASK);
	VM_BUG_ON(radix__pmd_trans_huge(*pmdp));
	/*
	 * khugepaged calls this for normal pmd
	 */
	pmd = *pmdp;
	pmd_clear(pmdp);
	/*FIXME!!  Verify whether we need this kick below */
	kick_all_cpus_sync();
	flush_tlb_range(vma, address, address + HPAGE_PMD_SIZE);
	return pmd;
}

/*
 * For us pgtable_t is pte_t *. Inorder to save the deposisted
 * page table, we consider the allocated page table as a list
 * head. On withdraw we need to make sure we zero out the used
 * list_head memory area.
 */
void radix__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
				 pgtable_t pgtable)
{
        struct list_head *lh = (struct list_head *) pgtable;

        assert_spin_locked(pmd_lockptr(mm, pmdp));

        /* FIFO */
        if (!pmd_huge_pte(mm, pmdp))
                INIT_LIST_HEAD(lh);
        else
                list_add(lh, (struct list_head *) pmd_huge_pte(mm, pmdp));
        pmd_huge_pte(mm, pmdp) = pgtable;
}

pgtable_t radix__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp)
{
        pte_t *ptep;
        pgtable_t pgtable;
        struct list_head *lh;

        assert_spin_locked(pmd_lockptr(mm, pmdp));

        /* FIFO */
        pgtable = pmd_huge_pte(mm, pmdp);
        lh = (struct list_head *) pgtable;
        if (list_empty(lh))
                pmd_huge_pte(mm, pmdp) = NULL;
        else {
                pmd_huge_pte(mm, pmdp) = (pgtable_t) lh->next;
                list_del(lh);
        }
        ptep = (pte_t *) pgtable;
        *ptep = __pte(0);
        ptep++;
        *ptep = __pte(0);
        return pgtable;
}


pmd_t radix__pmdp_huge_get_and_clear(struct mm_struct *mm,
			       unsigned long addr, pmd_t *pmdp)
{
	pmd_t old_pmd;
	unsigned long old;

	old = radix__pmd_hugepage_update(mm, addr, pmdp, ~0UL, 0);
	old_pmd = __pmd(old);
	/*
	 * Serialize against find_linux_pte_or_hugepte which does lock-less
	 * lookup in page tables with local interrupts disabled. For huge pages
	 * it casts pmd_t to pte_t. Since format of pte_t is different from
	 * pmd_t we want to prevent transit from pmd pointing to page table
	 * to pmd pointing to huge page (and back) while interrupts are disabled.
	 * We clear pmd to possibly replace it with page table pointer in
	 * different code paths. So make sure we wait for the parallel
	 * find_linux_pte_or_hugepage to finish.
	 */
	kick_all_cpus_sync();
	return old_pmd;
}

int radix__has_transparent_hugepage(void)
{
	/* For radix 2M at PMD level means thp */
	if (mmu_psize_defs[MMU_PAGE_2M].shift == PMD_SHIFT)
		return 1;
	return 0;
}
#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
Commit	Line	Data
2bfd65e4 AK	1	/*
	2	* Page table handling routines for radix page table.
	3	*
	4	* Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation.
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version
	9	* 2 of the License, or (at your option) any later version.
	10	*/
	11	#include <linux/sched.h>
	12	#include <linux/memblock.h>
	13	#include <linux/of_fdt.h>
	14
	15	#include <asm/pgtable.h>
	16	#include <asm/pgalloc.h>
	17	#include <asm/dma.h>
	18	#include <asm/machdep.h>
	19	#include <asm/mmu.h>
	20	#include <asm/firmware.h>
	21
bde3eb62 AK	22	#include <trace/events/thp.h>
bde3eb62 AK	23
2bfd65e4 AK	24	static int native_update_partition_table(u64 patb1)
	25	{
	26	partition_tb->patb1 = cpu_to_be64(patb1);
	27	return 0;
	28	}
	29
	30	static __ref void *early_alloc_pgtable(unsigned long size)
	31	{
	32	void *pt;
	33
	34	pt = __va(memblock_alloc_base(size, size, MEMBLOCK_ALLOC_ANYWHERE));
	35	memset(pt, 0, size);
	36
	37	return pt;
	38	}
	39
	40	int radix__map_kernel_page(unsigned long ea, unsigned long pa,
	41	pgprot_t flags,
	42	unsigned int map_page_size)
	43	{
	44	pgd_t *pgdp;
	45	pud_t *pudp;
	46	pmd_t *pmdp;
	47	pte_t *ptep;
	48	/*
	49	* Make sure task size is correct as per the max adddr
	50	*/
	51	BUILD_BUG_ON(TASK_SIZE_USER64 > RADIX_PGTABLE_RANGE);
	52	if (slab_is_available()) {
	53	pgdp = pgd_offset_k(ea);
	54	pudp = pud_alloc(&init_mm, pgdp, ea);
	55	if (!pudp)
	56	return -ENOMEM;
	57	if (map_page_size == PUD_SIZE) {
	58	ptep = (pte_t *)pudp;
	59	goto set_the_pte;
	60	}
	61	pmdp = pmd_alloc(&init_mm, pudp, ea);
	62	if (!pmdp)
	63	return -ENOMEM;
	64	if (map_page_size == PMD_SIZE) {
	65	ptep = (pte_t *)pudp;
	66	goto set_the_pte;
	67	}
	68	ptep = pte_alloc_kernel(pmdp, ea);
	69	if (!ptep)
	70	return -ENOMEM;
	71	} else {
	72	pgdp = pgd_offset_k(ea);
	73	if (pgd_none(*pgdp)) {
	74	pudp = early_alloc_pgtable(PUD_TABLE_SIZE);
	75	BUG_ON(pudp == NULL);
	76	pgd_populate(&init_mm, pgdp, pudp);
	77	}
	78	pudp = pud_offset(pgdp, ea);
	79	if (map_page_size == PUD_SIZE) {
	80	ptep = (pte_t *)pudp;
	81	goto set_the_pte;
	82	}
	83	if (pud_none(*pudp)) {
	84	pmdp = early_alloc_pgtable(PMD_TABLE_SIZE);
	85	BUG_ON(pmdp == NULL);
	86	pud_populate(&init_mm, pudp, pmdp);
	87	}
88	pmdp = pmd_offset(pudp, ea);
89	if (map_page_size == PMD_SIZE) {
90	ptep = (pte_t *)pudp;
91	goto set_the_pte;
92	}
93	if (!pmd_present(*pmdp)) {
94	ptep = early_alloc_pgtable(PAGE_SIZE);
95	BUG_ON(ptep == NULL);
96	pmd_populate_kernel(&init_mm, pmdp, ptep);
97	}
98	ptep = pte_offset_kernel(pmdp, ea);
99	}
100
101	set_the_pte:
102	set_pte_at(&init_mm, ea, ptep, pfn_pte(pa >> PAGE_SHIFT, flags));
103	smp_wmb();
104	return 0;
105	}
106
107	static void __init radix_init_pgtable(void)
108	{
109	int loop_count;
110	u64 base, end, start_addr;
111	unsigned long rts_field;
112	struct memblock_region *reg;
113	unsigned long linear_page_size;
114
115	/* We don't support slb for radix */
116	mmu_slb_size = 0;
117	/*
118	* Create the linear mapping, using standard page size for now
119	*/
120	loop_count = 0;
121	for_each_memblock(memory, reg) {
122
123	start_addr = reg->base;
124
125	redo:
126	if (loop_count < 1 && mmu_psize_defs[MMU_PAGE_1G].shift)
127	linear_page_size = PUD_SIZE;
128	else if (loop_count < 2 && mmu_psize_defs[MMU_PAGE_2M].shift)
129	linear_page_size = PMD_SIZE;
130	else
131	linear_page_size = PAGE_SIZE;
132
133	base = _ALIGN_UP(start_addr, linear_page_size);
134	end = _ALIGN_DOWN(reg->base + reg->size, linear_page_size);
135
136	pr_info("Mapping range 0x%lx - 0x%lx with 0x%lx\n",
137	(unsigned long)base, (unsigned long)end,
138	linear_page_size);
139
140	while (base < end) {
141	radix__map_kernel_page((unsigned long)__va(base),
142	base, PAGE_KERNEL_X,
143	linear_page_size);
144	base += linear_page_size;
145	}
146	/*
147	* map the rest using lower page size
148	*/
149	if (end < reg->base + reg->size) {
150	start_addr = end;
151	loop_count++;
152	goto redo;
153	}
154	}
155	/*
156	* Allocate Partition table and process table for the
157	* host.
158	*/
159	BUILD_BUG_ON_MSG((PRTB_SIZE_SHIFT > 23), "Process table size too large.");
160	process_tb = early_alloc_pgtable(1UL << PRTB_SIZE_SHIFT);
161	/*
162	* Fill in the process table.
2bfd65e4	163	*/
b23d9c5b	164	rts_field = radix__get_tree_size();
2bfd65e4 AK	165	process_tb->prtb0 = cpu_to_be64(rts_field \| __pa(init_mm.pgd) \| RADIX_PGD_INDEX_SIZE);
	166	/*
	167	* Fill in the partition table. We are suppose to use effective address
	168	* of process table here. But our linear mapping also enable us to use
	169	* physical address here.
	170	*/
	171	ppc_md.update_partition_table(__pa(process_tb) \| (PRTB_SIZE_SHIFT - 12) \| PATB_GR);
	172	pr_info("Process table %p and radix root for kernel: %p\n", process_tb, init_mm.pgd);
	173	}
	174
	175	static void __init radix_init_partition_table(void)
	176	{
	177	unsigned long rts_field;
b23d9c5b AK	178
b23d9c5b AK	179	rts_field = radix__get_tree_size();
2bfd65e4 AK	180
	181	BUILD_BUG_ON_MSG((PATB_SIZE_SHIFT > 24), "Partition table size too large.");
	182	partition_tb = early_alloc_pgtable(1UL << PATB_SIZE_SHIFT);
	183	partition_tb->patb0 = cpu_to_be64(rts_field \| __pa(init_mm.pgd) \|
	184	RADIX_PGD_INDEX_SIZE \| PATB_HR);
56547411 AK	185	pr_info("Initializing Radix MMU\n");
56547411 AK	186	pr_info("Partition table %p\n", partition_tb);
2bfd65e4 AK	187
	188	memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
	189	/*
	190	* update partition table control register,
	191	* 64 K size.
	192	*/
	193	mtspr(SPRN_PTCR, __pa(partition_tb) \| (PATB_SIZE_SHIFT - 12));
	194	}
	195
	196	void __init radix_init_native(void)
	197	{
	198	ppc_md.update_partition_table = native_update_partition_table;
	199	}
	200
	201	static int __init get_idx_from_shift(unsigned int shift)
	202	{
	203	int idx = -1;
	204
	205	switch (shift) {
	206	case 0xc:
	207	idx = MMU_PAGE_4K;
	208	break;
	209	case 0x10:
	210	idx = MMU_PAGE_64K;
	211	break;
	212	case 0x15:
	213	idx = MMU_PAGE_2M;
	214	break;
	215	case 0x1e:
	216	idx = MMU_PAGE_1G;
	217	break;
	218	}
	219	return idx;
	220	}
	221
	222	static int __init radix_dt_scan_page_sizes(unsigned long node,
	223	const char *uname, int depth,
	224	void *data)
	225	{
	226	int size = 0;
	227	int shift, idx;
	228	unsigned int ap;
	229	const __be32 *prop;
	230	const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
	231
	232	/* We are scanning "cpu" nodes only */
	233	if (type == NULL \|\| strcmp(type, "cpu") != 0)
	234	return 0;
	235
	236	prop = of_get_flat_dt_prop(node, "ibm,processor-radix-AP-encodings", &size);
	237	if (!prop)
	238	return 0;
	239
	240	pr_info("Page sizes from device-tree:\n");
	241	for (; size >= 4; size -= 4, ++prop) {
	242
	243	struct mmu_psize_def *def;
	244
	245	/* top 3 bit is AP encoding */
	246	shift = be32_to_cpu(prop[0]) & ~(0xe << 28);
	247	ap = be32_to_cpu(prop[0]) >> 29;
	248	pr_info("Page size sift = %d AP=0x%x\n", shift, ap);
	249
	250	idx = get_idx_from_shift(shift);
251	if (idx < 0)
252	continue;
253
254	def = &mmu_psize_defs[idx];
255	def->shift = shift;
256	def->ap = ap;
257	}
258
259	/* needed ? */
260	cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
261	return 1;
262	}
263
264	static void __init radix_init_page_sizes(void)
265	{
266	int rc;
267
268	/*
269	* Try to find the available page sizes in the device-tree
270	*/
271	rc = of_scan_flat_dt(radix_dt_scan_page_sizes, NULL);
272	if (rc != 0) /* Found */
273	goto found;
274	/*
275	* let's assume we have page 4k and 64k support
276	*/
277	mmu_psize_defs[MMU_PAGE_4K].shift = 12;
278	mmu_psize_defs[MMU_PAGE_4K].ap = 0x0;
279
280	mmu_psize_defs[MMU_PAGE_64K].shift = 16;
281	mmu_psize_defs[MMU_PAGE_64K].ap = 0x5;
282	found:
283	#ifdef CONFIG_SPARSEMEM_VMEMMAP
284	if (mmu_psize_defs[MMU_PAGE_2M].shift) {
285	/*
286	* map vmemmap using 2M if available
287	*/
288	mmu_vmemmap_psize = MMU_PAGE_2M;
289	}
290	#endif /* CONFIG_SPARSEMEM_VMEMMAP */
291	return;
292	}
293
294	void __init radix__early_init_mmu(void)
295	{
296	unsigned long lpcr;
2bfd65e4 AK	297
	298	#ifdef CONFIG_PPC_64K_PAGES
	299	/* PAGE_SIZE mappings */
	300	mmu_virtual_psize = MMU_PAGE_64K;
	301	#else
	302	mmu_virtual_psize = MMU_PAGE_4K;
	303	#endif
	304
	305	#ifdef CONFIG_SPARSEMEM_VMEMMAP
	306	/* vmemmap mapping */
	307	mmu_vmemmap_psize = mmu_virtual_psize;
	308	#endif
	309	/*
	310	* initialize page table size
	311	*/
	312	__pte_index_size = RADIX_PTE_INDEX_SIZE;
	313	__pmd_index_size = RADIX_PMD_INDEX_SIZE;
	314	__pud_index_size = RADIX_PUD_INDEX_SIZE;
	315	__pgd_index_size = RADIX_PGD_INDEX_SIZE;
	316	__pmd_cache_index = RADIX_PMD_INDEX_SIZE;
	317	__pte_table_size = RADIX_PTE_TABLE_SIZE;
	318	__pmd_table_size = RADIX_PMD_TABLE_SIZE;
	319	__pud_table_size = RADIX_PUD_TABLE_SIZE;
	320	__pgd_table_size = RADIX_PGD_TABLE_SIZE;
	321
a2f41eb9 AK	322	__pmd_val_bits = RADIX_PMD_VAL_BITS;
	323	__pud_val_bits = RADIX_PUD_VAL_BITS;
	324	__pgd_val_bits = RADIX_PGD_VAL_BITS;
2bfd65e4	325
d6a9996e AK	326	__kernel_virt_start = RADIX_KERN_VIRT_START;
	327	__kernel_virt_size = RADIX_KERN_VIRT_SIZE;
	328	__vmalloc_start = RADIX_VMALLOC_START;
	329	__vmalloc_end = RADIX_VMALLOC_END;
	330	vmemmap = (struct page *)RADIX_VMEMMAP_BASE;
	331	ioremap_bot = IOREMAP_BASE;
bfa37087 DS	332
	333	#ifdef CONFIG_PCI
	334	pci_io_base = ISA_IO_BASE;
	335	#endif
	336
5ed7ecd0 AK	337	/*
	338	* For now radix also use the same frag size
	339	*/
	340	__pte_frag_nr = H_PTE_FRAG_NR;
	341	__pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT;
d6a9996e	342
a2f41eb9	343	radix_init_page_sizes();
d6c88600 AK	344	if (!firmware_has_feature(FW_FEATURE_LPAR)) {
d6c88600 AK	345	lpcr = mfspr(SPRN_LPCR);
bf16cdf4	346	mtspr(SPRN_LPCR, lpcr \| LPCR_UPRT \| LPCR_HR);
2bfd65e4	347	radix_init_partition_table();
d6c88600	348	}
2bfd65e4 AK	349
	350	radix_init_pgtable();
	351	}
	352
	353	void radix__early_init_mmu_secondary(void)
	354	{
	355	unsigned long lpcr;
	356	/*
d6c88600	357	* update partition table control register and UPRT
2bfd65e4	358	*/
d6c88600 AK	359	if (!firmware_has_feature(FW_FEATURE_LPAR)) {
d6c88600 AK	360	lpcr = mfspr(SPRN_LPCR);
bf16cdf4	361	mtspr(SPRN_LPCR, lpcr \| LPCR_UPRT \| LPCR_HR);
d6c88600	362
2bfd65e4 AK	363	mtspr(SPRN_PTCR,
2bfd65e4 AK	364	__pa(partition_tb) \| (PATB_SIZE_SHIFT - 12));
d6c88600	365	}
2bfd65e4 AK	366	}
	367
	368	void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base,
	369	phys_addr_t first_memblock_size)
	370	{
177ba7c6 AK	371	/* We don't currently support the first MEMBLOCK not mapping 0
	372	* physical on those processors
	373	*/
	374	BUG_ON(first_memblock_base != 0);
	375	/*
	376	* We limit the allocation that depend on ppc64_rma_size
	377	* to first_memblock_size. We also clamp it to 1GB to
	378	* avoid some funky things such as RTAS bugs.
	379	*
	380	* On radix config we really don't have a limitation
	381	* on real mode access. But keeping it as above works
	382	* well enough.
	383	*/
	384	ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000);
	385	/*
	386	* Finally limit subsequent allocations. We really don't want
	387	* to limit the memblock allocations to rma_size. FIXME!! should
	388	* we even limit at all ?
	389	*/
2bfd65e4 AK	390	memblock_set_current_limit(first_memblock_base + first_memblock_size);
2bfd65e4 AK	391	}
d9225ad9 AK	392
	393	#ifdef CONFIG_SPARSEMEM_VMEMMAP
	394	int __meminit radix__vmemmap_create_mapping(unsigned long start,
	395	unsigned long page_size,
	396	unsigned long phys)
	397	{
	398	/* Create a PTE encoding */
	399	unsigned long flags = _PAGE_PRESENT \| _PAGE_ACCESSED \| _PAGE_KERNEL_RW;
	400
	401	BUG_ON(radix__map_kernel_page(start, phys, __pgprot(flags), page_size));
	402	return 0;
	403	}
	404
	405	#ifdef CONFIG_MEMORY_HOTPLUG
	406	void radix__vmemmap_remove_mapping(unsigned long start, unsigned long page_size)
	407	{
	408	/* FIXME!! intel does more. We should free page tables mapping vmemmap ? */
	409	}
	410	#endif
	411	#endif
bde3eb62 AK	412
	413	#ifdef CONFIG_TRANSPARENT_HUGEPAGE
	414
	415	unsigned long radix__pmd_hugepage_update(struct mm_struct *mm, unsigned long addr,
	416	pmd_t *pmdp, unsigned long clr,
	417	unsigned long set)
	418	{
	419	unsigned long old;
	420
	421	#ifdef CONFIG_DEBUG_VM
	422	WARN_ON(!radix__pmd_trans_huge(*pmdp));
	423	assert_spin_locked(&mm->page_table_lock);
	424	#endif
	425
	426	old = radix__pte_update(mm, addr, (pte_t *)pmdp, clr, set, 1);
	427	trace_hugepage_update(addr, old, clr, set);
	428
	429	return old;
	430	}
	431
	432	pmd_t radix__pmdp_collapse_flush(struct vm_area_struct *vma, unsigned long address,
	433	pmd_t *pmdp)
	434
	435	{
	436	pmd_t pmd;
	437
	438	VM_BUG_ON(address & ~HPAGE_PMD_MASK);
	439	VM_BUG_ON(radix__pmd_trans_huge(*pmdp));
	440	/*
	441	* khugepaged calls this for normal pmd
	442	*/
	443	pmd = *pmdp;
	444	pmd_clear(pmdp);
	445	/FIXME!! Verify whether we need this kick below /
	446	kick_all_cpus_sync();
	447	flush_tlb_range(vma, address, address + HPAGE_PMD_SIZE);
	448	return pmd;
	449	}
	450
	451	/*
	452	* For us pgtable_t is pte_t *. Inorder to save the deposisted
	453	* page table, we consider the allocated page table as a list
	454	* head. On withdraw we need to make sure we zero out the used
	455	* list_head memory area.
	456	*/
	457	void radix__pgtable_trans_huge_deposit(struct mm_struct mm, pmd_t pmdp,
	458	pgtable_t pgtable)
	459	{
	460	struct list_head lh = (struct list_head ) pgtable;
	461
	462	assert_spin_locked(pmd_lockptr(mm, pmdp));
	463
	464	/* FIFO */
	465	if (!pmd_huge_pte(mm, pmdp))
	466	INIT_LIST_HEAD(lh);
	467	else
	468	list_add(lh, (struct list_head *) pmd_huge_pte(mm, pmdp));
	469	pmd_huge_pte(mm, pmdp) = pgtable;
	470	}
	471
	472	pgtable_t radix__pgtable_trans_huge_withdraw(struct mm_struct mm, pmd_t pmdp)
	473	{
	474	pte_t *ptep;
	475	pgtable_t pgtable;
476	struct list_head *lh;
477
478	assert_spin_locked(pmd_lockptr(mm, pmdp));
479
480	/* FIFO */
481	pgtable = pmd_huge_pte(mm, pmdp);
482	lh = (struct list_head *) pgtable;
483	if (list_empty(lh))
484	pmd_huge_pte(mm, pmdp) = NULL;
485	else {
486	pmd_huge_pte(mm, pmdp) = (pgtable_t) lh->next;
487	list_del(lh);
488	}
489	ptep = (pte_t *) pgtable;
490	*ptep = __pte(0);
491	ptep++;
492	*ptep = __pte(0);
493	return pgtable;
494	}
495
496
497	pmd_t radix__pmdp_huge_get_and_clear(struct mm_struct *mm,
498	unsigned long addr, pmd_t *pmdp)
499	{
500	pmd_t old_pmd;
501	unsigned long old;
502
503	old = radix__pmd_hugepage_update(mm, addr, pmdp, ~0UL, 0);
504	old_pmd = __pmd(old);
505	/*
506	* Serialize against find_linux_pte_or_hugepte which does lock-less
507	* lookup in page tables with local interrupts disabled. For huge pages
508	* it casts pmd_t to pte_t. Since format of pte_t is different from
509	* pmd_t we want to prevent transit from pmd pointing to page table
510	* to pmd pointing to huge page (and back) while interrupts are disabled.
511	* We clear pmd to possibly replace it with page table pointer in
512	* different code paths. So make sure we wait for the parallel
513	* find_linux_pte_or_hugepage to finish.
514	*/
515	kick_all_cpus_sync();
516	return old_pmd;
517	}
518
519	int radix__has_transparent_hugepage(void)
520	{
521	/* For radix 2M at PMD level means thp */
522	if (mmu_psize_defs[MMU_PAGE_2M].shift == PMD_SHIFT)
523	return 1;
524	return 0;
525	}
526	#endif /* CONFIG_TRANSPARENT_HUGEPAGE */