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[mirror_ubuntu-bionic-kernel.git] / arch / powerpc / mm / pgtable-radix.c
CommitLineData
2bfd65e4
AK		 1/*
2 * Page table handling routines for radix page table.
3 *
4 * Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
589ee628 11#include <linux/sched/mm.h>
2bfd65e4
AK		 12#include <linux/memblock.h>
13#include <linux/of_fdt.h>
14
15#include <asm/pgtable.h>
16#include <asm/pgalloc.h>
17#include <asm/dma.h>
18#include <asm/machdep.h>
19#include <asm/mmu.h>
20#include <asm/firmware.h>
1d0761d2 21#include <asm/powernv.h>
2bfd65e4 22
bde3eb62
AK		 23#include <trace/events/thp.h>
24
83209bc8
AK		 25static int native_register_process_table(unsigned long base, unsigned long pg_sz,
26 unsigned long table_size)
2bfd65e4 27{
83209bc8
AK		 28 unsigned long patb1 = base | table_size | PATB_GR;
29
2bfd65e4
AK		 30 partition_tb->patb1 = cpu_to_be64(patb1);
31 return 0;
32}
33
34static __ref void *early_alloc_pgtable(unsigned long size)
35{
36 void *pt;
37
38 pt = __va(memblock_alloc_base(size, size, MEMBLOCK_ALLOC_ANYWHERE));
39 memset(pt, 0, size);
40
41 return pt;
42}
43
44int radix__map_kernel_page(unsigned long ea, unsigned long pa,
45 pgprot_t flags,
46 unsigned int map_page_size)
47{
48 pgd_t *pgdp;
49 pud_t *pudp;
50 pmd_t *pmdp;
51 pte_t *ptep;
52 /*
53 * Make sure task size is correct as per the max adddr
54 */
55 BUILD_BUG_ON(TASK_SIZE_USER64 > RADIX_PGTABLE_RANGE);
56 if (slab_is_available()) {
57 pgdp = pgd_offset_k(ea);
58 pudp = pud_alloc(&init_mm, pgdp, ea);
59 if (!pudp)
60 return -ENOMEM;
61 if (map_page_size == PUD_SIZE) {
62 ptep = (pte_t *)pudp;
63 goto set_the_pte;
64 }
65 pmdp = pmd_alloc(&init_mm, pudp, ea);
66 if (!pmdp)
67 return -ENOMEM;
68 if (map_page_size == PMD_SIZE) {
a0615a16 69 ptep = pmdp_ptep(pmdp);
2bfd65e4
AK		 70 goto set_the_pte;
71 }
72 ptep = pte_alloc_kernel(pmdp, ea);
73 if (!ptep)
74 return -ENOMEM;
75 } else {
76 pgdp = pgd_offset_k(ea);
77 if (pgd_none(*pgdp)) {
78 pudp = early_alloc_pgtable(PUD_TABLE_SIZE);
79 BUG_ON(pudp == NULL);
80 pgd_populate(&init_mm, pgdp, pudp);
81 }
82 pudp = pud_offset(pgdp, ea);
83 if (map_page_size == PUD_SIZE) {
84 ptep = (pte_t *)pudp;
85 goto set_the_pte;
86 }
87 if (pud_none(*pudp)) {
88 pmdp = early_alloc_pgtable(PMD_TABLE_SIZE);
89 BUG_ON(pmdp == NULL);
90 pud_populate(&init_mm, pudp, pmdp);
91 }
92 pmdp = pmd_offset(pudp, ea);
93 if (map_page_size == PMD_SIZE) {
a0615a16 94 ptep = pmdp_ptep(pmdp);
2bfd65e4
AK		 95 goto set_the_pte;
96 }
97 if (!pmd_present(*pmdp)) {
98 ptep = early_alloc_pgtable(PAGE_SIZE);
99 BUG_ON(ptep == NULL);
100 pmd_populate_kernel(&init_mm, pmdp, ptep);
101 }
102 ptep = pte_offset_kernel(pmdp, ea);
103 }
104
105set_the_pte:
106 set_pte_at(&init_mm, ea, ptep, pfn_pte(pa >> PAGE_SHIFT, flags));
107 smp_wmb();
108 return 0;
109}
110
b5200ec9
RA		 111static inline void __meminit print_mapping(unsigned long start,
112 unsigned long end,
113 unsigned long size)
114{
115 if (end <= start)
116 return;
117
118 pr_info("Mapped range 0x%lx - 0x%lx with 0x%lx\n", start, end, size);
119}
120
121static int __meminit create_physical_mapping(unsigned long start,
122 unsigned long end)
123{
124 unsigned long addr, mapping_size = 0;
125
126 start = _ALIGN_UP(start, PAGE_SIZE);
127 for (addr = start; addr < end; addr += mapping_size) {
128 unsigned long gap, previous_size;
129 int rc;
130
131 gap = end - addr;
132 previous_size = mapping_size;
133
134 if (IS_ALIGNED(addr, PUD_SIZE) && gap >= PUD_SIZE &&
135 mmu_psize_defs[MMU_PAGE_1G].shift)
136 mapping_size = PUD_SIZE;
137 else if (IS_ALIGNED(addr, PMD_SIZE) && gap >= PMD_SIZE &&
138 mmu_psize_defs[MMU_PAGE_2M].shift)
139 mapping_size = PMD_SIZE;
140 else
141 mapping_size = PAGE_SIZE;
142
143 if (mapping_size != previous_size) {
144 print_mapping(start, addr, previous_size);
145 start = addr;
146 }
147
148 rc = radix__map_kernel_page((unsigned long)__va(addr), addr,
149 PAGE_KERNEL_X, mapping_size);
150 if (rc)
151 return rc;
152 }
153
154 print_mapping(start, addr, mapping_size);
155 return 0;
156}
157
2bfd65e4
AK		 158static void __init radix_init_pgtable(void)
159{
2bfd65e4
AK		 160 unsigned long rts_field;
161 struct memblock_region *reg;
2bfd65e4
AK		 162
163 /* We don't support slb for radix */
164 mmu_slb_size = 0;
165 /*
166 * Create the linear mapping, using standard page size for now
167 */
b5200ec9
RA		 168 for_each_memblock(memory, reg)
169 WARN_ON(create_physical_mapping(reg->base,
170 reg->base + reg->size));
2bfd65e4
AK		 171 /*
172 * Allocate Partition table and process table for the
173 * host.
174 */
555c1632 175 BUILD_BUG_ON_MSG((PRTB_SIZE_SHIFT > 36), "Process table size too large.");
2bfd65e4
AK		 176 process_tb = early_alloc_pgtable(1UL << PRTB_SIZE_SHIFT);
177 /*
178 * Fill in the process table.
2bfd65e4 179 */
b23d9c5b 180 rts_field = radix__get_tree_size();
2bfd65e4
AK		 181 process_tb->prtb0 = cpu_to_be64(rts_field | __pa(init_mm.pgd) | RADIX_PGD_INDEX_SIZE);
182 /*
183 * Fill in the partition table. We are suppose to use effective address
184 * of process table here. But our linear mapping also enable us to use
185 * physical address here.
186 */
eea8148c 187 register_process_table(__pa(process_tb), 0, PRTB_SIZE_SHIFT - 12);
2bfd65e4 188 pr_info("Process table %p and radix root for kernel: %p\n", process_tb, init_mm.pgd);
7a70d728
PM		 189 asm volatile("ptesync" : : : "memory");
190 asm volatile(PPC_TLBIE_5(%0,%1,2,1,1) : :
191 "r" (TLBIEL_INVAL_SET_LPID), "r" (0));
192 asm volatile("eieio; tlbsync; ptesync" : : : "memory");
2bfd65e4
AK		 193}
194
195static void __init radix_init_partition_table(void)
196{
9d661958 197 unsigned long rts_field, dw0;
b23d9c5b 198
9d661958 199 mmu_partition_table_init();
b23d9c5b 200 rts_field = radix__get_tree_size();
9d661958
PM		 201 dw0 = rts_field | __pa(init_mm.pgd) | RADIX_PGD_INDEX_SIZE | PATB_HR;
202 mmu_partition_table_set_entry(0, dw0, 0);
2bfd65e4 203
56547411
AK		 204 pr_info("Initializing Radix MMU\n");
205 pr_info("Partition table %p\n", partition_tb);
2bfd65e4
AK		 206}
207
208void __init radix_init_native(void)
209{
eea8148c 210 register_process_table = native_register_process_table;
2bfd65e4
AK		 211}
212
213static int __init get_idx_from_shift(unsigned int shift)
214{
215 int idx = -1;
216
217 switch (shift) {
218 case 0xc:
219 idx = MMU_PAGE_4K;
220 break;
221 case 0x10:
222 idx = MMU_PAGE_64K;
223 break;
224 case 0x15:
225 idx = MMU_PAGE_2M;
226 break;
227 case 0x1e:
228 idx = MMU_PAGE_1G;
229 break;
230 }
231 return idx;
232}
233
234static int __init radix_dt_scan_page_sizes(unsigned long node,
235 const char *uname, int depth,
236 void *data)
237{
238 int size = 0;
239 int shift, idx;
240 unsigned int ap;
241 const __be32 *prop;
242 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
243
244 /* We are scanning "cpu" nodes only */
245 if (type == NULL || strcmp(type, "cpu") != 0)
246 return 0;
247
248 prop = of_get_flat_dt_prop(node, "ibm,processor-radix-AP-encodings", &size);
249 if (!prop)
250 return 0;
251
252 pr_info("Page sizes from device-tree:\n");
253 for (; size >= 4; size -= 4, ++prop) {
254
255 struct mmu_psize_def *def;
256
257 /* top 3 bit is AP encoding */
258 shift = be32_to_cpu(prop[0]) & ~(0xe << 28);
259 ap = be32_to_cpu(prop[0]) >> 29;
ac8d3818 260 pr_info("Page size shift = %d AP=0x%x\n", shift, ap);
2bfd65e4
AK		 261
262 idx = get_idx_from_shift(shift);
263 if (idx < 0)
264 continue;
265
266 def = &mmu_psize_defs[idx];
267 def->shift = shift;
268 def->ap = ap;
269 }
270
271 /* needed ? */
272 cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
273 return 1;
274}
275
2537b09c 276void __init radix__early_init_devtree(void)
2bfd65e4
AK		 277{
278 int rc;
279
280 /*
281 * Try to find the available page sizes in the device-tree
282 */
283 rc = of_scan_flat_dt(radix_dt_scan_page_sizes, NULL);
284 if (rc != 0) /* Found */
285 goto found;
286 /*
287 * let's assume we have page 4k and 64k support
288 */
289 mmu_psize_defs[MMU_PAGE_4K].shift = 12;
290 mmu_psize_defs[MMU_PAGE_4K].ap = 0x0;
291
292 mmu_psize_defs[MMU_PAGE_64K].shift = 16;
293 mmu_psize_defs[MMU_PAGE_64K].ap = 0x5;
294found:
295#ifdef CONFIG_SPARSEMEM_VMEMMAP
296 if (mmu_psize_defs[MMU_PAGE_2M].shift) {
297 /*
298 * map vmemmap using 2M if available
299 */
300 mmu_vmemmap_psize = MMU_PAGE_2M;
301 }
302#endif /* CONFIG_SPARSEMEM_VMEMMAP */
303 return;
304}
305
ad410674
AK		 306static void update_hid_for_radix(void)
307{
308 unsigned long hid0;
309 unsigned long rb = 3UL << PPC_BITLSHIFT(53); /* IS = 3 */
310
311 asm volatile("ptesync": : :"memory");
312 /* prs = 0, ric = 2, rs = 0, r = 1 is = 3 */
313 asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
314 : : "r"(rb), "i"(1), "i"(0), "i"(2), "r"(0) : "memory");
315 /* prs = 1, ric = 2, rs = 0, r = 1 is = 3 */
316 asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
317 : : "r"(rb), "i"(1), "i"(1), "i"(2), "r"(0) : "memory");
318 asm volatile("eieio; tlbsync; ptesync; isync; slbia": : :"memory");
319 /*
320 * now switch the HID
321 */
322 hid0 = mfspr(SPRN_HID0);
323 hid0 |= HID0_POWER9_RADIX;
324 mtspr(SPRN_HID0, hid0);
325 asm volatile("isync": : :"memory");
326
327 /* Wait for it to happen */
328 while (!(mfspr(SPRN_HID0) & HID0_POWER9_RADIX))
329 cpu_relax();
330}
331
ee97b6b9
BS		 332static void radix_init_amor(void)
333{
334 /*
335 * In HV mode, we init AMOR (Authority Mask Override Register) so that
336 * the hypervisor and guest can setup IAMR (Instruction Authority Mask
337 * Register), enable key 0 and set it to 1.
338 *
339 * AMOR = 0b1100 .... 0000 (Mask for key 0 is 11)
340 */
341 mtspr(SPRN_AMOR, (3ul << 62));
342}
343
3b10d009
BS		 344static void radix_init_iamr(void)
345{
346 unsigned long iamr;
347
348 /*
349 * The IAMR should set to 0 on DD1.
350 */
351 if (cpu_has_feature(CPU_FTR_POWER9_DD1))
352 iamr = 0;
353 else
354 iamr = (1ul << 62);
355
356 /*
357 * Radix always uses key0 of the IAMR to determine if an access is
358 * allowed. We set bit 0 (IBM bit 1) of key0, to prevent instruction
359 * fetch.
360 */
361 mtspr(SPRN_IAMR, iamr);
362}
363
2bfd65e4
AK		 364void __init radix__early_init_mmu(void)
365{
366 unsigned long lpcr;
2bfd65e4
AK		 367
368#ifdef CONFIG_PPC_64K_PAGES
369 /* PAGE_SIZE mappings */
370 mmu_virtual_psize = MMU_PAGE_64K;
371#else
372 mmu_virtual_psize = MMU_PAGE_4K;
373#endif
374
375#ifdef CONFIG_SPARSEMEM_VMEMMAP
376 /* vmemmap mapping */
377 mmu_vmemmap_psize = mmu_virtual_psize;
378#endif
379 /*
380 * initialize page table size
381 */
382 __pte_index_size = RADIX_PTE_INDEX_SIZE;
383 __pmd_index_size = RADIX_PMD_INDEX_SIZE;
384 __pud_index_size = RADIX_PUD_INDEX_SIZE;
385 __pgd_index_size = RADIX_PGD_INDEX_SIZE;
386 __pmd_cache_index = RADIX_PMD_INDEX_SIZE;
387 __pte_table_size = RADIX_PTE_TABLE_SIZE;
388 __pmd_table_size = RADIX_PMD_TABLE_SIZE;
389 __pud_table_size = RADIX_PUD_TABLE_SIZE;
390 __pgd_table_size = RADIX_PGD_TABLE_SIZE;
391
a2f41eb9
AK		 392 __pmd_val_bits = RADIX_PMD_VAL_BITS;
393 __pud_val_bits = RADIX_PUD_VAL_BITS;
394 __pgd_val_bits = RADIX_PGD_VAL_BITS;
2bfd65e4 395
d6a9996e
AK		 396 __kernel_virt_start = RADIX_KERN_VIRT_START;
397 __kernel_virt_size = RADIX_KERN_VIRT_SIZE;
398 __vmalloc_start = RADIX_VMALLOC_START;
399 __vmalloc_end = RADIX_VMALLOC_END;
400 vmemmap = (struct page *)RADIX_VMEMMAP_BASE;
401 ioremap_bot = IOREMAP_BASE;
bfa37087
DS		 402
403#ifdef CONFIG_PCI
404 pci_io_base = ISA_IO_BASE;
405#endif
406
5ed7ecd0
AK		 407 /*
408 * For now radix also use the same frag size
409 */
410 __pte_frag_nr = H_PTE_FRAG_NR;
411 __pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT;
d6a9996e 412
d6c88600 413 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
166dd7d3 414 radix_init_native();
ad410674
AK		 415 if (cpu_has_feature(CPU_FTR_POWER9_DD1))
416 update_hid_for_radix();
d6c88600 417 lpcr = mfspr(SPRN_LPCR);
bf16cdf4 418 mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
2bfd65e4 419 radix_init_partition_table();
ee97b6b9 420 radix_init_amor();
cc3d2940
PM		 421 } else {
422 radix_init_pseries();
d6c88600 423 }
2bfd65e4 424
9d661958
PM		 425 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
426
3b10d009 427 radix_init_iamr();
2bfd65e4
AK		 428 radix_init_pgtable();
429}
430
431void radix__early_init_mmu_secondary(void)
432{
433 unsigned long lpcr;
434 /*
d6c88600 435 * update partition table control register and UPRT
2bfd65e4 436 */
d6c88600 437 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
cac4a185
AK		 438
439 if (cpu_has_feature(CPU_FTR_POWER9_DD1))
440 update_hid_for_radix();
441
d6c88600 442 lpcr = mfspr(SPRN_LPCR);
bf16cdf4 443 mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
d6c88600 444
2bfd65e4
AK		 445 mtspr(SPRN_PTCR,
446 __pa(partition_tb) | (PATB_SIZE_SHIFT - 12));
ee97b6b9 447 radix_init_amor();
d6c88600 448 }
3b10d009 449 radix_init_iamr();
2bfd65e4
AK		 450}
451
fe036a06
BH		 452void radix__mmu_cleanup_all(void)
453{
454 unsigned long lpcr;
455
456 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
457 lpcr = mfspr(SPRN_LPCR);
458 mtspr(SPRN_LPCR, lpcr & ~LPCR_UPRT);
459 mtspr(SPRN_PTCR, 0);
1d0761d2 460 powernv_set_nmmu_ptcr(0);
fe036a06
BH		 461 radix__flush_tlb_all();
462 }
463}
464
2bfd65e4
AK		 465void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base,
466 phys_addr_t first_memblock_size)
467{
177ba7c6
AK		 468 /* We don't currently support the first MEMBLOCK not mapping 0
469 * physical on those processors
470 */
471 BUG_ON(first_memblock_base != 0);
472 /*
473 * We limit the allocation that depend on ppc64_rma_size
474 * to first_memblock_size. We also clamp it to 1GB to
475 * avoid some funky things such as RTAS bugs.
476 *
477 * On radix config we really don't have a limitation
478 * on real mode access. But keeping it as above works
479 * well enough.
480 */
481 ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000);
482 /*
483 * Finally limit subsequent allocations. We really don't want
484 * to limit the memblock allocations to rma_size. FIXME!! should
485 * we even limit at all ?
486 */
2bfd65e4
AK		 487 memblock_set_current_limit(first_memblock_base + first_memblock_size);
488}
d9225ad9 489
6cc27341 490#ifdef CONFIG_MEMORY_HOTPLUG
4b5d62ca
RA		 491static void free_pte_table(pte_t *pte_start, pmd_t *pmd)
492{
493 pte_t *pte;
494 int i;
495
496 for (i = 0; i < PTRS_PER_PTE; i++) {
497 pte = pte_start + i;
498 if (!pte_none(*pte))
499 return;
500 }
501
502 pte_free_kernel(&init_mm, pte_start);
503 pmd_clear(pmd);
504}
505
506static void free_pmd_table(pmd_t *pmd_start, pud_t *pud)
507{
508 pmd_t *pmd;
509 int i;
510
511 for (i = 0; i < PTRS_PER_PMD; i++) {
512 pmd = pmd_start + i;
513 if (!pmd_none(*pmd))
514 return;
515 }
516
517 pmd_free(&init_mm, pmd_start);
518 pud_clear(pud);
519}
520
521static void remove_pte_table(pte_t *pte_start, unsigned long addr,
522 unsigned long end)
523{
524 unsigned long next;
525 pte_t *pte;
526
527 pte = pte_start + pte_index(addr);
528 for (; addr < end; addr = next, pte++) {
529 next = (addr + PAGE_SIZE) & PAGE_MASK;
530 if (next > end)
531 next = end;
532
533 if (!pte_present(*pte))
534 continue;
535
0d0a4bc2
RA		 536 if (!PAGE_ALIGNED(addr) || !PAGE_ALIGNED(next)) {
537 /*
538 * The vmemmap_free() and remove_section_mapping()
539 * codepaths call us with aligned addresses.
540 */
541 WARN_ONCE(1, "%s: unaligned range\n", __func__);
542 continue;
543 }
544
4b5d62ca
RA		 545 pte_clear(&init_mm, addr, pte);
546 }
547}
548
549static void remove_pmd_table(pmd_t *pmd_start, unsigned long addr,
550 unsigned long end)
551{
552 unsigned long next;
553 pte_t *pte_base;
554 pmd_t *pmd;
555
556 pmd = pmd_start + pmd_index(addr);
557 for (; addr < end; addr = next, pmd++) {
558 next = pmd_addr_end(addr, end);
559
560 if (!pmd_present(*pmd))
561 continue;
562
563 if (pmd_huge(*pmd)) {
0d0a4bc2
RA		 564 if (!IS_ALIGNED(addr, PMD_SIZE) ||
565 !IS_ALIGNED(next, PMD_SIZE)) {
566 WARN_ONCE(1, "%s: unaligned range\n", __func__);
567 continue;
568 }
569
4b5d62ca
RA		 570 pte_clear(&init_mm, addr, (pte_t *)pmd);
571 continue;
572 }
573
574 pte_base = (pte_t *)pmd_page_vaddr(*pmd);
575 remove_pte_table(pte_base, addr, next);
576 free_pte_table(pte_base, pmd);
577 }
578}
579
580static void remove_pud_table(pud_t *pud_start, unsigned long addr,
581 unsigned long end)
582{
583 unsigned long next;
584 pmd_t *pmd_base;
585 pud_t *pud;
586
587 pud = pud_start + pud_index(addr);
588 for (; addr < end; addr = next, pud++) {
589 next = pud_addr_end(addr, end);
590
591 if (!pud_present(*pud))
592 continue;
593
594 if (pud_huge(*pud)) {
0d0a4bc2
RA		 595 if (!IS_ALIGNED(addr, PUD_SIZE) ||
596 !IS_ALIGNED(next, PUD_SIZE)) {
597 WARN_ONCE(1, "%s: unaligned range\n", __func__);
598 continue;
599 }
600
4b5d62ca
RA		 601 pte_clear(&init_mm, addr, (pte_t *)pud);
602 continue;
603 }
604
605 pmd_base = (pmd_t *)pud_page_vaddr(*pud);
606 remove_pmd_table(pmd_base, addr, next);
607 free_pmd_table(pmd_base, pud);
608 }
609}
610
611static void remove_pagetable(unsigned long start, unsigned long end)
612{
613 unsigned long addr, next;
614 pud_t *pud_base;
615 pgd_t *pgd;
616
617 spin_lock(&init_mm.page_table_lock);
618
619 for (addr = start; addr < end; addr = next) {
620 next = pgd_addr_end(addr, end);
621
622 pgd = pgd_offset_k(addr);
623 if (!pgd_present(*pgd))
624 continue;
625
626 if (pgd_huge(*pgd)) {
0d0a4bc2
RA		 627 if (!IS_ALIGNED(addr, PGDIR_SIZE) ||
628 !IS_ALIGNED(next, PGDIR_SIZE)) {
629 WARN_ONCE(1, "%s: unaligned range\n", __func__);
630 continue;
631 }
632
4b5d62ca
RA		 633 pte_clear(&init_mm, addr, (pte_t *)pgd);
634 continue;
635 }
636
637 pud_base = (pud_t *)pgd_page_vaddr(*pgd);
638 remove_pud_table(pud_base, addr, next);
639 }
640
641 spin_unlock(&init_mm.page_table_lock);
642 radix__flush_tlb_kernel_range(start, end);
643}
644
6cc27341
RA		 645int __ref radix__create_section_mapping(unsigned long start, unsigned long end)
646{
647 return create_physical_mapping(start, end);
648}
4b5d62ca
RA		 649
650int radix__remove_section_mapping(unsigned long start, unsigned long end)
651{
652 remove_pagetable(start, end);
653 return 0;
654}
6cc27341
RA		 655#endif /* CONFIG_MEMORY_HOTPLUG */
656
d9225ad9
AK		 657#ifdef CONFIG_SPARSEMEM_VMEMMAP
658int __meminit radix__vmemmap_create_mapping(unsigned long start,
659 unsigned long page_size,
660 unsigned long phys)
661{
662 /* Create a PTE encoding */
663 unsigned long flags = _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_KERNEL_RW;
664
665 BUG_ON(radix__map_kernel_page(start, phys, __pgprot(flags), page_size));
666 return 0;
667}
668
669#ifdef CONFIG_MEMORY_HOTPLUG
670void radix__vmemmap_remove_mapping(unsigned long start, unsigned long page_size)
671{
0d0a4bc2 672 remove_pagetable(start, start + page_size);
d9225ad9
AK		 673}
674#endif
675#endif
bde3eb62
AK		 676
677#ifdef CONFIG_TRANSPARENT_HUGEPAGE
678
679unsigned long radix__pmd_hugepage_update(struct mm_struct *mm, unsigned long addr,
680 pmd_t *pmdp, unsigned long clr,
681 unsigned long set)
682{
683 unsigned long old;
684
685#ifdef CONFIG_DEBUG_VM
686 WARN_ON(!radix__pmd_trans_huge(*pmdp));
687 assert_spin_locked(&mm->page_table_lock);
688#endif
689
690 old = radix__pte_update(mm, addr, (pte_t *)pmdp, clr, set, 1);
691 trace_hugepage_update(addr, old, clr, set);
692
693 return old;
694}
695
696pmd_t radix__pmdp_collapse_flush(struct vm_area_struct *vma, unsigned long address,
697 pmd_t *pmdp)
698
699{
700 pmd_t pmd;
701
702 VM_BUG_ON(address & ~HPAGE_PMD_MASK);
703 VM_BUG_ON(radix__pmd_trans_huge(*pmdp));
704 /*
705 * khugepaged calls this for normal pmd
706 */
707 pmd = *pmdp;
708 pmd_clear(pmdp);
709 /*FIXME!! Verify whether we need this kick below */
710 kick_all_cpus_sync();
711 flush_tlb_range(vma, address, address + HPAGE_PMD_SIZE);
712 return pmd;
713}
714
715/*
716 * For us pgtable_t is pte_t *. Inorder to save the deposisted
717 * page table, we consider the allocated page table as a list
718 * head. On withdraw we need to make sure we zero out the used
719 * list_head memory area.
720 */
721void radix__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
722 pgtable_t pgtable)
723{
724 struct list_head *lh = (struct list_head *) pgtable;
725
726 assert_spin_locked(pmd_lockptr(mm, pmdp));
727
728 /* FIFO */
729 if (!pmd_huge_pte(mm, pmdp))
730 INIT_LIST_HEAD(lh);
731 else
732 list_add(lh, (struct list_head *) pmd_huge_pte(mm, pmdp));
733 pmd_huge_pte(mm, pmdp) = pgtable;
734}
735
736pgtable_t radix__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp)
737{
738 pte_t *ptep;
739 pgtable_t pgtable;
740 struct list_head *lh;
741
742 assert_spin_locked(pmd_lockptr(mm, pmdp));
743
744 /* FIFO */
745 pgtable = pmd_huge_pte(mm, pmdp);
746 lh = (struct list_head *) pgtable;
747 if (list_empty(lh))
748 pmd_huge_pte(mm, pmdp) = NULL;
749 else {
750 pmd_huge_pte(mm, pmdp) = (pgtable_t) lh->next;
751 list_del(lh);
752 }
753 ptep = (pte_t *) pgtable;
754 *ptep = __pte(0);
755 ptep++;
756 *ptep = __pte(0);
757 return pgtable;
758}
759
760
761pmd_t radix__pmdp_huge_get_and_clear(struct mm_struct *mm,
762 unsigned long addr, pmd_t *pmdp)
763{
764 pmd_t old_pmd;
765 unsigned long old;
766
767 old = radix__pmd_hugepage_update(mm, addr, pmdp, ~0UL, 0);
768 old_pmd = __pmd(old);
769 /*
770 * Serialize against find_linux_pte_or_hugepte which does lock-less
771 * lookup in page tables with local interrupts disabled. For huge pages
772 * it casts pmd_t to pte_t. Since format of pte_t is different from
773 * pmd_t we want to prevent transit from pmd pointing to page table
774 * to pmd pointing to huge page (and back) while interrupts are disabled.
775 * We clear pmd to possibly replace it with page table pointer in
776 * different code paths. So make sure we wait for the parallel
777 * find_linux_pte_or_hugepage to finish.
778 */
779 kick_all_cpus_sync();
780 return old_pmd;
781}
782
783int radix__has_transparent_hugepage(void)
784{
785 /* For radix 2M at PMD level means thp */
786 if (mmu_psize_defs[MMU_PAGE_2M].shift == PMD_SHIFT)
787 return 1;
788 return 0;
789}
790#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
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