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2bfd65e4 AK |
1 | /* |
2 | * Page table handling routines for radix page table. | |
3 | * | |
4 | * Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | #include <linux/sched.h> | |
12 | #include <linux/memblock.h> | |
13 | #include <linux/of_fdt.h> | |
14 | ||
15 | #include <asm/pgtable.h> | |
16 | #include <asm/pgalloc.h> | |
17 | #include <asm/dma.h> | |
18 | #include <asm/machdep.h> | |
19 | #include <asm/mmu.h> | |
20 | #include <asm/firmware.h> | |
1d0761d2 | 21 | #include <asm/powernv.h> |
2bfd65e4 | 22 | |
bde3eb62 AK |
23 | #include <trace/events/thp.h> |
24 | ||
83209bc8 AK |
25 | static int native_register_process_table(unsigned long base, unsigned long pg_sz, |
26 | unsigned long table_size) | |
2bfd65e4 | 27 | { |
83209bc8 AK |
28 | unsigned long patb1 = base | table_size | PATB_GR; |
29 | ||
2bfd65e4 AK |
30 | partition_tb->patb1 = cpu_to_be64(patb1); |
31 | return 0; | |
32 | } | |
33 | ||
34 | static __ref void *early_alloc_pgtable(unsigned long size) | |
35 | { | |
36 | void *pt; | |
37 | ||
38 | pt = __va(memblock_alloc_base(size, size, MEMBLOCK_ALLOC_ANYWHERE)); | |
39 | memset(pt, 0, size); | |
40 | ||
41 | return pt; | |
42 | } | |
43 | ||
44 | int radix__map_kernel_page(unsigned long ea, unsigned long pa, | |
45 | pgprot_t flags, | |
46 | unsigned int map_page_size) | |
47 | { | |
48 | pgd_t *pgdp; | |
49 | pud_t *pudp; | |
50 | pmd_t *pmdp; | |
51 | pte_t *ptep; | |
52 | /* | |
53 | * Make sure task size is correct as per the max adddr | |
54 | */ | |
55 | BUILD_BUG_ON(TASK_SIZE_USER64 > RADIX_PGTABLE_RANGE); | |
56 | if (slab_is_available()) { | |
57 | pgdp = pgd_offset_k(ea); | |
58 | pudp = pud_alloc(&init_mm, pgdp, ea); | |
59 | if (!pudp) | |
60 | return -ENOMEM; | |
61 | if (map_page_size == PUD_SIZE) { | |
62 | ptep = (pte_t *)pudp; | |
63 | goto set_the_pte; | |
64 | } | |
65 | pmdp = pmd_alloc(&init_mm, pudp, ea); | |
66 | if (!pmdp) | |
67 | return -ENOMEM; | |
68 | if (map_page_size == PMD_SIZE) { | |
69 | ptep = (pte_t *)pudp; | |
70 | goto set_the_pte; | |
71 | } | |
72 | ptep = pte_alloc_kernel(pmdp, ea); | |
73 | if (!ptep) | |
74 | return -ENOMEM; | |
75 | } else { | |
76 | pgdp = pgd_offset_k(ea); | |
77 | if (pgd_none(*pgdp)) { | |
78 | pudp = early_alloc_pgtable(PUD_TABLE_SIZE); | |
79 | BUG_ON(pudp == NULL); | |
80 | pgd_populate(&init_mm, pgdp, pudp); | |
81 | } | |
82 | pudp = pud_offset(pgdp, ea); | |
83 | if (map_page_size == PUD_SIZE) { | |
84 | ptep = (pte_t *)pudp; | |
85 | goto set_the_pte; | |
86 | } | |
87 | if (pud_none(*pudp)) { | |
88 | pmdp = early_alloc_pgtable(PMD_TABLE_SIZE); | |
89 | BUG_ON(pmdp == NULL); | |
90 | pud_populate(&init_mm, pudp, pmdp); | |
91 | } | |
92 | pmdp = pmd_offset(pudp, ea); | |
93 | if (map_page_size == PMD_SIZE) { | |
94 | ptep = (pte_t *)pudp; | |
95 | goto set_the_pte; | |
96 | } | |
97 | if (!pmd_present(*pmdp)) { | |
98 | ptep = early_alloc_pgtable(PAGE_SIZE); | |
99 | BUG_ON(ptep == NULL); | |
100 | pmd_populate_kernel(&init_mm, pmdp, ptep); | |
101 | } | |
102 | ptep = pte_offset_kernel(pmdp, ea); | |
103 | } | |
104 | ||
105 | set_the_pte: | |
106 | set_pte_at(&init_mm, ea, ptep, pfn_pte(pa >> PAGE_SHIFT, flags)); | |
107 | smp_wmb(); | |
108 | return 0; | |
109 | } | |
110 | ||
b5200ec9 RA |
111 | static inline void __meminit print_mapping(unsigned long start, |
112 | unsigned long end, | |
113 | unsigned long size) | |
114 | { | |
115 | if (end <= start) | |
116 | return; | |
117 | ||
118 | pr_info("Mapped range 0x%lx - 0x%lx with 0x%lx\n", start, end, size); | |
119 | } | |
120 | ||
121 | static int __meminit create_physical_mapping(unsigned long start, | |
122 | unsigned long end) | |
123 | { | |
124 | unsigned long addr, mapping_size = 0; | |
125 | ||
126 | start = _ALIGN_UP(start, PAGE_SIZE); | |
127 | for (addr = start; addr < end; addr += mapping_size) { | |
128 | unsigned long gap, previous_size; | |
129 | int rc; | |
130 | ||
131 | gap = end - addr; | |
132 | previous_size = mapping_size; | |
133 | ||
134 | if (IS_ALIGNED(addr, PUD_SIZE) && gap >= PUD_SIZE && | |
135 | mmu_psize_defs[MMU_PAGE_1G].shift) | |
136 | mapping_size = PUD_SIZE; | |
137 | else if (IS_ALIGNED(addr, PMD_SIZE) && gap >= PMD_SIZE && | |
138 | mmu_psize_defs[MMU_PAGE_2M].shift) | |
139 | mapping_size = PMD_SIZE; | |
140 | else | |
141 | mapping_size = PAGE_SIZE; | |
142 | ||
143 | if (mapping_size != previous_size) { | |
144 | print_mapping(start, addr, previous_size); | |
145 | start = addr; | |
146 | } | |
147 | ||
148 | rc = radix__map_kernel_page((unsigned long)__va(addr), addr, | |
149 | PAGE_KERNEL_X, mapping_size); | |
150 | if (rc) | |
151 | return rc; | |
152 | } | |
153 | ||
154 | print_mapping(start, addr, mapping_size); | |
155 | return 0; | |
156 | } | |
157 | ||
2bfd65e4 AK |
158 | static void __init radix_init_pgtable(void) |
159 | { | |
2bfd65e4 AK |
160 | unsigned long rts_field; |
161 | struct memblock_region *reg; | |
2bfd65e4 AK |
162 | |
163 | /* We don't support slb for radix */ | |
164 | mmu_slb_size = 0; | |
165 | /* | |
166 | * Create the linear mapping, using standard page size for now | |
167 | */ | |
b5200ec9 RA |
168 | for_each_memblock(memory, reg) |
169 | WARN_ON(create_physical_mapping(reg->base, | |
170 | reg->base + reg->size)); | |
2bfd65e4 AK |
171 | /* |
172 | * Allocate Partition table and process table for the | |
173 | * host. | |
174 | */ | |
555c1632 | 175 | BUILD_BUG_ON_MSG((PRTB_SIZE_SHIFT > 36), "Process table size too large."); |
2bfd65e4 AK |
176 | process_tb = early_alloc_pgtable(1UL << PRTB_SIZE_SHIFT); |
177 | /* | |
178 | * Fill in the process table. | |
2bfd65e4 | 179 | */ |
b23d9c5b | 180 | rts_field = radix__get_tree_size(); |
2bfd65e4 AK |
181 | process_tb->prtb0 = cpu_to_be64(rts_field | __pa(init_mm.pgd) | RADIX_PGD_INDEX_SIZE); |
182 | /* | |
183 | * Fill in the partition table. We are suppose to use effective address | |
184 | * of process table here. But our linear mapping also enable us to use | |
185 | * physical address here. | |
186 | */ | |
eea8148c | 187 | register_process_table(__pa(process_tb), 0, PRTB_SIZE_SHIFT - 12); |
2bfd65e4 AK |
188 | pr_info("Process table %p and radix root for kernel: %p\n", process_tb, init_mm.pgd); |
189 | } | |
190 | ||
191 | static void __init radix_init_partition_table(void) | |
192 | { | |
9d661958 | 193 | unsigned long rts_field, dw0; |
b23d9c5b | 194 | |
9d661958 | 195 | mmu_partition_table_init(); |
b23d9c5b | 196 | rts_field = radix__get_tree_size(); |
9d661958 PM |
197 | dw0 = rts_field | __pa(init_mm.pgd) | RADIX_PGD_INDEX_SIZE | PATB_HR; |
198 | mmu_partition_table_set_entry(0, dw0, 0); | |
2bfd65e4 | 199 | |
56547411 AK |
200 | pr_info("Initializing Radix MMU\n"); |
201 | pr_info("Partition table %p\n", partition_tb); | |
2bfd65e4 AK |
202 | } |
203 | ||
204 | void __init radix_init_native(void) | |
205 | { | |
eea8148c | 206 | register_process_table = native_register_process_table; |
2bfd65e4 AK |
207 | } |
208 | ||
209 | static int __init get_idx_from_shift(unsigned int shift) | |
210 | { | |
211 | int idx = -1; | |
212 | ||
213 | switch (shift) { | |
214 | case 0xc: | |
215 | idx = MMU_PAGE_4K; | |
216 | break; | |
217 | case 0x10: | |
218 | idx = MMU_PAGE_64K; | |
219 | break; | |
220 | case 0x15: | |
221 | idx = MMU_PAGE_2M; | |
222 | break; | |
223 | case 0x1e: | |
224 | idx = MMU_PAGE_1G; | |
225 | break; | |
226 | } | |
227 | return idx; | |
228 | } | |
229 | ||
230 | static int __init radix_dt_scan_page_sizes(unsigned long node, | |
231 | const char *uname, int depth, | |
232 | void *data) | |
233 | { | |
234 | int size = 0; | |
235 | int shift, idx; | |
236 | unsigned int ap; | |
237 | const __be32 *prop; | |
238 | const char *type = of_get_flat_dt_prop(node, "device_type", NULL); | |
239 | ||
240 | /* We are scanning "cpu" nodes only */ | |
241 | if (type == NULL || strcmp(type, "cpu") != 0) | |
242 | return 0; | |
243 | ||
244 | prop = of_get_flat_dt_prop(node, "ibm,processor-radix-AP-encodings", &size); | |
245 | if (!prop) | |
246 | return 0; | |
247 | ||
248 | pr_info("Page sizes from device-tree:\n"); | |
249 | for (; size >= 4; size -= 4, ++prop) { | |
250 | ||
251 | struct mmu_psize_def *def; | |
252 | ||
253 | /* top 3 bit is AP encoding */ | |
254 | shift = be32_to_cpu(prop[0]) & ~(0xe << 28); | |
255 | ap = be32_to_cpu(prop[0]) >> 29; | |
ac8d3818 | 256 | pr_info("Page size shift = %d AP=0x%x\n", shift, ap); |
2bfd65e4 AK |
257 | |
258 | idx = get_idx_from_shift(shift); | |
259 | if (idx < 0) | |
260 | continue; | |
261 | ||
262 | def = &mmu_psize_defs[idx]; | |
263 | def->shift = shift; | |
264 | def->ap = ap; | |
265 | } | |
266 | ||
267 | /* needed ? */ | |
268 | cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B; | |
269 | return 1; | |
270 | } | |
271 | ||
2537b09c | 272 | void __init radix__early_init_devtree(void) |
2bfd65e4 AK |
273 | { |
274 | int rc; | |
275 | ||
276 | /* | |
277 | * Try to find the available page sizes in the device-tree | |
278 | */ | |
279 | rc = of_scan_flat_dt(radix_dt_scan_page_sizes, NULL); | |
280 | if (rc != 0) /* Found */ | |
281 | goto found; | |
282 | /* | |
283 | * let's assume we have page 4k and 64k support | |
284 | */ | |
285 | mmu_psize_defs[MMU_PAGE_4K].shift = 12; | |
286 | mmu_psize_defs[MMU_PAGE_4K].ap = 0x0; | |
287 | ||
288 | mmu_psize_defs[MMU_PAGE_64K].shift = 16; | |
289 | mmu_psize_defs[MMU_PAGE_64K].ap = 0x5; | |
290 | found: | |
291 | #ifdef CONFIG_SPARSEMEM_VMEMMAP | |
292 | if (mmu_psize_defs[MMU_PAGE_2M].shift) { | |
293 | /* | |
294 | * map vmemmap using 2M if available | |
295 | */ | |
296 | mmu_vmemmap_psize = MMU_PAGE_2M; | |
297 | } | |
298 | #endif /* CONFIG_SPARSEMEM_VMEMMAP */ | |
299 | return; | |
300 | } | |
301 | ||
ad410674 AK |
302 | static void update_hid_for_radix(void) |
303 | { | |
304 | unsigned long hid0; | |
305 | unsigned long rb = 3UL << PPC_BITLSHIFT(53); /* IS = 3 */ | |
306 | ||
307 | asm volatile("ptesync": : :"memory"); | |
308 | /* prs = 0, ric = 2, rs = 0, r = 1 is = 3 */ | |
309 | asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1) | |
310 | : : "r"(rb), "i"(1), "i"(0), "i"(2), "r"(0) : "memory"); | |
311 | /* prs = 1, ric = 2, rs = 0, r = 1 is = 3 */ | |
312 | asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1) | |
313 | : : "r"(rb), "i"(1), "i"(1), "i"(2), "r"(0) : "memory"); | |
314 | asm volatile("eieio; tlbsync; ptesync; isync; slbia": : :"memory"); | |
315 | /* | |
316 | * now switch the HID | |
317 | */ | |
318 | hid0 = mfspr(SPRN_HID0); | |
319 | hid0 |= HID0_POWER9_RADIX; | |
320 | mtspr(SPRN_HID0, hid0); | |
321 | asm volatile("isync": : :"memory"); | |
322 | ||
323 | /* Wait for it to happen */ | |
324 | while (!(mfspr(SPRN_HID0) & HID0_POWER9_RADIX)) | |
325 | cpu_relax(); | |
326 | } | |
327 | ||
ee97b6b9 BS |
328 | static void radix_init_amor(void) |
329 | { | |
330 | /* | |
331 | * In HV mode, we init AMOR (Authority Mask Override Register) so that | |
332 | * the hypervisor and guest can setup IAMR (Instruction Authority Mask | |
333 | * Register), enable key 0 and set it to 1. | |
334 | * | |
335 | * AMOR = 0b1100 .... 0000 (Mask for key 0 is 11) | |
336 | */ | |
337 | mtspr(SPRN_AMOR, (3ul << 62)); | |
338 | } | |
339 | ||
3b10d009 BS |
340 | static void radix_init_iamr(void) |
341 | { | |
342 | unsigned long iamr; | |
343 | ||
344 | /* | |
345 | * The IAMR should set to 0 on DD1. | |
346 | */ | |
347 | if (cpu_has_feature(CPU_FTR_POWER9_DD1)) | |
348 | iamr = 0; | |
349 | else | |
350 | iamr = (1ul << 62); | |
351 | ||
352 | /* | |
353 | * Radix always uses key0 of the IAMR to determine if an access is | |
354 | * allowed. We set bit 0 (IBM bit 1) of key0, to prevent instruction | |
355 | * fetch. | |
356 | */ | |
357 | mtspr(SPRN_IAMR, iamr); | |
358 | } | |
359 | ||
2bfd65e4 AK |
360 | void __init radix__early_init_mmu(void) |
361 | { | |
362 | unsigned long lpcr; | |
2bfd65e4 AK |
363 | |
364 | #ifdef CONFIG_PPC_64K_PAGES | |
365 | /* PAGE_SIZE mappings */ | |
366 | mmu_virtual_psize = MMU_PAGE_64K; | |
367 | #else | |
368 | mmu_virtual_psize = MMU_PAGE_4K; | |
369 | #endif | |
370 | ||
371 | #ifdef CONFIG_SPARSEMEM_VMEMMAP | |
372 | /* vmemmap mapping */ | |
373 | mmu_vmemmap_psize = mmu_virtual_psize; | |
374 | #endif | |
375 | /* | |
376 | * initialize page table size | |
377 | */ | |
378 | __pte_index_size = RADIX_PTE_INDEX_SIZE; | |
379 | __pmd_index_size = RADIX_PMD_INDEX_SIZE; | |
380 | __pud_index_size = RADIX_PUD_INDEX_SIZE; | |
381 | __pgd_index_size = RADIX_PGD_INDEX_SIZE; | |
382 | __pmd_cache_index = RADIX_PMD_INDEX_SIZE; | |
383 | __pte_table_size = RADIX_PTE_TABLE_SIZE; | |
384 | __pmd_table_size = RADIX_PMD_TABLE_SIZE; | |
385 | __pud_table_size = RADIX_PUD_TABLE_SIZE; | |
386 | __pgd_table_size = RADIX_PGD_TABLE_SIZE; | |
387 | ||
a2f41eb9 AK |
388 | __pmd_val_bits = RADIX_PMD_VAL_BITS; |
389 | __pud_val_bits = RADIX_PUD_VAL_BITS; | |
390 | __pgd_val_bits = RADIX_PGD_VAL_BITS; | |
2bfd65e4 | 391 | |
d6a9996e AK |
392 | __kernel_virt_start = RADIX_KERN_VIRT_START; |
393 | __kernel_virt_size = RADIX_KERN_VIRT_SIZE; | |
394 | __vmalloc_start = RADIX_VMALLOC_START; | |
395 | __vmalloc_end = RADIX_VMALLOC_END; | |
396 | vmemmap = (struct page *)RADIX_VMEMMAP_BASE; | |
397 | ioremap_bot = IOREMAP_BASE; | |
bfa37087 DS |
398 | |
399 | #ifdef CONFIG_PCI | |
400 | pci_io_base = ISA_IO_BASE; | |
401 | #endif | |
402 | ||
5ed7ecd0 AK |
403 | /* |
404 | * For now radix also use the same frag size | |
405 | */ | |
406 | __pte_frag_nr = H_PTE_FRAG_NR; | |
407 | __pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT; | |
d6a9996e | 408 | |
d6c88600 | 409 | if (!firmware_has_feature(FW_FEATURE_LPAR)) { |
166dd7d3 | 410 | radix_init_native(); |
ad410674 AK |
411 | if (cpu_has_feature(CPU_FTR_POWER9_DD1)) |
412 | update_hid_for_radix(); | |
d6c88600 | 413 | lpcr = mfspr(SPRN_LPCR); |
bf16cdf4 | 414 | mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR); |
2bfd65e4 | 415 | radix_init_partition_table(); |
ee97b6b9 | 416 | radix_init_amor(); |
d6c88600 | 417 | } |
2bfd65e4 | 418 | |
9d661958 PM |
419 | memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE); |
420 | ||
3b10d009 | 421 | radix_init_iamr(); |
2bfd65e4 AK |
422 | radix_init_pgtable(); |
423 | } | |
424 | ||
425 | void radix__early_init_mmu_secondary(void) | |
426 | { | |
427 | unsigned long lpcr; | |
428 | /* | |
d6c88600 | 429 | * update partition table control register and UPRT |
2bfd65e4 | 430 | */ |
d6c88600 | 431 | if (!firmware_has_feature(FW_FEATURE_LPAR)) { |
cac4a185 AK |
432 | |
433 | if (cpu_has_feature(CPU_FTR_POWER9_DD1)) | |
434 | update_hid_for_radix(); | |
435 | ||
d6c88600 | 436 | lpcr = mfspr(SPRN_LPCR); |
bf16cdf4 | 437 | mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR); |
d6c88600 | 438 | |
2bfd65e4 AK |
439 | mtspr(SPRN_PTCR, |
440 | __pa(partition_tb) | (PATB_SIZE_SHIFT - 12)); | |
ee97b6b9 | 441 | radix_init_amor(); |
d6c88600 | 442 | } |
3b10d009 | 443 | radix_init_iamr(); |
2bfd65e4 AK |
444 | } |
445 | ||
fe036a06 BH |
446 | void radix__mmu_cleanup_all(void) |
447 | { | |
448 | unsigned long lpcr; | |
449 | ||
450 | if (!firmware_has_feature(FW_FEATURE_LPAR)) { | |
451 | lpcr = mfspr(SPRN_LPCR); | |
452 | mtspr(SPRN_LPCR, lpcr & ~LPCR_UPRT); | |
453 | mtspr(SPRN_PTCR, 0); | |
1d0761d2 | 454 | powernv_set_nmmu_ptcr(0); |
fe036a06 BH |
455 | radix__flush_tlb_all(); |
456 | } | |
457 | } | |
458 | ||
2bfd65e4 AK |
459 | void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base, |
460 | phys_addr_t first_memblock_size) | |
461 | { | |
177ba7c6 AK |
462 | /* We don't currently support the first MEMBLOCK not mapping 0 |
463 | * physical on those processors | |
464 | */ | |
465 | BUG_ON(first_memblock_base != 0); | |
466 | /* | |
467 | * We limit the allocation that depend on ppc64_rma_size | |
468 | * to first_memblock_size. We also clamp it to 1GB to | |
469 | * avoid some funky things such as RTAS bugs. | |
470 | * | |
471 | * On radix config we really don't have a limitation | |
472 | * on real mode access. But keeping it as above works | |
473 | * well enough. | |
474 | */ | |
475 | ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000); | |
476 | /* | |
477 | * Finally limit subsequent allocations. We really don't want | |
478 | * to limit the memblock allocations to rma_size. FIXME!! should | |
479 | * we even limit at all ? | |
480 | */ | |
2bfd65e4 AK |
481 | memblock_set_current_limit(first_memblock_base + first_memblock_size); |
482 | } | |
d9225ad9 | 483 | |
6cc27341 RA |
484 | #ifdef CONFIG_MEMORY_HOTPLUG |
485 | int __ref radix__create_section_mapping(unsigned long start, unsigned long end) | |
486 | { | |
487 | return create_physical_mapping(start, end); | |
488 | } | |
489 | #endif /* CONFIG_MEMORY_HOTPLUG */ | |
490 | ||
d9225ad9 AK |
491 | #ifdef CONFIG_SPARSEMEM_VMEMMAP |
492 | int __meminit radix__vmemmap_create_mapping(unsigned long start, | |
493 | unsigned long page_size, | |
494 | unsigned long phys) | |
495 | { | |
496 | /* Create a PTE encoding */ | |
497 | unsigned long flags = _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_KERNEL_RW; | |
498 | ||
499 | BUG_ON(radix__map_kernel_page(start, phys, __pgprot(flags), page_size)); | |
500 | return 0; | |
501 | } | |
502 | ||
503 | #ifdef CONFIG_MEMORY_HOTPLUG | |
504 | void radix__vmemmap_remove_mapping(unsigned long start, unsigned long page_size) | |
505 | { | |
506 | /* FIXME!! intel does more. We should free page tables mapping vmemmap ? */ | |
507 | } | |
508 | #endif | |
509 | #endif | |
bde3eb62 AK |
510 | |
511 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE | |
512 | ||
513 | unsigned long radix__pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, | |
514 | pmd_t *pmdp, unsigned long clr, | |
515 | unsigned long set) | |
516 | { | |
517 | unsigned long old; | |
518 | ||
519 | #ifdef CONFIG_DEBUG_VM | |
520 | WARN_ON(!radix__pmd_trans_huge(*pmdp)); | |
521 | assert_spin_locked(&mm->page_table_lock); | |
522 | #endif | |
523 | ||
524 | old = radix__pte_update(mm, addr, (pte_t *)pmdp, clr, set, 1); | |
525 | trace_hugepage_update(addr, old, clr, set); | |
526 | ||
527 | return old; | |
528 | } | |
529 | ||
530 | pmd_t radix__pmdp_collapse_flush(struct vm_area_struct *vma, unsigned long address, | |
531 | pmd_t *pmdp) | |
532 | ||
533 | { | |
534 | pmd_t pmd; | |
535 | ||
536 | VM_BUG_ON(address & ~HPAGE_PMD_MASK); | |
537 | VM_BUG_ON(radix__pmd_trans_huge(*pmdp)); | |
538 | /* | |
539 | * khugepaged calls this for normal pmd | |
540 | */ | |
541 | pmd = *pmdp; | |
542 | pmd_clear(pmdp); | |
543 | /*FIXME!! Verify whether we need this kick below */ | |
544 | kick_all_cpus_sync(); | |
545 | flush_tlb_range(vma, address, address + HPAGE_PMD_SIZE); | |
546 | return pmd; | |
547 | } | |
548 | ||
549 | /* | |
550 | * For us pgtable_t is pte_t *. Inorder to save the deposisted | |
551 | * page table, we consider the allocated page table as a list | |
552 | * head. On withdraw we need to make sure we zero out the used | |
553 | * list_head memory area. | |
554 | */ | |
555 | void radix__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, | |
556 | pgtable_t pgtable) | |
557 | { | |
558 | struct list_head *lh = (struct list_head *) pgtable; | |
559 | ||
560 | assert_spin_locked(pmd_lockptr(mm, pmdp)); | |
561 | ||
562 | /* FIFO */ | |
563 | if (!pmd_huge_pte(mm, pmdp)) | |
564 | INIT_LIST_HEAD(lh); | |
565 | else | |
566 | list_add(lh, (struct list_head *) pmd_huge_pte(mm, pmdp)); | |
567 | pmd_huge_pte(mm, pmdp) = pgtable; | |
568 | } | |
569 | ||
570 | pgtable_t radix__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp) | |
571 | { | |
572 | pte_t *ptep; | |
573 | pgtable_t pgtable; | |
574 | struct list_head *lh; | |
575 | ||
576 | assert_spin_locked(pmd_lockptr(mm, pmdp)); | |
577 | ||
578 | /* FIFO */ | |
579 | pgtable = pmd_huge_pte(mm, pmdp); | |
580 | lh = (struct list_head *) pgtable; | |
581 | if (list_empty(lh)) | |
582 | pmd_huge_pte(mm, pmdp) = NULL; | |
583 | else { | |
584 | pmd_huge_pte(mm, pmdp) = (pgtable_t) lh->next; | |
585 | list_del(lh); | |
586 | } | |
587 | ptep = (pte_t *) pgtable; | |
588 | *ptep = __pte(0); | |
589 | ptep++; | |
590 | *ptep = __pte(0); | |
591 | return pgtable; | |
592 | } | |
593 | ||
594 | ||
595 | pmd_t radix__pmdp_huge_get_and_clear(struct mm_struct *mm, | |
596 | unsigned long addr, pmd_t *pmdp) | |
597 | { | |
598 | pmd_t old_pmd; | |
599 | unsigned long old; | |
600 | ||
601 | old = radix__pmd_hugepage_update(mm, addr, pmdp, ~0UL, 0); | |
602 | old_pmd = __pmd(old); | |
603 | /* | |
604 | * Serialize against find_linux_pte_or_hugepte which does lock-less | |
605 | * lookup in page tables with local interrupts disabled. For huge pages | |
606 | * it casts pmd_t to pte_t. Since format of pte_t is different from | |
607 | * pmd_t we want to prevent transit from pmd pointing to page table | |
608 | * to pmd pointing to huge page (and back) while interrupts are disabled. | |
609 | * We clear pmd to possibly replace it with page table pointer in | |
610 | * different code paths. So make sure we wait for the parallel | |
611 | * find_linux_pte_or_hugepage to finish. | |
612 | */ | |
613 | kick_all_cpus_sync(); | |
614 | return old_pmd; | |
615 | } | |
616 | ||
617 | int radix__has_transparent_hugepage(void) | |
618 | { | |
619 | /* For radix 2M at PMD level means thp */ | |
620 | if (mmu_psize_defs[MMU_PAGE_2M].shift == PMD_SHIFT) | |
621 | return 1; | |
622 | return 0; | |
623 | } | |
624 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ |