[mirror_ubuntu-zesty-kernel.git] / arch / powerpc / mm / pgtable-radix.c

/*
 * Page table handling routines for radix page table.
 *
 * Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */
#include <linux/sched.h>
#include <linux/memblock.h>
#include <linux/of_fdt.h>

#include <asm/pgtable.h>
#include <asm/pgalloc.h>
#include <asm/dma.h>
#include <asm/machdep.h>
#include <asm/mmu.h>
#include <asm/firmware.h>

#include <trace/events/thp.h>

static int native_register_process_table(unsigned long base, unsigned long pg_sz,
					 unsigned long table_size)
{
	unsigned long patb1 = base | table_size | PATB_GR;

	partition_tb->patb1 = cpu_to_be64(patb1);
	return 0;
}

static __ref void *early_alloc_pgtable(unsigned long size)
{
	void *pt;

	pt = __va(memblock_alloc_base(size, size, MEMBLOCK_ALLOC_ANYWHERE));
	memset(pt, 0, size);

	return pt;
}

int radix__map_kernel_page(unsigned long ea, unsigned long pa,
			  pgprot_t flags,
			  unsigned int map_page_size)
{
	pgd_t *pgdp;
	pud_t *pudp;
	pmd_t *pmdp;
	pte_t *ptep;
	/*
	 * Make sure task size is correct as per the max adddr
	 */
	BUILD_BUG_ON(TASK_SIZE_USER64 > RADIX_PGTABLE_RANGE);
	if (slab_is_available()) {
		pgdp = pgd_offset_k(ea);
		pudp = pud_alloc(&init_mm, pgdp, ea);
		if (!pudp)
			return -ENOMEM;
		if (map_page_size == PUD_SIZE) {
			ptep = (pte_t *)pudp;
			goto set_the_pte;
		}
		pmdp = pmd_alloc(&init_mm, pudp, ea);
		if (!pmdp)
			return -ENOMEM;
		if (map_page_size == PMD_SIZE) {
			ptep = (pte_t *)pudp;
			goto set_the_pte;
		}
		ptep = pte_alloc_kernel(pmdp, ea);
		if (!ptep)
			return -ENOMEM;
	} else {
		pgdp = pgd_offset_k(ea);
		if (pgd_none(*pgdp)) {
			pudp = early_alloc_pgtable(PUD_TABLE_SIZE);
			BUG_ON(pudp == NULL);
			pgd_populate(&init_mm, pgdp, pudp);
		}
		pudp = pud_offset(pgdp, ea);
		if (map_page_size == PUD_SIZE) {
			ptep = (pte_t *)pudp;
			goto set_the_pte;
		}
		if (pud_none(*pudp)) {
			pmdp = early_alloc_pgtable(PMD_TABLE_SIZE);
			BUG_ON(pmdp == NULL);
			pud_populate(&init_mm, pudp, pmdp);
		}
		pmdp = pmd_offset(pudp, ea);
		if (map_page_size == PMD_SIZE) {
			ptep = (pte_t *)pudp;
			goto set_the_pte;
		}
		if (!pmd_present(*pmdp)) {
			ptep = early_alloc_pgtable(PAGE_SIZE);
			BUG_ON(ptep == NULL);
			pmd_populate_kernel(&init_mm, pmdp, ptep);
		}
		ptep = pte_offset_kernel(pmdp, ea);
	}

set_the_pte:
	set_pte_at(&init_mm, ea, ptep, pfn_pte(pa >> PAGE_SHIFT, flags));
	smp_wmb();
	return 0;
}

static void __init radix_init_pgtable(void)
{
	int loop_count;
	u64 base, end, start_addr;
	unsigned long rts_field;
	struct memblock_region *reg;
	unsigned long linear_page_size;

	/* We don't support slb for radix */
	mmu_slb_size = 0;
	/*
	 * Create the linear mapping, using standard page size for now
	 */
	loop_count = 0;
	for_each_memblock(memory, reg) {

		start_addr = reg->base;

redo:
		if (loop_count < 1 && mmu_psize_defs[MMU_PAGE_1G].shift)
			linear_page_size = PUD_SIZE;
		else if (loop_count < 2 && mmu_psize_defs[MMU_PAGE_2M].shift)
			linear_page_size = PMD_SIZE;
		else
			linear_page_size = PAGE_SIZE;

		base = _ALIGN_UP(start_addr, linear_page_size);
		end = _ALIGN_DOWN(reg->base + reg->size, linear_page_size);

		pr_info("Mapping range 0x%lx - 0x%lx with 0x%lx\n",
			(unsigned long)base, (unsigned long)end,
			linear_page_size);

		while (base < end) {
			radix__map_kernel_page((unsigned long)__va(base),
					      base, PAGE_KERNEL_X,
					      linear_page_size);
			base += linear_page_size;
		}
		/*
		 * map the rest using lower page size
		 */
		if (end < reg->base + reg->size) {
			start_addr = end;
			loop_count++;
			goto redo;
		}
	}
	/*
	 * Allocate Partition table and process table for the
	 * host.
	 */
	BUILD_BUG_ON_MSG((PRTB_SIZE_SHIFT > 36), "Process table size too large.");
	process_tb = early_alloc_pgtable(1UL << PRTB_SIZE_SHIFT);
	/*
	 * Fill in the process table.
	 */
	rts_field = radix__get_tree_size();
	process_tb->prtb0 = cpu_to_be64(rts_field | __pa(init_mm.pgd) | RADIX_PGD_INDEX_SIZE);
	/*
	 * Fill in the partition table. We are suppose to use effective address
	 * of process table here. But our linear mapping also enable us to use
	 * physical address here.
	 */
	register_process_table(__pa(process_tb), 0, PRTB_SIZE_SHIFT - 12);
	pr_info("Process table %p and radix root for kernel: %p\n", process_tb, init_mm.pgd);
}

static void __init radix_init_partition_table(void)
{
	unsigned long rts_field, dw0;

	mmu_partition_table_init();
	rts_field = radix__get_tree_size();
	dw0 = rts_field | __pa(init_mm.pgd) | RADIX_PGD_INDEX_SIZE | PATB_HR;
	mmu_partition_table_set_entry(0, dw0, 0);

	pr_info("Initializing Radix MMU\n");
	pr_info("Partition table %p\n", partition_tb);
}

void __init radix_init_native(void)
{
	register_process_table = native_register_process_table;
}

static int __init get_idx_from_shift(unsigned int shift)
{
	int idx = -1;

	switch (shift) {
	case 0xc:
		idx = MMU_PAGE_4K;
		break;
	case 0x10:
		idx = MMU_PAGE_64K;
		break;
	case 0x15:
		idx = MMU_PAGE_2M;
		break;
	case 0x1e:
		idx = MMU_PAGE_1G;
		break;
	}
	return idx;
}

static int __init radix_dt_scan_page_sizes(unsigned long node,
					   const char *uname, int depth,
					   void *data)
{
	int size = 0;
	int shift, idx;
	unsigned int ap;
	const __be32 *prop;
	const char *type = of_get_flat_dt_prop(node, "device_type", NULL);

	/* We are scanning "cpu" nodes only */
	if (type == NULL || strcmp(type, "cpu") != 0)
		return 0;

	prop = of_get_flat_dt_prop(node, "ibm,processor-radix-AP-encodings", &size);
	if (!prop)
		return 0;

	pr_info("Page sizes from device-tree:\n");
	for (; size >= 4; size -= 4, ++prop) {

		struct mmu_psize_def *def;

		/* top 3 bit is AP encoding */
		shift = be32_to_cpu(prop[0]) & ~(0xe << 28);
		ap = be32_to_cpu(prop[0]) >> 29;
		pr_info("Page size shift = %d AP=0x%x\n", shift, ap);

		idx = get_idx_from_shift(shift);
		if (idx < 0)
			continue;

		def = &mmu_psize_defs[idx];
		def->shift = shift;
		def->ap  = ap;
	}

	/* needed ? */
	cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
	return 1;
}

void __init radix__early_init_devtree(void)
{
	int rc;

	/*
	 * Try to find the available page sizes in the device-tree
	 */
	rc = of_scan_flat_dt(radix_dt_scan_page_sizes, NULL);
	if (rc != 0)  /* Found */
		goto found;
	/*
	 * let's assume we have page 4k and 64k support
	 */
	mmu_psize_defs[MMU_PAGE_4K].shift = 12;
	mmu_psize_defs[MMU_PAGE_4K].ap = 0x0;

	mmu_psize_defs[MMU_PAGE_64K].shift = 16;
	mmu_psize_defs[MMU_PAGE_64K].ap = 0x5;
found:
#ifdef CONFIG_SPARSEMEM_VMEMMAP
	if (mmu_psize_defs[MMU_PAGE_2M].shift) {
		/*
		 * map vmemmap using 2M if available
		 */
		mmu_vmemmap_psize = MMU_PAGE_2M;
	}
#endif /* CONFIG_SPARSEMEM_VMEMMAP */
	return;
}

static void update_hid_for_radix(void)
{
	unsigned long hid0;
	unsigned long rb = 3UL << PPC_BITLSHIFT(53); /* IS = 3 */

	asm volatile("ptesync": : :"memory");
	/* prs = 0, ric = 2, rs = 0, r = 1 is = 3 */
	asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
		     : : "r"(rb), "i"(1), "i"(0), "i"(2), "r"(0) : "memory");
	/* prs = 1, ric = 2, rs = 0, r = 1 is = 3 */
	asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
		     : : "r"(rb), "i"(1), "i"(1), "i"(2), "r"(0) : "memory");
	asm volatile("eieio; tlbsync; ptesync; isync; slbia": : :"memory");
	/*
	 * now switch the HID
	 */
	hid0  = mfspr(SPRN_HID0);
	hid0 |= HID0_POWER9_RADIX;
	mtspr(SPRN_HID0, hid0);
	asm volatile("isync": : :"memory");

	/* Wait for it to happen */
	while (!(mfspr(SPRN_HID0) & HID0_POWER9_RADIX))
		cpu_relax();
}

static void radix_init_amor(void)
{
	/*
	* In HV mode, we init AMOR (Authority Mask Override Register) so that
	* the hypervisor and guest can setup IAMR (Instruction Authority Mask
	* Register), enable key 0 and set it to 1.
	*
	* AMOR = 0b1100 .... 0000 (Mask for key 0 is 11)
	*/
	mtspr(SPRN_AMOR, (3ul << 62));
}

void __init radix__early_init_mmu(void)
{
	unsigned long lpcr;

#ifdef CONFIG_PPC_64K_PAGES
	/* PAGE_SIZE mappings */
	mmu_virtual_psize = MMU_PAGE_64K;
#else
	mmu_virtual_psize = MMU_PAGE_4K;
#endif

#ifdef CONFIG_SPARSEMEM_VMEMMAP
	/* vmemmap mapping */
	mmu_vmemmap_psize = mmu_virtual_psize;
#endif
	/*
	 * initialize page table size
	 */
	__pte_index_size = RADIX_PTE_INDEX_SIZE;
	__pmd_index_size = RADIX_PMD_INDEX_SIZE;
	__pud_index_size = RADIX_PUD_INDEX_SIZE;
	__pgd_index_size = RADIX_PGD_INDEX_SIZE;
	__pmd_cache_index = RADIX_PMD_INDEX_SIZE;
	__pte_table_size = RADIX_PTE_TABLE_SIZE;
	__pmd_table_size = RADIX_PMD_TABLE_SIZE;
	__pud_table_size = RADIX_PUD_TABLE_SIZE;
	__pgd_table_size = RADIX_PGD_TABLE_SIZE;

	__pmd_val_bits = RADIX_PMD_VAL_BITS;
	__pud_val_bits = RADIX_PUD_VAL_BITS;
	__pgd_val_bits = RADIX_PGD_VAL_BITS;

	__kernel_virt_start = RADIX_KERN_VIRT_START;
	__kernel_virt_size = RADIX_KERN_VIRT_SIZE;
	__vmalloc_start = RADIX_VMALLOC_START;
	__vmalloc_end = RADIX_VMALLOC_END;
	vmemmap = (struct page *)RADIX_VMEMMAP_BASE;
	ioremap_bot = IOREMAP_BASE;

#ifdef CONFIG_PCI
	pci_io_base = ISA_IO_BASE;
#endif

	/*
	 * For now radix also use the same frag size
	 */
	__pte_frag_nr = H_PTE_FRAG_NR;
	__pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT;

	if (!firmware_has_feature(FW_FEATURE_LPAR)) {
		radix_init_native();
		if (cpu_has_feature(CPU_FTR_POWER9_DD1))
			update_hid_for_radix();
		lpcr = mfspr(SPRN_LPCR);
		mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
		radix_init_partition_table();
		radix_init_amor();
	}

	memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);

	radix_init_pgtable();
}

void radix__early_init_mmu_secondary(void)
{
	unsigned long lpcr;
	/*
	 * update partition table control register and UPRT
	 */
	if (!firmware_has_feature(FW_FEATURE_LPAR)) {
		lpcr = mfspr(SPRN_LPCR);
		mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);

		mtspr(SPRN_PTCR,
		      __pa(partition_tb) | (PATB_SIZE_SHIFT - 12));
		radix_init_amor();
	}
}

void radix__mmu_cleanup_all(void)
{
	unsigned long lpcr;

	if (!firmware_has_feature(FW_FEATURE_LPAR)) {
		lpcr = mfspr(SPRN_LPCR);
		mtspr(SPRN_LPCR, lpcr & ~LPCR_UPRT);
		mtspr(SPRN_PTCR, 0);
		radix__flush_tlb_all();
	}
}

void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base,
				phys_addr_t first_memblock_size)
{
	/* We don't currently support the first MEMBLOCK not mapping 0
	 * physical on those processors
	 */
	BUG_ON(first_memblock_base != 0);
	/*
	 * We limit the allocation that depend on ppc64_rma_size
	 * to first_memblock_size. We also clamp it to 1GB to
	 * avoid some funky things such as RTAS bugs.
	 *
	 * On radix config we really don't have a limitation
	 * on real mode access. But keeping it as above works
	 * well enough.
	 */
	ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000);
	/*
	 * Finally limit subsequent allocations. We really don't want
	 * to limit the memblock allocations to rma_size. FIXME!! should
	 * we even limit at all ?
	 */
	memblock_set_current_limit(first_memblock_base + first_memblock_size);
}

#ifdef CONFIG_SPARSEMEM_VMEMMAP
int __meminit radix__vmemmap_create_mapping(unsigned long start,
				      unsigned long page_size,
				      unsigned long phys)
{
	/* Create a PTE encoding */
	unsigned long flags = _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_KERNEL_RW;

	BUG_ON(radix__map_kernel_page(start, phys, __pgprot(flags), page_size));
	return 0;
}

#ifdef CONFIG_MEMORY_HOTPLUG
void radix__vmemmap_remove_mapping(unsigned long start, unsigned long page_size)
{
	/* FIXME!! intel does more. We should free page tables mapping vmemmap ? */
}
#endif
#endif

#ifdef CONFIG_TRANSPARENT_HUGEPAGE

unsigned long radix__pmd_hugepage_update(struct mm_struct *mm, unsigned long addr,
				  pmd_t *pmdp, unsigned long clr,
				  unsigned long set)
{
	unsigned long old;

#ifdef CONFIG_DEBUG_VM
	WARN_ON(!radix__pmd_trans_huge(*pmdp));
	assert_spin_locked(&mm->page_table_lock);
#endif

	old = radix__pte_update(mm, addr, (pte_t *)pmdp, clr, set, 1);
	trace_hugepage_update(addr, old, clr, set);

	return old;
}

pmd_t radix__pmdp_collapse_flush(struct vm_area_struct *vma, unsigned long address,
			pmd_t *pmdp)

{
	pmd_t pmd;

	VM_BUG_ON(address & ~HPAGE_PMD_MASK);
	VM_BUG_ON(radix__pmd_trans_huge(*pmdp));
	/*
	 * khugepaged calls this for normal pmd
	 */
	pmd = *pmdp;
	pmd_clear(pmdp);
	/*FIXME!!  Verify whether we need this kick below */
	kick_all_cpus_sync();
	flush_tlb_range(vma, address, address + HPAGE_PMD_SIZE);
	return pmd;
}

/*
 * For us pgtable_t is pte_t *. Inorder to save the deposisted
 * page table, we consider the allocated page table as a list
 * head. On withdraw we need to make sure we zero out the used
 * list_head memory area.
 */
void radix__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
				 pgtable_t pgtable)
{
        struct list_head *lh = (struct list_head *) pgtable;

        assert_spin_locked(pmd_lockptr(mm, pmdp));

        /* FIFO */
        if (!pmd_huge_pte(mm, pmdp))
                INIT_LIST_HEAD(lh);
        else
                list_add(lh, (struct list_head *) pmd_huge_pte(mm, pmdp));
        pmd_huge_pte(mm, pmdp) = pgtable;
}

pgtable_t radix__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp)
{
        pte_t *ptep;
        pgtable_t pgtable;
        struct list_head *lh;

        assert_spin_locked(pmd_lockptr(mm, pmdp));

        /* FIFO */
        pgtable = pmd_huge_pte(mm, pmdp);
        lh = (struct list_head *) pgtable;
        if (list_empty(lh))
                pmd_huge_pte(mm, pmdp) = NULL;
        else {
                pmd_huge_pte(mm, pmdp) = (pgtable_t) lh->next;
                list_del(lh);
        }
        ptep = (pte_t *) pgtable;
        *ptep = __pte(0);
        ptep++;
        *ptep = __pte(0);
        return pgtable;
}


pmd_t radix__pmdp_huge_get_and_clear(struct mm_struct *mm,
			       unsigned long addr, pmd_t *pmdp)
{
	pmd_t old_pmd;
	unsigned long old;

	old = radix__pmd_hugepage_update(mm, addr, pmdp, ~0UL, 0);
	old_pmd = __pmd(old);
	/*
	 * Serialize against find_linux_pte_or_hugepte which does lock-less
	 * lookup in page tables with local interrupts disabled. For huge pages
	 * it casts pmd_t to pte_t. Since format of pte_t is different from
	 * pmd_t we want to prevent transit from pmd pointing to page table
	 * to pmd pointing to huge page (and back) while interrupts are disabled.
	 * We clear pmd to possibly replace it with page table pointer in
	 * different code paths. So make sure we wait for the parallel
	 * find_linux_pte_or_hugepage to finish.
	 */
	kick_all_cpus_sync();
	return old_pmd;
}

int radix__has_transparent_hugepage(void)
{
	/* For radix 2M at PMD level means thp */
	if (mmu_psize_defs[MMU_PAGE_2M].shift == PMD_SHIFT)
		return 1;
	return 0;
}
#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
Commit	Line	Data
2bfd65e4 AK	1	/*
	2	* Page table handling routines for radix page table.
	3	*
	4	* Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation.
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version
	9	* 2 of the License, or (at your option) any later version.
	10	*/
	11	#include <linux/sched.h>
	12	#include <linux/memblock.h>
	13	#include <linux/of_fdt.h>
	14
	15	#include <asm/pgtable.h>
	16	#include <asm/pgalloc.h>
	17	#include <asm/dma.h>
	18	#include <asm/machdep.h>
	19	#include <asm/mmu.h>
	20	#include <asm/firmware.h>
	21
bde3eb62 AK	22	#include <trace/events/thp.h>
bde3eb62 AK	23
83209bc8 AK	24	static int native_register_process_table(unsigned long base, unsigned long pg_sz,
83209bc8 AK	25	unsigned long table_size)
2bfd65e4	26	{
83209bc8 AK	27	unsigned long patb1 = base \| table_size \| PATB_GR;
83209bc8 AK	28
2bfd65e4 AK	29	partition_tb->patb1 = cpu_to_be64(patb1);
	30	return 0;
	31	}
	32
	33	static __ref void *early_alloc_pgtable(unsigned long size)
	34	{
	35	void *pt;
	36
	37	pt = __va(memblock_alloc_base(size, size, MEMBLOCK_ALLOC_ANYWHERE));
	38	memset(pt, 0, size);
	39
	40	return pt;
	41	}
	42
	43	int radix__map_kernel_page(unsigned long ea, unsigned long pa,
	44	pgprot_t flags,
	45	unsigned int map_page_size)
	46	{
	47	pgd_t *pgdp;
	48	pud_t *pudp;
	49	pmd_t *pmdp;
	50	pte_t *ptep;
	51	/*
	52	* Make sure task size is correct as per the max adddr
	53	*/
	54	BUILD_BUG_ON(TASK_SIZE_USER64 > RADIX_PGTABLE_RANGE);
	55	if (slab_is_available()) {
	56	pgdp = pgd_offset_k(ea);
	57	pudp = pud_alloc(&init_mm, pgdp, ea);
	58	if (!pudp)
	59	return -ENOMEM;
	60	if (map_page_size == PUD_SIZE) {
	61	ptep = (pte_t *)pudp;
	62	goto set_the_pte;
	63	}
	64	pmdp = pmd_alloc(&init_mm, pudp, ea);
	65	if (!pmdp)
	66	return -ENOMEM;
	67	if (map_page_size == PMD_SIZE) {
	68	ptep = (pte_t *)pudp;
	69	goto set_the_pte;
	70	}
	71	ptep = pte_alloc_kernel(pmdp, ea);
	72	if (!ptep)
	73	return -ENOMEM;
	74	} else {
	75	pgdp = pgd_offset_k(ea);
	76	if (pgd_none(*pgdp)) {
	77	pudp = early_alloc_pgtable(PUD_TABLE_SIZE);
	78	BUG_ON(pudp == NULL);
	79	pgd_populate(&init_mm, pgdp, pudp);
	80	}
	81	pudp = pud_offset(pgdp, ea);
	82	if (map_page_size == PUD_SIZE) {
	83	ptep = (pte_t *)pudp;
	84	goto set_the_pte;
	85	}
	86	if (pud_none(*pudp)) {
	87	pmdp = early_alloc_pgtable(PMD_TABLE_SIZE);
	88	BUG_ON(pmdp == NULL);
	89	pud_populate(&init_mm, pudp, pmdp);
	90	}
	91	pmdp = pmd_offset(pudp, ea);
	92	if (map_page_size == PMD_SIZE) {
93	ptep = (pte_t *)pudp;
94	goto set_the_pte;
95	}
96	if (!pmd_present(*pmdp)) {
97	ptep = early_alloc_pgtable(PAGE_SIZE);
98	BUG_ON(ptep == NULL);
99	pmd_populate_kernel(&init_mm, pmdp, ptep);
100	}
101	ptep = pte_offset_kernel(pmdp, ea);
102	}
103
104	set_the_pte:
105	set_pte_at(&init_mm, ea, ptep, pfn_pte(pa >> PAGE_SHIFT, flags));
106	smp_wmb();
107	return 0;
108	}
109
110	static void __init radix_init_pgtable(void)
111	{
112	int loop_count;
113	u64 base, end, start_addr;
114	unsigned long rts_field;
115	struct memblock_region *reg;
116	unsigned long linear_page_size;
117
118	/* We don't support slb for radix */
119	mmu_slb_size = 0;
120	/*
121	* Create the linear mapping, using standard page size for now
122	*/
123	loop_count = 0;
124	for_each_memblock(memory, reg) {
125
126	start_addr = reg->base;
127
128	redo:
129	if (loop_count < 1 && mmu_psize_defs[MMU_PAGE_1G].shift)
130	linear_page_size = PUD_SIZE;
131	else if (loop_count < 2 && mmu_psize_defs[MMU_PAGE_2M].shift)
132	linear_page_size = PMD_SIZE;
133	else
134	linear_page_size = PAGE_SIZE;
135
136	base = _ALIGN_UP(start_addr, linear_page_size);
137	end = _ALIGN_DOWN(reg->base + reg->size, linear_page_size);
138
139	pr_info("Mapping range 0x%lx - 0x%lx with 0x%lx\n",
140	(unsigned long)base, (unsigned long)end,
141	linear_page_size);
142
143	while (base < end) {
144	radix__map_kernel_page((unsigned long)__va(base),
145	base, PAGE_KERNEL_X,
146	linear_page_size);
147	base += linear_page_size;
148	}
149	/*
150	* map the rest using lower page size
151	*/
152	if (end < reg->base + reg->size) {
153	start_addr = end;
154	loop_count++;
155	goto redo;
156	}
157	}
158	/*
159	* Allocate Partition table and process table for the
160	* host.
161	*/
555c1632	162	BUILD_BUG_ON_MSG((PRTB_SIZE_SHIFT > 36), "Process table size too large.");
2bfd65e4 AK	163	process_tb = early_alloc_pgtable(1UL << PRTB_SIZE_SHIFT);
	164	/*
	165	* Fill in the process table.
2bfd65e4	166	*/
b23d9c5b	167	rts_field = radix__get_tree_size();
2bfd65e4 AK	168	process_tb->prtb0 = cpu_to_be64(rts_field \| __pa(init_mm.pgd) \| RADIX_PGD_INDEX_SIZE);
	169	/*
	170	* Fill in the partition table. We are suppose to use effective address
	171	* of process table here. But our linear mapping also enable us to use
	172	* physical address here.
	173	*/
eea8148c	174	register_process_table(__pa(process_tb), 0, PRTB_SIZE_SHIFT - 12);
2bfd65e4 AK	175	pr_info("Process table %p and radix root for kernel: %p\n", process_tb, init_mm.pgd);
	176	}
	177
	178	static void __init radix_init_partition_table(void)
	179	{
9d661958	180	unsigned long rts_field, dw0;
b23d9c5b	181
9d661958	182	mmu_partition_table_init();
b23d9c5b	183	rts_field = radix__get_tree_size();
9d661958 PM	184	dw0 = rts_field \| __pa(init_mm.pgd) \| RADIX_PGD_INDEX_SIZE \| PATB_HR;
9d661958 PM	185	mmu_partition_table_set_entry(0, dw0, 0);
2bfd65e4	186
56547411 AK	187	pr_info("Initializing Radix MMU\n");
56547411 AK	188	pr_info("Partition table %p\n", partition_tb);
2bfd65e4 AK	189	}
	190
	191	void __init radix_init_native(void)
	192	{
eea8148c	193	register_process_table = native_register_process_table;
2bfd65e4 AK	194	}
	195
	196	static int __init get_idx_from_shift(unsigned int shift)
	197	{
	198	int idx = -1;
	199
	200	switch (shift) {
	201	case 0xc:
	202	idx = MMU_PAGE_4K;
	203	break;
	204	case 0x10:
	205	idx = MMU_PAGE_64K;
	206	break;
	207	case 0x15:
	208	idx = MMU_PAGE_2M;
	209	break;
	210	case 0x1e:
	211	idx = MMU_PAGE_1G;
	212	break;
	213	}
	214	return idx;
	215	}
	216
	217	static int __init radix_dt_scan_page_sizes(unsigned long node,
	218	const char *uname, int depth,
	219	void *data)
	220	{
	221	int size = 0;
	222	int shift, idx;
	223	unsigned int ap;
	224	const __be32 *prop;
	225	const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
	226
	227	/* We are scanning "cpu" nodes only */
	228	if (type == NULL \|\| strcmp(type, "cpu") != 0)
	229	return 0;
	230
	231	prop = of_get_flat_dt_prop(node, "ibm,processor-radix-AP-encodings", &size);
	232	if (!prop)
	233	return 0;
	234
	235	pr_info("Page sizes from device-tree:\n");
	236	for (; size >= 4; size -= 4, ++prop) {
	237
	238	struct mmu_psize_def *def;
	239
	240	/* top 3 bit is AP encoding */
	241	shift = be32_to_cpu(prop[0]) & ~(0xe << 28);
	242	ap = be32_to_cpu(prop[0]) >> 29;
ac8d3818	243	pr_info("Page size shift = %d AP=0x%x\n", shift, ap);
2bfd65e4 AK	244
	245	idx = get_idx_from_shift(shift);
	246	if (idx < 0)
	247	continue;
	248
	249	def = &mmu_psize_defs[idx];
	250	def->shift = shift;
	251	def->ap = ap;
	252	}
	253
	254	/* needed ? */
	255	cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
	256	return 1;
	257	}
	258
2537b09c	259	void __init radix__early_init_devtree(void)
2bfd65e4 AK	260	{
	261	int rc;
	262
	263	/*
	264	* Try to find the available page sizes in the device-tree
	265	*/
	266	rc = of_scan_flat_dt(radix_dt_scan_page_sizes, NULL);
	267	if (rc != 0) /* Found */
	268	goto found;
	269	/*
	270	* let's assume we have page 4k and 64k support
	271	*/
	272	mmu_psize_defs[MMU_PAGE_4K].shift = 12;
	273	mmu_psize_defs[MMU_PAGE_4K].ap = 0x0;
	274
	275	mmu_psize_defs[MMU_PAGE_64K].shift = 16;
	276	mmu_psize_defs[MMU_PAGE_64K].ap = 0x5;
	277	found:
	278	#ifdef CONFIG_SPARSEMEM_VMEMMAP
	279	if (mmu_psize_defs[MMU_PAGE_2M].shift) {
	280	/*
	281	* map vmemmap using 2M if available
	282	*/
	283	mmu_vmemmap_psize = MMU_PAGE_2M;
	284	}
	285	#endif /* CONFIG_SPARSEMEM_VMEMMAP */
	286	return;
	287	}
	288
ad410674 AK	289	static void update_hid_for_radix(void)
	290	{
	291	unsigned long hid0;
	292	unsigned long rb = 3UL << PPC_BITLSHIFT(53); /* IS = 3 */
	293
	294	asm volatile("ptesync": : :"memory");
	295	/* prs = 0, ric = 2, rs = 0, r = 1 is = 3 */
	296	asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
	297	: : "r"(rb), "i"(1), "i"(0), "i"(2), "r"(0) : "memory");
	298	/* prs = 1, ric = 2, rs = 0, r = 1 is = 3 */
	299	asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
	300	: : "r"(rb), "i"(1), "i"(1), "i"(2), "r"(0) : "memory");
	301	asm volatile("eieio; tlbsync; ptesync; isync; slbia": : :"memory");
	302	/*
	303	* now switch the HID
	304	*/
	305	hid0 = mfspr(SPRN_HID0);
	306	hid0 \|= HID0_POWER9_RADIX;
	307	mtspr(SPRN_HID0, hid0);
	308	asm volatile("isync": : :"memory");
	309
	310	/* Wait for it to happen */
	311	while (!(mfspr(SPRN_HID0) & HID0_POWER9_RADIX))
	312	cpu_relax();
	313	}
	314
ee97b6b9 BS	315	static void radix_init_amor(void)
	316	{
	317	/*
	318	* In HV mode, we init AMOR (Authority Mask Override Register) so that
	319	* the hypervisor and guest can setup IAMR (Instruction Authority Mask
	320	* Register), enable key 0 and set it to 1.
	321	*
	322	* AMOR = 0b1100 .... 0000 (Mask for key 0 is 11)
	323	*/
	324	mtspr(SPRN_AMOR, (3ul << 62));
	325	}
	326
2bfd65e4 AK	327	void __init radix__early_init_mmu(void)
	328	{
	329	unsigned long lpcr;
2bfd65e4 AK	330
	331	#ifdef CONFIG_PPC_64K_PAGES
	332	/* PAGE_SIZE mappings */
	333	mmu_virtual_psize = MMU_PAGE_64K;
	334	#else
	335	mmu_virtual_psize = MMU_PAGE_4K;
	336	#endif
	337
	338	#ifdef CONFIG_SPARSEMEM_VMEMMAP
	339	/* vmemmap mapping */
	340	mmu_vmemmap_psize = mmu_virtual_psize;
	341	#endif
	342	/*
	343	* initialize page table size
	344	*/
	345	__pte_index_size = RADIX_PTE_INDEX_SIZE;
	346	__pmd_index_size = RADIX_PMD_INDEX_SIZE;
	347	__pud_index_size = RADIX_PUD_INDEX_SIZE;
	348	__pgd_index_size = RADIX_PGD_INDEX_SIZE;
	349	__pmd_cache_index = RADIX_PMD_INDEX_SIZE;
	350	__pte_table_size = RADIX_PTE_TABLE_SIZE;
	351	__pmd_table_size = RADIX_PMD_TABLE_SIZE;
	352	__pud_table_size = RADIX_PUD_TABLE_SIZE;
	353	__pgd_table_size = RADIX_PGD_TABLE_SIZE;
	354
a2f41eb9 AK	355	__pmd_val_bits = RADIX_PMD_VAL_BITS;
	356	__pud_val_bits = RADIX_PUD_VAL_BITS;
	357	__pgd_val_bits = RADIX_PGD_VAL_BITS;
2bfd65e4	358
d6a9996e AK	359	__kernel_virt_start = RADIX_KERN_VIRT_START;
	360	__kernel_virt_size = RADIX_KERN_VIRT_SIZE;
	361	__vmalloc_start = RADIX_VMALLOC_START;
	362	__vmalloc_end = RADIX_VMALLOC_END;
	363	vmemmap = (struct page *)RADIX_VMEMMAP_BASE;
	364	ioremap_bot = IOREMAP_BASE;
bfa37087 DS	365
	366	#ifdef CONFIG_PCI
	367	pci_io_base = ISA_IO_BASE;
	368	#endif
	369
5ed7ecd0 AK	370	/*
	371	* For now radix also use the same frag size
	372	*/
	373	__pte_frag_nr = H_PTE_FRAG_NR;
	374	__pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT;
d6a9996e	375
d6c88600	376	if (!firmware_has_feature(FW_FEATURE_LPAR)) {
166dd7d3	377	radix_init_native();
ad410674 AK	378	if (cpu_has_feature(CPU_FTR_POWER9_DD1))
ad410674 AK	379	update_hid_for_radix();
d6c88600	380	lpcr = mfspr(SPRN_LPCR);
bf16cdf4	381	mtspr(SPRN_LPCR, lpcr \| LPCR_UPRT \| LPCR_HR);
2bfd65e4	382	radix_init_partition_table();
ee97b6b9	383	radix_init_amor();
d6c88600	384	}
2bfd65e4	385
9d661958 PM	386	memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
9d661958 PM	387
2bfd65e4 AK	388	radix_init_pgtable();
	389	}
	390
	391	void radix__early_init_mmu_secondary(void)
	392	{
	393	unsigned long lpcr;
	394	/*
d6c88600	395	* update partition table control register and UPRT
2bfd65e4	396	*/
d6c88600 AK	397	if (!firmware_has_feature(FW_FEATURE_LPAR)) {
d6c88600 AK	398	lpcr = mfspr(SPRN_LPCR);
bf16cdf4	399	mtspr(SPRN_LPCR, lpcr \| LPCR_UPRT \| LPCR_HR);
d6c88600	400
2bfd65e4 AK	401	mtspr(SPRN_PTCR,
2bfd65e4 AK	402	__pa(partition_tb) \| (PATB_SIZE_SHIFT - 12));
ee97b6b9	403	radix_init_amor();
d6c88600	404	}
2bfd65e4 AK	405	}
2bfd65e4 AK	406
fe036a06 BH	407	void radix__mmu_cleanup_all(void)
	408	{
	409	unsigned long lpcr;
	410
	411	if (!firmware_has_feature(FW_FEATURE_LPAR)) {
	412	lpcr = mfspr(SPRN_LPCR);
	413	mtspr(SPRN_LPCR, lpcr & ~LPCR_UPRT);
	414	mtspr(SPRN_PTCR, 0);
	415	radix__flush_tlb_all();
	416	}
	417	}
	418
2bfd65e4 AK	419	void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base,
	420	phys_addr_t first_memblock_size)
	421	{
177ba7c6 AK	422	/* We don't currently support the first MEMBLOCK not mapping 0
	423	* physical on those processors
	424	*/
	425	BUG_ON(first_memblock_base != 0);
	426	/*
	427	* We limit the allocation that depend on ppc64_rma_size
	428	* to first_memblock_size. We also clamp it to 1GB to
	429	* avoid some funky things such as RTAS bugs.
	430	*
	431	* On radix config we really don't have a limitation
	432	* on real mode access. But keeping it as above works
	433	* well enough.
	434	*/
	435	ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000);
	436	/*
	437	* Finally limit subsequent allocations. We really don't want
	438	* to limit the memblock allocations to rma_size. FIXME!! should
	439	* we even limit at all ?
	440	*/
2bfd65e4 AK	441	memblock_set_current_limit(first_memblock_base + first_memblock_size);
2bfd65e4 AK	442	}
d9225ad9 AK	443
	444	#ifdef CONFIG_SPARSEMEM_VMEMMAP
	445	int __meminit radix__vmemmap_create_mapping(unsigned long start,
	446	unsigned long page_size,
	447	unsigned long phys)
	448	{
	449	/* Create a PTE encoding */
	450	unsigned long flags = _PAGE_PRESENT \| _PAGE_ACCESSED \| _PAGE_KERNEL_RW;
	451
	452	BUG_ON(radix__map_kernel_page(start, phys, __pgprot(flags), page_size));
	453	return 0;
	454	}
	455
	456	#ifdef CONFIG_MEMORY_HOTPLUG
	457	void radix__vmemmap_remove_mapping(unsigned long start, unsigned long page_size)
	458	{
	459	/* FIXME!! intel does more. We should free page tables mapping vmemmap ? */
	460	}
	461	#endif
	462	#endif
bde3eb62 AK	463
	464	#ifdef CONFIG_TRANSPARENT_HUGEPAGE
	465
	466	unsigned long radix__pmd_hugepage_update(struct mm_struct *mm, unsigned long addr,
	467	pmd_t *pmdp, unsigned long clr,
	468	unsigned long set)
	469	{
	470	unsigned long old;
	471
	472	#ifdef CONFIG_DEBUG_VM
	473	WARN_ON(!radix__pmd_trans_huge(*pmdp));
	474	assert_spin_locked(&mm->page_table_lock);
	475	#endif
	476
	477	old = radix__pte_update(mm, addr, (pte_t *)pmdp, clr, set, 1);
	478	trace_hugepage_update(addr, old, clr, set);
	479
	480	return old;
	481	}
	482
	483	pmd_t radix__pmdp_collapse_flush(struct vm_area_struct *vma, unsigned long address,
	484	pmd_t *pmdp)
	485
	486	{
	487	pmd_t pmd;
	488
	489	VM_BUG_ON(address & ~HPAGE_PMD_MASK);
	490	VM_BUG_ON(radix__pmd_trans_huge(*pmdp));
	491	/*
	492	* khugepaged calls this for normal pmd
	493	*/
	494	pmd = *pmdp;
	495	pmd_clear(pmdp);
	496	/FIXME!! Verify whether we need this kick below /
	497	kick_all_cpus_sync();
	498	flush_tlb_range(vma, address, address + HPAGE_PMD_SIZE);
	499	return pmd;
	500	}
	501
	502	/*
	503	* For us pgtable_t is pte_t *. Inorder to save the deposisted
	504	* page table, we consider the allocated page table as a list
	505	* head. On withdraw we need to make sure we zero out the used
	506	* list_head memory area.
	507	*/
	508	void radix__pgtable_trans_huge_deposit(struct mm_struct mm, pmd_t pmdp,
	509	pgtable_t pgtable)
	510	{
	511	struct list_head lh = (struct list_head ) pgtable;
	512
	513	assert_spin_locked(pmd_lockptr(mm, pmdp));
	514
	515	/* FIFO */
	516	if (!pmd_huge_pte(mm, pmdp))
	517	INIT_LIST_HEAD(lh);
	518	else
	519	list_add(lh, (struct list_head *) pmd_huge_pte(mm, pmdp));
	520	pmd_huge_pte(mm, pmdp) = pgtable;
	521	}
	522
	523	pgtable_t radix__pgtable_trans_huge_withdraw(struct mm_struct mm, pmd_t pmdp)
	524	{
	525	pte_t *ptep;
	526	pgtable_t pgtable;
527	struct list_head *lh;
528
529	assert_spin_locked(pmd_lockptr(mm, pmdp));
530
531	/* FIFO */
532	pgtable = pmd_huge_pte(mm, pmdp);
533	lh = (struct list_head *) pgtable;
534	if (list_empty(lh))
535	pmd_huge_pte(mm, pmdp) = NULL;
536	else {
537	pmd_huge_pte(mm, pmdp) = (pgtable_t) lh->next;
538	list_del(lh);
539	}
540	ptep = (pte_t *) pgtable;
541	*ptep = __pte(0);
542	ptep++;
543	*ptep = __pte(0);
544	return pgtable;
545	}
546
547
548	pmd_t radix__pmdp_huge_get_and_clear(struct mm_struct *mm,
549	unsigned long addr, pmd_t *pmdp)
550	{
551	pmd_t old_pmd;
552	unsigned long old;
553
554	old = radix__pmd_hugepage_update(mm, addr, pmdp, ~0UL, 0);
555	old_pmd = __pmd(old);
556	/*
557	* Serialize against find_linux_pte_or_hugepte which does lock-less
558	* lookup in page tables with local interrupts disabled. For huge pages
559	* it casts pmd_t to pte_t. Since format of pte_t is different from
560	* pmd_t we want to prevent transit from pmd pointing to page table
561	* to pmd pointing to huge page (and back) while interrupts are disabled.
562	* We clear pmd to possibly replace it with page table pointer in
563	* different code paths. So make sure we wait for the parallel
564	* find_linux_pte_or_hugepage to finish.
565	*/
566	kick_all_cpus_sync();
567	return old_pmd;
568	}
569
570	int radix__has_transparent_hugepage(void)
571	{
572	/* For radix 2M at PMD level means thp */
573	if (mmu_psize_defs[MMU_PAGE_2M].shift == PMD_SHIFT)
574	return 1;
575	return 0;
576	}
577	#endif /* CONFIG_TRANSPARENT_HUGEPAGE */