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1da177e4 LT |
1 | /* |
2 | * PowerPC64 SLB support. | |
3 | * | |
4 | * Copyright (C) 2004 David Gibson <dwg@au.ibm.com>, IBM | |
5cdcd9d6 | 5 | * Based on earlier code written by: |
1da177e4 LT |
6 | * Dave Engebretsen and Mike Corrigan {engebret|mikejc}@us.ibm.com |
7 | * Copyright (c) 2001 Dave Engebretsen | |
8 | * Copyright (C) 2002 Anton Blanchard <anton@au.ibm.com>, IBM | |
9 | * | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License | |
13 | * as published by the Free Software Foundation; either version | |
14 | * 2 of the License, or (at your option) any later version. | |
15 | */ | |
16 | ||
1da177e4 LT |
17 | #include <asm/pgtable.h> |
18 | #include <asm/mmu.h> | |
19 | #include <asm/mmu_context.h> | |
20 | #include <asm/paca.h> | |
21 | #include <asm/cputable.h> | |
3c726f8d | 22 | #include <asm/cacheflush.h> |
2f6093c8 MN |
23 | #include <asm/smp.h> |
24 | #include <linux/compiler.h> | |
aa39be09 | 25 | #include <asm/udbg.h> |
b68a70c4 | 26 | #include <asm/code-patching.h> |
3c726f8d | 27 | |
1da177e4 | 28 | |
3c726f8d BH |
29 | extern void slb_allocate_realmode(unsigned long ea); |
30 | extern void slb_allocate_user(unsigned long ea); | |
31 | ||
32 | static void slb_allocate(unsigned long ea) | |
33 | { | |
34 | /* Currently, we do real mode for all SLBs including user, but | |
35 | * that will change if we bring back dynamic VSIDs | |
36 | */ | |
37 | slb_allocate_realmode(ea); | |
38 | } | |
1da177e4 | 39 | |
3b575064 PM |
40 | #define slb_esid_mask(ssize) \ |
41 | (((ssize) == MMU_SEGSIZE_256M)? ESID_MASK: ESID_MASK_1T) | |
42 | ||
1189be65 | 43 | static inline unsigned long mk_esid_data(unsigned long ea, int ssize, |
2be682af | 44 | unsigned long entry) |
1da177e4 | 45 | { |
2be682af | 46 | return (ea & slb_esid_mask(ssize)) | SLB_ESID_V | entry; |
1da177e4 LT |
47 | } |
48 | ||
1189be65 PM |
49 | static inline unsigned long mk_vsid_data(unsigned long ea, int ssize, |
50 | unsigned long flags) | |
1da177e4 | 51 | { |
1189be65 PM |
52 | return (get_kernel_vsid(ea, ssize) << slb_vsid_shift(ssize)) | flags | |
53 | ((unsigned long) ssize << SLB_VSID_SSIZE_SHIFT); | |
1da177e4 LT |
54 | } |
55 | ||
1189be65 | 56 | static inline void slb_shadow_update(unsigned long ea, int ssize, |
67439b76 | 57 | unsigned long flags, |
2f6093c8 | 58 | unsigned long entry) |
1da177e4 | 59 | { |
2f6093c8 MN |
60 | /* |
61 | * Clear the ESID first so the entry is not valid while we are | |
00efee7d MN |
62 | * updating it. No write barriers are needed here, provided |
63 | * we only update the current CPU's SLB shadow buffer. | |
2f6093c8 MN |
64 | */ |
65 | get_slb_shadow()->save_area[entry].esid = 0; | |
7ffcf8ec AB |
66 | get_slb_shadow()->save_area[entry].vsid = |
67 | cpu_to_be64(mk_vsid_data(ea, ssize, flags)); | |
68 | get_slb_shadow()->save_area[entry].esid = | |
69 | cpu_to_be64(mk_esid_data(ea, ssize, entry)); | |
2f6093c8 MN |
70 | } |
71 | ||
edd0622b | 72 | static inline void slb_shadow_clear(unsigned long entry) |
2f6093c8 | 73 | { |
edd0622b | 74 | get_slb_shadow()->save_area[entry].esid = 0; |
1da177e4 LT |
75 | } |
76 | ||
1189be65 PM |
77 | static inline void create_shadowed_slbe(unsigned long ea, int ssize, |
78 | unsigned long flags, | |
175587cc PM |
79 | unsigned long entry) |
80 | { | |
81 | /* | |
82 | * Updating the shadow buffer before writing the SLB ensures | |
83 | * we don't get a stale entry here if we get preempted by PHYP | |
84 | * between these two statements. | |
85 | */ | |
1189be65 | 86 | slb_shadow_update(ea, ssize, flags, entry); |
175587cc PM |
87 | |
88 | asm volatile("slbmte %0,%1" : | |
1189be65 PM |
89 | : "r" (mk_vsid_data(ea, ssize, flags)), |
90 | "r" (mk_esid_data(ea, ssize, entry)) | |
175587cc PM |
91 | : "memory" ); |
92 | } | |
93 | ||
9c1e1052 | 94 | static void __slb_flush_and_rebolt(void) |
1da177e4 LT |
95 | { |
96 | /* If you change this make sure you change SLB_NUM_BOLTED | |
d8d164a9 | 97 | * and PR KVM appropriately too. */ |
bf72aeba | 98 | unsigned long linear_llp, vmalloc_llp, lflags, vflags; |
1189be65 | 99 | unsigned long ksp_esid_data, ksp_vsid_data; |
1da177e4 | 100 | |
3c726f8d | 101 | linear_llp = mmu_psize_defs[mmu_linear_psize].sllp; |
bf72aeba | 102 | vmalloc_llp = mmu_psize_defs[mmu_vmalloc_psize].sllp; |
3c726f8d | 103 | lflags = SLB_VSID_KERNEL | linear_llp; |
bf72aeba | 104 | vflags = SLB_VSID_KERNEL | vmalloc_llp; |
1da177e4 | 105 | |
1189be65 PM |
106 | ksp_esid_data = mk_esid_data(get_paca()->kstack, mmu_kernel_ssize, 2); |
107 | if ((ksp_esid_data & ~0xfffffffUL) <= PAGE_OFFSET) { | |
1da177e4 | 108 | ksp_esid_data &= ~SLB_ESID_V; |
1189be65 | 109 | ksp_vsid_data = 0; |
edd0622b PM |
110 | slb_shadow_clear(2); |
111 | } else { | |
112 | /* Update stack entry; others don't change */ | |
1189be65 | 113 | slb_shadow_update(get_paca()->kstack, mmu_kernel_ssize, lflags, 2); |
7ffcf8ec AB |
114 | ksp_vsid_data = |
115 | be64_to_cpu(get_slb_shadow()->save_area[2].vsid); | |
edd0622b | 116 | } |
2f6093c8 | 117 | |
1da177e4 LT |
118 | /* We need to do this all in asm, so we're sure we don't touch |
119 | * the stack between the slbia and rebolting it. */ | |
120 | asm volatile("isync\n" | |
121 | "slbia\n" | |
122 | /* Slot 1 - first VMALLOC segment */ | |
123 | "slbmte %0,%1\n" | |
124 | /* Slot 2 - kernel stack */ | |
125 | "slbmte %2,%3\n" | |
126 | "isync" | |
1189be65 PM |
127 | :: "r"(mk_vsid_data(VMALLOC_START, mmu_kernel_ssize, vflags)), |
128 | "r"(mk_esid_data(VMALLOC_START, mmu_kernel_ssize, 1)), | |
129 | "r"(ksp_vsid_data), | |
1da177e4 LT |
130 | "r"(ksp_esid_data) |
131 | : "memory"); | |
132 | } | |
133 | ||
9c1e1052 PM |
134 | void slb_flush_and_rebolt(void) |
135 | { | |
136 | ||
137 | WARN_ON(!irqs_disabled()); | |
138 | ||
139 | /* | |
140 | * We can't take a PMU exception in the following code, so hard | |
141 | * disable interrupts. | |
142 | */ | |
143 | hard_irq_disable(); | |
144 | ||
145 | __slb_flush_and_rebolt(); | |
146 | get_paca()->slb_cache_ptr = 0; | |
147 | } | |
148 | ||
67439b76 MN |
149 | void slb_vmalloc_update(void) |
150 | { | |
151 | unsigned long vflags; | |
152 | ||
153 | vflags = SLB_VSID_KERNEL | mmu_psize_defs[mmu_vmalloc_psize].sllp; | |
1189be65 | 154 | slb_shadow_update(VMALLOC_START, mmu_kernel_ssize, vflags, 1); |
67439b76 MN |
155 | slb_flush_and_rebolt(); |
156 | } | |
157 | ||
465ccab9 | 158 | /* Helper function to compare esids. There are four cases to handle. |
159 | * 1. The system is not 1T segment size capable. Use the GET_ESID compare. | |
160 | * 2. The system is 1T capable, both addresses are < 1T, use the GET_ESID compare. | |
161 | * 3. The system is 1T capable, only one of the two addresses is > 1T. This is not a match. | |
162 | * 4. The system is 1T capable, both addresses are > 1T, use the GET_ESID_1T macro to compare. | |
163 | */ | |
164 | static inline int esids_match(unsigned long addr1, unsigned long addr2) | |
165 | { | |
166 | int esid_1t_count; | |
167 | ||
168 | /* System is not 1T segment size capable. */ | |
44ae3ab3 | 169 | if (!mmu_has_feature(MMU_FTR_1T_SEGMENT)) |
465ccab9 | 170 | return (GET_ESID(addr1) == GET_ESID(addr2)); |
171 | ||
172 | esid_1t_count = (((addr1 >> SID_SHIFT_1T) != 0) + | |
173 | ((addr2 >> SID_SHIFT_1T) != 0)); | |
174 | ||
175 | /* both addresses are < 1T */ | |
176 | if (esid_1t_count == 0) | |
177 | return (GET_ESID(addr1) == GET_ESID(addr2)); | |
178 | ||
179 | /* One address < 1T, the other > 1T. Not a match */ | |
180 | if (esid_1t_count == 1) | |
181 | return 0; | |
182 | ||
183 | /* Both addresses are > 1T. */ | |
184 | return (GET_ESID_1T(addr1) == GET_ESID_1T(addr2)); | |
185 | } | |
186 | ||
1da177e4 LT |
187 | /* Flush all user entries from the segment table of the current processor. */ |
188 | void switch_slb(struct task_struct *tsk, struct mm_struct *mm) | |
189 | { | |
9c1e1052 | 190 | unsigned long offset; |
1189be65 | 191 | unsigned long slbie_data = 0; |
1da177e4 LT |
192 | unsigned long pc = KSTK_EIP(tsk); |
193 | unsigned long stack = KSTK_ESP(tsk); | |
de4376c2 | 194 | unsigned long exec_base; |
1da177e4 | 195 | |
9c1e1052 PM |
196 | /* |
197 | * We need interrupts hard-disabled here, not just soft-disabled, | |
198 | * so that a PMU interrupt can't occur, which might try to access | |
199 | * user memory (to get a stack trace) and possible cause an SLB miss | |
200 | * which would update the slb_cache/slb_cache_ptr fields in the PACA. | |
201 | */ | |
202 | hard_irq_disable(); | |
203 | offset = get_paca()->slb_cache_ptr; | |
44ae3ab3 | 204 | if (!mmu_has_feature(MMU_FTR_NO_SLBIE_B) && |
f66bce5e | 205 | offset <= SLB_CACHE_ENTRIES) { |
1da177e4 LT |
206 | int i; |
207 | asm volatile("isync" : : : "memory"); | |
208 | for (i = 0; i < offset; i++) { | |
1189be65 PM |
209 | slbie_data = (unsigned long)get_paca()->slb_cache[i] |
210 | << SID_SHIFT; /* EA */ | |
211 | slbie_data |= user_segment_size(slbie_data) | |
212 | << SLBIE_SSIZE_SHIFT; | |
213 | slbie_data |= SLBIE_C; /* C set for user addresses */ | |
214 | asm volatile("slbie %0" : : "r" (slbie_data)); | |
1da177e4 LT |
215 | } |
216 | asm volatile("isync" : : : "memory"); | |
217 | } else { | |
9c1e1052 | 218 | __slb_flush_and_rebolt(); |
1da177e4 LT |
219 | } |
220 | ||
221 | /* Workaround POWER5 < DD2.1 issue */ | |
222 | if (offset == 1 || offset > SLB_CACHE_ENTRIES) | |
1189be65 | 223 | asm volatile("slbie %0" : : "r" (slbie_data)); |
1da177e4 LT |
224 | |
225 | get_paca()->slb_cache_ptr = 0; | |
226 | get_paca()->context = mm->context; | |
227 | ||
228 | /* | |
229 | * preload some userspace segments into the SLB. | |
de4376c2 AB |
230 | * Almost all 32 and 64bit PowerPC executables are linked at |
231 | * 0x10000000 so it makes sense to preload this segment. | |
1da177e4 | 232 | */ |
de4376c2 | 233 | exec_base = 0x10000000; |
1da177e4 | 234 | |
5eb9bac0 | 235 | if (is_kernel_addr(pc) || is_kernel_addr(stack) || |
de4376c2 | 236 | is_kernel_addr(exec_base)) |
1da177e4 LT |
237 | return; |
238 | ||
5eb9bac0 | 239 | slb_allocate(pc); |
1da177e4 | 240 | |
5eb9bac0 AB |
241 | if (!esids_match(pc, stack)) |
242 | slb_allocate(stack); | |
1da177e4 | 243 | |
de4376c2 AB |
244 | if (!esids_match(pc, exec_base) && |
245 | !esids_match(stack, exec_base)) | |
246 | slb_allocate(exec_base); | |
1da177e4 LT |
247 | } |
248 | ||
3c726f8d BH |
249 | static inline void patch_slb_encoding(unsigned int *insn_addr, |
250 | unsigned int immed) | |
251 | { | |
79d0be74 AK |
252 | |
253 | /* | |
254 | * This function patches either an li or a cmpldi instruction with | |
255 | * a new immediate value. This relies on the fact that both li | |
256 | * (which is actually addi) and cmpldi both take a 16-bit immediate | |
257 | * value, and it is situated in the same location in the instruction, | |
258 | * ie. bits 16-31 (Big endian bit order) or the lower 16 bits. | |
259 | * The signedness of the immediate operand differs between the two | |
260 | * instructions however this code is only ever patching a small value, | |
261 | * much less than 1 << 15, so we can get away with it. | |
262 | * To patch the value we read the existing instruction, clear the | |
263 | * immediate value, and or in our new value, then write the instruction | |
264 | * back. | |
265 | */ | |
266 | unsigned int insn = (*insn_addr & 0xffff0000) | immed; | |
b68a70c4 | 267 | patch_instruction(insn_addr, insn); |
3c726f8d BH |
268 | } |
269 | ||
b86206e4 AB |
270 | extern u32 slb_miss_kernel_load_linear[]; |
271 | extern u32 slb_miss_kernel_load_io[]; | |
272 | extern u32 slb_compare_rr_to_size[]; | |
273 | extern u32 slb_miss_kernel_load_vmemmap[]; | |
274 | ||
46db2f86 BK |
275 | void slb_set_size(u16 size) |
276 | { | |
46db2f86 BK |
277 | if (mmu_slb_size == size) |
278 | return; | |
279 | ||
280 | mmu_slb_size = size; | |
281 | patch_slb_encoding(slb_compare_rr_to_size, mmu_slb_size); | |
282 | } | |
283 | ||
1da177e4 LT |
284 | void slb_initialize(void) |
285 | { | |
bf72aeba | 286 | unsigned long linear_llp, vmalloc_llp, io_llp; |
56291e19 | 287 | unsigned long lflags, vflags; |
3c726f8d | 288 | static int slb_encoding_inited; |
cec08e7a | 289 | #ifdef CONFIG_SPARSEMEM_VMEMMAP |
cec08e7a BH |
290 | unsigned long vmemmap_llp; |
291 | #endif | |
3c726f8d BH |
292 | |
293 | /* Prepare our SLB miss handler based on our page size */ | |
294 | linear_llp = mmu_psize_defs[mmu_linear_psize].sllp; | |
bf72aeba PM |
295 | io_llp = mmu_psize_defs[mmu_io_psize].sllp; |
296 | vmalloc_llp = mmu_psize_defs[mmu_vmalloc_psize].sllp; | |
297 | get_paca()->vmalloc_sllp = SLB_VSID_KERNEL | vmalloc_llp; | |
cec08e7a BH |
298 | #ifdef CONFIG_SPARSEMEM_VMEMMAP |
299 | vmemmap_llp = mmu_psize_defs[mmu_vmemmap_psize].sllp; | |
300 | #endif | |
3c726f8d BH |
301 | if (!slb_encoding_inited) { |
302 | slb_encoding_inited = 1; | |
303 | patch_slb_encoding(slb_miss_kernel_load_linear, | |
304 | SLB_VSID_KERNEL | linear_llp); | |
bf72aeba PM |
305 | patch_slb_encoding(slb_miss_kernel_load_io, |
306 | SLB_VSID_KERNEL | io_llp); | |
584f8b71 MN |
307 | patch_slb_encoding(slb_compare_rr_to_size, |
308 | mmu_slb_size); | |
3c726f8d | 309 | |
651e2dd2 ME |
310 | pr_devel("SLB: linear LLP = %04lx\n", linear_llp); |
311 | pr_devel("SLB: io LLP = %04lx\n", io_llp); | |
cec08e7a BH |
312 | |
313 | #ifdef CONFIG_SPARSEMEM_VMEMMAP | |
314 | patch_slb_encoding(slb_miss_kernel_load_vmemmap, | |
315 | SLB_VSID_KERNEL | vmemmap_llp); | |
651e2dd2 | 316 | pr_devel("SLB: vmemmap LLP = %04lx\n", vmemmap_llp); |
cec08e7a | 317 | #endif |
3c726f8d BH |
318 | } |
319 | ||
56291e19 SR |
320 | get_paca()->stab_rr = SLB_NUM_BOLTED; |
321 | ||
3c726f8d | 322 | lflags = SLB_VSID_KERNEL | linear_llp; |
bf72aeba | 323 | vflags = SLB_VSID_KERNEL | vmalloc_llp; |
1da177e4 | 324 | |
2be682af | 325 | /* Invalidate the entire SLB (even entry 0) & all the ERATS */ |
175587cc PM |
326 | asm volatile("isync":::"memory"); |
327 | asm volatile("slbmte %0,%0"::"r" (0) : "memory"); | |
328 | asm volatile("isync; slbia; isync":::"memory"); | |
1189be65 | 329 | create_shadowed_slbe(PAGE_OFFSET, mmu_kernel_ssize, lflags, 0); |
1189be65 | 330 | create_shadowed_slbe(VMALLOC_START, mmu_kernel_ssize, vflags, 1); |
175587cc | 331 | |
3b575064 PM |
332 | /* For the boot cpu, we're running on the stack in init_thread_union, |
333 | * which is in the first segment of the linear mapping, and also | |
334 | * get_paca()->kstack hasn't been initialized yet. | |
335 | * For secondary cpus, we need to bolt the kernel stack entry now. | |
336 | */ | |
dfbe0d3b | 337 | slb_shadow_clear(2); |
3b575064 PM |
338 | if (raw_smp_processor_id() != boot_cpuid && |
339 | (get_paca()->kstack & slb_esid_mask(mmu_kernel_ssize)) > PAGE_OFFSET) | |
340 | create_shadowed_slbe(get_paca()->kstack, | |
341 | mmu_kernel_ssize, lflags, 2); | |
dfbe0d3b | 342 | |
175587cc | 343 | asm volatile("isync":::"memory"); |
1da177e4 | 344 | } |