[mirror_ubuntu-jammy-kernel.git] / arch / powerpc / mm / slb.c

/*
 * PowerPC64 SLB support.
 *
 * Copyright (C) 2004 David Gibson <dwg@au.ibm.com>, IBM
 * Based on earlier code writteh by:
 * Dave Engebretsen and Mike Corrigan {engebret|mikejc}@us.ibm.com
 *    Copyright (c) 2001 Dave Engebretsen
 * Copyright (C) 2002 Anton Blanchard <anton@au.ibm.com>, IBM
 *
 *
 *      This program is free software; you can redistribute it and/or
 *      modify it under the terms of the GNU General Public License
 *      as published by the Free Software Foundation; either version
 *      2 of the License, or (at your option) any later version.
 */

#undef DEBUG

#include <asm/pgtable.h>
#include <asm/mmu.h>
#include <asm/mmu_context.h>
#include <asm/paca.h>
#include <asm/cputable.h>
#include <asm/cacheflush.h>

#ifdef DEBUG
#define DBG(fmt...) udbg_printf(fmt)
#else
#define DBG(fmt...)
#endif

extern void slb_allocate_realmode(unsigned long ea);
extern void slb_allocate_user(unsigned long ea);

static void slb_allocate(unsigned long ea)
{
	/* Currently, we do real mode for all SLBs including user, but
	 * that will change if we bring back dynamic VSIDs
	 */
	slb_allocate_realmode(ea);
}

static inline unsigned long mk_esid_data(unsigned long ea, unsigned long slot)
{
	return (ea & ESID_MASK) | SLB_ESID_V | slot;
}

static inline unsigned long mk_vsid_data(unsigned long ea, unsigned long flags)
{
	return (get_kernel_vsid(ea) << SLB_VSID_SHIFT) | flags;
}

static inline void create_slbe(unsigned long ea, unsigned long flags,
			       unsigned long entry)
{
	asm volatile("slbmte  %0,%1" :
		     : "r" (mk_vsid_data(ea, flags)),
		       "r" (mk_esid_data(ea, entry))
		     : "memory" );
}

void slb_flush_and_rebolt(void)
{
	/* If you change this make sure you change SLB_NUM_BOLTED
	 * appropriately too. */
	unsigned long linear_llp, vmalloc_llp, lflags, vflags;
	unsigned long ksp_esid_data;

	WARN_ON(!irqs_disabled());

	linear_llp = mmu_psize_defs[mmu_linear_psize].sllp;
	vmalloc_llp = mmu_psize_defs[mmu_vmalloc_psize].sllp;
	lflags = SLB_VSID_KERNEL | linear_llp;
	vflags = SLB_VSID_KERNEL | vmalloc_llp;

	ksp_esid_data = mk_esid_data(get_paca()->kstack, 2);
	if ((ksp_esid_data & ESID_MASK) == PAGE_OFFSET)
		ksp_esid_data &= ~SLB_ESID_V;

	/* We need to do this all in asm, so we're sure we don't touch
	 * the stack between the slbia and rebolting it. */
	asm volatile("isync\n"
		     "slbia\n"
		     /* Slot 1 - first VMALLOC segment */
		     "slbmte	%0,%1\n"
		     /* Slot 2 - kernel stack */
		     "slbmte	%2,%3\n"
		     "isync"
		     :: "r"(mk_vsid_data(VMALLOC_START, vflags)),
		        "r"(mk_esid_data(VMALLOC_START, 1)),
		        "r"(mk_vsid_data(ksp_esid_data, lflags)),
		        "r"(ksp_esid_data)
		     : "memory");
}

/* Flush all user entries from the segment table of the current processor. */
void switch_slb(struct task_struct *tsk, struct mm_struct *mm)
{
	unsigned long offset = get_paca()->slb_cache_ptr;
	unsigned long esid_data = 0;
	unsigned long pc = KSTK_EIP(tsk);
	unsigned long stack = KSTK_ESP(tsk);
	unsigned long unmapped_base;

	if (offset <= SLB_CACHE_ENTRIES) {
		int i;
		asm volatile("isync" : : : "memory");
		for (i = 0; i < offset; i++) {
			esid_data = ((unsigned long)get_paca()->slb_cache[i]
				<< SID_SHIFT) | SLBIE_C;
			asm volatile("slbie %0" : : "r" (esid_data));
		}
		asm volatile("isync" : : : "memory");
	} else {
		slb_flush_and_rebolt();
	}

	/* Workaround POWER5 < DD2.1 issue */
	if (offset == 1 || offset > SLB_CACHE_ENTRIES)
		asm volatile("slbie %0" : : "r" (esid_data));

	get_paca()->slb_cache_ptr = 0;
	get_paca()->context = mm->context;

	/*
	 * preload some userspace segments into the SLB.
	 */
	if (test_tsk_thread_flag(tsk, TIF_32BIT))
		unmapped_base = TASK_UNMAPPED_BASE_USER32;
	else
		unmapped_base = TASK_UNMAPPED_BASE_USER64;

	if (is_kernel_addr(pc))
		return;
	slb_allocate(pc);

	if (GET_ESID(pc) == GET_ESID(stack))
		return;

	if (is_kernel_addr(stack))
		return;
	slb_allocate(stack);

	if ((GET_ESID(pc) == GET_ESID(unmapped_base))
	    || (GET_ESID(stack) == GET_ESID(unmapped_base)))
		return;

	if (is_kernel_addr(unmapped_base))
		return;
	slb_allocate(unmapped_base);
}

static inline void patch_slb_encoding(unsigned int *insn_addr,
				      unsigned int immed)
{
	/* Assume the instruction had a "0" immediate value, just
	 * "or" in the new value
	 */
	*insn_addr |= immed;
	flush_icache_range((unsigned long)insn_addr, 4+
			   (unsigned long)insn_addr);
}

void slb_initialize(void)
{
	unsigned long linear_llp, vmalloc_llp, io_llp;
	static int slb_encoding_inited;
	extern unsigned int *slb_miss_kernel_load_linear;
	extern unsigned int *slb_miss_kernel_load_io;
#ifdef CONFIG_HUGETLB_PAGE
	extern unsigned int *slb_miss_user_load_huge;
	unsigned long huge_llp;

	huge_llp = mmu_psize_defs[mmu_huge_psize].sllp;
#endif

	/* Prepare our SLB miss handler based on our page size */
	linear_llp = mmu_psize_defs[mmu_linear_psize].sllp;
	io_llp = mmu_psize_defs[mmu_io_psize].sllp;
	vmalloc_llp = mmu_psize_defs[mmu_vmalloc_psize].sllp;
	get_paca()->vmalloc_sllp = SLB_VSID_KERNEL | vmalloc_llp;

	if (!slb_encoding_inited) {
		slb_encoding_inited = 1;
		patch_slb_encoding(slb_miss_kernel_load_linear,
				   SLB_VSID_KERNEL | linear_llp);
		patch_slb_encoding(slb_miss_kernel_load_io,
				   SLB_VSID_KERNEL | io_llp);

		DBG("SLB: linear  LLP = %04x\n", linear_llp);
		DBG("SLB: io      LLP = %04x\n", io_llp);
#ifdef CONFIG_HUGETLB_PAGE
		patch_slb_encoding(slb_miss_user_load_huge,
				   SLB_VSID_USER | huge_llp);
		DBG("SLB: huge    LLP = %04x\n", huge_llp);
#endif
	}

	/* On iSeries the bolted entries have already been set up by
	 * the hypervisor from the lparMap data in head.S */
#ifndef CONFIG_PPC_ISERIES
 {
	unsigned long lflags, vflags;

	lflags = SLB_VSID_KERNEL | linear_llp;
	vflags = SLB_VSID_KERNEL | vmalloc_llp;

	/* Invalidate the entire SLB (even slot 0) & all the ERATS */
	asm volatile("isync":::"memory");
	asm volatile("slbmte  %0,%0"::"r" (0) : "memory");
	asm volatile("isync; slbia; isync":::"memory");
	create_slbe(PAGE_OFFSET, lflags, 0);

	create_slbe(VMALLOC_START, vflags, 1);

	/* We don't bolt the stack for the time being - we're in boot,
	 * so the stack is in the bolted segment.  By the time it goes
	 * elsewhere, we'll call _switch() which will bolt in the new
	 * one. */
	asm volatile("isync":::"memory");
 }
#endif /* CONFIG_PPC_ISERIES */

	get_paca()->stab_rr = SLB_NUM_BOLTED;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* PowerPC64 SLB support.
	3	*
	4	* Copyright (C) 2004 David Gibson <dwg@au.ibm.com>, IBM
	5	* Based on earlier code writteh by:
	6	* Dave Engebretsen and Mike Corrigan {engebret\|mikejc}@us.ibm.com
	7	* Copyright (c) 2001 Dave Engebretsen
	8	* Copyright (C) 2002 Anton Blanchard <anton@au.ibm.com>, IBM
	9	*
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License
	13	* as published by the Free Software Foundation; either version
	14	* 2 of the License, or (at your option) any later version.
	15	*/
	16
3c726f8d BH	17	#undef DEBUG
3c726f8d BH	18
1da177e4 LT	19	#include <asm/pgtable.h>
	20	#include <asm/mmu.h>
	21	#include <asm/mmu_context.h>
	22	#include <asm/paca.h>
	23	#include <asm/cputable.h>
3c726f8d BH	24	#include <asm/cacheflush.h>
	25
	26	#ifdef DEBUG
	27	#define DBG(fmt...) udbg_printf(fmt)
	28	#else
	29	#define DBG(fmt...)
	30	#endif
1da177e4	31
3c726f8d BH	32	extern void slb_allocate_realmode(unsigned long ea);
	33	extern void slb_allocate_user(unsigned long ea);
	34
	35	static void slb_allocate(unsigned long ea)
	36	{
	37	/* Currently, we do real mode for all SLBs including user, but
	38	* that will change if we bring back dynamic VSIDs
	39	*/
	40	slb_allocate_realmode(ea);
	41	}
1da177e4 LT	42
	43	static inline unsigned long mk_esid_data(unsigned long ea, unsigned long slot)
	44	{
	45	return (ea & ESID_MASK) \| SLB_ESID_V \| slot;
	46	}
	47
	48	static inline unsigned long mk_vsid_data(unsigned long ea, unsigned long flags)
	49	{
	50	return (get_kernel_vsid(ea) << SLB_VSID_SHIFT) \| flags;
	51	}
	52
bb78cb72 OJ	53	static inline void create_slbe(unsigned long ea, unsigned long flags,
bb78cb72 OJ	54	unsigned long entry)
1da177e4 LT	55	{
	56	asm volatile("slbmte %0,%1" :
	57	: "r" (mk_vsid_data(ea, flags)),
	58	"r" (mk_esid_data(ea, entry))
	59	: "memory" );
	60	}
	61
bf72aeba	62	void slb_flush_and_rebolt(void)
1da177e4 LT	63	{
	64	/* If you change this make sure you change SLB_NUM_BOLTED
	65	* appropriately too. */
bf72aeba	66	unsigned long linear_llp, vmalloc_llp, lflags, vflags;
1da177e4 LT	67	unsigned long ksp_esid_data;
	68
	69	WARN_ON(!irqs_disabled());
	70
3c726f8d	71	linear_llp = mmu_psize_defs[mmu_linear_psize].sllp;
bf72aeba	72	vmalloc_llp = mmu_psize_defs[mmu_vmalloc_psize].sllp;
3c726f8d	73	lflags = SLB_VSID_KERNEL \| linear_llp;
bf72aeba	74	vflags = SLB_VSID_KERNEL \| vmalloc_llp;
1da177e4 LT	75
1da177e4 LT	76	ksp_esid_data = mk_esid_data(get_paca()->kstack, 2);
b5666f70	77	if ((ksp_esid_data & ESID_MASK) == PAGE_OFFSET)
1da177e4 LT	78	ksp_esid_data &= ~SLB_ESID_V;
	79
	80	/* We need to do this all in asm, so we're sure we don't touch
	81	* the stack between the slbia and rebolting it. */
	82	asm volatile("isync\n"
	83	"slbia\n"
	84	/* Slot 1 - first VMALLOC segment */
	85	"slbmte %0,%1\n"
	86	/* Slot 2 - kernel stack */
	87	"slbmte %2,%3\n"
	88	"isync"
14c89e7f DG	89	:: "r"(mk_vsid_data(VMALLOC_START, vflags)),
14c89e7f DG	90	"r"(mk_esid_data(VMALLOC_START, 1)),
3c726f8d	91	"r"(mk_vsid_data(ksp_esid_data, lflags)),
1da177e4 LT	92	"r"(ksp_esid_data)
	93	: "memory");
	94	}
	95
	96	/* Flush all user entries from the segment table of the current processor. */
	97	void switch_slb(struct task_struct tsk, struct mm_struct mm)
	98	{
	99	unsigned long offset = get_paca()->slb_cache_ptr;
	100	unsigned long esid_data = 0;
	101	unsigned long pc = KSTK_EIP(tsk);
	102	unsigned long stack = KSTK_ESP(tsk);
	103	unsigned long unmapped_base;
	104
	105	if (offset <= SLB_CACHE_ENTRIES) {
	106	int i;
	107	asm volatile("isync" : : : "memory");
	108	for (i = 0; i < offset; i++) {
14b34661 DG	109	esid_data = ((unsigned long)get_paca()->slb_cache[i]
14b34661 DG	110	<< SID_SHIFT) \| SLBIE_C;
1da177e4 LT	111	asm volatile("slbie %0" : : "r" (esid_data));
	112	}
	113	asm volatile("isync" : : : "memory");
	114	} else {
	115	slb_flush_and_rebolt();
	116	}
	117
	118	/* Workaround POWER5 < DD2.1 issue */
	119	if (offset == 1 \|\| offset > SLB_CACHE_ENTRIES)
	120	asm volatile("slbie %0" : : "r" (esid_data));
	121
	122	get_paca()->slb_cache_ptr = 0;
	123	get_paca()->context = mm->context;
	124
	125	/*
	126	* preload some userspace segments into the SLB.
	127	*/
	128	if (test_tsk_thread_flag(tsk, TIF_32BIT))
	129	unmapped_base = TASK_UNMAPPED_BASE_USER32;
	130	else
	131	unmapped_base = TASK_UNMAPPED_BASE_USER64;
	132
51fae6de	133	if (is_kernel_addr(pc))
1da177e4 LT	134	return;
	135	slb_allocate(pc);
	136
	137	if (GET_ESID(pc) == GET_ESID(stack))
	138	return;
	139
51fae6de	140	if (is_kernel_addr(stack))
1da177e4 LT	141	return;
	142	slb_allocate(stack);
	143
	144	if ((GET_ESID(pc) == GET_ESID(unmapped_base))
	145	\|\| (GET_ESID(stack) == GET_ESID(unmapped_base)))
	146	return;
	147
51fae6de	148	if (is_kernel_addr(unmapped_base))
1da177e4 LT	149	return;
	150	slb_allocate(unmapped_base);
	151	}
	152
3c726f8d BH	153	static inline void patch_slb_encoding(unsigned int *insn_addr,
	154	unsigned int immed)
	155	{
	156	/* Assume the instruction had a "0" immediate value, just
	157	* "or" in the new value
	158	*/
	159	*insn_addr \|= immed;
	160	flush_icache_range((unsigned long)insn_addr, 4+
	161	(unsigned long)insn_addr);
	162	}
	163
1da177e4 LT	164	void slb_initialize(void)
1da177e4 LT	165	{
bf72aeba	166	unsigned long linear_llp, vmalloc_llp, io_llp;
3c726f8d BH	167	static int slb_encoding_inited;
3c726f8d BH	168	extern unsigned int *slb_miss_kernel_load_linear;
bf72aeba	169	extern unsigned int *slb_miss_kernel_load_io;
3c726f8d BH	170	#ifdef CONFIG_HUGETLB_PAGE
	171	extern unsigned int *slb_miss_user_load_huge;
	172	unsigned long huge_llp;
	173
	174	huge_llp = mmu_psize_defs[mmu_huge_psize].sllp;
	175	#endif
	176
	177	/* Prepare our SLB miss handler based on our page size */
	178	linear_llp = mmu_psize_defs[mmu_linear_psize].sllp;
bf72aeba PM	179	io_llp = mmu_psize_defs[mmu_io_psize].sllp;
	180	vmalloc_llp = mmu_psize_defs[mmu_vmalloc_psize].sllp;
	181	get_paca()->vmalloc_sllp = SLB_VSID_KERNEL \| vmalloc_llp;
	182
3c726f8d BH	183	if (!slb_encoding_inited) {
	184	slb_encoding_inited = 1;
	185	patch_slb_encoding(slb_miss_kernel_load_linear,
	186	SLB_VSID_KERNEL \| linear_llp);
bf72aeba PM	187	patch_slb_encoding(slb_miss_kernel_load_io,
bf72aeba PM	188	SLB_VSID_KERNEL \| io_llp);
3c726f8d BH	189
3c726f8d BH	190	DBG("SLB: linear LLP = %04x\n", linear_llp);
bf72aeba	191	DBG("SLB: io LLP = %04x\n", io_llp);
3c726f8d BH	192	#ifdef CONFIG_HUGETLB_PAGE
	193	patch_slb_encoding(slb_miss_user_load_huge,
	194	SLB_VSID_USER \| huge_llp);
	195	DBG("SLB: huge LLP = %04x\n", huge_llp);
	196	#endif
	197	}
	198
1da177e4 LT	199	/* On iSeries the bolted entries have already been set up by
	200	* the hypervisor from the lparMap data in head.S */
	201	#ifndef CONFIG_PPC_ISERIES
3c726f8d BH	202	{
3c726f8d BH	203	unsigned long lflags, vflags;
1da177e4	204
3c726f8d	205	lflags = SLB_VSID_KERNEL \| linear_llp;
bf72aeba	206	vflags = SLB_VSID_KERNEL \| vmalloc_llp;
1da177e4	207
3c726f8d BH	208	/* Invalidate the entire SLB (even slot 0) & all the ERATS */
	209	asm volatile("isync":::"memory");
	210	asm volatile("slbmte %0,%0"::"r" (0) : "memory");
1da177e4	211	asm volatile("isync; slbia; isync":::"memory");
b5666f70	212	create_slbe(PAGE_OFFSET, lflags, 0);
3c726f8d	213
14c89e7f	214	create_slbe(VMALLOC_START, vflags, 1);
3c726f8d	215
1da177e4 LT	216	/* We don't bolt the stack for the time being - we're in boot,
	217	* so the stack is in the bolted segment. By the time it goes
	218	* elsewhere, we'll call _switch() which will bolt in the new
	219	* one. */
	220	asm volatile("isync":::"memory");
3c726f8d BH	221	}
3c726f8d BH	222	#endif /* CONFIG_PPC_ISERIES */
1da177e4 LT	223
	224	get_paca()->stab_rr = SLB_NUM_BOLTED;
	225	}