[mirror_ubuntu-zesty-kernel.git] / arch / powerpc / mm / tlb-radix.c

/*
 * TLB flush routines for radix kernels.
 *
 * Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#include <linux/mm.h>
#include <linux/hugetlb.h>
#include <linux/memblock.h>
#include <asm/ppc-opcode.h>

#include <asm/tlb.h>
#include <asm/tlbflush.h>

static DEFINE_RAW_SPINLOCK(native_tlbie_lock);

#define RIC_FLUSH_TLB 0
#define RIC_FLUSH_PWC 1
#define RIC_FLUSH_ALL 2

static inline void __tlbiel_pid(unsigned long pid, int set,
				unsigned long ric)
{
	unsigned long rb,rs,prs,r;

	rb = PPC_BIT(53); /* IS = 1 */
	rb |= set << PPC_BITLSHIFT(51);
	rs = ((unsigned long)pid) << PPC_BITLSHIFT(31);
	prs = 1; /* process scoped */
	r = 1;   /* raidx format */

	asm volatile("ptesync": : :"memory");
	asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
		     : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
	asm volatile("ptesync": : :"memory");
}

/*
 * We use 128 set in radix mode and 256 set in hpt mode.
 */
static inline void _tlbiel_pid(unsigned long pid, unsigned long ric)
{
	int set;

	for (set = 0; set < POWER9_TLB_SETS_RADIX ; set++) {
		__tlbiel_pid(pid, set, ric);
	}
	asm volatile(PPC_INVALIDATE_ERAT "; isync" : : :"memory");
}

static inline void _tlbie_pid(unsigned long pid, unsigned long ric)
{
	unsigned long rb,rs,prs,r;

	rb = PPC_BIT(53); /* IS = 1 */
	rs = pid << PPC_BITLSHIFT(31);
	prs = 1; /* process scoped */
	r = 1;   /* raidx format */

	asm volatile("ptesync": : :"memory");
	asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
		     : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
	asm volatile("eieio; tlbsync; ptesync": : :"memory");
}

static inline void _tlbiel_va(unsigned long va, unsigned long pid,
			      unsigned long ap, unsigned long ric)
{
	unsigned long rb,rs,prs,r;

	rb = va & ~(PPC_BITMASK(52, 63));
	rb |= ap << PPC_BITLSHIFT(58);
	rs = pid << PPC_BITLSHIFT(31);
	prs = 1; /* process scoped */
	r = 1;   /* raidx format */

	asm volatile("ptesync": : :"memory");
	asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
		     : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
	asm volatile("ptesync": : :"memory");
}

static inline void _tlbie_va(unsigned long va, unsigned long pid,
			     unsigned long ap, unsigned long ric)
{
	unsigned long rb,rs,prs,r;

	rb = va & ~(PPC_BITMASK(52, 63));
	rb |= ap << PPC_BITLSHIFT(58);
	rs = pid << PPC_BITLSHIFT(31);
	prs = 1; /* process scoped */
	r = 1;   /* raidx format */

	asm volatile("ptesync": : :"memory");
	asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
		     : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
	asm volatile("eieio; tlbsync; ptesync": : :"memory");
}

/*
 * Base TLB flushing operations:
 *
 *  - flush_tlb_mm(mm) flushes the specified mm context TLB's
 *  - flush_tlb_page(vma, vmaddr) flushes one page
 *  - flush_tlb_range(vma, start, end) flushes a range of pages
 *  - flush_tlb_kernel_range(start, end) flushes kernel pages
 *
 *  - local_* variants of page and mm only apply to the current
 *    processor
 */
void radix__local_flush_tlb_mm(struct mm_struct *mm)
{
	unsigned long pid;

	preempt_disable();
	pid = mm->context.id;
	if (pid != MMU_NO_CONTEXT)
		_tlbiel_pid(pid, RIC_FLUSH_ALL);
	preempt_enable();
}
EXPORT_SYMBOL(radix__local_flush_tlb_mm);

void radix__local_flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr)
{
	unsigned long pid;
	struct mm_struct *mm = tlb->mm;

	preempt_disable();

	pid = mm->context.id;
	if (pid != MMU_NO_CONTEXT)
		_tlbiel_pid(pid, RIC_FLUSH_PWC);

	preempt_enable();
}
EXPORT_SYMBOL(radix__local_flush_tlb_pwc);

void radix__local_flush_tlb_page_psize(struct mm_struct *mm, unsigned long vmaddr,
				       int psize)
{
	unsigned long pid;
	unsigned long ap = mmu_get_ap(psize);

	preempt_disable();
	pid = mm ? mm->context.id : 0;
	if (pid != MMU_NO_CONTEXT)
		_tlbiel_va(vmaddr, pid, ap, RIC_FLUSH_TLB);
	preempt_enable();
}

void radix__local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
{
#ifdef CONFIG_HUGETLB_PAGE
	/* need the return fix for nohash.c */
	if (vma && is_vm_hugetlb_page(vma))
		return __local_flush_hugetlb_page(vma, vmaddr);
#endif
	radix__local_flush_tlb_page_psize(vma ? vma->vm_mm : NULL, vmaddr,
					  mmu_virtual_psize);
}
EXPORT_SYMBOL(radix__local_flush_tlb_page);

#ifdef CONFIG_SMP
void radix__flush_tlb_mm(struct mm_struct *mm)
{
	unsigned long pid;

	preempt_disable();
	pid = mm->context.id;
	if (unlikely(pid == MMU_NO_CONTEXT))
		goto no_context;

	if (!mm_is_thread_local(mm)) {
		int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);

		if (lock_tlbie)
			raw_spin_lock(&native_tlbie_lock);
		_tlbie_pid(pid, RIC_FLUSH_ALL);
		if (lock_tlbie)
			raw_spin_unlock(&native_tlbie_lock);
	} else
		_tlbiel_pid(pid, RIC_FLUSH_ALL);
no_context:
	preempt_enable();
}
EXPORT_SYMBOL(radix__flush_tlb_mm);

void radix__flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr)
{
	unsigned long pid;
	struct mm_struct *mm = tlb->mm;

	preempt_disable();

	pid = mm->context.id;
	if (unlikely(pid == MMU_NO_CONTEXT))
		goto no_context;

	if (!mm_is_thread_local(mm)) {
		int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);

		if (lock_tlbie)
			raw_spin_lock(&native_tlbie_lock);
		_tlbie_pid(pid, RIC_FLUSH_PWC);
		if (lock_tlbie)
			raw_spin_unlock(&native_tlbie_lock);
	} else
		_tlbiel_pid(pid, RIC_FLUSH_PWC);
no_context:
	preempt_enable();
}
EXPORT_SYMBOL(radix__flush_tlb_pwc);

void radix__flush_tlb_page_psize(struct mm_struct *mm, unsigned long vmaddr,
				 int psize)
{
	unsigned long pid;
	unsigned long ap = mmu_get_ap(psize);

	preempt_disable();
	pid = mm ? mm->context.id : 0;
	if (unlikely(pid == MMU_NO_CONTEXT))
		goto bail;
	if (!mm_is_thread_local(mm)) {
		int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);

		if (lock_tlbie)
			raw_spin_lock(&native_tlbie_lock);
		_tlbie_va(vmaddr, pid, ap, RIC_FLUSH_TLB);
		if (lock_tlbie)
			raw_spin_unlock(&native_tlbie_lock);
	} else
		_tlbiel_va(vmaddr, pid, ap, RIC_FLUSH_TLB);
bail:
	preempt_enable();
}

void radix__flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
{
#ifdef CONFIG_HUGETLB_PAGE
	if (vma && is_vm_hugetlb_page(vma))
		return flush_hugetlb_page(vma, vmaddr);
#endif
	radix__flush_tlb_page_psize(vma ? vma->vm_mm : NULL, vmaddr,
				    mmu_virtual_psize);
}
EXPORT_SYMBOL(radix__flush_tlb_page);

#endif /* CONFIG_SMP */

void radix__flush_tlb_kernel_range(unsigned long start, unsigned long end)
{
	int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);

	if (lock_tlbie)
		raw_spin_lock(&native_tlbie_lock);
	_tlbie_pid(0, RIC_FLUSH_ALL);
	if (lock_tlbie)
		raw_spin_unlock(&native_tlbie_lock);
}
EXPORT_SYMBOL(radix__flush_tlb_kernel_range);

/*
 * Currently, for range flushing, we just do a full mm flush. Because
 * we use this in code path where we don' track the page size.
 */
void radix__flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
		     unsigned long end)

{
	struct mm_struct *mm = vma->vm_mm;
	radix__flush_tlb_mm(mm);
}
EXPORT_SYMBOL(radix__flush_tlb_range);

static int radix_get_mmu_psize(int page_size)
{
	int psize;

	if (page_size == (1UL << mmu_psize_defs[mmu_virtual_psize].shift))
		psize = mmu_virtual_psize;
	else if (page_size == (1UL << mmu_psize_defs[MMU_PAGE_2M].shift))
		psize = MMU_PAGE_2M;
	else if (page_size == (1UL << mmu_psize_defs[MMU_PAGE_1G].shift))
		psize = MMU_PAGE_1G;
	else
		return -1;
	return psize;
}

void radix__tlb_flush(struct mmu_gather *tlb)
{
	int psize = 0;
	struct mm_struct *mm = tlb->mm;
	int page_size = tlb->page_size;

	psize = radix_get_mmu_psize(page_size);
	/*
	 * if page size is not something we understand, do a full mm flush
	 */
	if (psize != -1 && !tlb->fullmm && !tlb->need_flush_all)
		radix__flush_tlb_range_psize(mm, tlb->start, tlb->end, psize);
	else
		radix__flush_tlb_mm(mm);
}

#define TLB_FLUSH_ALL -1UL
/*
 * Number of pages above which we will do a bcast tlbie. Just a
 * number at this point copied from x86
 */
static unsigned long tlb_single_page_flush_ceiling __read_mostly = 33;

void radix__flush_tlb_range_psize(struct mm_struct *mm, unsigned long start,
				  unsigned long end, int psize)
{
	unsigned long pid;
	unsigned long addr;
	int local = mm_is_thread_local(mm);
	unsigned long ap = mmu_get_ap(psize);
	int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
	unsigned long page_size = 1UL << mmu_psize_defs[psize].shift;


	preempt_disable();
	pid = mm ? mm->context.id : 0;
	if (unlikely(pid == MMU_NO_CONTEXT))
		goto err_out;

	if (end == TLB_FLUSH_ALL ||
	    (end - start) > tlb_single_page_flush_ceiling * page_size) {
		if (local)
			_tlbiel_pid(pid, RIC_FLUSH_TLB);
		else
			_tlbie_pid(pid, RIC_FLUSH_TLB);
		goto err_out;
	}
	for (addr = start; addr < end; addr += page_size) {

		if (local)
			_tlbiel_va(addr, pid, ap, RIC_FLUSH_TLB);
		else {
			if (lock_tlbie)
				raw_spin_lock(&native_tlbie_lock);
			_tlbie_va(addr, pid, ap, RIC_FLUSH_TLB);
			if (lock_tlbie)
				raw_spin_unlock(&native_tlbie_lock);
		}
	}
err_out:
	preempt_enable();
}

void radix__flush_tlb_lpid_va(unsigned long lpid, unsigned long gpa,
			      unsigned long page_size)
{
	unsigned long rb,rs,prs,r;
	unsigned long ap;
	unsigned long ric = RIC_FLUSH_TLB;

	ap = mmu_get_ap(radix_get_mmu_psize(page_size));
	rb = gpa & ~(PPC_BITMASK(52, 63));
	rb |= ap << PPC_BITLSHIFT(58);
	rs = lpid & ((1UL << 32) - 1);
	prs = 0; /* process scoped */
	r = 1;   /* raidx format */

	asm volatile("ptesync": : :"memory");
	asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
		     : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
	asm volatile("eieio; tlbsync; ptesync": : :"memory");
}
EXPORT_SYMBOL(radix__flush_tlb_lpid_va);

void radix__flush_tlb_lpid(unsigned long lpid)
{
	unsigned long rb,rs,prs,r;
	unsigned long ric = RIC_FLUSH_ALL;

	rb = 0x2 << PPC_BITLSHIFT(53); /* IS = 2 */
	rs = lpid & ((1UL << 32) - 1);
	prs = 0; /* partition scoped */
	r = 1;   /* raidx format */

	asm volatile("ptesync": : :"memory");
	asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
		     : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
	asm volatile("eieio; tlbsync; ptesync": : :"memory");
}
EXPORT_SYMBOL(radix__flush_tlb_lpid);

void radix__flush_pmd_tlb_range(struct vm_area_struct *vma,
				unsigned long start, unsigned long end)
{
	radix__flush_tlb_range_psize(vma->vm_mm, start, end, MMU_PAGE_2M);
}
EXPORT_SYMBOL(radix__flush_pmd_tlb_range);

void radix__flush_tlb_all(void)
{
	unsigned long rb,prs,r,rs;
	unsigned long ric = RIC_FLUSH_ALL;

	rb = 0x3 << PPC_BITLSHIFT(53); /* IS = 3 */
	prs = 0; /* partition scoped */
	r = 1;   /* raidx format */
	rs = 1 & ((1UL << 32) - 1); /* any LPID value to flush guest mappings */

	asm volatile("ptesync": : :"memory");
	/*
	 * now flush guest entries by passing PRS = 1 and LPID != 0
	 */
	asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
		     : : "r"(rb), "i"(r), "i"(1), "i"(ric), "r"(rs) : "memory");
	/*
	 * now flush host entires by passing PRS = 0 and LPID == 0
	 */
	asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
		     : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(0) : "memory");
	asm volatile("eieio; tlbsync; ptesync": : :"memory");
}

void radix__flush_tlb_pte_p9_dd1(unsigned long old_pte, struct mm_struct *mm,
				 unsigned long address)
{
	/*
	 * We track page size in pte only for DD1, So we can
	 * call this only on DD1.
	 */
	if (!cpu_has_feature(CPU_FTR_POWER9_DD1)) {
		VM_WARN_ON(1);
		return;
	}

	if (old_pte & _PAGE_LARGE)
		radix__flush_tlb_page_psize(mm, address, MMU_PAGE_2M);
	else
		radix__flush_tlb_page_psize(mm, address, mmu_virtual_psize);
}
Commit	Line	Data
1a472c9d AK	1	/*
	2	* TLB flush routines for radix kernels.
	3	*
	4	* Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation.
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version
	9	* 2 of the License, or (at your option) any later version.
	10	*/
	11
	12	#include <linux/mm.h>
	13	#include <linux/hugetlb.h>
	14	#include <linux/memblock.h>
8cd6d3c2	15	#include <asm/ppc-opcode.h>
1a472c9d AK	16
	17	#include <asm/tlb.h>
	18	#include <asm/tlbflush.h>
	19
	20	static DEFINE_RAW_SPINLOCK(native_tlbie_lock);
	21
36194812 AK	22	#define RIC_FLUSH_TLB 0
	23	#define RIC_FLUSH_PWC 1
	24	#define RIC_FLUSH_ALL 2
	25
	26	static inline void __tlbiel_pid(unsigned long pid, int set,
	27	unsigned long ric)
1a472c9d	28	{
36194812	29	unsigned long rb,rs,prs,r;
1a472c9d AK	30
	31	rb = PPC_BIT(53); /* IS = 1 */
	32	rb \|= set << PPC_BITLSHIFT(51);
	33	rs = ((unsigned long)pid) << PPC_BITLSHIFT(31);
	34	prs = 1; /* process scoped */
	35	r = 1; /* raidx format */
1a472c9d AK	36
1a472c9d AK	37	asm volatile("ptesync": : :"memory");
8cd6d3c2	38	asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
1a472c9d AK	39	: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
	40	asm volatile("ptesync": : :"memory");
	41	}
	42
	43	/*
	44	* We use 128 set in radix mode and 256 set in hpt mode.
	45	*/
36194812	46	static inline void _tlbiel_pid(unsigned long pid, unsigned long ric)
1a472c9d AK	47	{
	48	int set;
	49
	50	for (set = 0; set < POWER9_TLB_SETS_RADIX ; set++) {
36194812	51	__tlbiel_pid(pid, set, ric);
1a472c9d	52	}
90c1e3c2	53	asm volatile(PPC_INVALIDATE_ERAT "; isync" : : :"memory");
1a472c9d AK	54	}
1a472c9d AK	55
36194812	56	static inline void _tlbie_pid(unsigned long pid, unsigned long ric)
1a472c9d	57	{
36194812	58	unsigned long rb,rs,prs,r;
1a472c9d AK	59
	60	rb = PPC_BIT(53); /* IS = 1 */
	61	rs = pid << PPC_BITLSHIFT(31);
	62	prs = 1; /* process scoped */
	63	r = 1; /* raidx format */
1a472c9d AK	64
1a472c9d AK	65	asm volatile("ptesync": : :"memory");
8cd6d3c2	66	asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
1a472c9d AK	67	: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
	68	asm volatile("eieio; tlbsync; ptesync": : :"memory");
	69	}
	70
	71	static inline void _tlbiel_va(unsigned long va, unsigned long pid,
36194812	72	unsigned long ap, unsigned long ric)
1a472c9d	73	{
36194812	74	unsigned long rb,rs,prs,r;
1a472c9d AK	75
	76	rb = va & ~(PPC_BITMASK(52, 63));
	77	rb \|= ap << PPC_BITLSHIFT(58);
	78	rs = pid << PPC_BITLSHIFT(31);
	79	prs = 1; /* process scoped */
	80	r = 1; /* raidx format */
1a472c9d AK	81
1a472c9d AK	82	asm volatile("ptesync": : :"memory");
8cd6d3c2	83	asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
1a472c9d AK	84	: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
	85	asm volatile("ptesync": : :"memory");
	86	}
	87
	88	static inline void _tlbie_va(unsigned long va, unsigned long pid,
36194812	89	unsigned long ap, unsigned long ric)
1a472c9d	90	{
36194812	91	unsigned long rb,rs,prs,r;
1a472c9d AK	92
	93	rb = va & ~(PPC_BITMASK(52, 63));
	94	rb \|= ap << PPC_BITLSHIFT(58);
	95	rs = pid << PPC_BITLSHIFT(31);
	96	prs = 1; /* process scoped */
	97	r = 1; /* raidx format */
1a472c9d AK	98
1a472c9d AK	99	asm volatile("ptesync": : :"memory");
8cd6d3c2	100	asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
1a472c9d AK	101	: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
	102	asm volatile("eieio; tlbsync; ptesync": : :"memory");
	103	}
	104
	105	/*
	106	* Base TLB flushing operations:
	107	*
	108	* - flush_tlb_mm(mm) flushes the specified mm context TLB's
	109	* - flush_tlb_page(vma, vmaddr) flushes one page
	110	* - flush_tlb_range(vma, start, end) flushes a range of pages
	111	* - flush_tlb_kernel_range(start, end) flushes kernel pages
	112	*
	113	* - local_* variants of page and mm only apply to the current
	114	* processor
	115	*/
	116	void radix__local_flush_tlb_mm(struct mm_struct *mm)
	117	{
9690c157	118	unsigned long pid;
1a472c9d AK	119
	120	preempt_disable();
	121	pid = mm->context.id;
	122	if (pid != MMU_NO_CONTEXT)
36194812	123	_tlbiel_pid(pid, RIC_FLUSH_ALL);
1a472c9d AK	124	preempt_enable();
	125	}
	126	EXPORT_SYMBOL(radix__local_flush_tlb_mm);
	127
a145abf1 AK	128	void radix__local_flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr)
	129	{
	130	unsigned long pid;
	131	struct mm_struct *mm = tlb->mm;
	132
	133	preempt_disable();
	134
	135	pid = mm->context.id;
	136	if (pid != MMU_NO_CONTEXT)
	137	_tlbiel_pid(pid, RIC_FLUSH_PWC);
	138
	139	preempt_enable();
	140	}
	141	EXPORT_SYMBOL(radix__local_flush_tlb_pwc);
	142
f22dfc91	143	void radix__local_flush_tlb_page_psize(struct mm_struct *mm, unsigned long vmaddr,
fbfa26d8	144	int psize)
1a472c9d	145	{
9690c157	146	unsigned long pid;
fbfa26d8	147	unsigned long ap = mmu_get_ap(psize);
1a472c9d AK	148
	149	preempt_disable();
	150	pid = mm ? mm->context.id : 0;
	151	if (pid != MMU_NO_CONTEXT)
36194812	152	_tlbiel_va(vmaddr, pid, ap, RIC_FLUSH_TLB);
1a472c9d AK	153	preempt_enable();
	154	}
	155
	156	void radix__local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
	157	{
48483760 AK	158	#ifdef CONFIG_HUGETLB_PAGE
	159	/* need the return fix for nohash.c */
	160	if (vma && is_vm_hugetlb_page(vma))
	161	return __local_flush_hugetlb_page(vma, vmaddr);
	162	#endif
f22dfc91	163	radix__local_flush_tlb_page_psize(vma ? vma->vm_mm : NULL, vmaddr,
fbfa26d8	164	mmu_virtual_psize);
1a472c9d AK	165	}
	166	EXPORT_SYMBOL(radix__local_flush_tlb_page);
	167
	168	#ifdef CONFIG_SMP
1a472c9d AK	169	void radix__flush_tlb_mm(struct mm_struct *mm)
1a472c9d AK	170	{
9690c157	171	unsigned long pid;
1a472c9d AK	172
	173	preempt_disable();
	174	pid = mm->context.id;
	175	if (unlikely(pid == MMU_NO_CONTEXT))
	176	goto no_context;
	177
bd77c449	178	if (!mm_is_thread_local(mm)) {
1a472c9d AK	179	int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
	180
	181	if (lock_tlbie)
	182	raw_spin_lock(&native_tlbie_lock);
36194812	183	_tlbie_pid(pid, RIC_FLUSH_ALL);
1a472c9d AK	184	if (lock_tlbie)
	185	raw_spin_unlock(&native_tlbie_lock);
	186	} else
36194812	187	_tlbiel_pid(pid, RIC_FLUSH_ALL);
1a472c9d AK	188	no_context:
	189	preempt_enable();
	190	}
	191	EXPORT_SYMBOL(radix__flush_tlb_mm);
	192
a145abf1 AK	193	void radix__flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr)
	194	{
	195	unsigned long pid;
	196	struct mm_struct *mm = tlb->mm;
	197
	198	preempt_disable();
	199
	200	pid = mm->context.id;
	201	if (unlikely(pid == MMU_NO_CONTEXT))
	202	goto no_context;
	203
bd77c449	204	if (!mm_is_thread_local(mm)) {
a145abf1 AK	205	int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
	206
	207	if (lock_tlbie)
	208	raw_spin_lock(&native_tlbie_lock);
	209	_tlbie_pid(pid, RIC_FLUSH_PWC);
	210	if (lock_tlbie)
	211	raw_spin_unlock(&native_tlbie_lock);
	212	} else
	213	_tlbiel_pid(pid, RIC_FLUSH_PWC);
	214	no_context:
	215	preempt_enable();
	216	}
	217	EXPORT_SYMBOL(radix__flush_tlb_pwc);
	218
f22dfc91	219	void radix__flush_tlb_page_psize(struct mm_struct *mm, unsigned long vmaddr,
fbfa26d8	220	int psize)
1a472c9d	221	{
9690c157	222	unsigned long pid;
fbfa26d8	223	unsigned long ap = mmu_get_ap(psize);
1a472c9d AK	224
	225	preempt_disable();
	226	pid = mm ? mm->context.id : 0;
	227	if (unlikely(pid == MMU_NO_CONTEXT))
	228	goto bail;
bd77c449	229	if (!mm_is_thread_local(mm)) {
1a472c9d AK	230	int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
	231
	232	if (lock_tlbie)
	233	raw_spin_lock(&native_tlbie_lock);
36194812	234	_tlbie_va(vmaddr, pid, ap, RIC_FLUSH_TLB);
1a472c9d AK	235	if (lock_tlbie)
	236	raw_spin_unlock(&native_tlbie_lock);
	237	} else
36194812	238	_tlbiel_va(vmaddr, pid, ap, RIC_FLUSH_TLB);
1a472c9d AK	239	bail:
	240	preempt_enable();
	241	}
	242
	243	void radix__flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
	244	{
48483760 AK	245	#ifdef CONFIG_HUGETLB_PAGE
	246	if (vma && is_vm_hugetlb_page(vma))
	247	return flush_hugetlb_page(vma, vmaddr);
	248	#endif
f22dfc91	249	radix__flush_tlb_page_psize(vma ? vma->vm_mm : NULL, vmaddr,
fbfa26d8	250	mmu_virtual_psize);
1a472c9d AK	251	}
	252	EXPORT_SYMBOL(radix__flush_tlb_page);
	253
	254	#endif /* CONFIG_SMP */
	255
	256	void radix__flush_tlb_kernel_range(unsigned long start, unsigned long end)
	257	{
	258	int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
	259
	260	if (lock_tlbie)
	261	raw_spin_lock(&native_tlbie_lock);
36194812	262	_tlbie_pid(0, RIC_FLUSH_ALL);
1a472c9d AK	263	if (lock_tlbie)
	264	raw_spin_unlock(&native_tlbie_lock);
	265	}
	266	EXPORT_SYMBOL(radix__flush_tlb_kernel_range);
	267
	268	/*
	269	* Currently, for range flushing, we just do a full mm flush. Because
	270	* we use this in code path where we don' track the page size.
	271	*/
	272	void radix__flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
	273	unsigned long end)
	274
	275	{
	276	struct mm_struct *mm = vma->vm_mm;
	277	radix__flush_tlb_mm(mm);
	278	}
	279	EXPORT_SYMBOL(radix__flush_tlb_range);
	280
912cc87a AK	281	static int radix_get_mmu_psize(int page_size)
	282	{
	283	int psize;
	284
	285	if (page_size == (1UL << mmu_psize_defs[mmu_virtual_psize].shift))
	286	psize = mmu_virtual_psize;
	287	else if (page_size == (1UL << mmu_psize_defs[MMU_PAGE_2M].shift))
	288	psize = MMU_PAGE_2M;
	289	else if (page_size == (1UL << mmu_psize_defs[MMU_PAGE_1G].shift))
	290	psize = MMU_PAGE_1G;
	291	else
	292	return -1;
	293	return psize;
	294	}
1a472c9d AK	295
	296	void radix__tlb_flush(struct mmu_gather *tlb)
	297	{
8cb8140c	298	int psize = 0;
1a472c9d	299	struct mm_struct *mm = tlb->mm;
8cb8140c AK	300	int page_size = tlb->page_size;
	301
	302	psize = radix_get_mmu_psize(page_size);
	303	/*
	304	* if page size is not something we understand, do a full mm flush
	305	*/
	306	if (psize != -1 && !tlb->fullmm && !tlb->need_flush_all)
	307	radix__flush_tlb_range_psize(mm, tlb->start, tlb->end, psize);
	308	else
	309	radix__flush_tlb_mm(mm);
	310	}
	311
	312	#define TLB_FLUSH_ALL -1UL
	313	/*
	314	* Number of pages above which we will do a bcast tlbie. Just a
	315	* number at this point copied from x86
	316	*/
	317	static unsigned long tlb_single_page_flush_ceiling __read_mostly = 33;
	318
	319	void radix__flush_tlb_range_psize(struct mm_struct *mm, unsigned long start,
	320	unsigned long end, int psize)
	321	{
	322	unsigned long pid;
	323	unsigned long addr;
bd77c449	324	int local = mm_is_thread_local(mm);
8cb8140c AK	325	unsigned long ap = mmu_get_ap(psize);
	326	int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
	327	unsigned long page_size = 1UL << mmu_psize_defs[psize].shift;
	328
	329
	330	preempt_disable();
	331	pid = mm ? mm->context.id : 0;
	332	if (unlikely(pid == MMU_NO_CONTEXT))
	333	goto err_out;
	334
	335	if (end == TLB_FLUSH_ALL \|\|
	336	(end - start) > tlb_single_page_flush_ceiling * page_size) {
	337	if (local)
	338	_tlbiel_pid(pid, RIC_FLUSH_TLB);
	339	else
	340	_tlbie_pid(pid, RIC_FLUSH_TLB);
	341	goto err_out;
	342	}
	343	for (addr = start; addr < end; addr += page_size) {
	344
	345	if (local)
	346	_tlbiel_va(addr, pid, ap, RIC_FLUSH_TLB);
	347	else {
	348	if (lock_tlbie)
	349	raw_spin_lock(&native_tlbie_lock);
	350	_tlbie_va(addr, pid, ap, RIC_FLUSH_TLB);
	351	if (lock_tlbie)
	352	raw_spin_unlock(&native_tlbie_lock);
	353	}
	354	}
	355	err_out:
	356	preempt_enable();
1a472c9d	357	}
912cc87a AK	358
	359	void radix__flush_tlb_lpid_va(unsigned long lpid, unsigned long gpa,
	360	unsigned long page_size)
	361	{
	362	unsigned long rb,rs,prs,r;
	363	unsigned long ap;
	364	unsigned long ric = RIC_FLUSH_TLB;
	365
	366	ap = mmu_get_ap(radix_get_mmu_psize(page_size));
	367	rb = gpa & ~(PPC_BITMASK(52, 63));
	368	rb \|= ap << PPC_BITLSHIFT(58);
	369	rs = lpid & ((1UL << 32) - 1);
	370	prs = 0; /* process scoped */
	371	r = 1; /* raidx format */
	372
	373	asm volatile("ptesync": : :"memory");
	374	asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
	375	: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
	376	asm volatile("eieio; tlbsync; ptesync": : :"memory");
	377	}
	378	EXPORT_SYMBOL(radix__flush_tlb_lpid_va);
	379
	380	void radix__flush_tlb_lpid(unsigned long lpid)
	381	{
	382	unsigned long rb,rs,prs,r;
	383	unsigned long ric = RIC_FLUSH_ALL;
	384
	385	rb = 0x2 << PPC_BITLSHIFT(53); /* IS = 2 */
	386	rs = lpid & ((1UL << 32) - 1);
	387	prs = 0; /* partition scoped */
	388	r = 1; /* raidx format */
	389
	390	asm volatile("ptesync": : :"memory");
	391	asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
	392	: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
	393	asm volatile("eieio; tlbsync; ptesync": : :"memory");
	394	}
	395	EXPORT_SYMBOL(radix__flush_tlb_lpid);
d8e91e93 AK	396
	397	void radix__flush_pmd_tlb_range(struct vm_area_struct *vma,
	398	unsigned long start, unsigned long end)
	399	{
	400	radix__flush_tlb_range_psize(vma->vm_mm, start, end, MMU_PAGE_2M);
	401	}
	402	EXPORT_SYMBOL(radix__flush_pmd_tlb_range);
be34d300 AK	403
	404	void radix__flush_tlb_all(void)
	405	{
	406	unsigned long rb,prs,r,rs;
	407	unsigned long ric = RIC_FLUSH_ALL;
	408
	409	rb = 0x3 << PPC_BITLSHIFT(53); /* IS = 3 */
	410	prs = 0; /* partition scoped */
	411	r = 1; /* raidx format */
	412	rs = 1 & ((1UL << 32) - 1); /* any LPID value to flush guest mappings */
	413
	414	asm volatile("ptesync": : :"memory");
	415	/*
	416	* now flush guest entries by passing PRS = 1 and LPID != 0
	417	*/
	418	asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
	419	: : "r"(rb), "i"(r), "i"(1), "i"(ric), "r"(rs) : "memory");
	420	/*
	421	* now flush host entires by passing PRS = 0 and LPID == 0
	422	*/
	423	asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
	424	: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(0) : "memory");
	425	asm volatile("eieio; tlbsync; ptesync": : :"memory");
	426	}
6d3a0379 AK	427
	428	void radix__flush_tlb_pte_p9_dd1(unsigned long old_pte, struct mm_struct *mm,
	429	unsigned long address)
	430	{
	431	/*
	432	* We track page size in pte only for DD1, So we can
	433	* call this only on DD1.
	434	*/
	435	if (!cpu_has_feature(CPU_FTR_POWER9_DD1)) {
	436	VM_WARN_ON(1);
	437	return;
	438	}
	439
	440	if (old_pte & _PAGE_LARGE)
	441	radix__flush_tlb_page_psize(mm, address, MMU_PAGE_2M);
	442	else
	443	radix__flush_tlb_page_psize(mm, address, mmu_virtual_psize);
	444	}