[mirror_ubuntu-zesty-kernel.git] / arch / powerpc / mm / tlb-radix.c

/*
 * TLB flush routines for radix kernels.
 *
 * Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#include <linux/mm.h>
#include <linux/hugetlb.h>
#include <linux/memblock.h>
#include <asm/ppc-opcode.h>

#include <asm/tlb.h>
#include <asm/tlbflush.h>

static DEFINE_RAW_SPINLOCK(native_tlbie_lock);

#define RIC_FLUSH_TLB 0
#define RIC_FLUSH_PWC 1
#define RIC_FLUSH_ALL 2

static inline void __tlbiel_pid(unsigned long pid, int set,
				unsigned long ric)
{
	unsigned long rb,rs,prs,r;

	rb = PPC_BIT(53); /* IS = 1 */
	rb |= set << PPC_BITLSHIFT(51);
	rs = ((unsigned long)pid) << PPC_BITLSHIFT(31);
	prs = 1; /* process scoped */
	r = 1;   /* raidx format */

	asm volatile("ptesync": : :"memory");
	asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
		     : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
	asm volatile("ptesync": : :"memory");
}

/*
 * We use 128 set in radix mode and 256 set in hpt mode.
 */
static inline void _tlbiel_pid(unsigned long pid, unsigned long ric)
{
	int set;

	for (set = 0; set < POWER9_TLB_SETS_RADIX ; set++) {
		__tlbiel_pid(pid, set, ric);
	}
	return;
}

static inline void _tlbie_pid(unsigned long pid, unsigned long ric)
{
	unsigned long rb,rs,prs,r;

	rb = PPC_BIT(53); /* IS = 1 */
	rs = pid << PPC_BITLSHIFT(31);
	prs = 1; /* process scoped */
	r = 1;   /* raidx format */

	asm volatile("ptesync": : :"memory");
	asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
		     : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
	asm volatile("eieio; tlbsync; ptesync": : :"memory");
}

static inline void _tlbiel_va(unsigned long va, unsigned long pid,
			      unsigned long ap, unsigned long ric)
{
	unsigned long rb,rs,prs,r;

	rb = va & ~(PPC_BITMASK(52, 63));
	rb |= ap << PPC_BITLSHIFT(58);
	rs = pid << PPC_BITLSHIFT(31);
	prs = 1; /* process scoped */
	r = 1;   /* raidx format */

	asm volatile("ptesync": : :"memory");
	asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
		     : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
	asm volatile("ptesync": : :"memory");
}

static inline void _tlbie_va(unsigned long va, unsigned long pid,
			     unsigned long ap, unsigned long ric)
{
	unsigned long rb,rs,prs,r;

	rb = va & ~(PPC_BITMASK(52, 63));
	rb |= ap << PPC_BITLSHIFT(58);
	rs = pid << PPC_BITLSHIFT(31);
	prs = 1; /* process scoped */
	r = 1;   /* raidx format */

	asm volatile("ptesync": : :"memory");
	asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
		     : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
	asm volatile("eieio; tlbsync; ptesync": : :"memory");
}

/*
 * Base TLB flushing operations:
 *
 *  - flush_tlb_mm(mm) flushes the specified mm context TLB's
 *  - flush_tlb_page(vma, vmaddr) flushes one page
 *  - flush_tlb_range(vma, start, end) flushes a range of pages
 *  - flush_tlb_kernel_range(start, end) flushes kernel pages
 *
 *  - local_* variants of page and mm only apply to the current
 *    processor
 */
void radix__local_flush_tlb_mm(struct mm_struct *mm)
{
	unsigned long pid;

	preempt_disable();
	pid = mm->context.id;
	if (pid != MMU_NO_CONTEXT)
		_tlbiel_pid(pid, RIC_FLUSH_ALL);
	preempt_enable();
}
EXPORT_SYMBOL(radix__local_flush_tlb_mm);

void radix__local_flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr)
{
	unsigned long pid;
	struct mm_struct *mm = tlb->mm;

	preempt_disable();

	pid = mm->context.id;
	if (pid != MMU_NO_CONTEXT)
		_tlbiel_pid(pid, RIC_FLUSH_PWC);

	preempt_enable();
}
EXPORT_SYMBOL(radix__local_flush_tlb_pwc);

void radix___local_flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr,
			    unsigned long ap, int nid)
{
	unsigned long pid;

	preempt_disable();
	pid = mm ? mm->context.id : 0;
	if (pid != MMU_NO_CONTEXT)
		_tlbiel_va(vmaddr, pid, ap, RIC_FLUSH_TLB);
	preempt_enable();
}

void radix__local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
{
#ifdef CONFIG_HUGETLB_PAGE
	/* need the return fix for nohash.c */
	if (vma && is_vm_hugetlb_page(vma))
		return __local_flush_hugetlb_page(vma, vmaddr);
#endif
	radix___local_flush_tlb_page(vma ? vma->vm_mm : NULL, vmaddr,
			       mmu_get_ap(mmu_virtual_psize), 0);
}
EXPORT_SYMBOL(radix__local_flush_tlb_page);

#ifdef CONFIG_SMP
static int mm_is_core_local(struct mm_struct *mm)
{
	return cpumask_subset(mm_cpumask(mm),
			      topology_sibling_cpumask(smp_processor_id()));
}

void radix__flush_tlb_mm(struct mm_struct *mm)
{
	unsigned long pid;

	preempt_disable();
	pid = mm->context.id;
	if (unlikely(pid == MMU_NO_CONTEXT))
		goto no_context;

	if (!mm_is_core_local(mm)) {
		int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);

		if (lock_tlbie)
			raw_spin_lock(&native_tlbie_lock);
		_tlbie_pid(pid, RIC_FLUSH_ALL);
		if (lock_tlbie)
			raw_spin_unlock(&native_tlbie_lock);
	} else
		_tlbiel_pid(pid, RIC_FLUSH_ALL);
no_context:
	preempt_enable();
}
EXPORT_SYMBOL(radix__flush_tlb_mm);

void radix__flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr)
{
	unsigned long pid;
	struct mm_struct *mm = tlb->mm;

	preempt_disable();

	pid = mm->context.id;
	if (unlikely(pid == MMU_NO_CONTEXT))
		goto no_context;

	if (!mm_is_core_local(mm)) {
		int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);

		if (lock_tlbie)
			raw_spin_lock(&native_tlbie_lock);
		_tlbie_pid(pid, RIC_FLUSH_PWC);
		if (lock_tlbie)
			raw_spin_unlock(&native_tlbie_lock);
	} else
		_tlbiel_pid(pid, RIC_FLUSH_PWC);
no_context:
	preempt_enable();
}
EXPORT_SYMBOL(radix__flush_tlb_pwc);

void radix___flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr,
		       unsigned long ap, int nid)
{
	unsigned long pid;

	preempt_disable();
	pid = mm ? mm->context.id : 0;
	if (unlikely(pid == MMU_NO_CONTEXT))
		goto bail;
	if (!mm_is_core_local(mm)) {
		int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);

		if (lock_tlbie)
			raw_spin_lock(&native_tlbie_lock);
		_tlbie_va(vmaddr, pid, ap, RIC_FLUSH_TLB);
		if (lock_tlbie)
			raw_spin_unlock(&native_tlbie_lock);
	} else
		_tlbiel_va(vmaddr, pid, ap, RIC_FLUSH_TLB);
bail:
	preempt_enable();
}

void radix__flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
{
#ifdef CONFIG_HUGETLB_PAGE
	if (vma && is_vm_hugetlb_page(vma))
		return flush_hugetlb_page(vma, vmaddr);
#endif
	radix___flush_tlb_page(vma ? vma->vm_mm : NULL, vmaddr,
			 mmu_get_ap(mmu_virtual_psize), 0);
}
EXPORT_SYMBOL(radix__flush_tlb_page);

#endif /* CONFIG_SMP */

void radix__flush_tlb_kernel_range(unsigned long start, unsigned long end)
{
	int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);

	if (lock_tlbie)
		raw_spin_lock(&native_tlbie_lock);
	_tlbie_pid(0, RIC_FLUSH_ALL);
	if (lock_tlbie)
		raw_spin_unlock(&native_tlbie_lock);
}
EXPORT_SYMBOL(radix__flush_tlb_kernel_range);

/*
 * Currently, for range flushing, we just do a full mm flush. Because
 * we use this in code path where we don' track the page size.
 */
void radix__flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
		     unsigned long end)

{
	struct mm_struct *mm = vma->vm_mm;
	radix__flush_tlb_mm(mm);
}
EXPORT_SYMBOL(radix__flush_tlb_range);

static int radix_get_mmu_psize(int page_size)
{
	int psize;

	if (page_size == (1UL << mmu_psize_defs[mmu_virtual_psize].shift))
		psize = mmu_virtual_psize;
	else if (page_size == (1UL << mmu_psize_defs[MMU_PAGE_2M].shift))
		psize = MMU_PAGE_2M;
	else if (page_size == (1UL << mmu_psize_defs[MMU_PAGE_1G].shift))
		psize = MMU_PAGE_1G;
	else
		return -1;
	return psize;
}

void radix__tlb_flush(struct mmu_gather *tlb)
{
	struct mm_struct *mm = tlb->mm;
	radix__flush_tlb_mm(mm);
}

void radix__flush_tlb_lpid_va(unsigned long lpid, unsigned long gpa,
			      unsigned long page_size)
{
	unsigned long rb,rs,prs,r;
	unsigned long ap;
	unsigned long ric = RIC_FLUSH_TLB;

	ap = mmu_get_ap(radix_get_mmu_psize(page_size));
	rb = gpa & ~(PPC_BITMASK(52, 63));
	rb |= ap << PPC_BITLSHIFT(58);
	rs = lpid & ((1UL << 32) - 1);
	prs = 0; /* process scoped */
	r = 1;   /* raidx format */

	asm volatile("ptesync": : :"memory");
	asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
		     : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
	asm volatile("eieio; tlbsync; ptesync": : :"memory");
}
EXPORT_SYMBOL(radix__flush_tlb_lpid_va);

void radix__flush_tlb_lpid(unsigned long lpid)
{
	unsigned long rb,rs,prs,r;
	unsigned long ric = RIC_FLUSH_ALL;

	rb = 0x2 << PPC_BITLSHIFT(53); /* IS = 2 */
	rs = lpid & ((1UL << 32) - 1);
	prs = 0; /* partition scoped */
	r = 1;   /* raidx format */

	asm volatile("ptesync": : :"memory");
	asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
		     : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
	asm volatile("eieio; tlbsync; ptesync": : :"memory");
}
EXPORT_SYMBOL(radix__flush_tlb_lpid);
Commit	Line	Data
1a472c9d AK	1	/*
	2	* TLB flush routines for radix kernels.
	3	*
	4	* Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation.
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version
	9	* 2 of the License, or (at your option) any later version.
	10	*/
	11
	12	#include <linux/mm.h>
	13	#include <linux/hugetlb.h>
	14	#include <linux/memblock.h>
8cd6d3c2	15	#include <asm/ppc-opcode.h>
1a472c9d AK	16
	17	#include <asm/tlb.h>
	18	#include <asm/tlbflush.h>
	19
	20	static DEFINE_RAW_SPINLOCK(native_tlbie_lock);
	21
36194812 AK	22	#define RIC_FLUSH_TLB 0
	23	#define RIC_FLUSH_PWC 1
	24	#define RIC_FLUSH_ALL 2
	25
	26	static inline void __tlbiel_pid(unsigned long pid, int set,
	27	unsigned long ric)
1a472c9d	28	{
36194812	29	unsigned long rb,rs,prs,r;
1a472c9d AK	30
	31	rb = PPC_BIT(53); /* IS = 1 */
	32	rb \|= set << PPC_BITLSHIFT(51);
	33	rs = ((unsigned long)pid) << PPC_BITLSHIFT(31);
	34	prs = 1; /* process scoped */
	35	r = 1; /* raidx format */
1a472c9d AK	36
1a472c9d AK	37	asm volatile("ptesync": : :"memory");
8cd6d3c2	38	asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
1a472c9d AK	39	: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
	40	asm volatile("ptesync": : :"memory");
	41	}
	42
	43	/*
	44	* We use 128 set in radix mode and 256 set in hpt mode.
	45	*/
36194812	46	static inline void _tlbiel_pid(unsigned long pid, unsigned long ric)
1a472c9d AK	47	{
	48	int set;
	49
	50	for (set = 0; set < POWER9_TLB_SETS_RADIX ; set++) {
36194812	51	__tlbiel_pid(pid, set, ric);
1a472c9d AK	52	}
	53	return;
	54	}
	55
36194812	56	static inline void _tlbie_pid(unsigned long pid, unsigned long ric)
1a472c9d	57	{
36194812	58	unsigned long rb,rs,prs,r;
1a472c9d AK	59
	60	rb = PPC_BIT(53); /* IS = 1 */
	61	rs = pid << PPC_BITLSHIFT(31);
	62	prs = 1; /* process scoped */
	63	r = 1; /* raidx format */
1a472c9d AK	64
1a472c9d AK	65	asm volatile("ptesync": : :"memory");
8cd6d3c2	66	asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
1a472c9d AK	67	: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
	68	asm volatile("eieio; tlbsync; ptesync": : :"memory");
	69	}
	70
	71	static inline void _tlbiel_va(unsigned long va, unsigned long pid,
36194812	72	unsigned long ap, unsigned long ric)
1a472c9d	73	{
36194812	74	unsigned long rb,rs,prs,r;
1a472c9d AK	75
	76	rb = va & ~(PPC_BITMASK(52, 63));
	77	rb \|= ap << PPC_BITLSHIFT(58);
	78	rs = pid << PPC_BITLSHIFT(31);
	79	prs = 1; /* process scoped */
	80	r = 1; /* raidx format */
1a472c9d AK	81
1a472c9d AK	82	asm volatile("ptesync": : :"memory");
8cd6d3c2	83	asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
1a472c9d AK	84	: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
	85	asm volatile("ptesync": : :"memory");
	86	}
	87
	88	static inline void _tlbie_va(unsigned long va, unsigned long pid,
36194812	89	unsigned long ap, unsigned long ric)
1a472c9d	90	{
36194812	91	unsigned long rb,rs,prs,r;
1a472c9d AK	92
	93	rb = va & ~(PPC_BITMASK(52, 63));
	94	rb \|= ap << PPC_BITLSHIFT(58);
	95	rs = pid << PPC_BITLSHIFT(31);
	96	prs = 1; /* process scoped */
	97	r = 1; /* raidx format */
1a472c9d AK	98
1a472c9d AK	99	asm volatile("ptesync": : :"memory");
8cd6d3c2	100	asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
1a472c9d AK	101	: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
	102	asm volatile("eieio; tlbsync; ptesync": : :"memory");
	103	}
	104
	105	/*
	106	* Base TLB flushing operations:
	107	*
	108	* - flush_tlb_mm(mm) flushes the specified mm context TLB's
	109	* - flush_tlb_page(vma, vmaddr) flushes one page
	110	* - flush_tlb_range(vma, start, end) flushes a range of pages
	111	* - flush_tlb_kernel_range(start, end) flushes kernel pages
	112	*
	113	* - local_* variants of page and mm only apply to the current
	114	* processor
	115	*/
	116	void radix__local_flush_tlb_mm(struct mm_struct *mm)
	117	{
9690c157	118	unsigned long pid;
1a472c9d AK	119
	120	preempt_disable();
	121	pid = mm->context.id;
	122	if (pid != MMU_NO_CONTEXT)
36194812	123	_tlbiel_pid(pid, RIC_FLUSH_ALL);
1a472c9d AK	124	preempt_enable();
	125	}
	126	EXPORT_SYMBOL(radix__local_flush_tlb_mm);
	127
a145abf1 AK	128	void radix__local_flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr)
	129	{
	130	unsigned long pid;
	131	struct mm_struct *mm = tlb->mm;
	132
	133	preempt_disable();
	134
	135	pid = mm->context.id;
	136	if (pid != MMU_NO_CONTEXT)
	137	_tlbiel_pid(pid, RIC_FLUSH_PWC);
	138
	139	preempt_enable();
	140	}
	141	EXPORT_SYMBOL(radix__local_flush_tlb_pwc);
	142
1a472c9d AK	143	void radix___local_flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr,
	144	unsigned long ap, int nid)
	145	{
9690c157	146	unsigned long pid;
1a472c9d AK	147
	148	preempt_disable();
	149	pid = mm ? mm->context.id : 0;
	150	if (pid != MMU_NO_CONTEXT)
36194812	151	_tlbiel_va(vmaddr, pid, ap, RIC_FLUSH_TLB);
1a472c9d AK	152	preempt_enable();
	153	}
	154
	155	void radix__local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
	156	{
48483760 AK	157	#ifdef CONFIG_HUGETLB_PAGE
	158	/* need the return fix for nohash.c */
	159	if (vma && is_vm_hugetlb_page(vma))
	160	return __local_flush_hugetlb_page(vma, vmaddr);
	161	#endif
1a472c9d AK	162	radix___local_flush_tlb_page(vma ? vma->vm_mm : NULL, vmaddr,
	163	mmu_get_ap(mmu_virtual_psize), 0);
	164	}
	165	EXPORT_SYMBOL(radix__local_flush_tlb_page);
	166
	167	#ifdef CONFIG_SMP
	168	static int mm_is_core_local(struct mm_struct *mm)
	169	{
	170	return cpumask_subset(mm_cpumask(mm),
	171	topology_sibling_cpumask(smp_processor_id()));
	172	}
	173
	174	void radix__flush_tlb_mm(struct mm_struct *mm)
	175	{
9690c157	176	unsigned long pid;
1a472c9d AK	177
	178	preempt_disable();
	179	pid = mm->context.id;
	180	if (unlikely(pid == MMU_NO_CONTEXT))
	181	goto no_context;
	182
	183	if (!mm_is_core_local(mm)) {
	184	int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
	185
	186	if (lock_tlbie)
	187	raw_spin_lock(&native_tlbie_lock);
36194812	188	_tlbie_pid(pid, RIC_FLUSH_ALL);
1a472c9d AK	189	if (lock_tlbie)
	190	raw_spin_unlock(&native_tlbie_lock);
	191	} else
36194812	192	_tlbiel_pid(pid, RIC_FLUSH_ALL);
1a472c9d AK	193	no_context:
	194	preempt_enable();
	195	}
	196	EXPORT_SYMBOL(radix__flush_tlb_mm);
	197
a145abf1 AK	198	void radix__flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr)
	199	{
	200	unsigned long pid;
	201	struct mm_struct *mm = tlb->mm;
	202
	203	preempt_disable();
	204
	205	pid = mm->context.id;
	206	if (unlikely(pid == MMU_NO_CONTEXT))
	207	goto no_context;
	208
	209	if (!mm_is_core_local(mm)) {
	210	int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
	211
	212	if (lock_tlbie)
	213	raw_spin_lock(&native_tlbie_lock);
	214	_tlbie_pid(pid, RIC_FLUSH_PWC);
	215	if (lock_tlbie)
	216	raw_spin_unlock(&native_tlbie_lock);
	217	} else
	218	_tlbiel_pid(pid, RIC_FLUSH_PWC);
	219	no_context:
	220	preempt_enable();
	221	}
	222	EXPORT_SYMBOL(radix__flush_tlb_pwc);
	223
1a472c9d AK	224	void radix___flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr,
	225	unsigned long ap, int nid)
	226	{
9690c157	227	unsigned long pid;
1a472c9d AK	228
	229	preempt_disable();
	230	pid = mm ? mm->context.id : 0;
	231	if (unlikely(pid == MMU_NO_CONTEXT))
	232	goto bail;
	233	if (!mm_is_core_local(mm)) {
	234	int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
	235
	236	if (lock_tlbie)
	237	raw_spin_lock(&native_tlbie_lock);
36194812	238	_tlbie_va(vmaddr, pid, ap, RIC_FLUSH_TLB);
1a472c9d AK	239	if (lock_tlbie)
	240	raw_spin_unlock(&native_tlbie_lock);
	241	} else
36194812	242	_tlbiel_va(vmaddr, pid, ap, RIC_FLUSH_TLB);
1a472c9d AK	243	bail:
	244	preempt_enable();
	245	}
	246
	247	void radix__flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
	248	{
48483760 AK	249	#ifdef CONFIG_HUGETLB_PAGE
	250	if (vma && is_vm_hugetlb_page(vma))
	251	return flush_hugetlb_page(vma, vmaddr);
	252	#endif
1a472c9d AK	253	radix___flush_tlb_page(vma ? vma->vm_mm : NULL, vmaddr,
	254	mmu_get_ap(mmu_virtual_psize), 0);
	255	}
	256	EXPORT_SYMBOL(radix__flush_tlb_page);
	257
	258	#endif /* CONFIG_SMP */
	259
	260	void radix__flush_tlb_kernel_range(unsigned long start, unsigned long end)
	261	{
	262	int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
	263
	264	if (lock_tlbie)
	265	raw_spin_lock(&native_tlbie_lock);
36194812	266	_tlbie_pid(0, RIC_FLUSH_ALL);
1a472c9d AK	267	if (lock_tlbie)
	268	raw_spin_unlock(&native_tlbie_lock);
	269	}
	270	EXPORT_SYMBOL(radix__flush_tlb_kernel_range);
	271
	272	/*
	273	* Currently, for range flushing, we just do a full mm flush. Because
	274	* we use this in code path where we don' track the page size.
	275	*/
	276	void radix__flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
	277	unsigned long end)
	278
	279	{
	280	struct mm_struct *mm = vma->vm_mm;
	281	radix__flush_tlb_mm(mm);
	282	}
	283	EXPORT_SYMBOL(radix__flush_tlb_range);
	284
912cc87a AK	285	static int radix_get_mmu_psize(int page_size)
	286	{
	287	int psize;
	288
	289	if (page_size == (1UL << mmu_psize_defs[mmu_virtual_psize].shift))
	290	psize = mmu_virtual_psize;
	291	else if (page_size == (1UL << mmu_psize_defs[MMU_PAGE_2M].shift))
	292	psize = MMU_PAGE_2M;
	293	else if (page_size == (1UL << mmu_psize_defs[MMU_PAGE_1G].shift))
	294	psize = MMU_PAGE_1G;
	295	else
	296	return -1;
	297	return psize;
	298	}
1a472c9d AK	299
	300	void radix__tlb_flush(struct mmu_gather *tlb)
	301	{
	302	struct mm_struct *mm = tlb->mm;
	303	radix__flush_tlb_mm(mm);
	304	}
912cc87a AK	305
	306	void radix__flush_tlb_lpid_va(unsigned long lpid, unsigned long gpa,
	307	unsigned long page_size)
	308	{
	309	unsigned long rb,rs,prs,r;
	310	unsigned long ap;
	311	unsigned long ric = RIC_FLUSH_TLB;
	312
	313	ap = mmu_get_ap(radix_get_mmu_psize(page_size));
	314	rb = gpa & ~(PPC_BITMASK(52, 63));
	315	rb \|= ap << PPC_BITLSHIFT(58);
	316	rs = lpid & ((1UL << 32) - 1);
	317	prs = 0; /* process scoped */
	318	r = 1; /* raidx format */
	319
	320	asm volatile("ptesync": : :"memory");
	321	asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
	322	: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
	323	asm volatile("eieio; tlbsync; ptesync": : :"memory");
	324	}
	325	EXPORT_SYMBOL(radix__flush_tlb_lpid_va);
	326
	327	void radix__flush_tlb_lpid(unsigned long lpid)
	328	{
	329	unsigned long rb,rs,prs,r;
	330	unsigned long ric = RIC_FLUSH_ALL;
	331
	332	rb = 0x2 << PPC_BITLSHIFT(53); /* IS = 2 */
	333	rs = lpid & ((1UL << 32) - 1);
	334	prs = 0; /* partition scoped */
	335	r = 1; /* raidx format */
	336
	337	asm volatile("ptesync": : :"memory");
	338	asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
	339	: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
	340	asm volatile("eieio; tlbsync; ptesync": : :"memory");
	341	}
	342	EXPORT_SYMBOL(radix__flush_tlb_lpid);