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UBUNTU: Ubuntu-4.10.0-37.41
[mirror_ubuntu-zesty-kernel.git] / arch / powerpc / net / bpf_jit.h
CommitLineData
6ac0ba5a
NR		 1/*
2 * bpf_jit.h: BPF JIT compiler for PPC
0ca87f05
ME		 3 *
4 * Copyright 2011 Matt Evans <matt@ozlabs.org>, IBM Corporation
156d0e29 5 * 2016 Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com>
0ca87f05
ME		 6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
10 * of the License.
11 */
12#ifndef _BPF_JIT_H
13#define _BPF_JIT_H
14
0ca87f05
ME		 15#ifndef __ASSEMBLY__
16
156d0e29
NR		 17#include <asm/types.h>
18
19#ifdef PPC64_ELF_ABI_v1
0ca87f05 20#define FUNCTION_DESCR_SIZE 24
09ca5ab2
DK		 21#else
22#define FUNCTION_DESCR_SIZE 0
23#endif
0ca87f05
ME		 24
25/*
26 * 16-bit immediate helper macros: HA() is for use with sign-extending instrs
27 * (e.g. LD, ADDI). If the bottom 16 bits is "-ve", add another bit into the
28 * top half to negate the effect (i.e. 0xffff + 1 = 0x(1)0000).
29 */
30#define IMM_H(i) ((uintptr_t)(i)>>16)
31#define IMM_HA(i) (((uintptr_t)(i)>>16) + \
cef1e8cd 32 (((uintptr_t)(i) & 0x8000) >> 15))
0ca87f05
ME		 33#define IMM_L(i) ((uintptr_t)(i) & 0xffff)
34
35#define PLANT_INSTR(d, idx, instr) \
36 do { if (d) { (d)[idx] = instr; } idx++; } while (0)
37#define EMIT(instr) PLANT_INSTR(image, ctx->idx, instr)
38
39#define PPC_NOP() EMIT(PPC_INST_NOP)
40#define PPC_BLR() EMIT(PPC_INST_BLR)
41#define PPC_BLRL() EMIT(PPC_INST_BLRL)
cdaade71 42#define PPC_MTLR(r) EMIT(PPC_INST_MTLR | ___PPC_RT(r))
ce076141
NR		 43#define PPC_BCTR() EMIT(PPC_INST_BCTR)
44#define PPC_MTCTR(r) EMIT(PPC_INST_MTCTR | ___PPC_RT(r))
cdaade71
MN		 45#define PPC_ADDI(d, a, i) EMIT(PPC_INST_ADDI | ___PPC_RT(d) | \
46 ___PPC_RA(a) | IMM_L(i))
0ca87f05
ME		 47#define PPC_MR(d, a) PPC_OR(d, a, a)
48#define PPC_LI(r, i) PPC_ADDI(r, 0, i)
49#define PPC_ADDIS(d, a, i) EMIT(PPC_INST_ADDIS | \
cef1e8cd 50 ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i))
0ca87f05 51#define PPC_LIS(r, i) PPC_ADDIS(r, 0, i)
cdaade71
MN		 52#define PPC_STD(r, base, i) EMIT(PPC_INST_STD | ___PPC_RS(r) | \
53 ___PPC_RA(base) | ((i) & 0xfffc))
09ca5ab2
DK		 54#define PPC_STDU(r, base, i) EMIT(PPC_INST_STDU | ___PPC_RS(r) | \
55 ___PPC_RA(base) | ((i) & 0xfffc))
56#define PPC_STW(r, base, i) EMIT(PPC_INST_STW | ___PPC_RS(r) | \
cef1e8cd 57 ___PPC_RA(base) | IMM_L(i))
09ca5ab2 58#define PPC_STWU(r, base, i) EMIT(PPC_INST_STWU | ___PPC_RS(r) | \
cef1e8cd 59 ___PPC_RA(base) | IMM_L(i))
156d0e29
NR		 60#define PPC_STH(r, base, i) EMIT(PPC_INST_STH | ___PPC_RS(r) | \
61 ___PPC_RA(base) | IMM_L(i))
62#define PPC_STB(r, base, i) EMIT(PPC_INST_STB | ___PPC_RS(r) | \
63 ___PPC_RA(base) | IMM_L(i))
4e235761
DK		 64
65#define PPC_LBZ(r, base, i) EMIT(PPC_INST_LBZ | ___PPC_RT(r) | \
66 ___PPC_RA(base) | IMM_L(i))
cdaade71
MN		 67#define PPC_LD(r, base, i) EMIT(PPC_INST_LD | ___PPC_RT(r) | \
68 ___PPC_RA(base) | IMM_L(i))
69#define PPC_LWZ(r, base, i) EMIT(PPC_INST_LWZ | ___PPC_RT(r) | \
70 ___PPC_RA(base) | IMM_L(i))
71#define PPC_LHZ(r, base, i) EMIT(PPC_INST_LHZ | ___PPC_RT(r) | \
72 ___PPC_RA(base) | IMM_L(i))
9c662cad
PB		 73#define PPC_LHBRX(r, base, b) EMIT(PPC_INST_LHBRX | ___PPC_RT(r) | \
74 ___PPC_RA(base) | ___PPC_RB(b))
156d0e29
NR		 75#define PPC_LDBRX(r, base, b) EMIT(PPC_INST_LDBRX | ___PPC_RT(r) | \
76 ___PPC_RA(base) | ___PPC_RB(b))
77
78#define PPC_BPF_LDARX(t, a, b, eh) EMIT(PPC_INST_LDARX | ___PPC_RT(t) | \
79 ___PPC_RA(a) | ___PPC_RB(b) | \
80 __PPC_EH(eh))
81#define PPC_BPF_LWARX(t, a, b, eh) EMIT(PPC_INST_LWARX | ___PPC_RT(t) | \
82 ___PPC_RA(a) | ___PPC_RB(b) | \
83 __PPC_EH(eh))
84#define PPC_BPF_STWCX(s, a, b) EMIT(PPC_INST_STWCX | ___PPC_RS(s) | \
85 ___PPC_RA(a) | ___PPC_RB(b))
86#define PPC_BPF_STDCX(s, a, b) EMIT(PPC_INST_STDCX | ___PPC_RS(s) | \
87 ___PPC_RA(a) | ___PPC_RB(b))
09ca5ab2
DK		 88
89#ifdef CONFIG_PPC64
90#define PPC_BPF_LL(r, base, i) do { PPC_LD(r, base, i); } while(0)
91#define PPC_BPF_STL(r, base, i) do { PPC_STD(r, base, i); } while(0)
92#define PPC_BPF_STLU(r, base, i) do { PPC_STDU(r, base, i); } while(0)
93#else
94#define PPC_BPF_LL(r, base, i) do { PPC_LWZ(r, base, i); } while(0)
95#define PPC_BPF_STL(r, base, i) do { PPC_STW(r, base, i); } while(0)
96#define PPC_BPF_STLU(r, base, i) do { PPC_STWU(r, base, i); } while(0)
97#endif
98
cdaade71
MN		 99#define PPC_CMPWI(a, i) EMIT(PPC_INST_CMPWI | ___PPC_RA(a) | IMM_L(i))
100#define PPC_CMPDI(a, i) EMIT(PPC_INST_CMPDI | ___PPC_RA(a) | IMM_L(i))
156d0e29
NR		 101#define PPC_CMPW(a, b) EMIT(PPC_INST_CMPW | ___PPC_RA(a) | \
102 ___PPC_RB(b))
103#define PPC_CMPD(a, b) EMIT(PPC_INST_CMPD | ___PPC_RA(a) | \
104 ___PPC_RB(b))
cdaade71 105#define PPC_CMPLWI(a, i) EMIT(PPC_INST_CMPLWI | ___PPC_RA(a) | IMM_L(i))
156d0e29 106#define PPC_CMPLDI(a, i) EMIT(PPC_INST_CMPLDI | ___PPC_RA(a) | IMM_L(i))
cef1e8cd
NR		 107#define PPC_CMPLW(a, b) EMIT(PPC_INST_CMPLW | ___PPC_RA(a) | \
108 ___PPC_RB(b))
156d0e29
NR		 109#define PPC_CMPLD(a, b) EMIT(PPC_INST_CMPLD | ___PPC_RA(a) | \
110 ___PPC_RB(b))
0ca87f05 111
cdaade71
MN		 112#define PPC_SUB(d, a, b) EMIT(PPC_INST_SUB | ___PPC_RT(d) | \
113 ___PPC_RB(a) | ___PPC_RA(b))
114#define PPC_ADD(d, a, b) EMIT(PPC_INST_ADD | ___PPC_RT(d) | \
115 ___PPC_RA(a) | ___PPC_RB(b))
156d0e29
NR		 116#define PPC_MULD(d, a, b) EMIT(PPC_INST_MULLD | ___PPC_RT(d) | \
117 ___PPC_RA(a) | ___PPC_RB(b))
cef1e8cd 118#define PPC_MULW(d, a, b) EMIT(PPC_INST_MULLW | ___PPC_RT(d) | \
cdaade71
MN		 119 ___PPC_RA(a) | ___PPC_RB(b))
120#define PPC_MULHWU(d, a, b) EMIT(PPC_INST_MULHWU | ___PPC_RT(d) | \
121 ___PPC_RA(a) | ___PPC_RB(b))
122#define PPC_MULI(d, a, i) EMIT(PPC_INST_MULLI | ___PPC_RT(d) | \
123 ___PPC_RA(a) | IMM_L(i))
124#define PPC_DIVWU(d, a, b) EMIT(PPC_INST_DIVWU | ___PPC_RT(d) | \
125 ___PPC_RA(a) | ___PPC_RB(b))
156d0e29
NR		 126#define PPC_DIVD(d, a, b) EMIT(PPC_INST_DIVD | ___PPC_RT(d) | \
127 ___PPC_RA(a) | ___PPC_RB(b))
cdaade71
MN		 128#define PPC_AND(d, a, b) EMIT(PPC_INST_AND | ___PPC_RA(d) | \
129 ___PPC_RS(a) | ___PPC_RB(b))
130#define PPC_ANDI(d, a, i) EMIT(PPC_INST_ANDI | ___PPC_RA(d) | \
131 ___PPC_RS(a) | IMM_L(i))
132#define PPC_AND_DOT(d, a, b) EMIT(PPC_INST_ANDDOT | ___PPC_RA(d) | \
133 ___PPC_RS(a) | ___PPC_RB(b))
134#define PPC_OR(d, a, b) EMIT(PPC_INST_OR | ___PPC_RA(d) | \
135 ___PPC_RS(a) | ___PPC_RB(b))
156d0e29 136#define PPC_MR(d, a) PPC_OR(d, a, a)
cdaade71
MN		 137#define PPC_ORI(d, a, i) EMIT(PPC_INST_ORI | ___PPC_RA(d) | \
138 ___PPC_RS(a) | IMM_L(i))
139#define PPC_ORIS(d, a, i) EMIT(PPC_INST_ORIS | ___PPC_RA(d) | \
140 ___PPC_RS(a) | IMM_L(i))
02871903
DB		 141#define PPC_XOR(d, a, b) EMIT(PPC_INST_XOR | ___PPC_RA(d) | \
142 ___PPC_RS(a) | ___PPC_RB(b))
143#define PPC_XORI(d, a, i) EMIT(PPC_INST_XORI | ___PPC_RA(d) | \
144 ___PPC_RS(a) | IMM_L(i))
145#define PPC_XORIS(d, a, i) EMIT(PPC_INST_XORIS | ___PPC_RA(d) | \
146 ___PPC_RS(a) | IMM_L(i))
156d0e29
NR		 147#define PPC_EXTSW(d, a) EMIT(PPC_INST_EXTSW | ___PPC_RA(d) | \
148 ___PPC_RS(a))
cdaade71
MN		 149#define PPC_SLW(d, a, s) EMIT(PPC_INST_SLW | ___PPC_RA(d) | \
150 ___PPC_RS(a) | ___PPC_RB(s))
156d0e29
NR		 151#define PPC_SLD(d, a, s) EMIT(PPC_INST_SLD | ___PPC_RA(d) | \
152 ___PPC_RS(a) | ___PPC_RB(s))
cdaade71
MN		 153#define PPC_SRW(d, a, s) EMIT(PPC_INST_SRW | ___PPC_RA(d) | \
154 ___PPC_RS(a) | ___PPC_RB(s))
156d0e29
NR		 155#define PPC_SRD(d, a, s) EMIT(PPC_INST_SRD | ___PPC_RA(d) | \
156 ___PPC_RS(a) | ___PPC_RB(s))
157#define PPC_SRAD(d, a, s) EMIT(PPC_INST_SRAD | ___PPC_RA(d) | \
158 ___PPC_RS(a) | ___PPC_RB(s))
159#define PPC_SRADI(d, a, i) EMIT(PPC_INST_SRADI | ___PPC_RA(d) | \
f0cd8240 160 ___PPC_RS(a) | __PPC_SH64(i))
277285b8
NR		 161#define PPC_RLWINM(d, a, i, mb, me) EMIT(PPC_INST_RLWINM | ___PPC_RA(d) | \
162 ___PPC_RS(a) | __PPC_SH(i) | \
163 __PPC_MB(mb) | __PPC_ME(me))
156d0e29
NR		 164#define PPC_RLWIMI(d, a, i, mb, me) EMIT(PPC_INST_RLWIMI | ___PPC_RA(d) | \
165 ___PPC_RS(a) | __PPC_SH(i) | \
166 __PPC_MB(mb) | __PPC_ME(me))
167#define PPC_RLDICL(d, a, i, mb) EMIT(PPC_INST_RLDICL | ___PPC_RA(d) | \
f0cd8240
NR		 168 ___PPC_RS(a) | __PPC_SH64(i) | \
169 __PPC_MB64(mb))
277285b8 170#define PPC_RLDICR(d, a, i, me) EMIT(PPC_INST_RLDICR | ___PPC_RA(d) | \
f0cd8240
NR		 171 ___PPC_RS(a) | __PPC_SH64(i) | \
172 __PPC_ME64(me))
277285b8 173
0ca87f05 174/* slwi = rlwinm Rx, Ry, n, 0, 31-n */
277285b8 175#define PPC_SLWI(d, a, i) PPC_RLWINM(d, a, i, 0, 31-(i))
0ca87f05 176/* srwi = rlwinm Rx, Ry, 32-n, n, 31 */
277285b8 177#define PPC_SRWI(d, a, i) PPC_RLWINM(d, a, 32-(i), i, 31)
0ca87f05 178/* sldi = rldicr Rx, Ry, n, 63-n */
277285b8 179#define PPC_SLDI(d, a, i) PPC_RLDICR(d, a, i, 63-(i))
156d0e29
NR		 180/* sldi = rldicl Rx, Ry, 64-n, n */
181#define PPC_SRDI(d, a, i) PPC_RLDICL(d, a, 64-(i), i)
277285b8 182
cdaade71 183#define PPC_NEG(d, a) EMIT(PPC_INST_NEG | ___PPC_RT(d) | ___PPC_RA(a))
0ca87f05
ME		 184
185/* Long jump; (unconditional 'branch') */
186#define PPC_JMP(dest) EMIT(PPC_INST_BRANCH | \
187 (((dest) - (ctx->idx * 4)) & 0x03fffffc))
188/* "cond" here covers BO:BI fields. */
189#define PPC_BCC_SHORT(cond, dest) EMIT(PPC_INST_BRANCH_COND | \
190 (((cond) & 0x3ff) << 16) | \
191 (((dest) - (ctx->idx * 4)) & \
192 0xfffc))
aaf2f7e0
NR		 193/* Sign-extended 32-bit immediate load */
194#define PPC_LI32(d, i) do { \
195 if ((int)(uintptr_t)(i) >= -32768 && \
196 (int)(uintptr_t)(i) < 32768) \
197 PPC_LI(d, i); \
198 else { \
199 PPC_LIS(d, IMM_H(i)); \
200 if (IMM_L(i)) \
201 PPC_ORI(d, d, IMM_L(i)); \
0ca87f05 202 } } while(0)
aaf2f7e0 203
0ca87f05 204#define PPC_LI64(d, i) do { \
b1a05787
NR		 205 if ((long)(i) >= -2147483648 && \
206 (long)(i) < 2147483648) \
0ca87f05
ME		 207 PPC_LI32(d, i); \
208 else { \
b1a05787
NR		 209 if (!((uintptr_t)(i) & 0xffff800000000000ULL)) \
210 PPC_LI(d, ((uintptr_t)(i) >> 32) & 0xffff); \
211 else { \
212 PPC_LIS(d, ((uintptr_t)(i) >> 48)); \
213 if ((uintptr_t)(i) & 0x0000ffff00000000ULL) \
214 PPC_ORI(d, d, \
215 ((uintptr_t)(i) >> 32) & 0xffff); \
216 } \
0ca87f05
ME		 217 PPC_SLDI(d, d, 32); \
218 if ((uintptr_t)(i) & 0x00000000ffff0000ULL) \
219 PPC_ORIS(d, d, \
220 ((uintptr_t)(i) >> 16) & 0xffff); \
221 if ((uintptr_t)(i) & 0x000000000000ffffULL) \
222 PPC_ORI(d, d, (uintptr_t)(i) & 0xffff); \
b1a05787 223 } } while (0)
0ca87f05 224
09ca5ab2
DK		 225#ifdef CONFIG_PPC64
226#define PPC_FUNC_ADDR(d,i) do { PPC_LI64(d, i); } while(0)
227#else
228#define PPC_FUNC_ADDR(d,i) do { PPC_LI32(d, i); } while(0)
229#endif
230
0ca87f05
ME		 231static inline bool is_nearbranch(int offset)
232{
233 return (offset < 32768) && (offset >= -32768);
234}
235
236/*
237 * The fly in the ointment of code size changing from pass to pass is
238 * avoided by padding the short branch case with a NOP. If code size differs
239 * with different branch reaches we will have the issue of code moving from
240 * one pass to the next and will need a few passes to converge on a stable
241 * state.
242 */
243#define PPC_BCC(cond, dest) do { \
244 if (is_nearbranch((dest) - (ctx->idx * 4))) { \
245 PPC_BCC_SHORT(cond, dest); \
246 PPC_NOP(); \
247 } else { \
248 /* Flip the 'T or F' bit to invert comparison */ \
249 PPC_BCC_SHORT(cond ^ COND_CMP_TRUE, (ctx->idx+2)*4); \
250 PPC_JMP(dest); \
251 } } while(0)
252
253/* To create a branch condition, select a bit of cr0... */
254#define CR0_LT 0
255#define CR0_GT 1
256#define CR0_EQ 2
257/* ...and modify BO[3] */
258#define COND_CMP_TRUE 0x100
259#define COND_CMP_FALSE 0x000
260/* Together, they make all required comparisons: */
261#define COND_GT (CR0_GT | COND_CMP_TRUE)
262#define COND_GE (CR0_LT | COND_CMP_FALSE)
263#define COND_EQ (CR0_EQ | COND_CMP_TRUE)
264#define COND_NE (CR0_EQ | COND_CMP_FALSE)
265#define COND_LT (CR0_LT | COND_CMP_TRUE)
266
0ca87f05
ME		 267#endif
268
269#endif
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