[mirror_ubuntu-bionic-kernel.git] / arch / powerpc / oprofile / op_model_7450.c

/*
 * arch/powerpc/oprofile/op_model_7450.c
 *
 * Freescale 745x/744x oprofile support, based on fsl_booke support
 * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
 *
 * Copyright (c) 2004 Freescale Semiconductor, Inc
 *
 * Author: Andy Fleming
 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#include <linux/oprofile.h>
#include <linux/init.h>
#include <linux/smp.h>
#include <asm/ptrace.h>
#include <asm/system.h>
#include <asm/processor.h>
#include <asm/cputable.h>
#include <asm/page.h>
#include <asm/pmc.h>
#include <asm/oprofile_impl.h>

static unsigned long reset_value[OP_MAX_COUNTER];

static int oprofile_running;
static u32 mmcr0_val, mmcr1_val, mmcr2_val, num_pmcs;

#define MMCR0_PMC1_SHIFT	6
#define MMCR0_PMC2_SHIFT	0
#define MMCR1_PMC3_SHIFT	27
#define MMCR1_PMC4_SHIFT	22
#define MMCR1_PMC5_SHIFT	17
#define MMCR1_PMC6_SHIFT	11

#define mmcr0_event1(event) \
	((event << MMCR0_PMC1_SHIFT) & MMCR0_PMC1SEL)
#define mmcr0_event2(event) \
	((event << MMCR0_PMC2_SHIFT) & MMCR0_PMC2SEL)

#define mmcr1_event3(event) \
	((event << MMCR1_PMC3_SHIFT) & MMCR1_PMC3SEL)
#define mmcr1_event4(event) \
	((event << MMCR1_PMC4_SHIFT) & MMCR1_PMC4SEL)
#define mmcr1_event5(event) \
	((event << MMCR1_PMC5_SHIFT) & MMCR1_PMC5SEL)
#define mmcr1_event6(event) \
	((event << MMCR1_PMC6_SHIFT) & MMCR1_PMC6SEL)

#define MMCR0_INIT (MMCR0_FC | MMCR0_FCS | MMCR0_FCP | MMCR0_FCM1 | MMCR0_FCM0)

/* Unfreezes the counters on this CPU, enables the interrupt,
 * enables the counters to trigger the interrupt, and sets the
 * counters to only count when the mark bit is not set.
 */
static void pmc_start_ctrs(void)
{
	u32 mmcr0 = mfspr(SPRN_MMCR0);

	mmcr0 &= ~(MMCR0_FC | MMCR0_FCM0);
	mmcr0 |= (MMCR0_FCECE | MMCR0_PMC1CE | MMCR0_PMCnCE | MMCR0_PMXE);

	mtspr(SPRN_MMCR0, mmcr0);
}

/* Disables the counters on this CPU, and freezes them */
static void pmc_stop_ctrs(void)
{
	u32 mmcr0 = mfspr(SPRN_MMCR0);

	mmcr0 |= MMCR0_FC;
	mmcr0 &= ~(MMCR0_FCECE | MMCR0_PMC1CE | MMCR0_PMCnCE | MMCR0_PMXE);

	mtspr(SPRN_MMCR0, mmcr0);
}

/* Configures the counters on this CPU based on the global
 * settings */
static int fsl7450_cpu_setup(struct op_counter_config *ctr)
{
	/* freeze all counters */
	pmc_stop_ctrs();

	mtspr(SPRN_MMCR0, mmcr0_val);
	mtspr(SPRN_MMCR1, mmcr1_val);
	if (num_pmcs > 4)
		mtspr(SPRN_MMCR2, mmcr2_val);

	return 0;
}

/* Configures the global settings for the countes on all CPUs. */
static int fsl7450_reg_setup(struct op_counter_config *ctr,
			     struct op_system_config *sys,
			     int num_ctrs)
{
	int i;

	num_pmcs = num_ctrs;
	/* Our counters count up, and "count" refers to
	 * how much before the next interrupt, and we interrupt
	 * on overflow.  So we calculate the starting value
	 * which will give us "count" until overflow.
	 * Then we set the events on the enabled counters */
	for (i = 0; i < num_ctrs; ++i)
		reset_value[i] = 0x80000000UL - ctr[i].count;

	/* Set events for Counters 1 & 2 */
	mmcr0_val = MMCR0_INIT | mmcr0_event1(ctr[0].event)
		| mmcr0_event2(ctr[1].event);

	/* Setup user/kernel bits */
	if (sys->enable_kernel)
		mmcr0_val &= ~(MMCR0_FCS);

	if (sys->enable_user)
		mmcr0_val &= ~(MMCR0_FCP);

	/* Set events for Counters 3-6 */
	mmcr1_val = mmcr1_event3(ctr[2].event)
		| mmcr1_event4(ctr[3].event);
	if (num_ctrs > 4)
		mmcr1_val |= mmcr1_event5(ctr[4].event)
			| mmcr1_event6(ctr[5].event);

	mmcr2_val = 0;

	return 0;
}

/* Sets the counters on this CPU to the chosen values, and starts them */
static int fsl7450_start(struct op_counter_config *ctr)
{
	int i;

	mtmsr(mfmsr() | MSR_PMM);

	for (i = 0; i < num_pmcs; ++i) {
		if (ctr[i].enabled)
			classic_ctr_write(i, reset_value[i]);
		else
			classic_ctr_write(i, 0);
	}

	/* Clear the freeze bit, and enable the interrupt.
	 * The counters won't actually start until the rfi clears
	 * the PMM bit */
	pmc_start_ctrs();

	oprofile_running = 1;

	return 0;
}

/* Stop the counters on this CPU */
static void fsl7450_stop(void)
{
	/* freeze counters */
	pmc_stop_ctrs();

	oprofile_running = 0;

	mb();
}


/* Handle the interrupt on this CPU, and log a sample for each
 * event that triggered the interrupt */
static void fsl7450_handle_interrupt(struct pt_regs *regs,
				    struct op_counter_config *ctr)
{
	unsigned long pc;
	int is_kernel;
	int val;
	int i;

	/* set the PMM bit (see comment below) */
	mtmsr(mfmsr() | MSR_PMM);

	pc = mfspr(SPRN_SIAR);
	is_kernel = is_kernel_addr(pc);

	for (i = 0; i < num_pmcs; ++i) {
		val = classic_ctr_read(i);
		if (val < 0) {
			if (oprofile_running && ctr[i].enabled) {
				oprofile_add_ext_sample(pc, regs, i, is_kernel);
				classic_ctr_write(i, reset_value[i]);
			} else {
				classic_ctr_write(i, 0);
			}
		}
	}

	/* The freeze bit was set by the interrupt. */
	/* Clear the freeze bit, and reenable the interrupt.
	 * The counters won't actually start until the rfi clears
	 * the PM/M bit */
	pmc_start_ctrs();
}

struct op_powerpc_model op_model_7450= {
	.reg_setup		= fsl7450_reg_setup,
	.cpu_setup		= fsl7450_cpu_setup,
	.start			= fsl7450_start,
	.stop			= fsl7450_stop,
	.handle_interrupt	= fsl7450_handle_interrupt,
};
Commit	Line	Data
555d97ac	1	/*
f30c2269	2	* arch/powerpc/oprofile/op_model_7450.c
555d97ac AF	3	*
	4	* Freescale 745x/744x oprofile support, based on fsl_booke support
	5	* Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
	6	*
	7	* Copyright (c) 2004 Freescale Semiconductor, Inc
	8	*
	9	* Author: Andy Fleming
	10	* Maintainer: Kumar Gala <galak@kernel.crashing.org>
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License
	14	* as published by the Free Software Foundation; either version
	15	* 2 of the License, or (at your option) any later version.
	16	*/
	17
	18	#include <linux/oprofile.h>
	19	#include <linux/init.h>
	20	#include <linux/smp.h>
	21	#include <asm/ptrace.h>
	22	#include <asm/system.h>
	23	#include <asm/processor.h>
	24	#include <asm/cputable.h>
	25	#include <asm/page.h>
	26	#include <asm/pmc.h>
	27	#include <asm/oprofile_impl.h>
	28
	29	static unsigned long reset_value[OP_MAX_COUNTER];
	30
	31	static int oprofile_running;
f8ff96db	32	static u32 mmcr0_val, mmcr1_val, mmcr2_val, num_pmcs;
555d97ac AF	33
	34	#define MMCR0_PMC1_SHIFT 6
	35	#define MMCR0_PMC2_SHIFT 0
	36	#define MMCR1_PMC3_SHIFT 27
	37	#define MMCR1_PMC4_SHIFT 22
	38	#define MMCR1_PMC5_SHIFT 17
	39	#define MMCR1_PMC6_SHIFT 11
	40
	41	#define mmcr0_event1(event) \
	42	((event << MMCR0_PMC1_SHIFT) & MMCR0_PMC1SEL)
	43	#define mmcr0_event2(event) \
	44	((event << MMCR0_PMC2_SHIFT) & MMCR0_PMC2SEL)
	45
	46	#define mmcr1_event3(event) \
	47	((event << MMCR1_PMC3_SHIFT) & MMCR1_PMC3SEL)
	48	#define mmcr1_event4(event) \
	49	((event << MMCR1_PMC4_SHIFT) & MMCR1_PMC4SEL)
	50	#define mmcr1_event5(event) \
	51	((event << MMCR1_PMC5_SHIFT) & MMCR1_PMC5SEL)
	52	#define mmcr1_event6(event) \
	53	((event << MMCR1_PMC6_SHIFT) & MMCR1_PMC6SEL)
	54
	55	#define MMCR0_INIT (MMCR0_FC \| MMCR0_FCS \| MMCR0_FCP \| MMCR0_FCM1 \| MMCR0_FCM0)
	56
	57	/* Unfreezes the counters on this CPU, enables the interrupt,
	58	* enables the counters to trigger the interrupt, and sets the
	59	* counters to only count when the mark bit is not set.
	60	*/
	61	static void pmc_start_ctrs(void)
	62	{
	63	u32 mmcr0 = mfspr(SPRN_MMCR0);
	64
	65	mmcr0 &= ~(MMCR0_FC \| MMCR0_FCM0);
	66	mmcr0 \|= (MMCR0_FCECE \| MMCR0_PMC1CE \| MMCR0_PMCnCE \| MMCR0_PMXE);
	67
	68	mtspr(SPRN_MMCR0, mmcr0);
	69	}
	70
	71	/* Disables the counters on this CPU, and freezes them */
	72	static void pmc_stop_ctrs(void)
	73	{
	74	u32 mmcr0 = mfspr(SPRN_MMCR0);
	75
	76	mmcr0 \|= MMCR0_FC;
	77	mmcr0 &= ~(MMCR0_FCECE \| MMCR0_PMC1CE \| MMCR0_PMCnCE \| MMCR0_PMXE);
	78
	79	mtspr(SPRN_MMCR0, mmcr0);
	80	}
	81
	82	/* Configures the counters on this CPU based on the global
	83	* settings */
1474855d	84	static int fsl7450_cpu_setup(struct op_counter_config *ctr)
555d97ac AF	85	{
	86	/* freeze all counters */
	87	pmc_stop_ctrs();
	88
	89	mtspr(SPRN_MMCR0, mmcr0_val);
	90	mtspr(SPRN_MMCR1, mmcr1_val);
f8ff96db OP	91	if (num_pmcs > 4)
f8ff96db OP	92	mtspr(SPRN_MMCR2, mmcr2_val);
1474855d BN	93
1474855d BN	94	return 0;
555d97ac AF	95	}
555d97ac AF	96
555d97ac	97	/* Configures the global settings for the countes on all CPUs. */
1474855d	98	static int fsl7450_reg_setup(struct op_counter_config *ctr,
555d97ac AF	99	struct op_system_config *sys,
	100	int num_ctrs)
	101	{
	102	int i;
	103
f8ff96db	104	num_pmcs = num_ctrs;
555d97ac AF	105	/* Our counters count up, and "count" refers to
	106	* how much before the next interrupt, and we interrupt
	107	* on overflow. So we calculate the starting value
	108	* which will give us "count" until overflow.
	109	* Then we set the events on the enabled counters */
f8ff96db	110	for (i = 0; i < num_ctrs; ++i)
555d97ac AF	111	reset_value[i] = 0x80000000UL - ctr[i].count;
	112
	113	/* Set events for Counters 1 & 2 */
	114	mmcr0_val = MMCR0_INIT \| mmcr0_event1(ctr[0].event)
	115	\| mmcr0_event2(ctr[1].event);
	116
	117	/* Setup user/kernel bits */
	118	if (sys->enable_kernel)
	119	mmcr0_val &= ~(MMCR0_FCS);
	120
	121	if (sys->enable_user)
	122	mmcr0_val &= ~(MMCR0_FCP);
	123
	124	/* Set events for Counters 3-6 */
	125	mmcr1_val = mmcr1_event3(ctr[2].event)
f8ff96db OP	126	\| mmcr1_event4(ctr[3].event);
	127	if (num_ctrs > 4)
	128	mmcr1_val \|= mmcr1_event5(ctr[4].event)
	129	\| mmcr1_event6(ctr[5].event);
555d97ac AF	130
555d97ac AF	131	mmcr2_val = 0;
1474855d BN	132
1474855d BN	133	return 0;
555d97ac AF	134	}
	135
	136	/* Sets the counters on this CPU to the chosen values, and starts them */
1474855d	137	static int fsl7450_start(struct op_counter_config *ctr)
555d97ac AF	138	{
	139	int i;
	140
	141	mtmsr(mfmsr() \| MSR_PMM);
	142
f8ff96db	143	for (i = 0; i < num_pmcs; ++i) {
555d97ac	144	if (ctr[i].enabled)
c69b767a	145	classic_ctr_write(i, reset_value[i]);
555d97ac	146	else
c69b767a	147	classic_ctr_write(i, 0);
555d97ac AF	148	}
	149
	150	/* Clear the freeze bit, and enable the interrupt.
	151	* The counters won't actually start until the rfi clears
	152	* the PMM bit */
	153	pmc_start_ctrs();
	154
	155	oprofile_running = 1;
1474855d BN	156
1474855d BN	157	return 0;
555d97ac AF	158	}
	159
	160	/* Stop the counters on this CPU */
	161	static void fsl7450_stop(void)
	162	{
	163	/* freeze counters */
	164	pmc_stop_ctrs();
	165
	166	oprofile_running = 0;
	167
	168	mb();
	169	}
	170
	171
	172	/* Handle the interrupt on this CPU, and log a sample for each
	173	* event that triggered the interrupt */
	174	static void fsl7450_handle_interrupt(struct pt_regs *regs,
	175	struct op_counter_config *ctr)
	176	{
	177	unsigned long pc;
	178	int is_kernel;
	179	int val;
	180	int i;
	181
	182	/* set the PMM bit (see comment below) */
	183	mtmsr(mfmsr() \| MSR_PMM);
	184
	185	pc = mfspr(SPRN_SIAR);
fa465f8c	186	is_kernel = is_kernel_addr(pc);
555d97ac	187
f8ff96db	188	for (i = 0; i < num_pmcs; ++i) {
c69b767a	189	val = classic_ctr_read(i);
555d97ac AF	190	if (val < 0) {
555d97ac AF	191	if (oprofile_running && ctr[i].enabled) {
fa465f8c	192	oprofile_add_ext_sample(pc, regs, i, is_kernel);
c69b767a	193	classic_ctr_write(i, reset_value[i]);
555d97ac	194	} else {
c69b767a	195	classic_ctr_write(i, 0);
555d97ac AF	196	}
	197	}
	198	}
	199
	200	/* The freeze bit was set by the interrupt. */
	201	/* Clear the freeze bit, and reenable the interrupt.
	202	* The counters won't actually start until the rfi clears
1474855d	203	* the PM/M bit */
555d97ac AF	204	pmc_start_ctrs();
	205	}
	206
	207	struct op_powerpc_model op_model_7450= {
	208	.reg_setup = fsl7450_reg_setup,
	209	.cpu_setup = fsl7450_cpu_setup,
	210	.start = fsl7450_start,
	211	.stop = fsl7450_stop,
	212	.handle_interrupt = fsl7450_handle_interrupt,
	213	};