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Commit | Line | Data |
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4574910e | 1 | /* |
cdd6c482 | 2 | * Performance event support - powerpc architecture code |
4574910e PM |
3 | * |
4 | * Copyright 2008-2009 Paul Mackerras, IBM Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/sched.h> | |
cdd6c482 | 13 | #include <linux/perf_event.h> |
4574910e PM |
14 | #include <linux/percpu.h> |
15 | #include <linux/hardirq.h> | |
69123184 | 16 | #include <linux/uaccess.h> |
4574910e PM |
17 | #include <asm/reg.h> |
18 | #include <asm/pmc.h> | |
01d0287f | 19 | #include <asm/machdep.h> |
0475f9ea | 20 | #include <asm/firmware.h> |
0bbd0d4b | 21 | #include <asm/ptrace.h> |
69123184 | 22 | #include <asm/code-patching.h> |
4574910e | 23 | |
3925f46b AK |
24 | #define BHRB_MAX_ENTRIES 32 |
25 | #define BHRB_TARGET 0x0000000000000002 | |
26 | #define BHRB_PREDICTION 0x0000000000000001 | |
b0d436c7 | 27 | #define BHRB_EA 0xFFFFFFFFFFFFFFFCUL |
3925f46b | 28 | |
cdd6c482 IM |
29 | struct cpu_hw_events { |
30 | int n_events; | |
4574910e PM |
31 | int n_percpu; |
32 | int disabled; | |
33 | int n_added; | |
ab7ef2e5 PM |
34 | int n_limited; |
35 | u8 pmcs_enabled; | |
cdd6c482 IM |
36 | struct perf_event *event[MAX_HWEVENTS]; |
37 | u64 events[MAX_HWEVENTS]; | |
38 | unsigned int flags[MAX_HWEVENTS]; | |
9de5cb0f ME |
39 | /* |
40 | * The order of the MMCR array is: | |
41 | * - 64-bit, MMCR0, MMCR1, MMCRA, MMCR2 | |
42 | * - 32-bit, MMCR0, MMCR1, MMCR2 | |
43 | */ | |
44 | unsigned long mmcr[4]; | |
a8f90e90 PM |
45 | struct perf_event *limited_counter[MAX_LIMITED_HWCOUNTERS]; |
46 | u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS]; | |
cdd6c482 IM |
47 | u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; |
48 | unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; | |
49 | unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; | |
8e6d5573 LM |
50 | |
51 | unsigned int group_flag; | |
fbbe0701 | 52 | unsigned int txn_flags; |
8e6d5573 | 53 | int n_txn_start; |
3925f46b AK |
54 | |
55 | /* BHRB bits */ | |
56 | u64 bhrb_filter; /* BHRB HW branch filter */ | |
f0322f7f | 57 | unsigned int bhrb_users; |
3925f46b AK |
58 | void *bhrb_context; |
59 | struct perf_branch_stack bhrb_stack; | |
60 | struct perf_branch_entry bhrb_entries[BHRB_MAX_ENTRIES]; | |
4574910e | 61 | }; |
3925f46b | 62 | |
e51df2c1 | 63 | static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); |
4574910e | 64 | |
e51df2c1 | 65 | static struct power_pmu *ppmu; |
4574910e | 66 | |
d095cd46 | 67 | /* |
57c0c15b | 68 | * Normally, to ignore kernel events we set the FCS (freeze counters |
d095cd46 PM |
69 | * in supervisor mode) bit in MMCR0, but if the kernel runs with the |
70 | * hypervisor bit set in the MSR, or if we are running on a processor | |
71 | * where the hypervisor bit is forced to 1 (as on Apple G5 processors), | |
72 | * then we need to use the FCHV bit to ignore kernel events. | |
73 | */ | |
cdd6c482 | 74 | static unsigned int freeze_events_kernel = MMCR0_FCS; |
d095cd46 | 75 | |
98fb1807 PM |
76 | /* |
77 | * 32-bit doesn't have MMCRA but does have an MMCR2, | |
78 | * and a few other names are different. | |
79 | */ | |
80 | #ifdef CONFIG_PPC32 | |
81 | ||
82 | #define MMCR0_FCHV 0 | |
83 | #define MMCR0_PMCjCE MMCR0_PMCnCE | |
7a7a41f9 | 84 | #define MMCR0_FC56 0 |
378a6ee9 | 85 | #define MMCR0_PMAO 0 |
330a1eb7 | 86 | #define MMCR0_EBE 0 |
76cb8a78 | 87 | #define MMCR0_BHRBA 0 |
330a1eb7 ME |
88 | #define MMCR0_PMCC 0 |
89 | #define MMCR0_PMCC_U6 0 | |
98fb1807 PM |
90 | |
91 | #define SPRN_MMCRA SPRN_MMCR2 | |
92 | #define MMCRA_SAMPLE_ENABLE 0 | |
93 | ||
94 | static inline unsigned long perf_ip_adjust(struct pt_regs *regs) | |
95 | { | |
96 | return 0; | |
97 | } | |
98fb1807 PM |
98 | static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) { } |
99 | static inline u32 perf_get_misc_flags(struct pt_regs *regs) | |
100 | { | |
101 | return 0; | |
102 | } | |
75382aa7 AB |
103 | static inline void perf_read_regs(struct pt_regs *regs) |
104 | { | |
105 | regs->result = 0; | |
106 | } | |
98fb1807 PM |
107 | static inline int perf_intr_is_nmi(struct pt_regs *regs) |
108 | { | |
109 | return 0; | |
110 | } | |
111 | ||
e6878835 | 112 | static inline int siar_valid(struct pt_regs *regs) |
113 | { | |
114 | return 1; | |
115 | } | |
116 | ||
330a1eb7 ME |
117 | static bool is_ebb_event(struct perf_event *event) { return false; } |
118 | static int ebb_event_check(struct perf_event *event) { return 0; } | |
119 | static void ebb_event_add(struct perf_event *event) { } | |
120 | static void ebb_switch_out(unsigned long mmcr0) { } | |
9de5cb0f | 121 | static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw) |
330a1eb7 | 122 | { |
9de5cb0f | 123 | return cpuhw->mmcr[0]; |
330a1eb7 ME |
124 | } |
125 | ||
d52f2dc4 MN |
126 | static inline void power_pmu_bhrb_enable(struct perf_event *event) {} |
127 | static inline void power_pmu_bhrb_disable(struct perf_event *event) {} | |
acba3c7e | 128 | static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) {} |
d52f2dc4 | 129 | static inline void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) {} |
c2e37a26 | 130 | static void pmao_restore_workaround(bool ebb) { } |
98fb1807 PM |
131 | #endif /* CONFIG_PPC32 */ |
132 | ||
33904054 ME |
133 | static bool regs_use_siar(struct pt_regs *regs) |
134 | { | |
72e349f1 AB |
135 | /* |
136 | * When we take a performance monitor exception the regs are setup | |
137 | * using perf_read_regs() which overloads some fields, in particular | |
138 | * regs->result to tell us whether to use SIAR. | |
139 | * | |
140 | * However if the regs are from another exception, eg. a syscall, then | |
141 | * they have not been setup using perf_read_regs() and so regs->result | |
142 | * is something random. | |
143 | */ | |
144 | return ((TRAP(regs) == 0xf00) && regs->result); | |
33904054 ME |
145 | } |
146 | ||
98fb1807 PM |
147 | /* |
148 | * Things that are specific to 64-bit implementations. | |
149 | */ | |
150 | #ifdef CONFIG_PPC64 | |
151 | ||
152 | static inline unsigned long perf_ip_adjust(struct pt_regs *regs) | |
153 | { | |
154 | unsigned long mmcra = regs->dsisr; | |
155 | ||
7a786832 | 156 | if ((ppmu->flags & PPMU_HAS_SSLOT) && (mmcra & MMCRA_SAMPLE_ENABLE)) { |
98fb1807 PM |
157 | unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT; |
158 | if (slot > 1) | |
159 | return 4 * (slot - 1); | |
160 | } | |
7a786832 | 161 | |
98fb1807 PM |
162 | return 0; |
163 | } | |
164 | ||
98fb1807 PM |
165 | /* |
166 | * The user wants a data address recorded. | |
167 | * If we're not doing instruction sampling, give them the SDAR | |
168 | * (sampled data address). If we are doing instruction sampling, then | |
169 | * only give them the SDAR if it corresponds to the instruction | |
58a032c3 ME |
170 | * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC, the |
171 | * [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA, or the SDAR_VALID bit in SIER. | |
98fb1807 PM |
172 | */ |
173 | static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) | |
174 | { | |
175 | unsigned long mmcra = regs->dsisr; | |
58a032c3 | 176 | bool sdar_valid; |
e6878835 | 177 | |
58a032c3 ME |
178 | if (ppmu->flags & PPMU_HAS_SIER) |
179 | sdar_valid = regs->dar & SIER_SDAR_VALID; | |
180 | else { | |
181 | unsigned long sdsync; | |
182 | ||
183 | if (ppmu->flags & PPMU_SIAR_VALID) | |
184 | sdsync = POWER7P_MMCRA_SDAR_VALID; | |
185 | else if (ppmu->flags & PPMU_ALT_SIPR) | |
186 | sdsync = POWER6_MMCRA_SDSYNC; | |
187 | else | |
188 | sdsync = MMCRA_SDSYNC; | |
189 | ||
190 | sdar_valid = mmcra & sdsync; | |
191 | } | |
98fb1807 | 192 | |
58a032c3 | 193 | if (!(mmcra & MMCRA_SAMPLE_ENABLE) || sdar_valid) |
98fb1807 PM |
194 | *addrp = mfspr(SPRN_SDAR); |
195 | } | |
196 | ||
5682c460 | 197 | static bool regs_sihv(struct pt_regs *regs) |
68b30bb9 AB |
198 | { |
199 | unsigned long sihv = MMCRA_SIHV; | |
200 | ||
8f61aa32 ME |
201 | if (ppmu->flags & PPMU_HAS_SIER) |
202 | return !!(regs->dar & SIER_SIHV); | |
203 | ||
68b30bb9 AB |
204 | if (ppmu->flags & PPMU_ALT_SIPR) |
205 | sihv = POWER6_MMCRA_SIHV; | |
206 | ||
5682c460 | 207 | return !!(regs->dsisr & sihv); |
68b30bb9 AB |
208 | } |
209 | ||
5682c460 | 210 | static bool regs_sipr(struct pt_regs *regs) |
68b30bb9 AB |
211 | { |
212 | unsigned long sipr = MMCRA_SIPR; | |
213 | ||
8f61aa32 ME |
214 | if (ppmu->flags & PPMU_HAS_SIER) |
215 | return !!(regs->dar & SIER_SIPR); | |
216 | ||
68b30bb9 AB |
217 | if (ppmu->flags & PPMU_ALT_SIPR) |
218 | sipr = POWER6_MMCRA_SIPR; | |
219 | ||
5682c460 | 220 | return !!(regs->dsisr & sipr); |
68b30bb9 AB |
221 | } |
222 | ||
1ce447b9 BH |
223 | static inline u32 perf_flags_from_msr(struct pt_regs *regs) |
224 | { | |
225 | if (regs->msr & MSR_PR) | |
226 | return PERF_RECORD_MISC_USER; | |
227 | if ((regs->msr & MSR_HV) && freeze_events_kernel != MMCR0_FCHV) | |
228 | return PERF_RECORD_MISC_HYPERVISOR; | |
229 | return PERF_RECORD_MISC_KERNEL; | |
230 | } | |
231 | ||
98fb1807 PM |
232 | static inline u32 perf_get_misc_flags(struct pt_regs *regs) |
233 | { | |
33904054 | 234 | bool use_siar = regs_use_siar(regs); |
98fb1807 | 235 | |
75382aa7 | 236 | if (!use_siar) |
1ce447b9 BH |
237 | return perf_flags_from_msr(regs); |
238 | ||
239 | /* | |
240 | * If we don't have flags in MMCRA, rather than using | |
241 | * the MSR, we intuit the flags from the address in | |
242 | * SIAR which should give slightly more reliable | |
243 | * results | |
244 | */ | |
cbda6aa1 | 245 | if (ppmu->flags & PPMU_NO_SIPR) { |
1ce447b9 BH |
246 | unsigned long siar = mfspr(SPRN_SIAR); |
247 | if (siar >= PAGE_OFFSET) | |
248 | return PERF_RECORD_MISC_KERNEL; | |
249 | return PERF_RECORD_MISC_USER; | |
250 | } | |
98fb1807 | 251 | |
7abb840b | 252 | /* PR has priority over HV, so order below is important */ |
5682c460 | 253 | if (regs_sipr(regs)) |
7abb840b | 254 | return PERF_RECORD_MISC_USER; |
5682c460 ME |
255 | |
256 | if (regs_sihv(regs) && (freeze_events_kernel != MMCR0_FCHV)) | |
cdd6c482 | 257 | return PERF_RECORD_MISC_HYPERVISOR; |
5682c460 | 258 | |
7abb840b | 259 | return PERF_RECORD_MISC_KERNEL; |
98fb1807 PM |
260 | } |
261 | ||
262 | /* | |
263 | * Overload regs->dsisr to store MMCRA so we only need to read it once | |
264 | * on each interrupt. | |
8f61aa32 | 265 | * Overload regs->dar to store SIER if we have it. |
75382aa7 AB |
266 | * Overload regs->result to specify whether we should use the MSR (result |
267 | * is zero) or the SIAR (result is non zero). | |
98fb1807 PM |
268 | */ |
269 | static inline void perf_read_regs(struct pt_regs *regs) | |
270 | { | |
75382aa7 AB |
271 | unsigned long mmcra = mfspr(SPRN_MMCRA); |
272 | int marked = mmcra & MMCRA_SAMPLE_ENABLE; | |
273 | int use_siar; | |
274 | ||
5682c460 | 275 | regs->dsisr = mmcra; |
8f61aa32 | 276 | |
cbda6aa1 ME |
277 | if (ppmu->flags & PPMU_HAS_SIER) |
278 | regs->dar = mfspr(SPRN_SIER); | |
8f61aa32 | 279 | |
5c093efa AB |
280 | /* |
281 | * If this isn't a PMU exception (eg a software event) the SIAR is | |
282 | * not valid. Use pt_regs. | |
283 | * | |
284 | * If it is a marked event use the SIAR. | |
285 | * | |
286 | * If the PMU doesn't update the SIAR for non marked events use | |
287 | * pt_regs. | |
288 | * | |
289 | * If the PMU has HV/PR flags then check to see if they | |
290 | * place the exception in userspace. If so, use pt_regs. In | |
291 | * continuous sampling mode the SIAR and the PMU exception are | |
292 | * not synchronised, so they may be many instructions apart. | |
293 | * This can result in confusing backtraces. We still want | |
294 | * hypervisor samples as well as samples in the kernel with | |
295 | * interrupts off hence the userspace check. | |
296 | */ | |
75382aa7 AB |
297 | if (TRAP(regs) != 0xf00) |
298 | use_siar = 0; | |
5c093efa AB |
299 | else if (marked) |
300 | use_siar = 1; | |
301 | else if ((ppmu->flags & PPMU_NO_CONT_SAMPLING)) | |
302 | use_siar = 0; | |
cbda6aa1 | 303 | else if (!(ppmu->flags & PPMU_NO_SIPR) && regs_sipr(regs)) |
75382aa7 AB |
304 | use_siar = 0; |
305 | else | |
306 | use_siar = 1; | |
307 | ||
cbda6aa1 | 308 | regs->result = use_siar; |
98fb1807 PM |
309 | } |
310 | ||
311 | /* | |
312 | * If interrupts were soft-disabled when a PMU interrupt occurs, treat | |
313 | * it as an NMI. | |
314 | */ | |
315 | static inline int perf_intr_is_nmi(struct pt_regs *regs) | |
316 | { | |
317 | return !regs->softe; | |
318 | } | |
319 | ||
e6878835 | 320 | /* |
321 | * On processors like P7+ that have the SIAR-Valid bit, marked instructions | |
322 | * must be sampled only if the SIAR-valid bit is set. | |
323 | * | |
324 | * For unmarked instructions and for processors that don't have the SIAR-Valid | |
325 | * bit, assume that SIAR is valid. | |
326 | */ | |
327 | static inline int siar_valid(struct pt_regs *regs) | |
328 | { | |
329 | unsigned long mmcra = regs->dsisr; | |
330 | int marked = mmcra & MMCRA_SAMPLE_ENABLE; | |
331 | ||
58a032c3 ME |
332 | if (marked) { |
333 | if (ppmu->flags & PPMU_HAS_SIER) | |
334 | return regs->dar & SIER_SIAR_VALID; | |
335 | ||
336 | if (ppmu->flags & PPMU_SIAR_VALID) | |
337 | return mmcra & POWER7P_MMCRA_SIAR_VALID; | |
338 | } | |
e6878835 | 339 | |
340 | return 1; | |
341 | } | |
342 | ||
d52f2dc4 MN |
343 | |
344 | /* Reset all possible BHRB entries */ | |
345 | static void power_pmu_bhrb_reset(void) | |
346 | { | |
347 | asm volatile(PPC_CLRBHRB); | |
348 | } | |
349 | ||
350 | static void power_pmu_bhrb_enable(struct perf_event *event) | |
351 | { | |
69111bac | 352 | struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); |
d52f2dc4 MN |
353 | |
354 | if (!ppmu->bhrb_nr) | |
355 | return; | |
356 | ||
357 | /* Clear BHRB if we changed task context to avoid data leaks */ | |
358 | if (event->ctx->task && cpuhw->bhrb_context != event->ctx) { | |
359 | power_pmu_bhrb_reset(); | |
360 | cpuhw->bhrb_context = event->ctx; | |
361 | } | |
362 | cpuhw->bhrb_users++; | |
acba3c7e | 363 | perf_sched_cb_inc(event->ctx->pmu); |
d52f2dc4 MN |
364 | } |
365 | ||
366 | static void power_pmu_bhrb_disable(struct perf_event *event) | |
367 | { | |
69111bac | 368 | struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); |
d52f2dc4 MN |
369 | |
370 | if (!ppmu->bhrb_nr) | |
371 | return; | |
372 | ||
f0322f7f | 373 | WARN_ON_ONCE(!cpuhw->bhrb_users); |
d52f2dc4 | 374 | cpuhw->bhrb_users--; |
acba3c7e | 375 | perf_sched_cb_dec(event->ctx->pmu); |
d52f2dc4 MN |
376 | |
377 | if (!cpuhw->disabled && !cpuhw->bhrb_users) { | |
378 | /* BHRB cannot be turned off when other | |
379 | * events are active on the PMU. | |
380 | */ | |
381 | ||
382 | /* avoid stale pointer */ | |
383 | cpuhw->bhrb_context = NULL; | |
384 | } | |
385 | } | |
386 | ||
387 | /* Called from ctxsw to prevent one process's branch entries to | |
388 | * mingle with the other process's entries during context switch. | |
389 | */ | |
acba3c7e | 390 | static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) |
d52f2dc4 | 391 | { |
acba3c7e PZ |
392 | if (!ppmu->bhrb_nr) |
393 | return; | |
394 | ||
395 | if (sched_in) | |
d52f2dc4 MN |
396 | power_pmu_bhrb_reset(); |
397 | } | |
69123184 MN |
398 | /* Calculate the to address for a branch */ |
399 | static __u64 power_pmu_bhrb_to(u64 addr) | |
400 | { | |
401 | unsigned int instr; | |
402 | int ret; | |
403 | __u64 target; | |
404 | ||
405 | if (is_kernel_addr(addr)) | |
406 | return branch_target((unsigned int *)addr); | |
407 | ||
408 | /* Userspace: need copy instruction here then translate it */ | |
409 | pagefault_disable(); | |
410 | ret = __get_user_inatomic(instr, (unsigned int __user *)addr); | |
411 | if (ret) { | |
412 | pagefault_enable(); | |
413 | return 0; | |
414 | } | |
415 | pagefault_enable(); | |
416 | ||
417 | target = branch_target(&instr); | |
418 | if ((!target) || (instr & BRANCH_ABSOLUTE)) | |
419 | return target; | |
420 | ||
421 | /* Translate relative branch target from kernel to user address */ | |
422 | return target - (unsigned long)&instr + addr; | |
423 | } | |
d52f2dc4 | 424 | |
d52f2dc4 | 425 | /* Processing BHRB entries */ |
e51df2c1 | 426 | static void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) |
d52f2dc4 MN |
427 | { |
428 | u64 val; | |
429 | u64 addr; | |
506e70d1 | 430 | int r_index, u_index, pred; |
d52f2dc4 MN |
431 | |
432 | r_index = 0; | |
433 | u_index = 0; | |
434 | while (r_index < ppmu->bhrb_nr) { | |
435 | /* Assembly read function */ | |
506e70d1 MN |
436 | val = read_bhrb(r_index++); |
437 | if (!val) | |
438 | /* Terminal marker: End of valid BHRB entries */ | |
d52f2dc4 | 439 | break; |
506e70d1 | 440 | else { |
d52f2dc4 MN |
441 | addr = val & BHRB_EA; |
442 | pred = val & BHRB_PREDICTION; | |
d52f2dc4 | 443 | |
506e70d1 MN |
444 | if (!addr) |
445 | /* invalid entry */ | |
d52f2dc4 | 446 | continue; |
d52f2dc4 | 447 | |
506e70d1 MN |
448 | /* Branches are read most recent first (ie. mfbhrb 0 is |
449 | * the most recent branch). | |
450 | * There are two types of valid entries: | |
451 | * 1) a target entry which is the to address of a | |
452 | * computed goto like a blr,bctr,btar. The next | |
453 | * entry read from the bhrb will be branch | |
454 | * corresponding to this target (ie. the actual | |
455 | * blr/bctr/btar instruction). | |
456 | * 2) a from address which is an actual branch. If a | |
457 | * target entry proceeds this, then this is the | |
458 | * matching branch for that target. If this is not | |
459 | * following a target entry, then this is a branch | |
460 | * where the target is given as an immediate field | |
461 | * in the instruction (ie. an i or b form branch). | |
462 | * In this case we need to read the instruction from | |
463 | * memory to determine the target/to address. | |
464 | */ | |
d52f2dc4 | 465 | |
d52f2dc4 | 466 | if (val & BHRB_TARGET) { |
506e70d1 MN |
467 | /* Target branches use two entries |
468 | * (ie. computed gotos/XL form) | |
469 | */ | |
470 | cpuhw->bhrb_entries[u_index].to = addr; | |
471 | cpuhw->bhrb_entries[u_index].mispred = pred; | |
472 | cpuhw->bhrb_entries[u_index].predicted = ~pred; | |
d52f2dc4 | 473 | |
506e70d1 MN |
474 | /* Get from address in next entry */ |
475 | val = read_bhrb(r_index++); | |
476 | addr = val & BHRB_EA; | |
477 | if (val & BHRB_TARGET) { | |
478 | /* Shouldn't have two targets in a | |
479 | row.. Reset index and try again */ | |
480 | r_index--; | |
481 | addr = 0; | |
482 | } | |
483 | cpuhw->bhrb_entries[u_index].from = addr; | |
d52f2dc4 | 484 | } else { |
506e70d1 MN |
485 | /* Branches to immediate field |
486 | (ie I or B form) */ | |
d52f2dc4 | 487 | cpuhw->bhrb_entries[u_index].from = addr; |
69123184 MN |
488 | cpuhw->bhrb_entries[u_index].to = |
489 | power_pmu_bhrb_to(addr); | |
d52f2dc4 MN |
490 | cpuhw->bhrb_entries[u_index].mispred = pred; |
491 | cpuhw->bhrb_entries[u_index].predicted = ~pred; | |
d52f2dc4 | 492 | } |
506e70d1 MN |
493 | u_index++; |
494 | ||
d52f2dc4 MN |
495 | } |
496 | } | |
497 | cpuhw->bhrb_stack.nr = u_index; | |
498 | return; | |
499 | } | |
500 | ||
330a1eb7 ME |
501 | static bool is_ebb_event(struct perf_event *event) |
502 | { | |
503 | /* | |
504 | * This could be a per-PMU callback, but we'd rather avoid the cost. We | |
505 | * check that the PMU supports EBB, meaning those that don't can still | |
506 | * use bit 63 of the event code for something else if they wish. | |
507 | */ | |
4d9690dd | 508 | return (ppmu->flags & PPMU_ARCH_207S) && |
8d7c55d0 | 509 | ((event->attr.config >> PERF_EVENT_CONFIG_EBB_SHIFT) & 1); |
330a1eb7 ME |
510 | } |
511 | ||
512 | static int ebb_event_check(struct perf_event *event) | |
513 | { | |
514 | struct perf_event *leader = event->group_leader; | |
515 | ||
516 | /* Event and group leader must agree on EBB */ | |
517 | if (is_ebb_event(leader) != is_ebb_event(event)) | |
518 | return -EINVAL; | |
519 | ||
520 | if (is_ebb_event(event)) { | |
521 | if (!(event->attach_state & PERF_ATTACH_TASK)) | |
522 | return -EINVAL; | |
523 | ||
524 | if (!leader->attr.pinned || !leader->attr.exclusive) | |
525 | return -EINVAL; | |
526 | ||
58b5fb00 ME |
527 | if (event->attr.freq || |
528 | event->attr.inherit || | |
529 | event->attr.sample_type || | |
530 | event->attr.sample_period || | |
531 | event->attr.enable_on_exec) | |
330a1eb7 ME |
532 | return -EINVAL; |
533 | } | |
534 | ||
535 | return 0; | |
536 | } | |
537 | ||
538 | static void ebb_event_add(struct perf_event *event) | |
539 | { | |
540 | if (!is_ebb_event(event) || current->thread.used_ebb) | |
541 | return; | |
542 | ||
543 | /* | |
544 | * IFF this is the first time we've added an EBB event, set | |
545 | * PMXE in the user MMCR0 so we can detect when it's cleared by | |
546 | * userspace. We need this so that we can context switch while | |
547 | * userspace is in the EBB handler (where PMXE is 0). | |
548 | */ | |
549 | current->thread.used_ebb = 1; | |
550 | current->thread.mmcr0 |= MMCR0_PMXE; | |
551 | } | |
552 | ||
553 | static void ebb_switch_out(unsigned long mmcr0) | |
554 | { | |
555 | if (!(mmcr0 & MMCR0_EBE)) | |
556 | return; | |
557 | ||
558 | current->thread.siar = mfspr(SPRN_SIAR); | |
559 | current->thread.sier = mfspr(SPRN_SIER); | |
560 | current->thread.sdar = mfspr(SPRN_SDAR); | |
561 | current->thread.mmcr0 = mmcr0 & MMCR0_USER_MASK; | |
562 | current->thread.mmcr2 = mfspr(SPRN_MMCR2) & MMCR2_USER_MASK; | |
563 | } | |
564 | ||
9de5cb0f | 565 | static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw) |
330a1eb7 | 566 | { |
9de5cb0f ME |
567 | unsigned long mmcr0 = cpuhw->mmcr[0]; |
568 | ||
330a1eb7 ME |
569 | if (!ebb) |
570 | goto out; | |
571 | ||
76cb8a78 ME |
572 | /* Enable EBB and read/write to all 6 PMCs and BHRB for userspace */ |
573 | mmcr0 |= MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC_U6; | |
330a1eb7 | 574 | |
c2e37a26 ME |
575 | /* |
576 | * Add any bits from the user MMCR0, FC or PMAO. This is compatible | |
577 | * with pmao_restore_workaround() because we may add PMAO but we never | |
578 | * clear it here. | |
579 | */ | |
330a1eb7 ME |
580 | mmcr0 |= current->thread.mmcr0; |
581 | ||
c2e37a26 ME |
582 | /* |
583 | * Be careful not to set PMXE if userspace had it cleared. This is also | |
584 | * compatible with pmao_restore_workaround() because it has already | |
585 | * cleared PMXE and we leave PMAO alone. | |
586 | */ | |
330a1eb7 ME |
587 | if (!(current->thread.mmcr0 & MMCR0_PMXE)) |
588 | mmcr0 &= ~MMCR0_PMXE; | |
589 | ||
590 | mtspr(SPRN_SIAR, current->thread.siar); | |
591 | mtspr(SPRN_SIER, current->thread.sier); | |
592 | mtspr(SPRN_SDAR, current->thread.sdar); | |
9de5cb0f ME |
593 | |
594 | /* | |
595 | * Merge the kernel & user values of MMCR2. The semantics we implement | |
596 | * are that the user MMCR2 can set bits, ie. cause counters to freeze, | |
597 | * but not clear bits. If a task wants to be able to clear bits, ie. | |
598 | * unfreeze counters, it should not set exclude_xxx in its events and | |
599 | * instead manage the MMCR2 entirely by itself. | |
600 | */ | |
601 | mtspr(SPRN_MMCR2, cpuhw->mmcr[3] | current->thread.mmcr2); | |
330a1eb7 ME |
602 | out: |
603 | return mmcr0; | |
604 | } | |
c2e37a26 ME |
605 | |
606 | static void pmao_restore_workaround(bool ebb) | |
607 | { | |
608 | unsigned pmcs[6]; | |
609 | ||
610 | if (!cpu_has_feature(CPU_FTR_PMAO_BUG)) | |
611 | return; | |
612 | ||
613 | /* | |
614 | * On POWER8E there is a hardware defect which affects the PMU context | |
615 | * switch logic, ie. power_pmu_disable/enable(). | |
616 | * | |
617 | * When a counter overflows PMXE is cleared and FC/PMAO is set in MMCR0 | |
618 | * by the hardware. Sometime later the actual PMU exception is | |
619 | * delivered. | |
620 | * | |
621 | * If we context switch, or simply disable/enable, the PMU prior to the | |
622 | * exception arriving, the exception will be lost when we clear PMAO. | |
623 | * | |
624 | * When we reenable the PMU, we will write the saved MMCR0 with PMAO | |
625 | * set, and this _should_ generate an exception. However because of the | |
626 | * defect no exception is generated when we write PMAO, and we get | |
627 | * stuck with no counters counting but no exception delivered. | |
628 | * | |
629 | * The workaround is to detect this case and tweak the hardware to | |
630 | * create another pending PMU exception. | |
631 | * | |
632 | * We do that by setting up PMC6 (cycles) for an imminent overflow and | |
633 | * enabling the PMU. That causes a new exception to be generated in the | |
634 | * chip, but we don't take it yet because we have interrupts hard | |
635 | * disabled. We then write back the PMU state as we want it to be seen | |
636 | * by the exception handler. When we reenable interrupts the exception | |
637 | * handler will be called and see the correct state. | |
638 | * | |
639 | * The logic is the same for EBB, except that the exception is gated by | |
640 | * us having interrupts hard disabled as well as the fact that we are | |
641 | * not in userspace. The exception is finally delivered when we return | |
642 | * to userspace. | |
643 | */ | |
644 | ||
645 | /* Only if PMAO is set and PMAO_SYNC is clear */ | |
646 | if ((current->thread.mmcr0 & (MMCR0_PMAO | MMCR0_PMAO_SYNC)) != MMCR0_PMAO) | |
647 | return; | |
648 | ||
649 | /* If we're doing EBB, only if BESCR[GE] is set */ | |
650 | if (ebb && !(current->thread.bescr & BESCR_GE)) | |
651 | return; | |
652 | ||
653 | /* | |
654 | * We are already soft-disabled in power_pmu_enable(). We need to hard | |
655 | * enable to actually prevent the PMU exception from firing. | |
656 | */ | |
657 | hard_irq_disable(); | |
658 | ||
659 | /* | |
660 | * This is a bit gross, but we know we're on POWER8E and have 6 PMCs. | |
661 | * Using read/write_pmc() in a for loop adds 12 function calls and | |
662 | * almost doubles our code size. | |
663 | */ | |
664 | pmcs[0] = mfspr(SPRN_PMC1); | |
665 | pmcs[1] = mfspr(SPRN_PMC2); | |
666 | pmcs[2] = mfspr(SPRN_PMC3); | |
667 | pmcs[3] = mfspr(SPRN_PMC4); | |
668 | pmcs[4] = mfspr(SPRN_PMC5); | |
669 | pmcs[5] = mfspr(SPRN_PMC6); | |
670 | ||
671 | /* Ensure all freeze bits are unset */ | |
672 | mtspr(SPRN_MMCR2, 0); | |
673 | ||
674 | /* Set up PMC6 to overflow in one cycle */ | |
675 | mtspr(SPRN_PMC6, 0x7FFFFFFE); | |
676 | ||
677 | /* Enable exceptions and unfreeze PMC6 */ | |
678 | mtspr(SPRN_MMCR0, MMCR0_PMXE | MMCR0_PMCjCE | MMCR0_PMAO); | |
679 | ||
680 | /* Now we need to refreeze and restore the PMCs */ | |
681 | mtspr(SPRN_MMCR0, MMCR0_FC | MMCR0_PMAO); | |
682 | ||
683 | mtspr(SPRN_PMC1, pmcs[0]); | |
684 | mtspr(SPRN_PMC2, pmcs[1]); | |
685 | mtspr(SPRN_PMC3, pmcs[2]); | |
686 | mtspr(SPRN_PMC4, pmcs[3]); | |
687 | mtspr(SPRN_PMC5, pmcs[4]); | |
688 | mtspr(SPRN_PMC6, pmcs[5]); | |
689 | } | |
98fb1807 PM |
690 | #endif /* CONFIG_PPC64 */ |
691 | ||
cdd6c482 | 692 | static void perf_event_interrupt(struct pt_regs *regs); |
7595d63b | 693 | |
4574910e | 694 | /* |
57c0c15b | 695 | * Read one performance monitor counter (PMC). |
4574910e PM |
696 | */ |
697 | static unsigned long read_pmc(int idx) | |
698 | { | |
699 | unsigned long val; | |
700 | ||
701 | switch (idx) { | |
702 | case 1: | |
703 | val = mfspr(SPRN_PMC1); | |
704 | break; | |
705 | case 2: | |
706 | val = mfspr(SPRN_PMC2); | |
707 | break; | |
708 | case 3: | |
709 | val = mfspr(SPRN_PMC3); | |
710 | break; | |
711 | case 4: | |
712 | val = mfspr(SPRN_PMC4); | |
713 | break; | |
714 | case 5: | |
715 | val = mfspr(SPRN_PMC5); | |
716 | break; | |
717 | case 6: | |
718 | val = mfspr(SPRN_PMC6); | |
719 | break; | |
98fb1807 | 720 | #ifdef CONFIG_PPC64 |
4574910e PM |
721 | case 7: |
722 | val = mfspr(SPRN_PMC7); | |
723 | break; | |
724 | case 8: | |
725 | val = mfspr(SPRN_PMC8); | |
726 | break; | |
98fb1807 | 727 | #endif /* CONFIG_PPC64 */ |
4574910e PM |
728 | default: |
729 | printk(KERN_ERR "oops trying to read PMC%d\n", idx); | |
730 | val = 0; | |
731 | } | |
732 | return val; | |
733 | } | |
734 | ||
735 | /* | |
736 | * Write one PMC. | |
737 | */ | |
738 | static void write_pmc(int idx, unsigned long val) | |
739 | { | |
740 | switch (idx) { | |
741 | case 1: | |
742 | mtspr(SPRN_PMC1, val); | |
743 | break; | |
744 | case 2: | |
745 | mtspr(SPRN_PMC2, val); | |
746 | break; | |
747 | case 3: | |
748 | mtspr(SPRN_PMC3, val); | |
749 | break; | |
750 | case 4: | |
751 | mtspr(SPRN_PMC4, val); | |
752 | break; | |
753 | case 5: | |
754 | mtspr(SPRN_PMC5, val); | |
755 | break; | |
756 | case 6: | |
757 | mtspr(SPRN_PMC6, val); | |
758 | break; | |
98fb1807 | 759 | #ifdef CONFIG_PPC64 |
4574910e PM |
760 | case 7: |
761 | mtspr(SPRN_PMC7, val); | |
762 | break; | |
763 | case 8: | |
764 | mtspr(SPRN_PMC8, val); | |
765 | break; | |
98fb1807 | 766 | #endif /* CONFIG_PPC64 */ |
4574910e PM |
767 | default: |
768 | printk(KERN_ERR "oops trying to write PMC%d\n", idx); | |
769 | } | |
770 | } | |
771 | ||
5f6d0380 AK |
772 | /* Called from sysrq_handle_showregs() */ |
773 | void perf_event_print_debug(void) | |
774 | { | |
775 | unsigned long sdar, sier, flags; | |
776 | u32 pmcs[MAX_HWEVENTS]; | |
777 | int i; | |
778 | ||
779 | if (!ppmu->n_counter) | |
780 | return; | |
781 | ||
782 | local_irq_save(flags); | |
783 | ||
784 | pr_info("CPU: %d PMU registers, ppmu = %s n_counters = %d", | |
785 | smp_processor_id(), ppmu->name, ppmu->n_counter); | |
786 | ||
787 | for (i = 0; i < ppmu->n_counter; i++) | |
788 | pmcs[i] = read_pmc(i + 1); | |
789 | ||
790 | for (; i < MAX_HWEVENTS; i++) | |
791 | pmcs[i] = 0xdeadbeef; | |
792 | ||
793 | pr_info("PMC1: %08x PMC2: %08x PMC3: %08x PMC4: %08x\n", | |
794 | pmcs[0], pmcs[1], pmcs[2], pmcs[3]); | |
795 | ||
796 | if (ppmu->n_counter > 4) | |
797 | pr_info("PMC5: %08x PMC6: %08x PMC7: %08x PMC8: %08x\n", | |
798 | pmcs[4], pmcs[5], pmcs[6], pmcs[7]); | |
799 | ||
800 | pr_info("MMCR0: %016lx MMCR1: %016lx MMCRA: %016lx\n", | |
801 | mfspr(SPRN_MMCR0), mfspr(SPRN_MMCR1), mfspr(SPRN_MMCRA)); | |
802 | ||
803 | sdar = sier = 0; | |
804 | #ifdef CONFIG_PPC64 | |
805 | sdar = mfspr(SPRN_SDAR); | |
806 | ||
807 | if (ppmu->flags & PPMU_HAS_SIER) | |
808 | sier = mfspr(SPRN_SIER); | |
809 | ||
4d9690dd | 810 | if (ppmu->flags & PPMU_ARCH_207S) { |
5f6d0380 AK |
811 | pr_info("MMCR2: %016lx EBBHR: %016lx\n", |
812 | mfspr(SPRN_MMCR2), mfspr(SPRN_EBBHR)); | |
813 | pr_info("EBBRR: %016lx BESCR: %016lx\n", | |
814 | mfspr(SPRN_EBBRR), mfspr(SPRN_BESCR)); | |
815 | } | |
816 | #endif | |
817 | pr_info("SIAR: %016lx SDAR: %016lx SIER: %016lx\n", | |
818 | mfspr(SPRN_SIAR), sdar, sier); | |
819 | ||
820 | local_irq_restore(flags); | |
821 | } | |
822 | ||
4574910e PM |
823 | /* |
824 | * Check if a set of events can all go on the PMU at once. | |
825 | * If they can't, this will look at alternative codes for the events | |
826 | * and see if any combination of alternative codes is feasible. | |
cdd6c482 | 827 | * The feasible set is returned in event_id[]. |
4574910e | 828 | */ |
cdd6c482 IM |
829 | static int power_check_constraints(struct cpu_hw_events *cpuhw, |
830 | u64 event_id[], unsigned int cflags[], | |
ab7ef2e5 | 831 | int n_ev) |
4574910e | 832 | { |
448d64f8 | 833 | unsigned long mask, value, nv; |
cdd6c482 IM |
834 | unsigned long smasks[MAX_HWEVENTS], svalues[MAX_HWEVENTS]; |
835 | int n_alt[MAX_HWEVENTS], choice[MAX_HWEVENTS]; | |
4574910e | 836 | int i, j; |
448d64f8 PM |
837 | unsigned long addf = ppmu->add_fields; |
838 | unsigned long tadd = ppmu->test_adder; | |
4574910e | 839 | |
a8f90e90 | 840 | if (n_ev > ppmu->n_counter) |
4574910e PM |
841 | return -1; |
842 | ||
843 | /* First see if the events will go on as-is */ | |
844 | for (i = 0; i < n_ev; ++i) { | |
ab7ef2e5 | 845 | if ((cflags[i] & PPMU_LIMITED_PMC_REQD) |
cdd6c482 IM |
846 | && !ppmu->limited_pmc_event(event_id[i])) { |
847 | ppmu->get_alternatives(event_id[i], cflags[i], | |
e51ee31e | 848 | cpuhw->alternatives[i]); |
cdd6c482 | 849 | event_id[i] = cpuhw->alternatives[i][0]; |
ab7ef2e5 | 850 | } |
cdd6c482 | 851 | if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0], |
e51ee31e | 852 | &cpuhw->avalues[i][0])) |
4574910e | 853 | return -1; |
4574910e PM |
854 | } |
855 | value = mask = 0; | |
856 | for (i = 0; i < n_ev; ++i) { | |
e51ee31e PM |
857 | nv = (value | cpuhw->avalues[i][0]) + |
858 | (value & cpuhw->avalues[i][0] & addf); | |
4574910e | 859 | if ((((nv + tadd) ^ value) & mask) != 0 || |
e51ee31e PM |
860 | (((nv + tadd) ^ cpuhw->avalues[i][0]) & |
861 | cpuhw->amasks[i][0]) != 0) | |
4574910e PM |
862 | break; |
863 | value = nv; | |
e51ee31e | 864 | mask |= cpuhw->amasks[i][0]; |
4574910e PM |
865 | } |
866 | if (i == n_ev) | |
867 | return 0; /* all OK */ | |
868 | ||
869 | /* doesn't work, gather alternatives... */ | |
870 | if (!ppmu->get_alternatives) | |
871 | return -1; | |
872 | for (i = 0; i < n_ev; ++i) { | |
ab7ef2e5 | 873 | choice[i] = 0; |
cdd6c482 | 874 | n_alt[i] = ppmu->get_alternatives(event_id[i], cflags[i], |
e51ee31e | 875 | cpuhw->alternatives[i]); |
4574910e | 876 | for (j = 1; j < n_alt[i]; ++j) |
e51ee31e PM |
877 | ppmu->get_constraint(cpuhw->alternatives[i][j], |
878 | &cpuhw->amasks[i][j], | |
879 | &cpuhw->avalues[i][j]); | |
4574910e PM |
880 | } |
881 | ||
882 | /* enumerate all possibilities and see if any will work */ | |
883 | i = 0; | |
884 | j = -1; | |
885 | value = mask = nv = 0; | |
886 | while (i < n_ev) { | |
887 | if (j >= 0) { | |
888 | /* we're backtracking, restore context */ | |
889 | value = svalues[i]; | |
890 | mask = smasks[i]; | |
891 | j = choice[i]; | |
892 | } | |
893 | /* | |
cdd6c482 | 894 | * See if any alternative k for event_id i, |
4574910e PM |
895 | * where k > j, will satisfy the constraints. |
896 | */ | |
897 | while (++j < n_alt[i]) { | |
e51ee31e PM |
898 | nv = (value | cpuhw->avalues[i][j]) + |
899 | (value & cpuhw->avalues[i][j] & addf); | |
4574910e | 900 | if ((((nv + tadd) ^ value) & mask) == 0 && |
e51ee31e PM |
901 | (((nv + tadd) ^ cpuhw->avalues[i][j]) |
902 | & cpuhw->amasks[i][j]) == 0) | |
4574910e PM |
903 | break; |
904 | } | |
905 | if (j >= n_alt[i]) { | |
906 | /* | |
907 | * No feasible alternative, backtrack | |
cdd6c482 | 908 | * to event_id i-1 and continue enumerating its |
4574910e PM |
909 | * alternatives from where we got up to. |
910 | */ | |
911 | if (--i < 0) | |
912 | return -1; | |
913 | } else { | |
914 | /* | |
cdd6c482 IM |
915 | * Found a feasible alternative for event_id i, |
916 | * remember where we got up to with this event_id, | |
917 | * go on to the next event_id, and start with | |
4574910e PM |
918 | * the first alternative for it. |
919 | */ | |
920 | choice[i] = j; | |
921 | svalues[i] = value; | |
922 | smasks[i] = mask; | |
923 | value = nv; | |
e51ee31e | 924 | mask |= cpuhw->amasks[i][j]; |
4574910e PM |
925 | ++i; |
926 | j = -1; | |
927 | } | |
928 | } | |
929 | ||
930 | /* OK, we have a feasible combination, tell the caller the solution */ | |
931 | for (i = 0; i < n_ev; ++i) | |
cdd6c482 | 932 | event_id[i] = cpuhw->alternatives[i][choice[i]]; |
4574910e PM |
933 | return 0; |
934 | } | |
935 | ||
0475f9ea | 936 | /* |
cdd6c482 | 937 | * Check if newly-added events have consistent settings for |
0475f9ea | 938 | * exclude_{user,kernel,hv} with each other and any previously |
cdd6c482 | 939 | * added events. |
0475f9ea | 940 | */ |
cdd6c482 | 941 | static int check_excludes(struct perf_event **ctrs, unsigned int cflags[], |
ab7ef2e5 | 942 | int n_prev, int n_new) |
0475f9ea | 943 | { |
ab7ef2e5 PM |
944 | int eu = 0, ek = 0, eh = 0; |
945 | int i, n, first; | |
cdd6c482 | 946 | struct perf_event *event; |
0475f9ea | 947 | |
9de5cb0f ME |
948 | /* |
949 | * If the PMU we're on supports per event exclude settings then we | |
950 | * don't need to do any of this logic. NB. This assumes no PMU has both | |
951 | * per event exclude and limited PMCs. | |
952 | */ | |
953 | if (ppmu->flags & PPMU_ARCH_207S) | |
954 | return 0; | |
955 | ||
0475f9ea PM |
956 | n = n_prev + n_new; |
957 | if (n <= 1) | |
958 | return 0; | |
959 | ||
ab7ef2e5 PM |
960 | first = 1; |
961 | for (i = 0; i < n; ++i) { | |
962 | if (cflags[i] & PPMU_LIMITED_PMC_OK) { | |
963 | cflags[i] &= ~PPMU_LIMITED_PMC_REQD; | |
964 | continue; | |
965 | } | |
cdd6c482 | 966 | event = ctrs[i]; |
ab7ef2e5 | 967 | if (first) { |
cdd6c482 IM |
968 | eu = event->attr.exclude_user; |
969 | ek = event->attr.exclude_kernel; | |
970 | eh = event->attr.exclude_hv; | |
ab7ef2e5 | 971 | first = 0; |
cdd6c482 IM |
972 | } else if (event->attr.exclude_user != eu || |
973 | event->attr.exclude_kernel != ek || | |
974 | event->attr.exclude_hv != eh) { | |
0475f9ea | 975 | return -EAGAIN; |
ab7ef2e5 | 976 | } |
0475f9ea | 977 | } |
ab7ef2e5 PM |
978 | |
979 | if (eu || ek || eh) | |
980 | for (i = 0; i < n; ++i) | |
981 | if (cflags[i] & PPMU_LIMITED_PMC_OK) | |
982 | cflags[i] |= PPMU_LIMITED_PMC_REQD; | |
983 | ||
0475f9ea PM |
984 | return 0; |
985 | } | |
986 | ||
86c74ab3 EM |
987 | static u64 check_and_compute_delta(u64 prev, u64 val) |
988 | { | |
989 | u64 delta = (val - prev) & 0xfffffffful; | |
990 | ||
991 | /* | |
992 | * POWER7 can roll back counter values, if the new value is smaller | |
993 | * than the previous value it will cause the delta and the counter to | |
994 | * have bogus values unless we rolled a counter over. If a coutner is | |
995 | * rolled back, it will be smaller, but within 256, which is the maximum | |
996 | * number of events to rollback at once. If we dectect a rollback | |
997 | * return 0. This can lead to a small lack of precision in the | |
998 | * counters. | |
999 | */ | |
1000 | if (prev > val && (prev - val) < 256) | |
1001 | delta = 0; | |
1002 | ||
1003 | return delta; | |
1004 | } | |
1005 | ||
cdd6c482 | 1006 | static void power_pmu_read(struct perf_event *event) |
4574910e | 1007 | { |
98fb1807 | 1008 | s64 val, delta, prev; |
4574910e | 1009 | |
a4eaf7f1 PZ |
1010 | if (event->hw.state & PERF_HES_STOPPED) |
1011 | return; | |
1012 | ||
cdd6c482 | 1013 | if (!event->hw.idx) |
4574910e | 1014 | return; |
330a1eb7 ME |
1015 | |
1016 | if (is_ebb_event(event)) { | |
1017 | val = read_pmc(event->hw.idx); | |
1018 | local64_set(&event->hw.prev_count, val); | |
1019 | return; | |
1020 | } | |
1021 | ||
4574910e PM |
1022 | /* |
1023 | * Performance monitor interrupts come even when interrupts | |
1024 | * are soft-disabled, as long as interrupts are hard-enabled. | |
1025 | * Therefore we treat them like NMIs. | |
1026 | */ | |
1027 | do { | |
e7850595 | 1028 | prev = local64_read(&event->hw.prev_count); |
4574910e | 1029 | barrier(); |
cdd6c482 | 1030 | val = read_pmc(event->hw.idx); |
86c74ab3 EM |
1031 | delta = check_and_compute_delta(prev, val); |
1032 | if (!delta) | |
1033 | return; | |
e7850595 | 1034 | } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev); |
4574910e | 1035 | |
e7850595 | 1036 | local64_add(delta, &event->count); |
f5602941 AB |
1037 | |
1038 | /* | |
1039 | * A number of places program the PMC with (0x80000000 - period_left). | |
1040 | * We never want period_left to be less than 1 because we will program | |
1041 | * the PMC with a value >= 0x800000000 and an edge detected PMC will | |
1042 | * roll around to 0 before taking an exception. We have seen this | |
1043 | * on POWER8. | |
1044 | * | |
1045 | * To fix this, clamp the minimum value of period_left to 1. | |
1046 | */ | |
1047 | do { | |
1048 | prev = local64_read(&event->hw.period_left); | |
1049 | val = prev - delta; | |
1050 | if (val < 1) | |
1051 | val = 1; | |
1052 | } while (local64_cmpxchg(&event->hw.period_left, prev, val) != prev); | |
4574910e PM |
1053 | } |
1054 | ||
ab7ef2e5 PM |
1055 | /* |
1056 | * On some machines, PMC5 and PMC6 can't be written, don't respect | |
1057 | * the freeze conditions, and don't generate interrupts. This tells | |
cdd6c482 | 1058 | * us if `event' is using such a PMC. |
ab7ef2e5 PM |
1059 | */ |
1060 | static int is_limited_pmc(int pmcnum) | |
1061 | { | |
0bbd0d4b PM |
1062 | return (ppmu->flags & PPMU_LIMITED_PMC5_6) |
1063 | && (pmcnum == 5 || pmcnum == 6); | |
ab7ef2e5 PM |
1064 | } |
1065 | ||
a8f90e90 | 1066 | static void freeze_limited_counters(struct cpu_hw_events *cpuhw, |
ab7ef2e5 PM |
1067 | unsigned long pmc5, unsigned long pmc6) |
1068 | { | |
cdd6c482 | 1069 | struct perf_event *event; |
ab7ef2e5 PM |
1070 | u64 val, prev, delta; |
1071 | int i; | |
1072 | ||
1073 | for (i = 0; i < cpuhw->n_limited; ++i) { | |
a8f90e90 | 1074 | event = cpuhw->limited_counter[i]; |
cdd6c482 | 1075 | if (!event->hw.idx) |
ab7ef2e5 | 1076 | continue; |
cdd6c482 | 1077 | val = (event->hw.idx == 5) ? pmc5 : pmc6; |
e7850595 | 1078 | prev = local64_read(&event->hw.prev_count); |
cdd6c482 | 1079 | event->hw.idx = 0; |
86c74ab3 EM |
1080 | delta = check_and_compute_delta(prev, val); |
1081 | if (delta) | |
1082 | local64_add(delta, &event->count); | |
ab7ef2e5 PM |
1083 | } |
1084 | } | |
1085 | ||
a8f90e90 | 1086 | static void thaw_limited_counters(struct cpu_hw_events *cpuhw, |
ab7ef2e5 PM |
1087 | unsigned long pmc5, unsigned long pmc6) |
1088 | { | |
cdd6c482 | 1089 | struct perf_event *event; |
86c74ab3 | 1090 | u64 val, prev; |
ab7ef2e5 PM |
1091 | int i; |
1092 | ||
1093 | for (i = 0; i < cpuhw->n_limited; ++i) { | |
a8f90e90 | 1094 | event = cpuhw->limited_counter[i]; |
cdd6c482 IM |
1095 | event->hw.idx = cpuhw->limited_hwidx[i]; |
1096 | val = (event->hw.idx == 5) ? pmc5 : pmc6; | |
86c74ab3 EM |
1097 | prev = local64_read(&event->hw.prev_count); |
1098 | if (check_and_compute_delta(prev, val)) | |
1099 | local64_set(&event->hw.prev_count, val); | |
cdd6c482 | 1100 | perf_event_update_userpage(event); |
ab7ef2e5 PM |
1101 | } |
1102 | } | |
1103 | ||
1104 | /* | |
cdd6c482 | 1105 | * Since limited events don't respect the freeze conditions, we |
ab7ef2e5 | 1106 | * have to read them immediately after freezing or unfreezing the |
cdd6c482 IM |
1107 | * other events. We try to keep the values from the limited |
1108 | * events as consistent as possible by keeping the delay (in | |
ab7ef2e5 | 1109 | * cycles and instructions) between freezing/unfreezing and reading |
cdd6c482 IM |
1110 | * the limited events as small and consistent as possible. |
1111 | * Therefore, if any limited events are in use, we read them | |
ab7ef2e5 PM |
1112 | * both, and always in the same order, to minimize variability, |
1113 | * and do it inside the same asm that writes MMCR0. | |
1114 | */ | |
cdd6c482 | 1115 | static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0) |
ab7ef2e5 PM |
1116 | { |
1117 | unsigned long pmc5, pmc6; | |
1118 | ||
1119 | if (!cpuhw->n_limited) { | |
1120 | mtspr(SPRN_MMCR0, mmcr0); | |
1121 | return; | |
1122 | } | |
1123 | ||
1124 | /* | |
1125 | * Write MMCR0, then read PMC5 and PMC6 immediately. | |
dcd945e0 PM |
1126 | * To ensure we don't get a performance monitor interrupt |
1127 | * between writing MMCR0 and freezing/thawing the limited | |
cdd6c482 | 1128 | * events, we first write MMCR0 with the event overflow |
dcd945e0 | 1129 | * interrupt enable bits turned off. |
ab7ef2e5 PM |
1130 | */ |
1131 | asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5" | |
1132 | : "=&r" (pmc5), "=&r" (pmc6) | |
dcd945e0 PM |
1133 | : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)), |
1134 | "i" (SPRN_MMCR0), | |
ab7ef2e5 PM |
1135 | "i" (SPRN_PMC5), "i" (SPRN_PMC6)); |
1136 | ||
1137 | if (mmcr0 & MMCR0_FC) | |
a8f90e90 | 1138 | freeze_limited_counters(cpuhw, pmc5, pmc6); |
ab7ef2e5 | 1139 | else |
a8f90e90 | 1140 | thaw_limited_counters(cpuhw, pmc5, pmc6); |
dcd945e0 PM |
1141 | |
1142 | /* | |
cdd6c482 | 1143 | * Write the full MMCR0 including the event overflow interrupt |
dcd945e0 PM |
1144 | * enable bits, if necessary. |
1145 | */ | |
1146 | if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE)) | |
1147 | mtspr(SPRN_MMCR0, mmcr0); | |
ab7ef2e5 PM |
1148 | } |
1149 | ||
4574910e | 1150 | /* |
cdd6c482 IM |
1151 | * Disable all events to prevent PMU interrupts and to allow |
1152 | * events to be added or removed. | |
4574910e | 1153 | */ |
a4eaf7f1 | 1154 | static void power_pmu_disable(struct pmu *pmu) |
4574910e | 1155 | { |
cdd6c482 | 1156 | struct cpu_hw_events *cpuhw; |
330a1eb7 | 1157 | unsigned long flags, mmcr0, val; |
4574910e | 1158 | |
f36a1a13 PM |
1159 | if (!ppmu) |
1160 | return; | |
4574910e | 1161 | local_irq_save(flags); |
69111bac | 1162 | cpuhw = this_cpu_ptr(&cpu_hw_events); |
4574910e | 1163 | |
448d64f8 | 1164 | if (!cpuhw->disabled) { |
01d0287f PM |
1165 | /* |
1166 | * Check if we ever enabled the PMU on this cpu. | |
1167 | */ | |
1168 | if (!cpuhw->pmcs_enabled) { | |
a6dbf93a | 1169 | ppc_enable_pmcs(); |
01d0287f PM |
1170 | cpuhw->pmcs_enabled = 1; |
1171 | } | |
1172 | ||
378a6ee9 | 1173 | /* |
76cb8a78 | 1174 | * Set the 'freeze counters' bit, clear EBE/BHRBA/PMCC/PMAO/FC56 |
378a6ee9 | 1175 | */ |
330a1eb7 | 1176 | val = mmcr0 = mfspr(SPRN_MMCR0); |
378a6ee9 | 1177 | val |= MMCR0_FC; |
76cb8a78 ME |
1178 | val &= ~(MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC | MMCR0_PMAO | |
1179 | MMCR0_FC56); | |
378a6ee9 ME |
1180 | |
1181 | /* | |
1182 | * The barrier is to make sure the mtspr has been | |
1183 | * executed and the PMU has frozen the events etc. | |
1184 | * before we return. | |
1185 | */ | |
1186 | write_mmcr0(cpuhw, val); | |
1187 | mb(); | |
1188 | ||
f708223d PM |
1189 | /* |
1190 | * Disable instruction sampling if it was enabled | |
1191 | */ | |
1192 | if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { | |
1193 | mtspr(SPRN_MMCRA, | |
1194 | cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); | |
1195 | mb(); | |
1196 | } | |
1197 | ||
378a6ee9 ME |
1198 | cpuhw->disabled = 1; |
1199 | cpuhw->n_added = 0; | |
330a1eb7 ME |
1200 | |
1201 | ebb_switch_out(mmcr0); | |
4574910e | 1202 | } |
330a1eb7 | 1203 | |
4574910e | 1204 | local_irq_restore(flags); |
4574910e PM |
1205 | } |
1206 | ||
1207 | /* | |
cdd6c482 IM |
1208 | * Re-enable all events if disable == 0. |
1209 | * If we were previously disabled and events were added, then | |
4574910e PM |
1210 | * put the new config on the PMU. |
1211 | */ | |
a4eaf7f1 | 1212 | static void power_pmu_enable(struct pmu *pmu) |
4574910e | 1213 | { |
cdd6c482 IM |
1214 | struct perf_event *event; |
1215 | struct cpu_hw_events *cpuhw; | |
4574910e PM |
1216 | unsigned long flags; |
1217 | long i; | |
330a1eb7 | 1218 | unsigned long val, mmcr0; |
4574910e | 1219 | s64 left; |
cdd6c482 | 1220 | unsigned int hwc_index[MAX_HWEVENTS]; |
ab7ef2e5 PM |
1221 | int n_lim; |
1222 | int idx; | |
330a1eb7 | 1223 | bool ebb; |
4574910e | 1224 | |
f36a1a13 PM |
1225 | if (!ppmu) |
1226 | return; | |
4574910e | 1227 | local_irq_save(flags); |
0a48843d | 1228 | |
69111bac | 1229 | cpuhw = this_cpu_ptr(&cpu_hw_events); |
0a48843d ME |
1230 | if (!cpuhw->disabled) |
1231 | goto out; | |
1232 | ||
4ea355b5 ME |
1233 | if (cpuhw->n_events == 0) { |
1234 | ppc_set_pmu_inuse(0); | |
1235 | goto out; | |
1236 | } | |
1237 | ||
4574910e PM |
1238 | cpuhw->disabled = 0; |
1239 | ||
330a1eb7 ME |
1240 | /* |
1241 | * EBB requires an exclusive group and all events must have the EBB | |
1242 | * flag set, or not set, so we can just check a single event. Also we | |
1243 | * know we have at least one event. | |
1244 | */ | |
1245 | ebb = is_ebb_event(cpuhw->event[0]); | |
1246 | ||
4574910e | 1247 | /* |
cdd6c482 | 1248 | * If we didn't change anything, or only removed events, |
4574910e PM |
1249 | * no need to recalculate MMCR* settings and reset the PMCs. |
1250 | * Just reenable the PMU with the current MMCR* settings | |
cdd6c482 | 1251 | * (possibly updated for removal of events). |
4574910e PM |
1252 | */ |
1253 | if (!cpuhw->n_added) { | |
f708223d | 1254 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); |
4574910e | 1255 | mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); |
f708223d | 1256 | goto out_enable; |
4574910e PM |
1257 | } |
1258 | ||
1259 | /* | |
79a4cb28 | 1260 | * Clear all MMCR settings and recompute them for the new set of events. |
4574910e | 1261 | */ |
79a4cb28 ME |
1262 | memset(cpuhw->mmcr, 0, sizeof(cpuhw->mmcr)); |
1263 | ||
cdd6c482 | 1264 | if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index, |
8abd818f | 1265 | cpuhw->mmcr, cpuhw->event)) { |
4574910e PM |
1266 | /* shouldn't ever get here */ |
1267 | printk(KERN_ERR "oops compute_mmcr failed\n"); | |
1268 | goto out; | |
1269 | } | |
1270 | ||
9de5cb0f ME |
1271 | if (!(ppmu->flags & PPMU_ARCH_207S)) { |
1272 | /* | |
1273 | * Add in MMCR0 freeze bits corresponding to the attr.exclude_* | |
1274 | * bits for the first event. We have already checked that all | |
1275 | * events have the same value for these bits as the first event. | |
1276 | */ | |
1277 | event = cpuhw->event[0]; | |
1278 | if (event->attr.exclude_user) | |
1279 | cpuhw->mmcr[0] |= MMCR0_FCP; | |
1280 | if (event->attr.exclude_kernel) | |
1281 | cpuhw->mmcr[0] |= freeze_events_kernel; | |
1282 | if (event->attr.exclude_hv) | |
1283 | cpuhw->mmcr[0] |= MMCR0_FCHV; | |
1284 | } | |
0475f9ea | 1285 | |
4574910e PM |
1286 | /* |
1287 | * Write the new configuration to MMCR* with the freeze | |
cdd6c482 IM |
1288 | * bit set and set the hardware events to their initial values. |
1289 | * Then unfreeze the events. | |
4574910e | 1290 | */ |
a6dbf93a | 1291 | ppc_set_pmu_inuse(1); |
f708223d | 1292 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); |
4574910e PM |
1293 | mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); |
1294 | mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)) | |
1295 | | MMCR0_FC); | |
9de5cb0f ME |
1296 | if (ppmu->flags & PPMU_ARCH_207S) |
1297 | mtspr(SPRN_MMCR2, cpuhw->mmcr[3]); | |
4574910e PM |
1298 | |
1299 | /* | |
cdd6c482 | 1300 | * Read off any pre-existing events that need to move |
4574910e PM |
1301 | * to another PMC. |
1302 | */ | |
cdd6c482 IM |
1303 | for (i = 0; i < cpuhw->n_events; ++i) { |
1304 | event = cpuhw->event[i]; | |
1305 | if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) { | |
1306 | power_pmu_read(event); | |
1307 | write_pmc(event->hw.idx, 0); | |
1308 | event->hw.idx = 0; | |
4574910e PM |
1309 | } |
1310 | } | |
1311 | ||
1312 | /* | |
cdd6c482 | 1313 | * Initialize the PMCs for all the new and moved events. |
4574910e | 1314 | */ |
ab7ef2e5 | 1315 | cpuhw->n_limited = n_lim = 0; |
cdd6c482 IM |
1316 | for (i = 0; i < cpuhw->n_events; ++i) { |
1317 | event = cpuhw->event[i]; | |
1318 | if (event->hw.idx) | |
4574910e | 1319 | continue; |
ab7ef2e5 PM |
1320 | idx = hwc_index[i] + 1; |
1321 | if (is_limited_pmc(idx)) { | |
a8f90e90 | 1322 | cpuhw->limited_counter[n_lim] = event; |
ab7ef2e5 PM |
1323 | cpuhw->limited_hwidx[n_lim] = idx; |
1324 | ++n_lim; | |
1325 | continue; | |
1326 | } | |
330a1eb7 ME |
1327 | |
1328 | if (ebb) | |
1329 | val = local64_read(&event->hw.prev_count); | |
1330 | else { | |
1331 | val = 0; | |
1332 | if (event->hw.sample_period) { | |
1333 | left = local64_read(&event->hw.period_left); | |
1334 | if (left < 0x80000000L) | |
1335 | val = 0x80000000L - left; | |
1336 | } | |
1337 | local64_set(&event->hw.prev_count, val); | |
4574910e | 1338 | } |
330a1eb7 | 1339 | |
cdd6c482 | 1340 | event->hw.idx = idx; |
a4eaf7f1 PZ |
1341 | if (event->hw.state & PERF_HES_STOPPED) |
1342 | val = 0; | |
ab7ef2e5 | 1343 | write_pmc(idx, val); |
330a1eb7 | 1344 | |
cdd6c482 | 1345 | perf_event_update_userpage(event); |
4574910e | 1346 | } |
ab7ef2e5 | 1347 | cpuhw->n_limited = n_lim; |
4574910e | 1348 | cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE; |
f708223d PM |
1349 | |
1350 | out_enable: | |
c2e37a26 ME |
1351 | pmao_restore_workaround(ebb); |
1352 | ||
9de5cb0f | 1353 | mmcr0 = ebb_switch_in(ebb, cpuhw); |
330a1eb7 | 1354 | |
f708223d | 1355 | mb(); |
b4d6c06c AK |
1356 | if (cpuhw->bhrb_users) |
1357 | ppmu->config_bhrb(cpuhw->bhrb_filter); | |
1358 | ||
330a1eb7 | 1359 | write_mmcr0(cpuhw, mmcr0); |
4574910e | 1360 | |
f708223d PM |
1361 | /* |
1362 | * Enable instruction sampling if necessary | |
1363 | */ | |
1364 | if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { | |
1365 | mb(); | |
1366 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2]); | |
1367 | } | |
1368 | ||
4574910e | 1369 | out: |
3925f46b | 1370 | |
4574910e PM |
1371 | local_irq_restore(flags); |
1372 | } | |
1373 | ||
cdd6c482 IM |
1374 | static int collect_events(struct perf_event *group, int max_count, |
1375 | struct perf_event *ctrs[], u64 *events, | |
ab7ef2e5 | 1376 | unsigned int *flags) |
4574910e PM |
1377 | { |
1378 | int n = 0; | |
cdd6c482 | 1379 | struct perf_event *event; |
4574910e | 1380 | |
cdd6c482 | 1381 | if (!is_software_event(group)) { |
4574910e PM |
1382 | if (n >= max_count) |
1383 | return -1; | |
1384 | ctrs[n] = group; | |
cdd6c482 | 1385 | flags[n] = group->hw.event_base; |
4574910e PM |
1386 | events[n++] = group->hw.config; |
1387 | } | |
a8f90e90 | 1388 | list_for_each_entry(event, &group->sibling_list, group_entry) { |
cdd6c482 IM |
1389 | if (!is_software_event(event) && |
1390 | event->state != PERF_EVENT_STATE_OFF) { | |
4574910e PM |
1391 | if (n >= max_count) |
1392 | return -1; | |
cdd6c482 IM |
1393 | ctrs[n] = event; |
1394 | flags[n] = event->hw.event_base; | |
1395 | events[n++] = event->hw.config; | |
4574910e PM |
1396 | } |
1397 | } | |
1398 | return n; | |
1399 | } | |
1400 | ||
4574910e | 1401 | /* |
cdd6c482 IM |
1402 | * Add a event to the PMU. |
1403 | * If all events are not already frozen, then we disable and | |
9e35ad38 | 1404 | * re-enable the PMU in order to get hw_perf_enable to do the |
4574910e PM |
1405 | * actual work of reconfiguring the PMU. |
1406 | */ | |
a4eaf7f1 | 1407 | static int power_pmu_add(struct perf_event *event, int ef_flags) |
4574910e | 1408 | { |
cdd6c482 | 1409 | struct cpu_hw_events *cpuhw; |
4574910e | 1410 | unsigned long flags; |
4574910e PM |
1411 | int n0; |
1412 | int ret = -EAGAIN; | |
1413 | ||
1414 | local_irq_save(flags); | |
33696fc0 | 1415 | perf_pmu_disable(event->pmu); |
4574910e PM |
1416 | |
1417 | /* | |
cdd6c482 | 1418 | * Add the event to the list (if there is room) |
4574910e PM |
1419 | * and check whether the total set is still feasible. |
1420 | */ | |
69111bac | 1421 | cpuhw = this_cpu_ptr(&cpu_hw_events); |
cdd6c482 | 1422 | n0 = cpuhw->n_events; |
a8f90e90 | 1423 | if (n0 >= ppmu->n_counter) |
4574910e | 1424 | goto out; |
cdd6c482 IM |
1425 | cpuhw->event[n0] = event; |
1426 | cpuhw->events[n0] = event->hw.config; | |
1427 | cpuhw->flags[n0] = event->hw.event_base; | |
8e6d5573 | 1428 | |
f53d168c | 1429 | /* |
1430 | * This event may have been disabled/stopped in record_and_restart() | |
1431 | * because we exceeded the ->event_limit. If re-starting the event, | |
1432 | * clear the ->hw.state (STOPPED and UPTODATE flags), so the user | |
1433 | * notification is re-enabled. | |
1434 | */ | |
a4eaf7f1 PZ |
1435 | if (!(ef_flags & PERF_EF_START)) |
1436 | event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE; | |
f53d168c | 1437 | else |
1438 | event->hw.state = 0; | |
a4eaf7f1 | 1439 | |
8e6d5573 LM |
1440 | /* |
1441 | * If group events scheduling transaction was started, | |
25985edc | 1442 | * skip the schedulability test here, it will be performed |
8e6d5573 LM |
1443 | * at commit time(->commit_txn) as a whole |
1444 | */ | |
8d2cacbb | 1445 | if (cpuhw->group_flag & PERF_EVENT_TXN) |
8e6d5573 LM |
1446 | goto nocheck; |
1447 | ||
cdd6c482 | 1448 | if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1)) |
0475f9ea | 1449 | goto out; |
e51ee31e | 1450 | if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1)) |
4574910e | 1451 | goto out; |
cdd6c482 | 1452 | event->hw.config = cpuhw->events[n0]; |
8e6d5573 LM |
1453 | |
1454 | nocheck: | |
330a1eb7 ME |
1455 | ebb_event_add(event); |
1456 | ||
cdd6c482 | 1457 | ++cpuhw->n_events; |
4574910e PM |
1458 | ++cpuhw->n_added; |
1459 | ||
1460 | ret = 0; | |
1461 | out: | |
ff3d79dc | 1462 | if (has_branch_stack(event)) { |
3925f46b | 1463 | power_pmu_bhrb_enable(event); |
ff3d79dc AK |
1464 | cpuhw->bhrb_filter = ppmu->bhrb_filter_map( |
1465 | event->attr.branch_sample_type); | |
1466 | } | |
3925f46b | 1467 | |
33696fc0 | 1468 | perf_pmu_enable(event->pmu); |
4574910e PM |
1469 | local_irq_restore(flags); |
1470 | return ret; | |
1471 | } | |
1472 | ||
1473 | /* | |
cdd6c482 | 1474 | * Remove a event from the PMU. |
4574910e | 1475 | */ |
a4eaf7f1 | 1476 | static void power_pmu_del(struct perf_event *event, int ef_flags) |
4574910e | 1477 | { |
cdd6c482 | 1478 | struct cpu_hw_events *cpuhw; |
4574910e | 1479 | long i; |
4574910e PM |
1480 | unsigned long flags; |
1481 | ||
1482 | local_irq_save(flags); | |
33696fc0 | 1483 | perf_pmu_disable(event->pmu); |
4574910e | 1484 | |
cdd6c482 IM |
1485 | power_pmu_read(event); |
1486 | ||
69111bac | 1487 | cpuhw = this_cpu_ptr(&cpu_hw_events); |
cdd6c482 IM |
1488 | for (i = 0; i < cpuhw->n_events; ++i) { |
1489 | if (event == cpuhw->event[i]) { | |
219a92a4 | 1490 | while (++i < cpuhw->n_events) { |
cdd6c482 | 1491 | cpuhw->event[i-1] = cpuhw->event[i]; |
219a92a4 ME |
1492 | cpuhw->events[i-1] = cpuhw->events[i]; |
1493 | cpuhw->flags[i-1] = cpuhw->flags[i]; | |
1494 | } | |
cdd6c482 IM |
1495 | --cpuhw->n_events; |
1496 | ppmu->disable_pmc(event->hw.idx - 1, cpuhw->mmcr); | |
1497 | if (event->hw.idx) { | |
1498 | write_pmc(event->hw.idx, 0); | |
1499 | event->hw.idx = 0; | |
ab7ef2e5 | 1500 | } |
cdd6c482 | 1501 | perf_event_update_userpage(event); |
4574910e PM |
1502 | break; |
1503 | } | |
1504 | } | |
ab7ef2e5 | 1505 | for (i = 0; i < cpuhw->n_limited; ++i) |
a8f90e90 | 1506 | if (event == cpuhw->limited_counter[i]) |
ab7ef2e5 PM |
1507 | break; |
1508 | if (i < cpuhw->n_limited) { | |
1509 | while (++i < cpuhw->n_limited) { | |
a8f90e90 | 1510 | cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i]; |
ab7ef2e5 PM |
1511 | cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i]; |
1512 | } | |
1513 | --cpuhw->n_limited; | |
1514 | } | |
cdd6c482 IM |
1515 | if (cpuhw->n_events == 0) { |
1516 | /* disable exceptions if no events are running */ | |
4574910e PM |
1517 | cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE); |
1518 | } | |
1519 | ||
3925f46b AK |
1520 | if (has_branch_stack(event)) |
1521 | power_pmu_bhrb_disable(event); | |
1522 | ||
33696fc0 | 1523 | perf_pmu_enable(event->pmu); |
4574910e PM |
1524 | local_irq_restore(flags); |
1525 | } | |
1526 | ||
8a7b8cb9 | 1527 | /* |
a4eaf7f1 PZ |
1528 | * POWER-PMU does not support disabling individual counters, hence |
1529 | * program their cycle counter to their max value and ignore the interrupts. | |
8a7b8cb9 | 1530 | */ |
a4eaf7f1 PZ |
1531 | |
1532 | static void power_pmu_start(struct perf_event *event, int ef_flags) | |
8a7b8cb9 | 1533 | { |
8a7b8cb9 | 1534 | unsigned long flags; |
a4eaf7f1 | 1535 | s64 left; |
9a45a940 | 1536 | unsigned long val; |
8a7b8cb9 | 1537 | |
cdd6c482 | 1538 | if (!event->hw.idx || !event->hw.sample_period) |
8a7b8cb9 | 1539 | return; |
a4eaf7f1 PZ |
1540 | |
1541 | if (!(event->hw.state & PERF_HES_STOPPED)) | |
1542 | return; | |
1543 | ||
1544 | if (ef_flags & PERF_EF_RELOAD) | |
1545 | WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); | |
1546 | ||
1547 | local_irq_save(flags); | |
1548 | perf_pmu_disable(event->pmu); | |
1549 | ||
1550 | event->hw.state = 0; | |
1551 | left = local64_read(&event->hw.period_left); | |
9a45a940 AB |
1552 | |
1553 | val = 0; | |
1554 | if (left < 0x80000000L) | |
1555 | val = 0x80000000L - left; | |
1556 | ||
1557 | write_pmc(event->hw.idx, val); | |
a4eaf7f1 PZ |
1558 | |
1559 | perf_event_update_userpage(event); | |
1560 | perf_pmu_enable(event->pmu); | |
1561 | local_irq_restore(flags); | |
1562 | } | |
1563 | ||
1564 | static void power_pmu_stop(struct perf_event *event, int ef_flags) | |
1565 | { | |
1566 | unsigned long flags; | |
1567 | ||
1568 | if (!event->hw.idx || !event->hw.sample_period) | |
1569 | return; | |
1570 | ||
1571 | if (event->hw.state & PERF_HES_STOPPED) | |
1572 | return; | |
1573 | ||
8a7b8cb9 | 1574 | local_irq_save(flags); |
33696fc0 | 1575 | perf_pmu_disable(event->pmu); |
a4eaf7f1 | 1576 | |
cdd6c482 | 1577 | power_pmu_read(event); |
a4eaf7f1 PZ |
1578 | event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; |
1579 | write_pmc(event->hw.idx, 0); | |
1580 | ||
cdd6c482 | 1581 | perf_event_update_userpage(event); |
33696fc0 | 1582 | perf_pmu_enable(event->pmu); |
8a7b8cb9 PM |
1583 | local_irq_restore(flags); |
1584 | } | |
1585 | ||
8e6d5573 LM |
1586 | /* |
1587 | * Start group events scheduling transaction | |
1588 | * Set the flag to make pmu::enable() not perform the | |
1589 | * schedulability test, it will be performed at commit time | |
fbbe0701 SB |
1590 | * |
1591 | * We only support PERF_PMU_TXN_ADD transactions. Save the | |
1592 | * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD | |
1593 | * transactions. | |
8e6d5573 | 1594 | */ |
fbbe0701 | 1595 | static void power_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags) |
8e6d5573 | 1596 | { |
69111bac | 1597 | struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); |
8e6d5573 | 1598 | |
fbbe0701 SB |
1599 | WARN_ON_ONCE(cpuhw->txn_flags); /* txn already in flight */ |
1600 | ||
1601 | cpuhw->txn_flags = txn_flags; | |
1602 | if (txn_flags & ~PERF_PMU_TXN_ADD) | |
1603 | return; | |
1604 | ||
33696fc0 | 1605 | perf_pmu_disable(pmu); |
8d2cacbb | 1606 | cpuhw->group_flag |= PERF_EVENT_TXN; |
8e6d5573 LM |
1607 | cpuhw->n_txn_start = cpuhw->n_events; |
1608 | } | |
1609 | ||
1610 | /* | |
1611 | * Stop group events scheduling transaction | |
1612 | * Clear the flag and pmu::enable() will perform the | |
1613 | * schedulability test. | |
1614 | */ | |
e51df2c1 | 1615 | static void power_pmu_cancel_txn(struct pmu *pmu) |
8e6d5573 | 1616 | { |
69111bac | 1617 | struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); |
fbbe0701 SB |
1618 | unsigned int txn_flags; |
1619 | ||
1620 | WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */ | |
1621 | ||
1622 | txn_flags = cpuhw->txn_flags; | |
1623 | cpuhw->txn_flags = 0; | |
1624 | if (txn_flags & ~PERF_PMU_TXN_ADD) | |
1625 | return; | |
8e6d5573 | 1626 | |
8d2cacbb | 1627 | cpuhw->group_flag &= ~PERF_EVENT_TXN; |
33696fc0 | 1628 | perf_pmu_enable(pmu); |
8e6d5573 LM |
1629 | } |
1630 | ||
1631 | /* | |
1632 | * Commit group events scheduling transaction | |
1633 | * Perform the group schedulability test as a whole | |
1634 | * Return 0 if success | |
1635 | */ | |
e51df2c1 | 1636 | static int power_pmu_commit_txn(struct pmu *pmu) |
8e6d5573 LM |
1637 | { |
1638 | struct cpu_hw_events *cpuhw; | |
1639 | long i, n; | |
1640 | ||
1641 | if (!ppmu) | |
1642 | return -EAGAIN; | |
fbbe0701 | 1643 | |
69111bac | 1644 | cpuhw = this_cpu_ptr(&cpu_hw_events); |
fbbe0701 SB |
1645 | WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */ |
1646 | ||
1647 | if (cpuhw->txn_flags & ~PERF_PMU_TXN_ADD) { | |
1648 | cpuhw->txn_flags = 0; | |
1649 | return 0; | |
1650 | } | |
1651 | ||
8e6d5573 LM |
1652 | n = cpuhw->n_events; |
1653 | if (check_excludes(cpuhw->event, cpuhw->flags, 0, n)) | |
1654 | return -EAGAIN; | |
1655 | i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n); | |
1656 | if (i < 0) | |
1657 | return -EAGAIN; | |
1658 | ||
1659 | for (i = cpuhw->n_txn_start; i < n; ++i) | |
1660 | cpuhw->event[i]->hw.config = cpuhw->events[i]; | |
1661 | ||
8d2cacbb | 1662 | cpuhw->group_flag &= ~PERF_EVENT_TXN; |
fbbe0701 | 1663 | cpuhw->txn_flags = 0; |
33696fc0 | 1664 | perf_pmu_enable(pmu); |
8e6d5573 LM |
1665 | return 0; |
1666 | } | |
1667 | ||
ab7ef2e5 | 1668 | /* |
cdd6c482 | 1669 | * Return 1 if we might be able to put event on a limited PMC, |
ab7ef2e5 | 1670 | * or 0 if not. |
cdd6c482 | 1671 | * A event can only go on a limited PMC if it counts something |
ab7ef2e5 PM |
1672 | * that a limited PMC can count, doesn't require interrupts, and |
1673 | * doesn't exclude any processor mode. | |
1674 | */ | |
cdd6c482 | 1675 | static int can_go_on_limited_pmc(struct perf_event *event, u64 ev, |
ab7ef2e5 PM |
1676 | unsigned int flags) |
1677 | { | |
1678 | int n; | |
ef923214 | 1679 | u64 alt[MAX_EVENT_ALTERNATIVES]; |
ab7ef2e5 | 1680 | |
cdd6c482 IM |
1681 | if (event->attr.exclude_user |
1682 | || event->attr.exclude_kernel | |
1683 | || event->attr.exclude_hv | |
1684 | || event->attr.sample_period) | |
ab7ef2e5 PM |
1685 | return 0; |
1686 | ||
1687 | if (ppmu->limited_pmc_event(ev)) | |
1688 | return 1; | |
1689 | ||
1690 | /* | |
cdd6c482 | 1691 | * The requested event_id isn't on a limited PMC already; |
ab7ef2e5 PM |
1692 | * see if any alternative code goes on a limited PMC. |
1693 | */ | |
1694 | if (!ppmu->get_alternatives) | |
1695 | return 0; | |
1696 | ||
1697 | flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD; | |
1698 | n = ppmu->get_alternatives(ev, flags, alt); | |
ab7ef2e5 | 1699 | |
ef923214 | 1700 | return n > 0; |
ab7ef2e5 PM |
1701 | } |
1702 | ||
1703 | /* | |
cdd6c482 IM |
1704 | * Find an alternative event_id that goes on a normal PMC, if possible, |
1705 | * and return the event_id code, or 0 if there is no such alternative. | |
1706 | * (Note: event_id code 0 is "don't count" on all machines.) | |
ab7ef2e5 | 1707 | */ |
ef923214 | 1708 | static u64 normal_pmc_alternative(u64 ev, unsigned long flags) |
ab7ef2e5 | 1709 | { |
ef923214 | 1710 | u64 alt[MAX_EVENT_ALTERNATIVES]; |
ab7ef2e5 PM |
1711 | int n; |
1712 | ||
1713 | flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD); | |
1714 | n = ppmu->get_alternatives(ev, flags, alt); | |
1715 | if (!n) | |
1716 | return 0; | |
1717 | return alt[0]; | |
1718 | } | |
1719 | ||
cdd6c482 IM |
1720 | /* Number of perf_events counting hardware events */ |
1721 | static atomic_t num_events; | |
7595d63b PM |
1722 | /* Used to avoid races in calling reserve/release_pmc_hardware */ |
1723 | static DEFINE_MUTEX(pmc_reserve_mutex); | |
1724 | ||
1725 | /* | |
cdd6c482 | 1726 | * Release the PMU if this is the last perf_event. |
7595d63b | 1727 | */ |
cdd6c482 | 1728 | static void hw_perf_event_destroy(struct perf_event *event) |
7595d63b | 1729 | { |
cdd6c482 | 1730 | if (!atomic_add_unless(&num_events, -1, 1)) { |
7595d63b | 1731 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 | 1732 | if (atomic_dec_return(&num_events) == 0) |
7595d63b PM |
1733 | release_pmc_hardware(); |
1734 | mutex_unlock(&pmc_reserve_mutex); | |
1735 | } | |
1736 | } | |
1737 | ||
106b506c | 1738 | /* |
cdd6c482 | 1739 | * Translate a generic cache event_id config to a raw event_id code. |
106b506c PM |
1740 | */ |
1741 | static int hw_perf_cache_event(u64 config, u64 *eventp) | |
1742 | { | |
1743 | unsigned long type, op, result; | |
1744 | int ev; | |
1745 | ||
1746 | if (!ppmu->cache_events) | |
1747 | return -EINVAL; | |
1748 | ||
1749 | /* unpack config */ | |
1750 | type = config & 0xff; | |
1751 | op = (config >> 8) & 0xff; | |
1752 | result = (config >> 16) & 0xff; | |
1753 | ||
1754 | if (type >= PERF_COUNT_HW_CACHE_MAX || | |
1755 | op >= PERF_COUNT_HW_CACHE_OP_MAX || | |
1756 | result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
1757 | return -EINVAL; | |
1758 | ||
1759 | ev = (*ppmu->cache_events)[type][op][result]; | |
1760 | if (ev == 0) | |
1761 | return -EOPNOTSUPP; | |
1762 | if (ev == -1) | |
1763 | return -EINVAL; | |
1764 | *eventp = ev; | |
1765 | return 0; | |
1766 | } | |
1767 | ||
b0a873eb | 1768 | static int power_pmu_event_init(struct perf_event *event) |
4574910e | 1769 | { |
ef923214 PM |
1770 | u64 ev; |
1771 | unsigned long flags; | |
cdd6c482 IM |
1772 | struct perf_event *ctrs[MAX_HWEVENTS]; |
1773 | u64 events[MAX_HWEVENTS]; | |
1774 | unsigned int cflags[MAX_HWEVENTS]; | |
4574910e | 1775 | int n; |
7595d63b | 1776 | int err; |
cdd6c482 | 1777 | struct cpu_hw_events *cpuhw; |
4574910e PM |
1778 | |
1779 | if (!ppmu) | |
b0a873eb PZ |
1780 | return -ENOENT; |
1781 | ||
3925f46b AK |
1782 | if (has_branch_stack(event)) { |
1783 | /* PMU has BHRB enabled */ | |
4d9690dd | 1784 | if (!(ppmu->flags & PPMU_ARCH_207S)) |
3925f46b AK |
1785 | return -EOPNOTSUPP; |
1786 | } | |
2481c5fa | 1787 | |
cdd6c482 | 1788 | switch (event->attr.type) { |
106b506c | 1789 | case PERF_TYPE_HARDWARE: |
cdd6c482 | 1790 | ev = event->attr.config; |
9aaa131a | 1791 | if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0) |
b0a873eb | 1792 | return -EOPNOTSUPP; |
4574910e | 1793 | ev = ppmu->generic_events[ev]; |
106b506c PM |
1794 | break; |
1795 | case PERF_TYPE_HW_CACHE: | |
cdd6c482 | 1796 | err = hw_perf_cache_event(event->attr.config, &ev); |
106b506c | 1797 | if (err) |
b0a873eb | 1798 | return err; |
106b506c PM |
1799 | break; |
1800 | case PERF_TYPE_RAW: | |
cdd6c482 | 1801 | ev = event->attr.config; |
106b506c | 1802 | break; |
90c8f954 | 1803 | default: |
b0a873eb | 1804 | return -ENOENT; |
4574910e | 1805 | } |
b0a873eb | 1806 | |
cdd6c482 IM |
1807 | event->hw.config_base = ev; |
1808 | event->hw.idx = 0; | |
4574910e | 1809 | |
0475f9ea PM |
1810 | /* |
1811 | * If we are not running on a hypervisor, force the | |
1812 | * exclude_hv bit to 0 so that we don't care what | |
d095cd46 | 1813 | * the user set it to. |
0475f9ea PM |
1814 | */ |
1815 | if (!firmware_has_feature(FW_FEATURE_LPAR)) | |
cdd6c482 | 1816 | event->attr.exclude_hv = 0; |
ab7ef2e5 PM |
1817 | |
1818 | /* | |
cdd6c482 | 1819 | * If this is a per-task event, then we can use |
ab7ef2e5 PM |
1820 | * PM_RUN_* events interchangeably with their non RUN_* |
1821 | * equivalents, e.g. PM_RUN_CYC instead of PM_CYC. | |
1822 | * XXX we should check if the task is an idle task. | |
1823 | */ | |
1824 | flags = 0; | |
57fa7214 | 1825 | if (event->attach_state & PERF_ATTACH_TASK) |
ab7ef2e5 PM |
1826 | flags |= PPMU_ONLY_COUNT_RUN; |
1827 | ||
1828 | /* | |
cdd6c482 IM |
1829 | * If this machine has limited events, check whether this |
1830 | * event_id could go on a limited event. | |
ab7ef2e5 | 1831 | */ |
0bbd0d4b | 1832 | if (ppmu->flags & PPMU_LIMITED_PMC5_6) { |
cdd6c482 | 1833 | if (can_go_on_limited_pmc(event, ev, flags)) { |
ab7ef2e5 PM |
1834 | flags |= PPMU_LIMITED_PMC_OK; |
1835 | } else if (ppmu->limited_pmc_event(ev)) { | |
1836 | /* | |
cdd6c482 | 1837 | * The requested event_id is on a limited PMC, |
ab7ef2e5 PM |
1838 | * but we can't use a limited PMC; see if any |
1839 | * alternative goes on a normal PMC. | |
1840 | */ | |
1841 | ev = normal_pmc_alternative(ev, flags); | |
1842 | if (!ev) | |
b0a873eb | 1843 | return -EINVAL; |
ab7ef2e5 PM |
1844 | } |
1845 | } | |
1846 | ||
330a1eb7 ME |
1847 | /* Extra checks for EBB */ |
1848 | err = ebb_event_check(event); | |
1849 | if (err) | |
1850 | return err; | |
1851 | ||
4574910e PM |
1852 | /* |
1853 | * If this is in a group, check if it can go on with all the | |
cdd6c482 | 1854 | * other hardware events in the group. We assume the event |
4574910e PM |
1855 | * hasn't been linked into its leader's sibling list at this point. |
1856 | */ | |
1857 | n = 0; | |
cdd6c482 | 1858 | if (event->group_leader != event) { |
a8f90e90 | 1859 | n = collect_events(event->group_leader, ppmu->n_counter - 1, |
ab7ef2e5 | 1860 | ctrs, events, cflags); |
4574910e | 1861 | if (n < 0) |
b0a873eb | 1862 | return -EINVAL; |
4574910e | 1863 | } |
0475f9ea | 1864 | events[n] = ev; |
cdd6c482 | 1865 | ctrs[n] = event; |
ab7ef2e5 PM |
1866 | cflags[n] = flags; |
1867 | if (check_excludes(ctrs, cflags, n, 1)) | |
b0a873eb | 1868 | return -EINVAL; |
e51ee31e | 1869 | |
cdd6c482 | 1870 | cpuhw = &get_cpu_var(cpu_hw_events); |
e51ee31e | 1871 | err = power_check_constraints(cpuhw, events, cflags, n + 1); |
3925f46b AK |
1872 | |
1873 | if (has_branch_stack(event)) { | |
1874 | cpuhw->bhrb_filter = ppmu->bhrb_filter_map( | |
1875 | event->attr.branch_sample_type); | |
1876 | ||
68de8867 JS |
1877 | if (cpuhw->bhrb_filter == -1) { |
1878 | put_cpu_var(cpu_hw_events); | |
3925f46b | 1879 | return -EOPNOTSUPP; |
68de8867 | 1880 | } |
3925f46b AK |
1881 | } |
1882 | ||
cdd6c482 | 1883 | put_cpu_var(cpu_hw_events); |
e51ee31e | 1884 | if (err) |
b0a873eb | 1885 | return -EINVAL; |
4574910e | 1886 | |
cdd6c482 IM |
1887 | event->hw.config = events[n]; |
1888 | event->hw.event_base = cflags[n]; | |
1889 | event->hw.last_period = event->hw.sample_period; | |
e7850595 | 1890 | local64_set(&event->hw.period_left, event->hw.last_period); |
7595d63b | 1891 | |
330a1eb7 ME |
1892 | /* |
1893 | * For EBB events we just context switch the PMC value, we don't do any | |
1894 | * of the sample_period logic. We use hw.prev_count for this. | |
1895 | */ | |
1896 | if (is_ebb_event(event)) | |
1897 | local64_set(&event->hw.prev_count, 0); | |
1898 | ||
7595d63b PM |
1899 | /* |
1900 | * See if we need to reserve the PMU. | |
cdd6c482 | 1901 | * If no events are currently in use, then we have to take a |
7595d63b PM |
1902 | * mutex to ensure that we don't race with another task doing |
1903 | * reserve_pmc_hardware or release_pmc_hardware. | |
1904 | */ | |
1905 | err = 0; | |
cdd6c482 | 1906 | if (!atomic_inc_not_zero(&num_events)) { |
7595d63b | 1907 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 IM |
1908 | if (atomic_read(&num_events) == 0 && |
1909 | reserve_pmc_hardware(perf_event_interrupt)) | |
7595d63b PM |
1910 | err = -EBUSY; |
1911 | else | |
cdd6c482 | 1912 | atomic_inc(&num_events); |
7595d63b PM |
1913 | mutex_unlock(&pmc_reserve_mutex); |
1914 | } | |
cdd6c482 | 1915 | event->destroy = hw_perf_event_destroy; |
7595d63b | 1916 | |
b0a873eb | 1917 | return err; |
4574910e PM |
1918 | } |
1919 | ||
35edc2a5 PZ |
1920 | static int power_pmu_event_idx(struct perf_event *event) |
1921 | { | |
1922 | return event->hw.idx; | |
1923 | } | |
1924 | ||
1c53a270 SB |
1925 | ssize_t power_events_sysfs_show(struct device *dev, |
1926 | struct device_attribute *attr, char *page) | |
1927 | { | |
1928 | struct perf_pmu_events_attr *pmu_attr; | |
1929 | ||
1930 | pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr); | |
1931 | ||
1932 | return sprintf(page, "event=0x%02llx\n", pmu_attr->id); | |
1933 | } | |
1934 | ||
e51df2c1 | 1935 | static struct pmu power_pmu = { |
a4eaf7f1 PZ |
1936 | .pmu_enable = power_pmu_enable, |
1937 | .pmu_disable = power_pmu_disable, | |
b0a873eb | 1938 | .event_init = power_pmu_event_init, |
a4eaf7f1 PZ |
1939 | .add = power_pmu_add, |
1940 | .del = power_pmu_del, | |
1941 | .start = power_pmu_start, | |
1942 | .stop = power_pmu_stop, | |
b0a873eb | 1943 | .read = power_pmu_read, |
b0a873eb PZ |
1944 | .start_txn = power_pmu_start_txn, |
1945 | .cancel_txn = power_pmu_cancel_txn, | |
1946 | .commit_txn = power_pmu_commit_txn, | |
35edc2a5 | 1947 | .event_idx = power_pmu_event_idx, |
acba3c7e | 1948 | .sched_task = power_pmu_sched_task, |
b0a873eb PZ |
1949 | }; |
1950 | ||
4574910e | 1951 | /* |
57c0c15b | 1952 | * A counter has overflowed; update its count and record |
4574910e PM |
1953 | * things if requested. Note that interrupts are hard-disabled |
1954 | * here so there is no possibility of being interrupted. | |
1955 | */ | |
cdd6c482 | 1956 | static void record_and_restart(struct perf_event *event, unsigned long val, |
a8b0ca17 | 1957 | struct pt_regs *regs) |
4574910e | 1958 | { |
cdd6c482 | 1959 | u64 period = event->hw.sample_period; |
4574910e PM |
1960 | s64 prev, delta, left; |
1961 | int record = 0; | |
1962 | ||
a4eaf7f1 PZ |
1963 | if (event->hw.state & PERF_HES_STOPPED) { |
1964 | write_pmc(event->hw.idx, 0); | |
1965 | return; | |
1966 | } | |
1967 | ||
4574910e | 1968 | /* we don't have to worry about interrupts here */ |
e7850595 | 1969 | prev = local64_read(&event->hw.prev_count); |
86c74ab3 | 1970 | delta = check_and_compute_delta(prev, val); |
e7850595 | 1971 | local64_add(delta, &event->count); |
4574910e PM |
1972 | |
1973 | /* | |
cdd6c482 | 1974 | * See if the total period for this event has expired, |
4574910e PM |
1975 | * and update for the next period. |
1976 | */ | |
1977 | val = 0; | |
e7850595 | 1978 | left = local64_read(&event->hw.period_left) - delta; |
e13e895f MN |
1979 | if (delta == 0) |
1980 | left++; | |
60db5e09 | 1981 | if (period) { |
4574910e | 1982 | if (left <= 0) { |
60db5e09 | 1983 | left += period; |
4574910e | 1984 | if (left <= 0) |
60db5e09 | 1985 | left = period; |
e6878835 | 1986 | record = siar_valid(regs); |
4bca770e | 1987 | event->hw.last_period = event->hw.sample_period; |
4574910e | 1988 | } |
98fb1807 PM |
1989 | if (left < 0x80000000LL) |
1990 | val = 0x80000000LL - left; | |
4574910e | 1991 | } |
4574910e | 1992 | |
a4eaf7f1 PZ |
1993 | write_pmc(event->hw.idx, val); |
1994 | local64_set(&event->hw.prev_count, val); | |
1995 | local64_set(&event->hw.period_left, left); | |
1996 | perf_event_update_userpage(event); | |
1997 | ||
4574910e PM |
1998 | /* |
1999 | * Finally record data if requested. | |
2000 | */ | |
0bbd0d4b | 2001 | if (record) { |
dc1d628a PZ |
2002 | struct perf_sample_data data; |
2003 | ||
fd0d000b | 2004 | perf_sample_data_init(&data, ~0ULL, event->hw.last_period); |
df1a132b | 2005 | |
cdd6c482 | 2006 | if (event->attr.sample_type & PERF_SAMPLE_ADDR) |
98fb1807 PM |
2007 | perf_get_data_addr(regs, &data.addr); |
2008 | ||
3925f46b AK |
2009 | if (event->attr.sample_type & PERF_SAMPLE_BRANCH_STACK) { |
2010 | struct cpu_hw_events *cpuhw; | |
69111bac | 2011 | cpuhw = this_cpu_ptr(&cpu_hw_events); |
3925f46b AK |
2012 | power_pmu_bhrb_read(cpuhw); |
2013 | data.br_stack = &cpuhw->bhrb_stack; | |
2014 | } | |
2015 | ||
a8b0ca17 | 2016 | if (perf_event_overflow(event, &data, regs)) |
a4eaf7f1 | 2017 | power_pmu_stop(event, 0); |
0bbd0d4b PM |
2018 | } |
2019 | } | |
2020 | ||
2021 | /* | |
2022 | * Called from generic code to get the misc flags (i.e. processor mode) | |
cdd6c482 | 2023 | * for an event_id. |
0bbd0d4b PM |
2024 | */ |
2025 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
2026 | { | |
98fb1807 | 2027 | u32 flags = perf_get_misc_flags(regs); |
0bbd0d4b | 2028 | |
98fb1807 PM |
2029 | if (flags) |
2030 | return flags; | |
cdd6c482 IM |
2031 | return user_mode(regs) ? PERF_RECORD_MISC_USER : |
2032 | PERF_RECORD_MISC_KERNEL; | |
0bbd0d4b PM |
2033 | } |
2034 | ||
2035 | /* | |
2036 | * Called from generic code to get the instruction pointer | |
cdd6c482 | 2037 | * for an event_id. |
0bbd0d4b PM |
2038 | */ |
2039 | unsigned long perf_instruction_pointer(struct pt_regs *regs) | |
2040 | { | |
33904054 | 2041 | bool use_siar = regs_use_siar(regs); |
0bbd0d4b | 2042 | |
e6878835 | 2043 | if (use_siar && siar_valid(regs)) |
75382aa7 | 2044 | return mfspr(SPRN_SIAR) + perf_ip_adjust(regs); |
e6878835 | 2045 | else if (use_siar) |
2046 | return 0; // no valid instruction pointer | |
75382aa7 | 2047 | else |
1ce447b9 | 2048 | return regs->nip; |
4574910e PM |
2049 | } |
2050 | ||
bc09c219 | 2051 | static bool pmc_overflow_power7(unsigned long val) |
0837e324 | 2052 | { |
0837e324 AB |
2053 | /* |
2054 | * Events on POWER7 can roll back if a speculative event doesn't | |
2055 | * eventually complete. Unfortunately in some rare cases they will | |
2056 | * raise a performance monitor exception. We need to catch this to | |
2057 | * ensure we reset the PMC. In all cases the PMC will be 256 or less | |
2058 | * cycles from overflow. | |
2059 | * | |
2060 | * We only do this if the first pass fails to find any overflowing | |
2061 | * PMCs because a user might set a period of less than 256 and we | |
2062 | * don't want to mistakenly reset them. | |
2063 | */ | |
bc09c219 MN |
2064 | if ((0x80000000 - val) <= 256) |
2065 | return true; | |
2066 | ||
2067 | return false; | |
2068 | } | |
2069 | ||
2070 | static bool pmc_overflow(unsigned long val) | |
2071 | { | |
2072 | if ((int)val < 0) | |
0837e324 AB |
2073 | return true; |
2074 | ||
2075 | return false; | |
2076 | } | |
2077 | ||
4574910e PM |
2078 | /* |
2079 | * Performance monitor interrupt stuff | |
2080 | */ | |
cdd6c482 | 2081 | static void perf_event_interrupt(struct pt_regs *regs) |
4574910e | 2082 | { |
bc09c219 | 2083 | int i, j; |
69111bac | 2084 | struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); |
cdd6c482 | 2085 | struct perf_event *event; |
bc09c219 MN |
2086 | unsigned long val[8]; |
2087 | int found, active; | |
ca8f2d7f PM |
2088 | int nmi; |
2089 | ||
ab7ef2e5 | 2090 | if (cpuhw->n_limited) |
a8f90e90 | 2091 | freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5), |
ab7ef2e5 PM |
2092 | mfspr(SPRN_PMC6)); |
2093 | ||
98fb1807 | 2094 | perf_read_regs(regs); |
0bbd0d4b | 2095 | |
98fb1807 | 2096 | nmi = perf_intr_is_nmi(regs); |
ca8f2d7f PM |
2097 | if (nmi) |
2098 | nmi_enter(); | |
2099 | else | |
2100 | irq_enter(); | |
4574910e | 2101 | |
bc09c219 MN |
2102 | /* Read all the PMCs since we'll need them a bunch of times */ |
2103 | for (i = 0; i < ppmu->n_counter; ++i) | |
2104 | val[i] = read_pmc(i + 1); | |
2105 | ||
2106 | /* Try to find what caused the IRQ */ | |
2107 | found = 0; | |
2108 | for (i = 0; i < ppmu->n_counter; ++i) { | |
2109 | if (!pmc_overflow(val[i])) | |
ab7ef2e5 | 2110 | continue; |
bc09c219 MN |
2111 | if (is_limited_pmc(i + 1)) |
2112 | continue; /* these won't generate IRQs */ | |
2113 | /* | |
2114 | * We've found one that's overflowed. For active | |
2115 | * counters we need to log this. For inactive | |
2116 | * counters, we need to reset it anyway | |
2117 | */ | |
2118 | found = 1; | |
2119 | active = 0; | |
2120 | for (j = 0; j < cpuhw->n_events; ++j) { | |
2121 | event = cpuhw->event[j]; | |
2122 | if (event->hw.idx == (i + 1)) { | |
2123 | active = 1; | |
2124 | record_and_restart(event, val[i], regs); | |
2125 | break; | |
2126 | } | |
4574910e | 2127 | } |
bc09c219 MN |
2128 | if (!active) |
2129 | /* reset non active counters that have overflowed */ | |
2130 | write_pmc(i + 1, 0); | |
4574910e | 2131 | } |
bc09c219 MN |
2132 | if (!found && pvr_version_is(PVR_POWER7)) { |
2133 | /* check active counters for special buggy p7 overflow */ | |
2134 | for (i = 0; i < cpuhw->n_events; ++i) { | |
2135 | event = cpuhw->event[i]; | |
2136 | if (!event->hw.idx || is_limited_pmc(event->hw.idx)) | |
ab7ef2e5 | 2137 | continue; |
bc09c219 MN |
2138 | if (pmc_overflow_power7(val[event->hw.idx - 1])) { |
2139 | /* event has overflowed in a buggy way*/ | |
2140 | found = 1; | |
2141 | record_and_restart(event, | |
2142 | val[event->hw.idx - 1], | |
2143 | regs); | |
2144 | } | |
4574910e PM |
2145 | } |
2146 | } | |
6772faa1 | 2147 | if (!found && !nmi && printk_ratelimit()) |
bc09c219 | 2148 | printk(KERN_WARNING "Can't find PMC that caused IRQ\n"); |
4574910e PM |
2149 | |
2150 | /* | |
2151 | * Reset MMCR0 to its normal value. This will set PMXE and | |
57c0c15b | 2152 | * clear FC (freeze counters) and PMAO (perf mon alert occurred) |
4574910e | 2153 | * and thus allow interrupts to occur again. |
cdd6c482 | 2154 | * XXX might want to use MSR.PM to keep the events frozen until |
4574910e PM |
2155 | * we get back out of this interrupt. |
2156 | */ | |
ab7ef2e5 | 2157 | write_mmcr0(cpuhw, cpuhw->mmcr[0]); |
4574910e | 2158 | |
ca8f2d7f PM |
2159 | if (nmi) |
2160 | nmi_exit(); | |
2161 | else | |
db4fb5ac | 2162 | irq_exit(); |
4574910e PM |
2163 | } |
2164 | ||
3f6da390 | 2165 | static void power_pmu_setup(int cpu) |
01d0287f | 2166 | { |
cdd6c482 | 2167 | struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu); |
01d0287f | 2168 | |
f36a1a13 PM |
2169 | if (!ppmu) |
2170 | return; | |
01d0287f PM |
2171 | memset(cpuhw, 0, sizeof(*cpuhw)); |
2172 | cpuhw->mmcr[0] = MMCR0_FC; | |
2173 | } | |
2174 | ||
061d19f2 | 2175 | static int |
85cfabbc | 2176 | power_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) |
3f6da390 PZ |
2177 | { |
2178 | unsigned int cpu = (long)hcpu; | |
2179 | ||
2180 | switch (action & ~CPU_TASKS_FROZEN) { | |
2181 | case CPU_UP_PREPARE: | |
2182 | power_pmu_setup(cpu); | |
2183 | break; | |
2184 | ||
2185 | default: | |
2186 | break; | |
2187 | } | |
2188 | ||
2189 | return NOTIFY_OK; | |
2190 | } | |
2191 | ||
061d19f2 | 2192 | int register_power_pmu(struct power_pmu *pmu) |
4574910e | 2193 | { |
079b3c56 PM |
2194 | if (ppmu) |
2195 | return -EBUSY; /* something's already registered */ | |
2196 | ||
2197 | ppmu = pmu; | |
2198 | pr_info("%s performance monitor hardware support registered\n", | |
2199 | pmu->name); | |
d095cd46 | 2200 | |
1c53a270 SB |
2201 | power_pmu.attr_groups = ppmu->attr_groups; |
2202 | ||
98fb1807 | 2203 | #ifdef MSR_HV |
d095cd46 PM |
2204 | /* |
2205 | * Use FCHV to ignore kernel events if MSR.HV is set. | |
2206 | */ | |
2207 | if (mfmsr() & MSR_HV) | |
cdd6c482 | 2208 | freeze_events_kernel = MMCR0_FCHV; |
98fb1807 | 2209 | #endif /* CONFIG_PPC64 */ |
d095cd46 | 2210 | |
2e80a82a | 2211 | perf_pmu_register(&power_pmu, "cpu", PERF_TYPE_RAW); |
3f6da390 PZ |
2212 | perf_cpu_notifier(power_pmu_notifier); |
2213 | ||
4574910e PM |
2214 | return 0; |
2215 | } |