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Commit | Line | Data |
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4574910e | 1 | /* |
cdd6c482 | 2 | * Performance event support - powerpc architecture code |
4574910e PM |
3 | * |
4 | * Copyright 2008-2009 Paul Mackerras, IBM Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/sched.h> | |
cdd6c482 | 13 | #include <linux/perf_event.h> |
4574910e PM |
14 | #include <linux/percpu.h> |
15 | #include <linux/hardirq.h> | |
69123184 | 16 | #include <linux/uaccess.h> |
4574910e PM |
17 | #include <asm/reg.h> |
18 | #include <asm/pmc.h> | |
01d0287f | 19 | #include <asm/machdep.h> |
0475f9ea | 20 | #include <asm/firmware.h> |
0bbd0d4b | 21 | #include <asm/ptrace.h> |
69123184 | 22 | #include <asm/code-patching.h> |
4574910e | 23 | |
3925f46b AK |
24 | #define BHRB_MAX_ENTRIES 32 |
25 | #define BHRB_TARGET 0x0000000000000002 | |
26 | #define BHRB_PREDICTION 0x0000000000000001 | |
b0d436c7 | 27 | #define BHRB_EA 0xFFFFFFFFFFFFFFFCUL |
3925f46b | 28 | |
cdd6c482 IM |
29 | struct cpu_hw_events { |
30 | int n_events; | |
4574910e PM |
31 | int n_percpu; |
32 | int disabled; | |
33 | int n_added; | |
ab7ef2e5 PM |
34 | int n_limited; |
35 | u8 pmcs_enabled; | |
cdd6c482 IM |
36 | struct perf_event *event[MAX_HWEVENTS]; |
37 | u64 events[MAX_HWEVENTS]; | |
38 | unsigned int flags[MAX_HWEVENTS]; | |
9de5cb0f ME |
39 | /* |
40 | * The order of the MMCR array is: | |
41 | * - 64-bit, MMCR0, MMCR1, MMCRA, MMCR2 | |
42 | * - 32-bit, MMCR0, MMCR1, MMCR2 | |
43 | */ | |
44 | unsigned long mmcr[4]; | |
a8f90e90 PM |
45 | struct perf_event *limited_counter[MAX_LIMITED_HWCOUNTERS]; |
46 | u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS]; | |
cdd6c482 IM |
47 | u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; |
48 | unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; | |
49 | unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; | |
8e6d5573 | 50 | |
fbbe0701 | 51 | unsigned int txn_flags; |
8e6d5573 | 52 | int n_txn_start; |
3925f46b AK |
53 | |
54 | /* BHRB bits */ | |
55 | u64 bhrb_filter; /* BHRB HW branch filter */ | |
f0322f7f | 56 | unsigned int bhrb_users; |
3925f46b AK |
57 | void *bhrb_context; |
58 | struct perf_branch_stack bhrb_stack; | |
59 | struct perf_branch_entry bhrb_entries[BHRB_MAX_ENTRIES]; | |
356d8ce3 | 60 | u64 ic_init; |
4574910e | 61 | }; |
3925f46b | 62 | |
e51df2c1 | 63 | static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); |
4574910e | 64 | |
e51df2c1 | 65 | static struct power_pmu *ppmu; |
4574910e | 66 | |
d095cd46 | 67 | /* |
57c0c15b | 68 | * Normally, to ignore kernel events we set the FCS (freeze counters |
d095cd46 PM |
69 | * in supervisor mode) bit in MMCR0, but if the kernel runs with the |
70 | * hypervisor bit set in the MSR, or if we are running on a processor | |
71 | * where the hypervisor bit is forced to 1 (as on Apple G5 processors), | |
72 | * then we need to use the FCHV bit to ignore kernel events. | |
73 | */ | |
cdd6c482 | 74 | static unsigned int freeze_events_kernel = MMCR0_FCS; |
d095cd46 | 75 | |
98fb1807 PM |
76 | /* |
77 | * 32-bit doesn't have MMCRA but does have an MMCR2, | |
78 | * and a few other names are different. | |
79 | */ | |
80 | #ifdef CONFIG_PPC32 | |
81 | ||
82 | #define MMCR0_FCHV 0 | |
83 | #define MMCR0_PMCjCE MMCR0_PMCnCE | |
7a7a41f9 | 84 | #define MMCR0_FC56 0 |
378a6ee9 | 85 | #define MMCR0_PMAO 0 |
330a1eb7 | 86 | #define MMCR0_EBE 0 |
76cb8a78 | 87 | #define MMCR0_BHRBA 0 |
330a1eb7 ME |
88 | #define MMCR0_PMCC 0 |
89 | #define MMCR0_PMCC_U6 0 | |
98fb1807 PM |
90 | |
91 | #define SPRN_MMCRA SPRN_MMCR2 | |
92 | #define MMCRA_SAMPLE_ENABLE 0 | |
93 | ||
94 | static inline unsigned long perf_ip_adjust(struct pt_regs *regs) | |
95 | { | |
96 | return 0; | |
97 | } | |
98fb1807 PM |
98 | static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) { } |
99 | static inline u32 perf_get_misc_flags(struct pt_regs *regs) | |
100 | { | |
101 | return 0; | |
102 | } | |
75382aa7 AB |
103 | static inline void perf_read_regs(struct pt_regs *regs) |
104 | { | |
105 | regs->result = 0; | |
106 | } | |
98fb1807 PM |
107 | static inline int perf_intr_is_nmi(struct pt_regs *regs) |
108 | { | |
109 | return 0; | |
110 | } | |
111 | ||
e6878835 | 112 | static inline int siar_valid(struct pt_regs *regs) |
113 | { | |
114 | return 1; | |
115 | } | |
116 | ||
330a1eb7 ME |
117 | static bool is_ebb_event(struct perf_event *event) { return false; } |
118 | static int ebb_event_check(struct perf_event *event) { return 0; } | |
119 | static void ebb_event_add(struct perf_event *event) { } | |
120 | static void ebb_switch_out(unsigned long mmcr0) { } | |
9de5cb0f | 121 | static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw) |
330a1eb7 | 122 | { |
9de5cb0f | 123 | return cpuhw->mmcr[0]; |
330a1eb7 ME |
124 | } |
125 | ||
d52f2dc4 MN |
126 | static inline void power_pmu_bhrb_enable(struct perf_event *event) {} |
127 | static inline void power_pmu_bhrb_disable(struct perf_event *event) {} | |
acba3c7e | 128 | static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) {} |
d52f2dc4 | 129 | static inline void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) {} |
c2e37a26 | 130 | static void pmao_restore_workaround(bool ebb) { } |
356d8ce3 MS |
131 | static bool use_ic(u64 event) |
132 | { | |
133 | return false; | |
134 | } | |
98fb1807 PM |
135 | #endif /* CONFIG_PPC32 */ |
136 | ||
33904054 ME |
137 | static bool regs_use_siar(struct pt_regs *regs) |
138 | { | |
72e349f1 AB |
139 | /* |
140 | * When we take a performance monitor exception the regs are setup | |
141 | * using perf_read_regs() which overloads some fields, in particular | |
142 | * regs->result to tell us whether to use SIAR. | |
143 | * | |
144 | * However if the regs are from another exception, eg. a syscall, then | |
145 | * they have not been setup using perf_read_regs() and so regs->result | |
146 | * is something random. | |
147 | */ | |
148 | return ((TRAP(regs) == 0xf00) && regs->result); | |
33904054 ME |
149 | } |
150 | ||
98fb1807 PM |
151 | /* |
152 | * Things that are specific to 64-bit implementations. | |
153 | */ | |
154 | #ifdef CONFIG_PPC64 | |
155 | ||
156 | static inline unsigned long perf_ip_adjust(struct pt_regs *regs) | |
157 | { | |
158 | unsigned long mmcra = regs->dsisr; | |
159 | ||
7a786832 | 160 | if ((ppmu->flags & PPMU_HAS_SSLOT) && (mmcra & MMCRA_SAMPLE_ENABLE)) { |
98fb1807 PM |
161 | unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT; |
162 | if (slot > 1) | |
163 | return 4 * (slot - 1); | |
164 | } | |
7a786832 | 165 | |
98fb1807 PM |
166 | return 0; |
167 | } | |
168 | ||
98fb1807 PM |
169 | /* |
170 | * The user wants a data address recorded. | |
171 | * If we're not doing instruction sampling, give them the SDAR | |
172 | * (sampled data address). If we are doing instruction sampling, then | |
173 | * only give them the SDAR if it corresponds to the instruction | |
58a032c3 ME |
174 | * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC, the |
175 | * [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA, or the SDAR_VALID bit in SIER. | |
98fb1807 PM |
176 | */ |
177 | static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) | |
178 | { | |
179 | unsigned long mmcra = regs->dsisr; | |
58a032c3 | 180 | bool sdar_valid; |
e6878835 | 181 | |
58a032c3 ME |
182 | if (ppmu->flags & PPMU_HAS_SIER) |
183 | sdar_valid = regs->dar & SIER_SDAR_VALID; | |
184 | else { | |
185 | unsigned long sdsync; | |
186 | ||
187 | if (ppmu->flags & PPMU_SIAR_VALID) | |
188 | sdsync = POWER7P_MMCRA_SDAR_VALID; | |
189 | else if (ppmu->flags & PPMU_ALT_SIPR) | |
190 | sdsync = POWER6_MMCRA_SDSYNC; | |
f04d1080 MS |
191 | else if (ppmu->flags & PPMU_NO_SIAR) |
192 | sdsync = MMCRA_SAMPLE_ENABLE; | |
58a032c3 ME |
193 | else |
194 | sdsync = MMCRA_SDSYNC; | |
195 | ||
196 | sdar_valid = mmcra & sdsync; | |
197 | } | |
98fb1807 | 198 | |
58a032c3 | 199 | if (!(mmcra & MMCRA_SAMPLE_ENABLE) || sdar_valid) |
98fb1807 PM |
200 | *addrp = mfspr(SPRN_SDAR); |
201 | } | |
202 | ||
5682c460 | 203 | static bool regs_sihv(struct pt_regs *regs) |
68b30bb9 AB |
204 | { |
205 | unsigned long sihv = MMCRA_SIHV; | |
206 | ||
8f61aa32 ME |
207 | if (ppmu->flags & PPMU_HAS_SIER) |
208 | return !!(regs->dar & SIER_SIHV); | |
209 | ||
68b30bb9 AB |
210 | if (ppmu->flags & PPMU_ALT_SIPR) |
211 | sihv = POWER6_MMCRA_SIHV; | |
212 | ||
5682c460 | 213 | return !!(regs->dsisr & sihv); |
68b30bb9 AB |
214 | } |
215 | ||
5682c460 | 216 | static bool regs_sipr(struct pt_regs *regs) |
68b30bb9 AB |
217 | { |
218 | unsigned long sipr = MMCRA_SIPR; | |
219 | ||
8f61aa32 ME |
220 | if (ppmu->flags & PPMU_HAS_SIER) |
221 | return !!(regs->dar & SIER_SIPR); | |
222 | ||
68b30bb9 AB |
223 | if (ppmu->flags & PPMU_ALT_SIPR) |
224 | sipr = POWER6_MMCRA_SIPR; | |
225 | ||
5682c460 | 226 | return !!(regs->dsisr & sipr); |
68b30bb9 AB |
227 | } |
228 | ||
1ce447b9 BH |
229 | static inline u32 perf_flags_from_msr(struct pt_regs *regs) |
230 | { | |
231 | if (regs->msr & MSR_PR) | |
232 | return PERF_RECORD_MISC_USER; | |
233 | if ((regs->msr & MSR_HV) && freeze_events_kernel != MMCR0_FCHV) | |
234 | return PERF_RECORD_MISC_HYPERVISOR; | |
235 | return PERF_RECORD_MISC_KERNEL; | |
236 | } | |
237 | ||
98fb1807 PM |
238 | static inline u32 perf_get_misc_flags(struct pt_regs *regs) |
239 | { | |
33904054 | 240 | bool use_siar = regs_use_siar(regs); |
98fb1807 | 241 | |
75382aa7 | 242 | if (!use_siar) |
1ce447b9 BH |
243 | return perf_flags_from_msr(regs); |
244 | ||
245 | /* | |
246 | * If we don't have flags in MMCRA, rather than using | |
247 | * the MSR, we intuit the flags from the address in | |
248 | * SIAR which should give slightly more reliable | |
249 | * results | |
250 | */ | |
cbda6aa1 | 251 | if (ppmu->flags & PPMU_NO_SIPR) { |
1ce447b9 | 252 | unsigned long siar = mfspr(SPRN_SIAR); |
a2391b35 | 253 | if (is_kernel_addr(siar)) |
1ce447b9 BH |
254 | return PERF_RECORD_MISC_KERNEL; |
255 | return PERF_RECORD_MISC_USER; | |
256 | } | |
98fb1807 | 257 | |
7abb840b | 258 | /* PR has priority over HV, so order below is important */ |
5682c460 | 259 | if (regs_sipr(regs)) |
7abb840b | 260 | return PERF_RECORD_MISC_USER; |
5682c460 ME |
261 | |
262 | if (regs_sihv(regs) && (freeze_events_kernel != MMCR0_FCHV)) | |
cdd6c482 | 263 | return PERF_RECORD_MISC_HYPERVISOR; |
5682c460 | 264 | |
7abb840b | 265 | return PERF_RECORD_MISC_KERNEL; |
98fb1807 PM |
266 | } |
267 | ||
268 | /* | |
269 | * Overload regs->dsisr to store MMCRA so we only need to read it once | |
270 | * on each interrupt. | |
8f61aa32 | 271 | * Overload regs->dar to store SIER if we have it. |
75382aa7 AB |
272 | * Overload regs->result to specify whether we should use the MSR (result |
273 | * is zero) or the SIAR (result is non zero). | |
98fb1807 PM |
274 | */ |
275 | static inline void perf_read_regs(struct pt_regs *regs) | |
276 | { | |
75382aa7 AB |
277 | unsigned long mmcra = mfspr(SPRN_MMCRA); |
278 | int marked = mmcra & MMCRA_SAMPLE_ENABLE; | |
279 | int use_siar; | |
280 | ||
5682c460 | 281 | regs->dsisr = mmcra; |
8f61aa32 | 282 | |
cbda6aa1 ME |
283 | if (ppmu->flags & PPMU_HAS_SIER) |
284 | regs->dar = mfspr(SPRN_SIER); | |
8f61aa32 | 285 | |
5c093efa AB |
286 | /* |
287 | * If this isn't a PMU exception (eg a software event) the SIAR is | |
288 | * not valid. Use pt_regs. | |
289 | * | |
290 | * If it is a marked event use the SIAR. | |
291 | * | |
292 | * If the PMU doesn't update the SIAR for non marked events use | |
293 | * pt_regs. | |
294 | * | |
295 | * If the PMU has HV/PR flags then check to see if they | |
296 | * place the exception in userspace. If so, use pt_regs. In | |
297 | * continuous sampling mode the SIAR and the PMU exception are | |
298 | * not synchronised, so they may be many instructions apart. | |
299 | * This can result in confusing backtraces. We still want | |
300 | * hypervisor samples as well as samples in the kernel with | |
301 | * interrupts off hence the userspace check. | |
302 | */ | |
75382aa7 AB |
303 | if (TRAP(regs) != 0xf00) |
304 | use_siar = 0; | |
27593d72 MS |
305 | else if ((ppmu->flags & PPMU_NO_SIAR)) |
306 | use_siar = 0; | |
5c093efa AB |
307 | else if (marked) |
308 | use_siar = 1; | |
309 | else if ((ppmu->flags & PPMU_NO_CONT_SAMPLING)) | |
310 | use_siar = 0; | |
cbda6aa1 | 311 | else if (!(ppmu->flags & PPMU_NO_SIPR) && regs_sipr(regs)) |
75382aa7 AB |
312 | use_siar = 0; |
313 | else | |
314 | use_siar = 1; | |
315 | ||
cbda6aa1 | 316 | regs->result = use_siar; |
98fb1807 PM |
317 | } |
318 | ||
319 | /* | |
320 | * If interrupts were soft-disabled when a PMU interrupt occurs, treat | |
321 | * it as an NMI. | |
322 | */ | |
323 | static inline int perf_intr_is_nmi(struct pt_regs *regs) | |
324 | { | |
325 | return !regs->softe; | |
326 | } | |
327 | ||
e6878835 | 328 | /* |
329 | * On processors like P7+ that have the SIAR-Valid bit, marked instructions | |
330 | * must be sampled only if the SIAR-valid bit is set. | |
331 | * | |
332 | * For unmarked instructions and for processors that don't have the SIAR-Valid | |
333 | * bit, assume that SIAR is valid. | |
334 | */ | |
335 | static inline int siar_valid(struct pt_regs *regs) | |
336 | { | |
337 | unsigned long mmcra = regs->dsisr; | |
338 | int marked = mmcra & MMCRA_SAMPLE_ENABLE; | |
339 | ||
58a032c3 ME |
340 | if (marked) { |
341 | if (ppmu->flags & PPMU_HAS_SIER) | |
342 | return regs->dar & SIER_SIAR_VALID; | |
343 | ||
344 | if (ppmu->flags & PPMU_SIAR_VALID) | |
345 | return mmcra & POWER7P_MMCRA_SIAR_VALID; | |
346 | } | |
e6878835 | 347 | |
348 | return 1; | |
349 | } | |
350 | ||
d52f2dc4 MN |
351 | |
352 | /* Reset all possible BHRB entries */ | |
353 | static void power_pmu_bhrb_reset(void) | |
354 | { | |
355 | asm volatile(PPC_CLRBHRB); | |
356 | } | |
357 | ||
358 | static void power_pmu_bhrb_enable(struct perf_event *event) | |
359 | { | |
69111bac | 360 | struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); |
d52f2dc4 MN |
361 | |
362 | if (!ppmu->bhrb_nr) | |
363 | return; | |
364 | ||
365 | /* Clear BHRB if we changed task context to avoid data leaks */ | |
366 | if (event->ctx->task && cpuhw->bhrb_context != event->ctx) { | |
367 | power_pmu_bhrb_reset(); | |
368 | cpuhw->bhrb_context = event->ctx; | |
369 | } | |
370 | cpuhw->bhrb_users++; | |
acba3c7e | 371 | perf_sched_cb_inc(event->ctx->pmu); |
d52f2dc4 MN |
372 | } |
373 | ||
374 | static void power_pmu_bhrb_disable(struct perf_event *event) | |
375 | { | |
69111bac | 376 | struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); |
d52f2dc4 MN |
377 | |
378 | if (!ppmu->bhrb_nr) | |
379 | return; | |
380 | ||
f0322f7f | 381 | WARN_ON_ONCE(!cpuhw->bhrb_users); |
d52f2dc4 | 382 | cpuhw->bhrb_users--; |
acba3c7e | 383 | perf_sched_cb_dec(event->ctx->pmu); |
d52f2dc4 MN |
384 | |
385 | if (!cpuhw->disabled && !cpuhw->bhrb_users) { | |
386 | /* BHRB cannot be turned off when other | |
387 | * events are active on the PMU. | |
388 | */ | |
389 | ||
390 | /* avoid stale pointer */ | |
391 | cpuhw->bhrb_context = NULL; | |
392 | } | |
393 | } | |
394 | ||
395 | /* Called from ctxsw to prevent one process's branch entries to | |
396 | * mingle with the other process's entries during context switch. | |
397 | */ | |
acba3c7e | 398 | static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) |
d52f2dc4 | 399 | { |
acba3c7e PZ |
400 | if (!ppmu->bhrb_nr) |
401 | return; | |
402 | ||
403 | if (sched_in) | |
d52f2dc4 MN |
404 | power_pmu_bhrb_reset(); |
405 | } | |
69123184 MN |
406 | /* Calculate the to address for a branch */ |
407 | static __u64 power_pmu_bhrb_to(u64 addr) | |
408 | { | |
409 | unsigned int instr; | |
410 | int ret; | |
411 | __u64 target; | |
412 | ||
f41d84dd RB |
413 | if (is_kernel_addr(addr)) { |
414 | if (probe_kernel_read(&instr, (void *)addr, sizeof(instr))) | |
415 | return 0; | |
416 | ||
417 | return branch_target(&instr); | |
418 | } | |
69123184 MN |
419 | |
420 | /* Userspace: need copy instruction here then translate it */ | |
421 | pagefault_disable(); | |
422 | ret = __get_user_inatomic(instr, (unsigned int __user *)addr); | |
423 | if (ret) { | |
424 | pagefault_enable(); | |
425 | return 0; | |
426 | } | |
427 | pagefault_enable(); | |
428 | ||
429 | target = branch_target(&instr); | |
430 | if ((!target) || (instr & BRANCH_ABSOLUTE)) | |
431 | return target; | |
432 | ||
433 | /* Translate relative branch target from kernel to user address */ | |
434 | return target - (unsigned long)&instr + addr; | |
435 | } | |
d52f2dc4 | 436 | |
d52f2dc4 | 437 | /* Processing BHRB entries */ |
e51df2c1 | 438 | static void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) |
d52f2dc4 MN |
439 | { |
440 | u64 val; | |
441 | u64 addr; | |
506e70d1 | 442 | int r_index, u_index, pred; |
d52f2dc4 MN |
443 | |
444 | r_index = 0; | |
445 | u_index = 0; | |
446 | while (r_index < ppmu->bhrb_nr) { | |
447 | /* Assembly read function */ | |
506e70d1 MN |
448 | val = read_bhrb(r_index++); |
449 | if (!val) | |
450 | /* Terminal marker: End of valid BHRB entries */ | |
d52f2dc4 | 451 | break; |
506e70d1 | 452 | else { |
d52f2dc4 MN |
453 | addr = val & BHRB_EA; |
454 | pred = val & BHRB_PREDICTION; | |
d52f2dc4 | 455 | |
506e70d1 MN |
456 | if (!addr) |
457 | /* invalid entry */ | |
d52f2dc4 | 458 | continue; |
d52f2dc4 | 459 | |
2c3eab47 MS |
460 | /* |
461 | * BHRB rolling buffer could very much contain the kernel | |
462 | * addresses at this point. Check the privileges before | |
463 | * exporting it to userspace (avoid exposure of regions | |
464 | * where we could have speculative execution) | |
465 | */ | |
466 | if (perf_paranoid_kernel() && !capable(CAP_SYS_ADMIN) && | |
467 | is_kernel_addr(addr)) | |
468 | continue; | |
469 | ||
506e70d1 MN |
470 | /* Branches are read most recent first (ie. mfbhrb 0 is |
471 | * the most recent branch). | |
472 | * There are two types of valid entries: | |
473 | * 1) a target entry which is the to address of a | |
474 | * computed goto like a blr,bctr,btar. The next | |
475 | * entry read from the bhrb will be branch | |
476 | * corresponding to this target (ie. the actual | |
477 | * blr/bctr/btar instruction). | |
478 | * 2) a from address which is an actual branch. If a | |
479 | * target entry proceeds this, then this is the | |
480 | * matching branch for that target. If this is not | |
481 | * following a target entry, then this is a branch | |
482 | * where the target is given as an immediate field | |
483 | * in the instruction (ie. an i or b form branch). | |
484 | * In this case we need to read the instruction from | |
485 | * memory to determine the target/to address. | |
486 | */ | |
d52f2dc4 | 487 | |
d52f2dc4 | 488 | if (val & BHRB_TARGET) { |
506e70d1 MN |
489 | /* Target branches use two entries |
490 | * (ie. computed gotos/XL form) | |
491 | */ | |
492 | cpuhw->bhrb_entries[u_index].to = addr; | |
493 | cpuhw->bhrb_entries[u_index].mispred = pred; | |
494 | cpuhw->bhrb_entries[u_index].predicted = ~pred; | |
d52f2dc4 | 495 | |
506e70d1 MN |
496 | /* Get from address in next entry */ |
497 | val = read_bhrb(r_index++); | |
498 | addr = val & BHRB_EA; | |
499 | if (val & BHRB_TARGET) { | |
500 | /* Shouldn't have two targets in a | |
501 | row.. Reset index and try again */ | |
502 | r_index--; | |
503 | addr = 0; | |
504 | } | |
505 | cpuhw->bhrb_entries[u_index].from = addr; | |
d52f2dc4 | 506 | } else { |
506e70d1 MN |
507 | /* Branches to immediate field |
508 | (ie I or B form) */ | |
d52f2dc4 | 509 | cpuhw->bhrb_entries[u_index].from = addr; |
69123184 MN |
510 | cpuhw->bhrb_entries[u_index].to = |
511 | power_pmu_bhrb_to(addr); | |
d52f2dc4 MN |
512 | cpuhw->bhrb_entries[u_index].mispred = pred; |
513 | cpuhw->bhrb_entries[u_index].predicted = ~pred; | |
d52f2dc4 | 514 | } |
506e70d1 MN |
515 | u_index++; |
516 | ||
d52f2dc4 MN |
517 | } |
518 | } | |
519 | cpuhw->bhrb_stack.nr = u_index; | |
520 | return; | |
521 | } | |
522 | ||
330a1eb7 ME |
523 | static bool is_ebb_event(struct perf_event *event) |
524 | { | |
525 | /* | |
526 | * This could be a per-PMU callback, but we'd rather avoid the cost. We | |
527 | * check that the PMU supports EBB, meaning those that don't can still | |
528 | * use bit 63 of the event code for something else if they wish. | |
529 | */ | |
4d9690dd | 530 | return (ppmu->flags & PPMU_ARCH_207S) && |
8d7c55d0 | 531 | ((event->attr.config >> PERF_EVENT_CONFIG_EBB_SHIFT) & 1); |
330a1eb7 ME |
532 | } |
533 | ||
534 | static int ebb_event_check(struct perf_event *event) | |
535 | { | |
536 | struct perf_event *leader = event->group_leader; | |
537 | ||
538 | /* Event and group leader must agree on EBB */ | |
539 | if (is_ebb_event(leader) != is_ebb_event(event)) | |
540 | return -EINVAL; | |
541 | ||
542 | if (is_ebb_event(event)) { | |
543 | if (!(event->attach_state & PERF_ATTACH_TASK)) | |
544 | return -EINVAL; | |
545 | ||
546 | if (!leader->attr.pinned || !leader->attr.exclusive) | |
547 | return -EINVAL; | |
548 | ||
58b5fb00 ME |
549 | if (event->attr.freq || |
550 | event->attr.inherit || | |
551 | event->attr.sample_type || | |
552 | event->attr.sample_period || | |
553 | event->attr.enable_on_exec) | |
330a1eb7 ME |
554 | return -EINVAL; |
555 | } | |
556 | ||
557 | return 0; | |
558 | } | |
559 | ||
560 | static void ebb_event_add(struct perf_event *event) | |
561 | { | |
562 | if (!is_ebb_event(event) || current->thread.used_ebb) | |
563 | return; | |
564 | ||
565 | /* | |
566 | * IFF this is the first time we've added an EBB event, set | |
567 | * PMXE in the user MMCR0 so we can detect when it's cleared by | |
568 | * userspace. We need this so that we can context switch while | |
569 | * userspace is in the EBB handler (where PMXE is 0). | |
570 | */ | |
571 | current->thread.used_ebb = 1; | |
572 | current->thread.mmcr0 |= MMCR0_PMXE; | |
573 | } | |
574 | ||
575 | static void ebb_switch_out(unsigned long mmcr0) | |
576 | { | |
577 | if (!(mmcr0 & MMCR0_EBE)) | |
578 | return; | |
579 | ||
580 | current->thread.siar = mfspr(SPRN_SIAR); | |
581 | current->thread.sier = mfspr(SPRN_SIER); | |
582 | current->thread.sdar = mfspr(SPRN_SDAR); | |
583 | current->thread.mmcr0 = mmcr0 & MMCR0_USER_MASK; | |
584 | current->thread.mmcr2 = mfspr(SPRN_MMCR2) & MMCR2_USER_MASK; | |
585 | } | |
586 | ||
9de5cb0f | 587 | static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw) |
330a1eb7 | 588 | { |
9de5cb0f ME |
589 | unsigned long mmcr0 = cpuhw->mmcr[0]; |
590 | ||
330a1eb7 ME |
591 | if (!ebb) |
592 | goto out; | |
593 | ||
76cb8a78 ME |
594 | /* Enable EBB and read/write to all 6 PMCs and BHRB for userspace */ |
595 | mmcr0 |= MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC_U6; | |
330a1eb7 | 596 | |
c2e37a26 ME |
597 | /* |
598 | * Add any bits from the user MMCR0, FC or PMAO. This is compatible | |
599 | * with pmao_restore_workaround() because we may add PMAO but we never | |
600 | * clear it here. | |
601 | */ | |
330a1eb7 ME |
602 | mmcr0 |= current->thread.mmcr0; |
603 | ||
c2e37a26 ME |
604 | /* |
605 | * Be careful not to set PMXE if userspace had it cleared. This is also | |
606 | * compatible with pmao_restore_workaround() because it has already | |
607 | * cleared PMXE and we leave PMAO alone. | |
608 | */ | |
330a1eb7 ME |
609 | if (!(current->thread.mmcr0 & MMCR0_PMXE)) |
610 | mmcr0 &= ~MMCR0_PMXE; | |
611 | ||
612 | mtspr(SPRN_SIAR, current->thread.siar); | |
613 | mtspr(SPRN_SIER, current->thread.sier); | |
614 | mtspr(SPRN_SDAR, current->thread.sdar); | |
9de5cb0f ME |
615 | |
616 | /* | |
617 | * Merge the kernel & user values of MMCR2. The semantics we implement | |
618 | * are that the user MMCR2 can set bits, ie. cause counters to freeze, | |
619 | * but not clear bits. If a task wants to be able to clear bits, ie. | |
620 | * unfreeze counters, it should not set exclude_xxx in its events and | |
621 | * instead manage the MMCR2 entirely by itself. | |
622 | */ | |
623 | mtspr(SPRN_MMCR2, cpuhw->mmcr[3] | current->thread.mmcr2); | |
330a1eb7 ME |
624 | out: |
625 | return mmcr0; | |
626 | } | |
c2e37a26 ME |
627 | |
628 | static void pmao_restore_workaround(bool ebb) | |
629 | { | |
630 | unsigned pmcs[6]; | |
631 | ||
632 | if (!cpu_has_feature(CPU_FTR_PMAO_BUG)) | |
633 | return; | |
634 | ||
635 | /* | |
636 | * On POWER8E there is a hardware defect which affects the PMU context | |
637 | * switch logic, ie. power_pmu_disable/enable(). | |
638 | * | |
639 | * When a counter overflows PMXE is cleared and FC/PMAO is set in MMCR0 | |
640 | * by the hardware. Sometime later the actual PMU exception is | |
641 | * delivered. | |
642 | * | |
643 | * If we context switch, or simply disable/enable, the PMU prior to the | |
644 | * exception arriving, the exception will be lost when we clear PMAO. | |
645 | * | |
646 | * When we reenable the PMU, we will write the saved MMCR0 with PMAO | |
647 | * set, and this _should_ generate an exception. However because of the | |
648 | * defect no exception is generated when we write PMAO, and we get | |
649 | * stuck with no counters counting but no exception delivered. | |
650 | * | |
651 | * The workaround is to detect this case and tweak the hardware to | |
652 | * create another pending PMU exception. | |
653 | * | |
654 | * We do that by setting up PMC6 (cycles) for an imminent overflow and | |
655 | * enabling the PMU. That causes a new exception to be generated in the | |
656 | * chip, but we don't take it yet because we have interrupts hard | |
657 | * disabled. We then write back the PMU state as we want it to be seen | |
658 | * by the exception handler. When we reenable interrupts the exception | |
659 | * handler will be called and see the correct state. | |
660 | * | |
661 | * The logic is the same for EBB, except that the exception is gated by | |
662 | * us having interrupts hard disabled as well as the fact that we are | |
663 | * not in userspace. The exception is finally delivered when we return | |
664 | * to userspace. | |
665 | */ | |
666 | ||
667 | /* Only if PMAO is set and PMAO_SYNC is clear */ | |
668 | if ((current->thread.mmcr0 & (MMCR0_PMAO | MMCR0_PMAO_SYNC)) != MMCR0_PMAO) | |
669 | return; | |
670 | ||
671 | /* If we're doing EBB, only if BESCR[GE] is set */ | |
672 | if (ebb && !(current->thread.bescr & BESCR_GE)) | |
673 | return; | |
674 | ||
675 | /* | |
676 | * We are already soft-disabled in power_pmu_enable(). We need to hard | |
58bffb5b | 677 | * disable to actually prevent the PMU exception from firing. |
c2e37a26 ME |
678 | */ |
679 | hard_irq_disable(); | |
680 | ||
681 | /* | |
682 | * This is a bit gross, but we know we're on POWER8E and have 6 PMCs. | |
683 | * Using read/write_pmc() in a for loop adds 12 function calls and | |
684 | * almost doubles our code size. | |
685 | */ | |
686 | pmcs[0] = mfspr(SPRN_PMC1); | |
687 | pmcs[1] = mfspr(SPRN_PMC2); | |
688 | pmcs[2] = mfspr(SPRN_PMC3); | |
689 | pmcs[3] = mfspr(SPRN_PMC4); | |
690 | pmcs[4] = mfspr(SPRN_PMC5); | |
691 | pmcs[5] = mfspr(SPRN_PMC6); | |
692 | ||
693 | /* Ensure all freeze bits are unset */ | |
694 | mtspr(SPRN_MMCR2, 0); | |
695 | ||
696 | /* Set up PMC6 to overflow in one cycle */ | |
697 | mtspr(SPRN_PMC6, 0x7FFFFFFE); | |
698 | ||
699 | /* Enable exceptions and unfreeze PMC6 */ | |
700 | mtspr(SPRN_MMCR0, MMCR0_PMXE | MMCR0_PMCjCE | MMCR0_PMAO); | |
701 | ||
702 | /* Now we need to refreeze and restore the PMCs */ | |
703 | mtspr(SPRN_MMCR0, MMCR0_FC | MMCR0_PMAO); | |
704 | ||
705 | mtspr(SPRN_PMC1, pmcs[0]); | |
706 | mtspr(SPRN_PMC2, pmcs[1]); | |
707 | mtspr(SPRN_PMC3, pmcs[2]); | |
708 | mtspr(SPRN_PMC4, pmcs[3]); | |
709 | mtspr(SPRN_PMC5, pmcs[4]); | |
710 | mtspr(SPRN_PMC6, pmcs[5]); | |
711 | } | |
356d8ce3 MS |
712 | |
713 | static bool use_ic(u64 event) | |
714 | { | |
715 | if (cpu_has_feature(CPU_FTR_POWER9_DD1) && | |
716 | (event == 0x200f2 || event == 0x300f2)) | |
717 | return true; | |
718 | ||
719 | return false; | |
720 | } | |
98fb1807 PM |
721 | #endif /* CONFIG_PPC64 */ |
722 | ||
cdd6c482 | 723 | static void perf_event_interrupt(struct pt_regs *regs); |
7595d63b | 724 | |
4574910e | 725 | /* |
57c0c15b | 726 | * Read one performance monitor counter (PMC). |
4574910e PM |
727 | */ |
728 | static unsigned long read_pmc(int idx) | |
729 | { | |
730 | unsigned long val; | |
731 | ||
732 | switch (idx) { | |
733 | case 1: | |
734 | val = mfspr(SPRN_PMC1); | |
735 | break; | |
736 | case 2: | |
737 | val = mfspr(SPRN_PMC2); | |
738 | break; | |
739 | case 3: | |
740 | val = mfspr(SPRN_PMC3); | |
741 | break; | |
742 | case 4: | |
743 | val = mfspr(SPRN_PMC4); | |
744 | break; | |
745 | case 5: | |
746 | val = mfspr(SPRN_PMC5); | |
747 | break; | |
748 | case 6: | |
749 | val = mfspr(SPRN_PMC6); | |
750 | break; | |
98fb1807 | 751 | #ifdef CONFIG_PPC64 |
4574910e PM |
752 | case 7: |
753 | val = mfspr(SPRN_PMC7); | |
754 | break; | |
755 | case 8: | |
756 | val = mfspr(SPRN_PMC8); | |
757 | break; | |
98fb1807 | 758 | #endif /* CONFIG_PPC64 */ |
4574910e PM |
759 | default: |
760 | printk(KERN_ERR "oops trying to read PMC%d\n", idx); | |
761 | val = 0; | |
762 | } | |
763 | return val; | |
764 | } | |
765 | ||
766 | /* | |
767 | * Write one PMC. | |
768 | */ | |
769 | static void write_pmc(int idx, unsigned long val) | |
770 | { | |
771 | switch (idx) { | |
772 | case 1: | |
773 | mtspr(SPRN_PMC1, val); | |
774 | break; | |
775 | case 2: | |
776 | mtspr(SPRN_PMC2, val); | |
777 | break; | |
778 | case 3: | |
779 | mtspr(SPRN_PMC3, val); | |
780 | break; | |
781 | case 4: | |
782 | mtspr(SPRN_PMC4, val); | |
783 | break; | |
784 | case 5: | |
785 | mtspr(SPRN_PMC5, val); | |
786 | break; | |
787 | case 6: | |
788 | mtspr(SPRN_PMC6, val); | |
789 | break; | |
98fb1807 | 790 | #ifdef CONFIG_PPC64 |
4574910e PM |
791 | case 7: |
792 | mtspr(SPRN_PMC7, val); | |
793 | break; | |
794 | case 8: | |
795 | mtspr(SPRN_PMC8, val); | |
796 | break; | |
98fb1807 | 797 | #endif /* CONFIG_PPC64 */ |
4574910e PM |
798 | default: |
799 | printk(KERN_ERR "oops trying to write PMC%d\n", idx); | |
800 | } | |
801 | } | |
802 | ||
5f6d0380 AK |
803 | /* Called from sysrq_handle_showregs() */ |
804 | void perf_event_print_debug(void) | |
805 | { | |
806 | unsigned long sdar, sier, flags; | |
807 | u32 pmcs[MAX_HWEVENTS]; | |
808 | int i; | |
809 | ||
4917fcb5 RB |
810 | if (!ppmu) { |
811 | pr_info("Performance monitor hardware not registered.\n"); | |
812 | return; | |
813 | } | |
814 | ||
5f6d0380 AK |
815 | if (!ppmu->n_counter) |
816 | return; | |
817 | ||
818 | local_irq_save(flags); | |
819 | ||
820 | pr_info("CPU: %d PMU registers, ppmu = %s n_counters = %d", | |
821 | smp_processor_id(), ppmu->name, ppmu->n_counter); | |
822 | ||
823 | for (i = 0; i < ppmu->n_counter; i++) | |
824 | pmcs[i] = read_pmc(i + 1); | |
825 | ||
826 | for (; i < MAX_HWEVENTS; i++) | |
827 | pmcs[i] = 0xdeadbeef; | |
828 | ||
829 | pr_info("PMC1: %08x PMC2: %08x PMC3: %08x PMC4: %08x\n", | |
830 | pmcs[0], pmcs[1], pmcs[2], pmcs[3]); | |
831 | ||
832 | if (ppmu->n_counter > 4) | |
833 | pr_info("PMC5: %08x PMC6: %08x PMC7: %08x PMC8: %08x\n", | |
834 | pmcs[4], pmcs[5], pmcs[6], pmcs[7]); | |
835 | ||
836 | pr_info("MMCR0: %016lx MMCR1: %016lx MMCRA: %016lx\n", | |
837 | mfspr(SPRN_MMCR0), mfspr(SPRN_MMCR1), mfspr(SPRN_MMCRA)); | |
838 | ||
839 | sdar = sier = 0; | |
840 | #ifdef CONFIG_PPC64 | |
841 | sdar = mfspr(SPRN_SDAR); | |
842 | ||
843 | if (ppmu->flags & PPMU_HAS_SIER) | |
844 | sier = mfspr(SPRN_SIER); | |
845 | ||
4d9690dd | 846 | if (ppmu->flags & PPMU_ARCH_207S) { |
5f6d0380 AK |
847 | pr_info("MMCR2: %016lx EBBHR: %016lx\n", |
848 | mfspr(SPRN_MMCR2), mfspr(SPRN_EBBHR)); | |
849 | pr_info("EBBRR: %016lx BESCR: %016lx\n", | |
850 | mfspr(SPRN_EBBRR), mfspr(SPRN_BESCR)); | |
851 | } | |
852 | #endif | |
853 | pr_info("SIAR: %016lx SDAR: %016lx SIER: %016lx\n", | |
854 | mfspr(SPRN_SIAR), sdar, sier); | |
855 | ||
856 | local_irq_restore(flags); | |
857 | } | |
858 | ||
4574910e PM |
859 | /* |
860 | * Check if a set of events can all go on the PMU at once. | |
861 | * If they can't, this will look at alternative codes for the events | |
862 | * and see if any combination of alternative codes is feasible. | |
cdd6c482 | 863 | * The feasible set is returned in event_id[]. |
4574910e | 864 | */ |
cdd6c482 IM |
865 | static int power_check_constraints(struct cpu_hw_events *cpuhw, |
866 | u64 event_id[], unsigned int cflags[], | |
ab7ef2e5 | 867 | int n_ev) |
4574910e | 868 | { |
448d64f8 | 869 | unsigned long mask, value, nv; |
cdd6c482 IM |
870 | unsigned long smasks[MAX_HWEVENTS], svalues[MAX_HWEVENTS]; |
871 | int n_alt[MAX_HWEVENTS], choice[MAX_HWEVENTS]; | |
4574910e | 872 | int i, j; |
448d64f8 PM |
873 | unsigned long addf = ppmu->add_fields; |
874 | unsigned long tadd = ppmu->test_adder; | |
4574910e | 875 | |
a8f90e90 | 876 | if (n_ev > ppmu->n_counter) |
4574910e PM |
877 | return -1; |
878 | ||
879 | /* First see if the events will go on as-is */ | |
880 | for (i = 0; i < n_ev; ++i) { | |
ab7ef2e5 | 881 | if ((cflags[i] & PPMU_LIMITED_PMC_REQD) |
cdd6c482 IM |
882 | && !ppmu->limited_pmc_event(event_id[i])) { |
883 | ppmu->get_alternatives(event_id[i], cflags[i], | |
e51ee31e | 884 | cpuhw->alternatives[i]); |
cdd6c482 | 885 | event_id[i] = cpuhw->alternatives[i][0]; |
ab7ef2e5 | 886 | } |
cdd6c482 | 887 | if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0], |
e51ee31e | 888 | &cpuhw->avalues[i][0])) |
4574910e | 889 | return -1; |
4574910e PM |
890 | } |
891 | value = mask = 0; | |
892 | for (i = 0; i < n_ev; ++i) { | |
e51ee31e PM |
893 | nv = (value | cpuhw->avalues[i][0]) + |
894 | (value & cpuhw->avalues[i][0] & addf); | |
4574910e | 895 | if ((((nv + tadd) ^ value) & mask) != 0 || |
e51ee31e PM |
896 | (((nv + tadd) ^ cpuhw->avalues[i][0]) & |
897 | cpuhw->amasks[i][0]) != 0) | |
4574910e PM |
898 | break; |
899 | value = nv; | |
e51ee31e | 900 | mask |= cpuhw->amasks[i][0]; |
4574910e PM |
901 | } |
902 | if (i == n_ev) | |
903 | return 0; /* all OK */ | |
904 | ||
905 | /* doesn't work, gather alternatives... */ | |
906 | if (!ppmu->get_alternatives) | |
907 | return -1; | |
908 | for (i = 0; i < n_ev; ++i) { | |
ab7ef2e5 | 909 | choice[i] = 0; |
cdd6c482 | 910 | n_alt[i] = ppmu->get_alternatives(event_id[i], cflags[i], |
e51ee31e | 911 | cpuhw->alternatives[i]); |
4574910e | 912 | for (j = 1; j < n_alt[i]; ++j) |
e51ee31e PM |
913 | ppmu->get_constraint(cpuhw->alternatives[i][j], |
914 | &cpuhw->amasks[i][j], | |
915 | &cpuhw->avalues[i][j]); | |
4574910e PM |
916 | } |
917 | ||
918 | /* enumerate all possibilities and see if any will work */ | |
919 | i = 0; | |
920 | j = -1; | |
921 | value = mask = nv = 0; | |
922 | while (i < n_ev) { | |
923 | if (j >= 0) { | |
924 | /* we're backtracking, restore context */ | |
925 | value = svalues[i]; | |
926 | mask = smasks[i]; | |
927 | j = choice[i]; | |
928 | } | |
929 | /* | |
cdd6c482 | 930 | * See if any alternative k for event_id i, |
4574910e PM |
931 | * where k > j, will satisfy the constraints. |
932 | */ | |
933 | while (++j < n_alt[i]) { | |
e51ee31e PM |
934 | nv = (value | cpuhw->avalues[i][j]) + |
935 | (value & cpuhw->avalues[i][j] & addf); | |
4574910e | 936 | if ((((nv + tadd) ^ value) & mask) == 0 && |
e51ee31e PM |
937 | (((nv + tadd) ^ cpuhw->avalues[i][j]) |
938 | & cpuhw->amasks[i][j]) == 0) | |
4574910e PM |
939 | break; |
940 | } | |
941 | if (j >= n_alt[i]) { | |
942 | /* | |
943 | * No feasible alternative, backtrack | |
cdd6c482 | 944 | * to event_id i-1 and continue enumerating its |
4574910e PM |
945 | * alternatives from where we got up to. |
946 | */ | |
947 | if (--i < 0) | |
948 | return -1; | |
949 | } else { | |
950 | /* | |
cdd6c482 IM |
951 | * Found a feasible alternative for event_id i, |
952 | * remember where we got up to with this event_id, | |
953 | * go on to the next event_id, and start with | |
4574910e PM |
954 | * the first alternative for it. |
955 | */ | |
956 | choice[i] = j; | |
957 | svalues[i] = value; | |
958 | smasks[i] = mask; | |
959 | value = nv; | |
e51ee31e | 960 | mask |= cpuhw->amasks[i][j]; |
4574910e PM |
961 | ++i; |
962 | j = -1; | |
963 | } | |
964 | } | |
965 | ||
966 | /* OK, we have a feasible combination, tell the caller the solution */ | |
967 | for (i = 0; i < n_ev; ++i) | |
cdd6c482 | 968 | event_id[i] = cpuhw->alternatives[i][choice[i]]; |
4574910e PM |
969 | return 0; |
970 | } | |
971 | ||
0475f9ea | 972 | /* |
cdd6c482 | 973 | * Check if newly-added events have consistent settings for |
0475f9ea | 974 | * exclude_{user,kernel,hv} with each other and any previously |
cdd6c482 | 975 | * added events. |
0475f9ea | 976 | */ |
cdd6c482 | 977 | static int check_excludes(struct perf_event **ctrs, unsigned int cflags[], |
ab7ef2e5 | 978 | int n_prev, int n_new) |
0475f9ea | 979 | { |
ab7ef2e5 PM |
980 | int eu = 0, ek = 0, eh = 0; |
981 | int i, n, first; | |
cdd6c482 | 982 | struct perf_event *event; |
0475f9ea | 983 | |
9de5cb0f ME |
984 | /* |
985 | * If the PMU we're on supports per event exclude settings then we | |
986 | * don't need to do any of this logic. NB. This assumes no PMU has both | |
987 | * per event exclude and limited PMCs. | |
988 | */ | |
989 | if (ppmu->flags & PPMU_ARCH_207S) | |
990 | return 0; | |
991 | ||
0475f9ea PM |
992 | n = n_prev + n_new; |
993 | if (n <= 1) | |
994 | return 0; | |
995 | ||
ab7ef2e5 PM |
996 | first = 1; |
997 | for (i = 0; i < n; ++i) { | |
998 | if (cflags[i] & PPMU_LIMITED_PMC_OK) { | |
999 | cflags[i] &= ~PPMU_LIMITED_PMC_REQD; | |
1000 | continue; | |
1001 | } | |
cdd6c482 | 1002 | event = ctrs[i]; |
ab7ef2e5 | 1003 | if (first) { |
cdd6c482 IM |
1004 | eu = event->attr.exclude_user; |
1005 | ek = event->attr.exclude_kernel; | |
1006 | eh = event->attr.exclude_hv; | |
ab7ef2e5 | 1007 | first = 0; |
cdd6c482 IM |
1008 | } else if (event->attr.exclude_user != eu || |
1009 | event->attr.exclude_kernel != ek || | |
1010 | event->attr.exclude_hv != eh) { | |
0475f9ea | 1011 | return -EAGAIN; |
ab7ef2e5 | 1012 | } |
0475f9ea | 1013 | } |
ab7ef2e5 PM |
1014 | |
1015 | if (eu || ek || eh) | |
1016 | for (i = 0; i < n; ++i) | |
1017 | if (cflags[i] & PPMU_LIMITED_PMC_OK) | |
1018 | cflags[i] |= PPMU_LIMITED_PMC_REQD; | |
1019 | ||
0475f9ea PM |
1020 | return 0; |
1021 | } | |
1022 | ||
86c74ab3 EM |
1023 | static u64 check_and_compute_delta(u64 prev, u64 val) |
1024 | { | |
1025 | u64 delta = (val - prev) & 0xfffffffful; | |
1026 | ||
1027 | /* | |
1028 | * POWER7 can roll back counter values, if the new value is smaller | |
1029 | * than the previous value it will cause the delta and the counter to | |
1030 | * have bogus values unless we rolled a counter over. If a coutner is | |
1031 | * rolled back, it will be smaller, but within 256, which is the maximum | |
027dfac6 | 1032 | * number of events to rollback at once. If we detect a rollback |
86c74ab3 EM |
1033 | * return 0. This can lead to a small lack of precision in the |
1034 | * counters. | |
1035 | */ | |
1036 | if (prev > val && (prev - val) < 256) | |
1037 | delta = 0; | |
1038 | ||
1039 | return delta; | |
1040 | } | |
1041 | ||
cdd6c482 | 1042 | static void power_pmu_read(struct perf_event *event) |
4574910e | 1043 | { |
98fb1807 | 1044 | s64 val, delta, prev; |
356d8ce3 | 1045 | struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); |
4574910e | 1046 | |
a4eaf7f1 PZ |
1047 | if (event->hw.state & PERF_HES_STOPPED) |
1048 | return; | |
1049 | ||
cdd6c482 | 1050 | if (!event->hw.idx) |
4574910e | 1051 | return; |
330a1eb7 ME |
1052 | |
1053 | if (is_ebb_event(event)) { | |
1054 | val = read_pmc(event->hw.idx); | |
356d8ce3 MS |
1055 | if (use_ic(event->attr.config)) { |
1056 | val = mfspr(SPRN_IC); | |
1057 | if (val > cpuhw->ic_init) | |
1058 | val = val - cpuhw->ic_init; | |
1059 | else | |
1060 | val = val + (0 - cpuhw->ic_init); | |
1061 | } | |
330a1eb7 ME |
1062 | local64_set(&event->hw.prev_count, val); |
1063 | return; | |
1064 | } | |
1065 | ||
4574910e PM |
1066 | /* |
1067 | * Performance monitor interrupts come even when interrupts | |
1068 | * are soft-disabled, as long as interrupts are hard-enabled. | |
1069 | * Therefore we treat them like NMIs. | |
1070 | */ | |
1071 | do { | |
e7850595 | 1072 | prev = local64_read(&event->hw.prev_count); |
4574910e | 1073 | barrier(); |
cdd6c482 | 1074 | val = read_pmc(event->hw.idx); |
356d8ce3 MS |
1075 | if (use_ic(event->attr.config)) { |
1076 | val = mfspr(SPRN_IC); | |
1077 | if (val > cpuhw->ic_init) | |
1078 | val = val - cpuhw->ic_init; | |
1079 | else | |
1080 | val = val + (0 - cpuhw->ic_init); | |
1081 | } | |
86c74ab3 EM |
1082 | delta = check_and_compute_delta(prev, val); |
1083 | if (!delta) | |
1084 | return; | |
e7850595 | 1085 | } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev); |
4574910e | 1086 | |
e7850595 | 1087 | local64_add(delta, &event->count); |
f5602941 AB |
1088 | |
1089 | /* | |
1090 | * A number of places program the PMC with (0x80000000 - period_left). | |
1091 | * We never want period_left to be less than 1 because we will program | |
1092 | * the PMC with a value >= 0x800000000 and an edge detected PMC will | |
1093 | * roll around to 0 before taking an exception. We have seen this | |
1094 | * on POWER8. | |
1095 | * | |
1096 | * To fix this, clamp the minimum value of period_left to 1. | |
1097 | */ | |
1098 | do { | |
1099 | prev = local64_read(&event->hw.period_left); | |
1100 | val = prev - delta; | |
1101 | if (val < 1) | |
1102 | val = 1; | |
1103 | } while (local64_cmpxchg(&event->hw.period_left, prev, val) != prev); | |
4574910e PM |
1104 | } |
1105 | ||
ab7ef2e5 PM |
1106 | /* |
1107 | * On some machines, PMC5 and PMC6 can't be written, don't respect | |
1108 | * the freeze conditions, and don't generate interrupts. This tells | |
cdd6c482 | 1109 | * us if `event' is using such a PMC. |
ab7ef2e5 PM |
1110 | */ |
1111 | static int is_limited_pmc(int pmcnum) | |
1112 | { | |
0bbd0d4b PM |
1113 | return (ppmu->flags & PPMU_LIMITED_PMC5_6) |
1114 | && (pmcnum == 5 || pmcnum == 6); | |
ab7ef2e5 PM |
1115 | } |
1116 | ||
a8f90e90 | 1117 | static void freeze_limited_counters(struct cpu_hw_events *cpuhw, |
ab7ef2e5 PM |
1118 | unsigned long pmc5, unsigned long pmc6) |
1119 | { | |
cdd6c482 | 1120 | struct perf_event *event; |
ab7ef2e5 PM |
1121 | u64 val, prev, delta; |
1122 | int i; | |
1123 | ||
1124 | for (i = 0; i < cpuhw->n_limited; ++i) { | |
a8f90e90 | 1125 | event = cpuhw->limited_counter[i]; |
cdd6c482 | 1126 | if (!event->hw.idx) |
ab7ef2e5 | 1127 | continue; |
cdd6c482 | 1128 | val = (event->hw.idx == 5) ? pmc5 : pmc6; |
e7850595 | 1129 | prev = local64_read(&event->hw.prev_count); |
cdd6c482 | 1130 | event->hw.idx = 0; |
86c74ab3 EM |
1131 | delta = check_and_compute_delta(prev, val); |
1132 | if (delta) | |
1133 | local64_add(delta, &event->count); | |
ab7ef2e5 PM |
1134 | } |
1135 | } | |
1136 | ||
a8f90e90 | 1137 | static void thaw_limited_counters(struct cpu_hw_events *cpuhw, |
ab7ef2e5 PM |
1138 | unsigned long pmc5, unsigned long pmc6) |
1139 | { | |
cdd6c482 | 1140 | struct perf_event *event; |
86c74ab3 | 1141 | u64 val, prev; |
ab7ef2e5 PM |
1142 | int i; |
1143 | ||
1144 | for (i = 0; i < cpuhw->n_limited; ++i) { | |
a8f90e90 | 1145 | event = cpuhw->limited_counter[i]; |
cdd6c482 IM |
1146 | event->hw.idx = cpuhw->limited_hwidx[i]; |
1147 | val = (event->hw.idx == 5) ? pmc5 : pmc6; | |
86c74ab3 EM |
1148 | prev = local64_read(&event->hw.prev_count); |
1149 | if (check_and_compute_delta(prev, val)) | |
1150 | local64_set(&event->hw.prev_count, val); | |
cdd6c482 | 1151 | perf_event_update_userpage(event); |
ab7ef2e5 PM |
1152 | } |
1153 | } | |
1154 | ||
1155 | /* | |
cdd6c482 | 1156 | * Since limited events don't respect the freeze conditions, we |
ab7ef2e5 | 1157 | * have to read them immediately after freezing or unfreezing the |
cdd6c482 IM |
1158 | * other events. We try to keep the values from the limited |
1159 | * events as consistent as possible by keeping the delay (in | |
ab7ef2e5 | 1160 | * cycles and instructions) between freezing/unfreezing and reading |
cdd6c482 IM |
1161 | * the limited events as small and consistent as possible. |
1162 | * Therefore, if any limited events are in use, we read them | |
ab7ef2e5 PM |
1163 | * both, and always in the same order, to minimize variability, |
1164 | * and do it inside the same asm that writes MMCR0. | |
1165 | */ | |
cdd6c482 | 1166 | static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0) |
ab7ef2e5 PM |
1167 | { |
1168 | unsigned long pmc5, pmc6; | |
1169 | ||
1170 | if (!cpuhw->n_limited) { | |
1171 | mtspr(SPRN_MMCR0, mmcr0); | |
1172 | return; | |
1173 | } | |
1174 | ||
1175 | /* | |
1176 | * Write MMCR0, then read PMC5 and PMC6 immediately. | |
dcd945e0 PM |
1177 | * To ensure we don't get a performance monitor interrupt |
1178 | * between writing MMCR0 and freezing/thawing the limited | |
cdd6c482 | 1179 | * events, we first write MMCR0 with the event overflow |
dcd945e0 | 1180 | * interrupt enable bits turned off. |
ab7ef2e5 PM |
1181 | */ |
1182 | asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5" | |
1183 | : "=&r" (pmc5), "=&r" (pmc6) | |
dcd945e0 PM |
1184 | : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)), |
1185 | "i" (SPRN_MMCR0), | |
ab7ef2e5 PM |
1186 | "i" (SPRN_PMC5), "i" (SPRN_PMC6)); |
1187 | ||
1188 | if (mmcr0 & MMCR0_FC) | |
a8f90e90 | 1189 | freeze_limited_counters(cpuhw, pmc5, pmc6); |
ab7ef2e5 | 1190 | else |
a8f90e90 | 1191 | thaw_limited_counters(cpuhw, pmc5, pmc6); |
dcd945e0 PM |
1192 | |
1193 | /* | |
cdd6c482 | 1194 | * Write the full MMCR0 including the event overflow interrupt |
dcd945e0 PM |
1195 | * enable bits, if necessary. |
1196 | */ | |
1197 | if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE)) | |
1198 | mtspr(SPRN_MMCR0, mmcr0); | |
ab7ef2e5 PM |
1199 | } |
1200 | ||
4574910e | 1201 | /* |
cdd6c482 IM |
1202 | * Disable all events to prevent PMU interrupts and to allow |
1203 | * events to be added or removed. | |
4574910e | 1204 | */ |
a4eaf7f1 | 1205 | static void power_pmu_disable(struct pmu *pmu) |
4574910e | 1206 | { |
cdd6c482 | 1207 | struct cpu_hw_events *cpuhw; |
330a1eb7 | 1208 | unsigned long flags, mmcr0, val; |
4574910e | 1209 | |
f36a1a13 PM |
1210 | if (!ppmu) |
1211 | return; | |
4574910e | 1212 | local_irq_save(flags); |
69111bac | 1213 | cpuhw = this_cpu_ptr(&cpu_hw_events); |
4574910e | 1214 | |
448d64f8 | 1215 | if (!cpuhw->disabled) { |
01d0287f PM |
1216 | /* |
1217 | * Check if we ever enabled the PMU on this cpu. | |
1218 | */ | |
1219 | if (!cpuhw->pmcs_enabled) { | |
a6dbf93a | 1220 | ppc_enable_pmcs(); |
01d0287f PM |
1221 | cpuhw->pmcs_enabled = 1; |
1222 | } | |
1223 | ||
378a6ee9 | 1224 | /* |
76cb8a78 | 1225 | * Set the 'freeze counters' bit, clear EBE/BHRBA/PMCC/PMAO/FC56 |
378a6ee9 | 1226 | */ |
330a1eb7 | 1227 | val = mmcr0 = mfspr(SPRN_MMCR0); |
378a6ee9 | 1228 | val |= MMCR0_FC; |
76cb8a78 ME |
1229 | val &= ~(MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC | MMCR0_PMAO | |
1230 | MMCR0_FC56); | |
378a6ee9 ME |
1231 | |
1232 | /* | |
1233 | * The barrier is to make sure the mtspr has been | |
1234 | * executed and the PMU has frozen the events etc. | |
1235 | * before we return. | |
1236 | */ | |
1237 | write_mmcr0(cpuhw, val); | |
1238 | mb(); | |
04099570 | 1239 | isync(); |
378a6ee9 | 1240 | |
f708223d PM |
1241 | /* |
1242 | * Disable instruction sampling if it was enabled | |
1243 | */ | |
1244 | if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { | |
1245 | mtspr(SPRN_MMCRA, | |
1246 | cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); | |
1247 | mb(); | |
04099570 | 1248 | isync(); |
f708223d PM |
1249 | } |
1250 | ||
378a6ee9 ME |
1251 | cpuhw->disabled = 1; |
1252 | cpuhw->n_added = 0; | |
330a1eb7 ME |
1253 | |
1254 | ebb_switch_out(mmcr0); | |
04099570 ME |
1255 | |
1256 | #ifdef CONFIG_PPC64 | |
1257 | /* | |
1258 | * These are readable by userspace, may contain kernel | |
1259 | * addresses and are not switched by context switch, so clear | |
1260 | * them now to avoid leaking anything to userspace in general | |
1261 | * including to another process. | |
1262 | */ | |
1263 | if (ppmu->flags & PPMU_ARCH_207S) { | |
1264 | mtspr(SPRN_SDAR, 0); | |
1265 | mtspr(SPRN_SIAR, 0); | |
1266 | } | |
1267 | #endif | |
4574910e | 1268 | } |
330a1eb7 | 1269 | |
4574910e | 1270 | local_irq_restore(flags); |
4574910e PM |
1271 | } |
1272 | ||
1273 | /* | |
cdd6c482 IM |
1274 | * Re-enable all events if disable == 0. |
1275 | * If we were previously disabled and events were added, then | |
4574910e PM |
1276 | * put the new config on the PMU. |
1277 | */ | |
a4eaf7f1 | 1278 | static void power_pmu_enable(struct pmu *pmu) |
4574910e | 1279 | { |
cdd6c482 IM |
1280 | struct perf_event *event; |
1281 | struct cpu_hw_events *cpuhw; | |
4574910e PM |
1282 | unsigned long flags; |
1283 | long i; | |
330a1eb7 | 1284 | unsigned long val, mmcr0; |
4574910e | 1285 | s64 left; |
cdd6c482 | 1286 | unsigned int hwc_index[MAX_HWEVENTS]; |
ab7ef2e5 PM |
1287 | int n_lim; |
1288 | int idx; | |
330a1eb7 | 1289 | bool ebb; |
4574910e | 1290 | |
f36a1a13 PM |
1291 | if (!ppmu) |
1292 | return; | |
4574910e | 1293 | local_irq_save(flags); |
0a48843d | 1294 | |
69111bac | 1295 | cpuhw = this_cpu_ptr(&cpu_hw_events); |
0a48843d ME |
1296 | if (!cpuhw->disabled) |
1297 | goto out; | |
1298 | ||
4ea355b5 ME |
1299 | if (cpuhw->n_events == 0) { |
1300 | ppc_set_pmu_inuse(0); | |
1301 | goto out; | |
1302 | } | |
1303 | ||
4574910e PM |
1304 | cpuhw->disabled = 0; |
1305 | ||
330a1eb7 ME |
1306 | /* |
1307 | * EBB requires an exclusive group and all events must have the EBB | |
1308 | * flag set, or not set, so we can just check a single event. Also we | |
1309 | * know we have at least one event. | |
1310 | */ | |
1311 | ebb = is_ebb_event(cpuhw->event[0]); | |
1312 | ||
4574910e | 1313 | /* |
cdd6c482 | 1314 | * If we didn't change anything, or only removed events, |
4574910e PM |
1315 | * no need to recalculate MMCR* settings and reset the PMCs. |
1316 | * Just reenable the PMU with the current MMCR* settings | |
cdd6c482 | 1317 | * (possibly updated for removal of events). |
4574910e PM |
1318 | */ |
1319 | if (!cpuhw->n_added) { | |
f708223d | 1320 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); |
4574910e | 1321 | mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); |
f708223d | 1322 | goto out_enable; |
4574910e PM |
1323 | } |
1324 | ||
1325 | /* | |
79a4cb28 | 1326 | * Clear all MMCR settings and recompute them for the new set of events. |
4574910e | 1327 | */ |
79a4cb28 ME |
1328 | memset(cpuhw->mmcr, 0, sizeof(cpuhw->mmcr)); |
1329 | ||
cdd6c482 | 1330 | if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index, |
8abd818f | 1331 | cpuhw->mmcr, cpuhw->event)) { |
4574910e PM |
1332 | /* shouldn't ever get here */ |
1333 | printk(KERN_ERR "oops compute_mmcr failed\n"); | |
1334 | goto out; | |
1335 | } | |
1336 | ||
9de5cb0f ME |
1337 | if (!(ppmu->flags & PPMU_ARCH_207S)) { |
1338 | /* | |
1339 | * Add in MMCR0 freeze bits corresponding to the attr.exclude_* | |
1340 | * bits for the first event. We have already checked that all | |
1341 | * events have the same value for these bits as the first event. | |
1342 | */ | |
1343 | event = cpuhw->event[0]; | |
1344 | if (event->attr.exclude_user) | |
1345 | cpuhw->mmcr[0] |= MMCR0_FCP; | |
1346 | if (event->attr.exclude_kernel) | |
1347 | cpuhw->mmcr[0] |= freeze_events_kernel; | |
1348 | if (event->attr.exclude_hv) | |
1349 | cpuhw->mmcr[0] |= MMCR0_FCHV; | |
1350 | } | |
0475f9ea | 1351 | |
4574910e PM |
1352 | /* |
1353 | * Write the new configuration to MMCR* with the freeze | |
cdd6c482 IM |
1354 | * bit set and set the hardware events to their initial values. |
1355 | * Then unfreeze the events. | |
4574910e | 1356 | */ |
a6dbf93a | 1357 | ppc_set_pmu_inuse(1); |
f708223d | 1358 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); |
4574910e PM |
1359 | mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); |
1360 | mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)) | |
1361 | | MMCR0_FC); | |
9de5cb0f ME |
1362 | if (ppmu->flags & PPMU_ARCH_207S) |
1363 | mtspr(SPRN_MMCR2, cpuhw->mmcr[3]); | |
4574910e PM |
1364 | |
1365 | /* | |
cdd6c482 | 1366 | * Read off any pre-existing events that need to move |
4574910e PM |
1367 | * to another PMC. |
1368 | */ | |
cdd6c482 IM |
1369 | for (i = 0; i < cpuhw->n_events; ++i) { |
1370 | event = cpuhw->event[i]; | |
1371 | if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) { | |
1372 | power_pmu_read(event); | |
1373 | write_pmc(event->hw.idx, 0); | |
1374 | event->hw.idx = 0; | |
4574910e PM |
1375 | } |
1376 | } | |
1377 | ||
1378 | /* | |
cdd6c482 | 1379 | * Initialize the PMCs for all the new and moved events. |
4574910e | 1380 | */ |
ab7ef2e5 | 1381 | cpuhw->n_limited = n_lim = 0; |
cdd6c482 IM |
1382 | for (i = 0; i < cpuhw->n_events; ++i) { |
1383 | event = cpuhw->event[i]; | |
1384 | if (event->hw.idx) | |
4574910e | 1385 | continue; |
ab7ef2e5 PM |
1386 | idx = hwc_index[i] + 1; |
1387 | if (is_limited_pmc(idx)) { | |
a8f90e90 | 1388 | cpuhw->limited_counter[n_lim] = event; |
ab7ef2e5 PM |
1389 | cpuhw->limited_hwidx[n_lim] = idx; |
1390 | ++n_lim; | |
1391 | continue; | |
1392 | } | |
330a1eb7 ME |
1393 | |
1394 | if (ebb) | |
1395 | val = local64_read(&event->hw.prev_count); | |
1396 | else { | |
1397 | val = 0; | |
1398 | if (event->hw.sample_period) { | |
1399 | left = local64_read(&event->hw.period_left); | |
1400 | if (left < 0x80000000L) | |
1401 | val = 0x80000000L - left; | |
1402 | } | |
1403 | local64_set(&event->hw.prev_count, val); | |
4574910e | 1404 | } |
330a1eb7 | 1405 | |
cdd6c482 | 1406 | event->hw.idx = idx; |
a4eaf7f1 PZ |
1407 | if (event->hw.state & PERF_HES_STOPPED) |
1408 | val = 0; | |
ab7ef2e5 | 1409 | write_pmc(idx, val); |
330a1eb7 | 1410 | |
cdd6c482 | 1411 | perf_event_update_userpage(event); |
4574910e | 1412 | } |
ab7ef2e5 | 1413 | cpuhw->n_limited = n_lim; |
4574910e | 1414 | cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE; |
f708223d PM |
1415 | |
1416 | out_enable: | |
c2e37a26 ME |
1417 | pmao_restore_workaround(ebb); |
1418 | ||
9de5cb0f | 1419 | mmcr0 = ebb_switch_in(ebb, cpuhw); |
330a1eb7 | 1420 | |
f708223d | 1421 | mb(); |
b4d6c06c AK |
1422 | if (cpuhw->bhrb_users) |
1423 | ppmu->config_bhrb(cpuhw->bhrb_filter); | |
1424 | ||
330a1eb7 | 1425 | write_mmcr0(cpuhw, mmcr0); |
4574910e | 1426 | |
f708223d PM |
1427 | /* |
1428 | * Enable instruction sampling if necessary | |
1429 | */ | |
1430 | if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { | |
1431 | mb(); | |
1432 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2]); | |
1433 | } | |
1434 | ||
4574910e | 1435 | out: |
3925f46b | 1436 | |
4574910e PM |
1437 | local_irq_restore(flags); |
1438 | } | |
1439 | ||
cdd6c482 IM |
1440 | static int collect_events(struct perf_event *group, int max_count, |
1441 | struct perf_event *ctrs[], u64 *events, | |
ab7ef2e5 | 1442 | unsigned int *flags) |
4574910e PM |
1443 | { |
1444 | int n = 0; | |
cdd6c482 | 1445 | struct perf_event *event; |
4574910e | 1446 | |
5aa04b3e | 1447 | if (group->pmu->task_ctx_nr == perf_hw_context) { |
4574910e PM |
1448 | if (n >= max_count) |
1449 | return -1; | |
1450 | ctrs[n] = group; | |
cdd6c482 | 1451 | flags[n] = group->hw.event_base; |
4574910e PM |
1452 | events[n++] = group->hw.config; |
1453 | } | |
a8f90e90 | 1454 | list_for_each_entry(event, &group->sibling_list, group_entry) { |
5aa04b3e | 1455 | if (event->pmu->task_ctx_nr == perf_hw_context && |
cdd6c482 | 1456 | event->state != PERF_EVENT_STATE_OFF) { |
4574910e PM |
1457 | if (n >= max_count) |
1458 | return -1; | |
cdd6c482 IM |
1459 | ctrs[n] = event; |
1460 | flags[n] = event->hw.event_base; | |
1461 | events[n++] = event->hw.config; | |
4574910e PM |
1462 | } |
1463 | } | |
1464 | return n; | |
1465 | } | |
1466 | ||
4574910e | 1467 | /* |
cdd6c482 IM |
1468 | * Add a event to the PMU. |
1469 | * If all events are not already frozen, then we disable and | |
9e35ad38 | 1470 | * re-enable the PMU in order to get hw_perf_enable to do the |
4574910e PM |
1471 | * actual work of reconfiguring the PMU. |
1472 | */ | |
a4eaf7f1 | 1473 | static int power_pmu_add(struct perf_event *event, int ef_flags) |
4574910e | 1474 | { |
cdd6c482 | 1475 | struct cpu_hw_events *cpuhw; |
4574910e | 1476 | unsigned long flags; |
4574910e PM |
1477 | int n0; |
1478 | int ret = -EAGAIN; | |
1479 | ||
1480 | local_irq_save(flags); | |
33696fc0 | 1481 | perf_pmu_disable(event->pmu); |
4574910e PM |
1482 | |
1483 | /* | |
cdd6c482 | 1484 | * Add the event to the list (if there is room) |
4574910e PM |
1485 | * and check whether the total set is still feasible. |
1486 | */ | |
69111bac | 1487 | cpuhw = this_cpu_ptr(&cpu_hw_events); |
cdd6c482 | 1488 | n0 = cpuhw->n_events; |
a8f90e90 | 1489 | if (n0 >= ppmu->n_counter) |
4574910e | 1490 | goto out; |
cdd6c482 IM |
1491 | cpuhw->event[n0] = event; |
1492 | cpuhw->events[n0] = event->hw.config; | |
1493 | cpuhw->flags[n0] = event->hw.event_base; | |
8e6d5573 | 1494 | |
f53d168c | 1495 | /* |
1496 | * This event may have been disabled/stopped in record_and_restart() | |
1497 | * because we exceeded the ->event_limit. If re-starting the event, | |
1498 | * clear the ->hw.state (STOPPED and UPTODATE flags), so the user | |
1499 | * notification is re-enabled. | |
1500 | */ | |
a4eaf7f1 PZ |
1501 | if (!(ef_flags & PERF_EF_START)) |
1502 | event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE; | |
f53d168c | 1503 | else |
1504 | event->hw.state = 0; | |
a4eaf7f1 | 1505 | |
8e6d5573 LM |
1506 | /* |
1507 | * If group events scheduling transaction was started, | |
25985edc | 1508 | * skip the schedulability test here, it will be performed |
8e6d5573 LM |
1509 | * at commit time(->commit_txn) as a whole |
1510 | */ | |
8f3e5684 | 1511 | if (cpuhw->txn_flags & PERF_PMU_TXN_ADD) |
8e6d5573 LM |
1512 | goto nocheck; |
1513 | ||
cdd6c482 | 1514 | if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1)) |
0475f9ea | 1515 | goto out; |
e51ee31e | 1516 | if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1)) |
4574910e | 1517 | goto out; |
cdd6c482 | 1518 | event->hw.config = cpuhw->events[n0]; |
8e6d5573 LM |
1519 | |
1520 | nocheck: | |
330a1eb7 ME |
1521 | ebb_event_add(event); |
1522 | ||
cdd6c482 | 1523 | ++cpuhw->n_events; |
4574910e PM |
1524 | ++cpuhw->n_added; |
1525 | ||
1526 | ret = 0; | |
1527 | out: | |
ff3d79dc | 1528 | if (has_branch_stack(event)) { |
3925f46b | 1529 | power_pmu_bhrb_enable(event); |
ff3d79dc AK |
1530 | cpuhw->bhrb_filter = ppmu->bhrb_filter_map( |
1531 | event->attr.branch_sample_type); | |
1532 | } | |
3925f46b | 1533 | |
356d8ce3 MS |
1534 | /* |
1535 | * Workaround for POWER9 DD1 to use the Instruction Counter | |
1536 | * register value for instruction counting | |
1537 | */ | |
1538 | if (use_ic(event->attr.config)) | |
1539 | cpuhw->ic_init = mfspr(SPRN_IC); | |
1540 | ||
33696fc0 | 1541 | perf_pmu_enable(event->pmu); |
4574910e PM |
1542 | local_irq_restore(flags); |
1543 | return ret; | |
1544 | } | |
1545 | ||
1546 | /* | |
cdd6c482 | 1547 | * Remove a event from the PMU. |
4574910e | 1548 | */ |
a4eaf7f1 | 1549 | static void power_pmu_del(struct perf_event *event, int ef_flags) |
4574910e | 1550 | { |
cdd6c482 | 1551 | struct cpu_hw_events *cpuhw; |
4574910e | 1552 | long i; |
4574910e PM |
1553 | unsigned long flags; |
1554 | ||
1555 | local_irq_save(flags); | |
33696fc0 | 1556 | perf_pmu_disable(event->pmu); |
4574910e | 1557 | |
cdd6c482 IM |
1558 | power_pmu_read(event); |
1559 | ||
69111bac | 1560 | cpuhw = this_cpu_ptr(&cpu_hw_events); |
cdd6c482 IM |
1561 | for (i = 0; i < cpuhw->n_events; ++i) { |
1562 | if (event == cpuhw->event[i]) { | |
219a92a4 | 1563 | while (++i < cpuhw->n_events) { |
cdd6c482 | 1564 | cpuhw->event[i-1] = cpuhw->event[i]; |
219a92a4 ME |
1565 | cpuhw->events[i-1] = cpuhw->events[i]; |
1566 | cpuhw->flags[i-1] = cpuhw->flags[i]; | |
1567 | } | |
cdd6c482 IM |
1568 | --cpuhw->n_events; |
1569 | ppmu->disable_pmc(event->hw.idx - 1, cpuhw->mmcr); | |
1570 | if (event->hw.idx) { | |
1571 | write_pmc(event->hw.idx, 0); | |
1572 | event->hw.idx = 0; | |
ab7ef2e5 | 1573 | } |
cdd6c482 | 1574 | perf_event_update_userpage(event); |
4574910e PM |
1575 | break; |
1576 | } | |
1577 | } | |
ab7ef2e5 | 1578 | for (i = 0; i < cpuhw->n_limited; ++i) |
a8f90e90 | 1579 | if (event == cpuhw->limited_counter[i]) |
ab7ef2e5 PM |
1580 | break; |
1581 | if (i < cpuhw->n_limited) { | |
1582 | while (++i < cpuhw->n_limited) { | |
a8f90e90 | 1583 | cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i]; |
ab7ef2e5 PM |
1584 | cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i]; |
1585 | } | |
1586 | --cpuhw->n_limited; | |
1587 | } | |
cdd6c482 IM |
1588 | if (cpuhw->n_events == 0) { |
1589 | /* disable exceptions if no events are running */ | |
4574910e PM |
1590 | cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE); |
1591 | } | |
1592 | ||
3925f46b AK |
1593 | if (has_branch_stack(event)) |
1594 | power_pmu_bhrb_disable(event); | |
1595 | ||
33696fc0 | 1596 | perf_pmu_enable(event->pmu); |
4574910e PM |
1597 | local_irq_restore(flags); |
1598 | } | |
1599 | ||
8a7b8cb9 | 1600 | /* |
a4eaf7f1 PZ |
1601 | * POWER-PMU does not support disabling individual counters, hence |
1602 | * program their cycle counter to their max value and ignore the interrupts. | |
8a7b8cb9 | 1603 | */ |
a4eaf7f1 PZ |
1604 | |
1605 | static void power_pmu_start(struct perf_event *event, int ef_flags) | |
8a7b8cb9 | 1606 | { |
8a7b8cb9 | 1607 | unsigned long flags; |
a4eaf7f1 | 1608 | s64 left; |
9a45a940 | 1609 | unsigned long val; |
8a7b8cb9 | 1610 | |
cdd6c482 | 1611 | if (!event->hw.idx || !event->hw.sample_period) |
8a7b8cb9 | 1612 | return; |
a4eaf7f1 PZ |
1613 | |
1614 | if (!(event->hw.state & PERF_HES_STOPPED)) | |
1615 | return; | |
1616 | ||
1617 | if (ef_flags & PERF_EF_RELOAD) | |
1618 | WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); | |
1619 | ||
1620 | local_irq_save(flags); | |
1621 | perf_pmu_disable(event->pmu); | |
1622 | ||
1623 | event->hw.state = 0; | |
1624 | left = local64_read(&event->hw.period_left); | |
9a45a940 AB |
1625 | |
1626 | val = 0; | |
1627 | if (left < 0x80000000L) | |
1628 | val = 0x80000000L - left; | |
1629 | ||
1630 | write_pmc(event->hw.idx, val); | |
a4eaf7f1 PZ |
1631 | |
1632 | perf_event_update_userpage(event); | |
1633 | perf_pmu_enable(event->pmu); | |
1634 | local_irq_restore(flags); | |
1635 | } | |
1636 | ||
1637 | static void power_pmu_stop(struct perf_event *event, int ef_flags) | |
1638 | { | |
1639 | unsigned long flags; | |
1640 | ||
1641 | if (!event->hw.idx || !event->hw.sample_period) | |
1642 | return; | |
1643 | ||
1644 | if (event->hw.state & PERF_HES_STOPPED) | |
1645 | return; | |
1646 | ||
8a7b8cb9 | 1647 | local_irq_save(flags); |
33696fc0 | 1648 | perf_pmu_disable(event->pmu); |
a4eaf7f1 | 1649 | |
cdd6c482 | 1650 | power_pmu_read(event); |
a4eaf7f1 PZ |
1651 | event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; |
1652 | write_pmc(event->hw.idx, 0); | |
1653 | ||
cdd6c482 | 1654 | perf_event_update_userpage(event); |
33696fc0 | 1655 | perf_pmu_enable(event->pmu); |
8a7b8cb9 PM |
1656 | local_irq_restore(flags); |
1657 | } | |
1658 | ||
8e6d5573 LM |
1659 | /* |
1660 | * Start group events scheduling transaction | |
1661 | * Set the flag to make pmu::enable() not perform the | |
1662 | * schedulability test, it will be performed at commit time | |
fbbe0701 SB |
1663 | * |
1664 | * We only support PERF_PMU_TXN_ADD transactions. Save the | |
1665 | * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD | |
1666 | * transactions. | |
8e6d5573 | 1667 | */ |
fbbe0701 | 1668 | static void power_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags) |
8e6d5573 | 1669 | { |
69111bac | 1670 | struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); |
8e6d5573 | 1671 | |
fbbe0701 SB |
1672 | WARN_ON_ONCE(cpuhw->txn_flags); /* txn already in flight */ |
1673 | ||
1674 | cpuhw->txn_flags = txn_flags; | |
1675 | if (txn_flags & ~PERF_PMU_TXN_ADD) | |
1676 | return; | |
1677 | ||
33696fc0 | 1678 | perf_pmu_disable(pmu); |
8e6d5573 LM |
1679 | cpuhw->n_txn_start = cpuhw->n_events; |
1680 | } | |
1681 | ||
1682 | /* | |
1683 | * Stop group events scheduling transaction | |
1684 | * Clear the flag and pmu::enable() will perform the | |
1685 | * schedulability test. | |
1686 | */ | |
e51df2c1 | 1687 | static void power_pmu_cancel_txn(struct pmu *pmu) |
8e6d5573 | 1688 | { |
69111bac | 1689 | struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); |
fbbe0701 SB |
1690 | unsigned int txn_flags; |
1691 | ||
1692 | WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */ | |
1693 | ||
1694 | txn_flags = cpuhw->txn_flags; | |
1695 | cpuhw->txn_flags = 0; | |
1696 | if (txn_flags & ~PERF_PMU_TXN_ADD) | |
1697 | return; | |
8e6d5573 | 1698 | |
33696fc0 | 1699 | perf_pmu_enable(pmu); |
8e6d5573 LM |
1700 | } |
1701 | ||
1702 | /* | |
1703 | * Commit group events scheduling transaction | |
1704 | * Perform the group schedulability test as a whole | |
1705 | * Return 0 if success | |
1706 | */ | |
e51df2c1 | 1707 | static int power_pmu_commit_txn(struct pmu *pmu) |
8e6d5573 LM |
1708 | { |
1709 | struct cpu_hw_events *cpuhw; | |
1710 | long i, n; | |
1711 | ||
1712 | if (!ppmu) | |
1713 | return -EAGAIN; | |
fbbe0701 | 1714 | |
69111bac | 1715 | cpuhw = this_cpu_ptr(&cpu_hw_events); |
fbbe0701 SB |
1716 | WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */ |
1717 | ||
1718 | if (cpuhw->txn_flags & ~PERF_PMU_TXN_ADD) { | |
1719 | cpuhw->txn_flags = 0; | |
1720 | return 0; | |
1721 | } | |
1722 | ||
8e6d5573 LM |
1723 | n = cpuhw->n_events; |
1724 | if (check_excludes(cpuhw->event, cpuhw->flags, 0, n)) | |
1725 | return -EAGAIN; | |
1726 | i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n); | |
1727 | if (i < 0) | |
1728 | return -EAGAIN; | |
1729 | ||
1730 | for (i = cpuhw->n_txn_start; i < n; ++i) | |
1731 | cpuhw->event[i]->hw.config = cpuhw->events[i]; | |
1732 | ||
fbbe0701 | 1733 | cpuhw->txn_flags = 0; |
33696fc0 | 1734 | perf_pmu_enable(pmu); |
8e6d5573 LM |
1735 | return 0; |
1736 | } | |
1737 | ||
ab7ef2e5 | 1738 | /* |
cdd6c482 | 1739 | * Return 1 if we might be able to put event on a limited PMC, |
ab7ef2e5 | 1740 | * or 0 if not. |
cdd6c482 | 1741 | * A event can only go on a limited PMC if it counts something |
ab7ef2e5 PM |
1742 | * that a limited PMC can count, doesn't require interrupts, and |
1743 | * doesn't exclude any processor mode. | |
1744 | */ | |
cdd6c482 | 1745 | static int can_go_on_limited_pmc(struct perf_event *event, u64 ev, |
ab7ef2e5 PM |
1746 | unsigned int flags) |
1747 | { | |
1748 | int n; | |
ef923214 | 1749 | u64 alt[MAX_EVENT_ALTERNATIVES]; |
ab7ef2e5 | 1750 | |
cdd6c482 IM |
1751 | if (event->attr.exclude_user |
1752 | || event->attr.exclude_kernel | |
1753 | || event->attr.exclude_hv | |
1754 | || event->attr.sample_period) | |
ab7ef2e5 PM |
1755 | return 0; |
1756 | ||
1757 | if (ppmu->limited_pmc_event(ev)) | |
1758 | return 1; | |
1759 | ||
1760 | /* | |
cdd6c482 | 1761 | * The requested event_id isn't on a limited PMC already; |
ab7ef2e5 PM |
1762 | * see if any alternative code goes on a limited PMC. |
1763 | */ | |
1764 | if (!ppmu->get_alternatives) | |
1765 | return 0; | |
1766 | ||
1767 | flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD; | |
1768 | n = ppmu->get_alternatives(ev, flags, alt); | |
ab7ef2e5 | 1769 | |
ef923214 | 1770 | return n > 0; |
ab7ef2e5 PM |
1771 | } |
1772 | ||
1773 | /* | |
cdd6c482 IM |
1774 | * Find an alternative event_id that goes on a normal PMC, if possible, |
1775 | * and return the event_id code, or 0 if there is no such alternative. | |
1776 | * (Note: event_id code 0 is "don't count" on all machines.) | |
ab7ef2e5 | 1777 | */ |
ef923214 | 1778 | static u64 normal_pmc_alternative(u64 ev, unsigned long flags) |
ab7ef2e5 | 1779 | { |
ef923214 | 1780 | u64 alt[MAX_EVENT_ALTERNATIVES]; |
ab7ef2e5 PM |
1781 | int n; |
1782 | ||
1783 | flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD); | |
1784 | n = ppmu->get_alternatives(ev, flags, alt); | |
1785 | if (!n) | |
1786 | return 0; | |
1787 | return alt[0]; | |
1788 | } | |
1789 | ||
cdd6c482 IM |
1790 | /* Number of perf_events counting hardware events */ |
1791 | static atomic_t num_events; | |
7595d63b PM |
1792 | /* Used to avoid races in calling reserve/release_pmc_hardware */ |
1793 | static DEFINE_MUTEX(pmc_reserve_mutex); | |
1794 | ||
1795 | /* | |
cdd6c482 | 1796 | * Release the PMU if this is the last perf_event. |
7595d63b | 1797 | */ |
cdd6c482 | 1798 | static void hw_perf_event_destroy(struct perf_event *event) |
7595d63b | 1799 | { |
cdd6c482 | 1800 | if (!atomic_add_unless(&num_events, -1, 1)) { |
7595d63b | 1801 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 | 1802 | if (atomic_dec_return(&num_events) == 0) |
7595d63b PM |
1803 | release_pmc_hardware(); |
1804 | mutex_unlock(&pmc_reserve_mutex); | |
1805 | } | |
1806 | } | |
1807 | ||
106b506c | 1808 | /* |
cdd6c482 | 1809 | * Translate a generic cache event_id config to a raw event_id code. |
106b506c PM |
1810 | */ |
1811 | static int hw_perf_cache_event(u64 config, u64 *eventp) | |
1812 | { | |
1813 | unsigned long type, op, result; | |
1814 | int ev; | |
1815 | ||
1816 | if (!ppmu->cache_events) | |
1817 | return -EINVAL; | |
1818 | ||
1819 | /* unpack config */ | |
1820 | type = config & 0xff; | |
1821 | op = (config >> 8) & 0xff; | |
1822 | result = (config >> 16) & 0xff; | |
1823 | ||
1824 | if (type >= PERF_COUNT_HW_CACHE_MAX || | |
1825 | op >= PERF_COUNT_HW_CACHE_OP_MAX || | |
1826 | result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
1827 | return -EINVAL; | |
1828 | ||
1829 | ev = (*ppmu->cache_events)[type][op][result]; | |
1830 | if (ev == 0) | |
1831 | return -EOPNOTSUPP; | |
1832 | if (ev == -1) | |
1833 | return -EINVAL; | |
1834 | *eventp = ev; | |
1835 | return 0; | |
1836 | } | |
1837 | ||
b0a873eb | 1838 | static int power_pmu_event_init(struct perf_event *event) |
4574910e | 1839 | { |
ef923214 PM |
1840 | u64 ev; |
1841 | unsigned long flags; | |
cdd6c482 IM |
1842 | struct perf_event *ctrs[MAX_HWEVENTS]; |
1843 | u64 events[MAX_HWEVENTS]; | |
1844 | unsigned int cflags[MAX_HWEVENTS]; | |
4574910e | 1845 | int n; |
7595d63b | 1846 | int err; |
cdd6c482 | 1847 | struct cpu_hw_events *cpuhw; |
65fa6e17 | 1848 | u64 bhrb_filter; |
4574910e PM |
1849 | |
1850 | if (!ppmu) | |
b0a873eb PZ |
1851 | return -ENOENT; |
1852 | ||
3925f46b AK |
1853 | if (has_branch_stack(event)) { |
1854 | /* PMU has BHRB enabled */ | |
4d9690dd | 1855 | if (!(ppmu->flags & PPMU_ARCH_207S)) |
3925f46b AK |
1856 | return -EOPNOTSUPP; |
1857 | } | |
2481c5fa | 1858 | |
cdd6c482 | 1859 | switch (event->attr.type) { |
106b506c | 1860 | case PERF_TYPE_HARDWARE: |
cdd6c482 | 1861 | ev = event->attr.config; |
9aaa131a | 1862 | if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0) |
b0a873eb | 1863 | return -EOPNOTSUPP; |
4574910e | 1864 | ev = ppmu->generic_events[ev]; |
106b506c PM |
1865 | break; |
1866 | case PERF_TYPE_HW_CACHE: | |
cdd6c482 | 1867 | err = hw_perf_cache_event(event->attr.config, &ev); |
106b506c | 1868 | if (err) |
b0a873eb | 1869 | return err; |
106b506c PM |
1870 | break; |
1871 | case PERF_TYPE_RAW: | |
cdd6c482 | 1872 | ev = event->attr.config; |
106b506c | 1873 | break; |
90c8f954 | 1874 | default: |
b0a873eb | 1875 | return -ENOENT; |
4574910e | 1876 | } |
b0a873eb | 1877 | |
cdd6c482 IM |
1878 | event->hw.config_base = ev; |
1879 | event->hw.idx = 0; | |
4574910e | 1880 | |
0475f9ea PM |
1881 | /* |
1882 | * If we are not running on a hypervisor, force the | |
1883 | * exclude_hv bit to 0 so that we don't care what | |
d095cd46 | 1884 | * the user set it to. |
0475f9ea PM |
1885 | */ |
1886 | if (!firmware_has_feature(FW_FEATURE_LPAR)) | |
cdd6c482 | 1887 | event->attr.exclude_hv = 0; |
ab7ef2e5 PM |
1888 | |
1889 | /* | |
cdd6c482 | 1890 | * If this is a per-task event, then we can use |
ab7ef2e5 PM |
1891 | * PM_RUN_* events interchangeably with their non RUN_* |
1892 | * equivalents, e.g. PM_RUN_CYC instead of PM_CYC. | |
1893 | * XXX we should check if the task is an idle task. | |
1894 | */ | |
1895 | flags = 0; | |
57fa7214 | 1896 | if (event->attach_state & PERF_ATTACH_TASK) |
ab7ef2e5 PM |
1897 | flags |= PPMU_ONLY_COUNT_RUN; |
1898 | ||
1899 | /* | |
cdd6c482 IM |
1900 | * If this machine has limited events, check whether this |
1901 | * event_id could go on a limited event. | |
ab7ef2e5 | 1902 | */ |
0bbd0d4b | 1903 | if (ppmu->flags & PPMU_LIMITED_PMC5_6) { |
cdd6c482 | 1904 | if (can_go_on_limited_pmc(event, ev, flags)) { |
ab7ef2e5 PM |
1905 | flags |= PPMU_LIMITED_PMC_OK; |
1906 | } else if (ppmu->limited_pmc_event(ev)) { | |
1907 | /* | |
cdd6c482 | 1908 | * The requested event_id is on a limited PMC, |
ab7ef2e5 PM |
1909 | * but we can't use a limited PMC; see if any |
1910 | * alternative goes on a normal PMC. | |
1911 | */ | |
1912 | ev = normal_pmc_alternative(ev, flags); | |
1913 | if (!ev) | |
b0a873eb | 1914 | return -EINVAL; |
ab7ef2e5 PM |
1915 | } |
1916 | } | |
1917 | ||
330a1eb7 ME |
1918 | /* Extra checks for EBB */ |
1919 | err = ebb_event_check(event); | |
1920 | if (err) | |
1921 | return err; | |
1922 | ||
4574910e PM |
1923 | /* |
1924 | * If this is in a group, check if it can go on with all the | |
cdd6c482 | 1925 | * other hardware events in the group. We assume the event |
4574910e PM |
1926 | * hasn't been linked into its leader's sibling list at this point. |
1927 | */ | |
1928 | n = 0; | |
cdd6c482 | 1929 | if (event->group_leader != event) { |
a8f90e90 | 1930 | n = collect_events(event->group_leader, ppmu->n_counter - 1, |
ab7ef2e5 | 1931 | ctrs, events, cflags); |
4574910e | 1932 | if (n < 0) |
b0a873eb | 1933 | return -EINVAL; |
4574910e | 1934 | } |
0475f9ea | 1935 | events[n] = ev; |
cdd6c482 | 1936 | ctrs[n] = event; |
ab7ef2e5 PM |
1937 | cflags[n] = flags; |
1938 | if (check_excludes(ctrs, cflags, n, 1)) | |
b0a873eb | 1939 | return -EINVAL; |
e51ee31e | 1940 | |
cdd6c482 | 1941 | cpuhw = &get_cpu_var(cpu_hw_events); |
e51ee31e | 1942 | err = power_check_constraints(cpuhw, events, cflags, n + 1); |
3925f46b AK |
1943 | |
1944 | if (has_branch_stack(event)) { | |
65fa6e17 | 1945 | bhrb_filter = ppmu->bhrb_filter_map( |
3925f46b AK |
1946 | event->attr.branch_sample_type); |
1947 | ||
65fa6e17 | 1948 | if (bhrb_filter == -1) { |
68de8867 | 1949 | put_cpu_var(cpu_hw_events); |
3925f46b | 1950 | return -EOPNOTSUPP; |
68de8867 | 1951 | } |
65fa6e17 | 1952 | cpuhw->bhrb_filter = bhrb_filter; |
3925f46b AK |
1953 | } |
1954 | ||
cdd6c482 | 1955 | put_cpu_var(cpu_hw_events); |
e51ee31e | 1956 | if (err) |
b0a873eb | 1957 | return -EINVAL; |
4574910e | 1958 | |
cdd6c482 IM |
1959 | event->hw.config = events[n]; |
1960 | event->hw.event_base = cflags[n]; | |
1961 | event->hw.last_period = event->hw.sample_period; | |
e7850595 | 1962 | local64_set(&event->hw.period_left, event->hw.last_period); |
7595d63b | 1963 | |
330a1eb7 ME |
1964 | /* |
1965 | * For EBB events we just context switch the PMC value, we don't do any | |
1966 | * of the sample_period logic. We use hw.prev_count for this. | |
1967 | */ | |
1968 | if (is_ebb_event(event)) | |
1969 | local64_set(&event->hw.prev_count, 0); | |
1970 | ||
7595d63b PM |
1971 | /* |
1972 | * See if we need to reserve the PMU. | |
cdd6c482 | 1973 | * If no events are currently in use, then we have to take a |
7595d63b PM |
1974 | * mutex to ensure that we don't race with another task doing |
1975 | * reserve_pmc_hardware or release_pmc_hardware. | |
1976 | */ | |
1977 | err = 0; | |
cdd6c482 | 1978 | if (!atomic_inc_not_zero(&num_events)) { |
7595d63b | 1979 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 IM |
1980 | if (atomic_read(&num_events) == 0 && |
1981 | reserve_pmc_hardware(perf_event_interrupt)) | |
7595d63b PM |
1982 | err = -EBUSY; |
1983 | else | |
cdd6c482 | 1984 | atomic_inc(&num_events); |
7595d63b PM |
1985 | mutex_unlock(&pmc_reserve_mutex); |
1986 | } | |
cdd6c482 | 1987 | event->destroy = hw_perf_event_destroy; |
7595d63b | 1988 | |
b0a873eb | 1989 | return err; |
4574910e PM |
1990 | } |
1991 | ||
35edc2a5 PZ |
1992 | static int power_pmu_event_idx(struct perf_event *event) |
1993 | { | |
1994 | return event->hw.idx; | |
1995 | } | |
1996 | ||
1c53a270 SB |
1997 | ssize_t power_events_sysfs_show(struct device *dev, |
1998 | struct device_attribute *attr, char *page) | |
1999 | { | |
2000 | struct perf_pmu_events_attr *pmu_attr; | |
2001 | ||
2002 | pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr); | |
2003 | ||
2004 | return sprintf(page, "event=0x%02llx\n", pmu_attr->id); | |
2005 | } | |
2006 | ||
e51df2c1 | 2007 | static struct pmu power_pmu = { |
a4eaf7f1 PZ |
2008 | .pmu_enable = power_pmu_enable, |
2009 | .pmu_disable = power_pmu_disable, | |
b0a873eb | 2010 | .event_init = power_pmu_event_init, |
a4eaf7f1 PZ |
2011 | .add = power_pmu_add, |
2012 | .del = power_pmu_del, | |
2013 | .start = power_pmu_start, | |
2014 | .stop = power_pmu_stop, | |
b0a873eb | 2015 | .read = power_pmu_read, |
b0a873eb PZ |
2016 | .start_txn = power_pmu_start_txn, |
2017 | .cancel_txn = power_pmu_cancel_txn, | |
2018 | .commit_txn = power_pmu_commit_txn, | |
35edc2a5 | 2019 | .event_idx = power_pmu_event_idx, |
acba3c7e | 2020 | .sched_task = power_pmu_sched_task, |
b0a873eb PZ |
2021 | }; |
2022 | ||
4574910e | 2023 | /* |
57c0c15b | 2024 | * A counter has overflowed; update its count and record |
4574910e PM |
2025 | * things if requested. Note that interrupts are hard-disabled |
2026 | * here so there is no possibility of being interrupted. | |
2027 | */ | |
cdd6c482 | 2028 | static void record_and_restart(struct perf_event *event, unsigned long val, |
a8b0ca17 | 2029 | struct pt_regs *regs) |
4574910e | 2030 | { |
cdd6c482 | 2031 | u64 period = event->hw.sample_period; |
4574910e PM |
2032 | s64 prev, delta, left; |
2033 | int record = 0; | |
2034 | ||
a4eaf7f1 PZ |
2035 | if (event->hw.state & PERF_HES_STOPPED) { |
2036 | write_pmc(event->hw.idx, 0); | |
2037 | return; | |
2038 | } | |
2039 | ||
4574910e | 2040 | /* we don't have to worry about interrupts here */ |
e7850595 | 2041 | prev = local64_read(&event->hw.prev_count); |
86c74ab3 | 2042 | delta = check_and_compute_delta(prev, val); |
e7850595 | 2043 | local64_add(delta, &event->count); |
4574910e PM |
2044 | |
2045 | /* | |
cdd6c482 | 2046 | * See if the total period for this event has expired, |
4574910e PM |
2047 | * and update for the next period. |
2048 | */ | |
2049 | val = 0; | |
e7850595 | 2050 | left = local64_read(&event->hw.period_left) - delta; |
e13e895f MN |
2051 | if (delta == 0) |
2052 | left++; | |
60db5e09 | 2053 | if (period) { |
4574910e | 2054 | if (left <= 0) { |
60db5e09 | 2055 | left += period; |
4574910e | 2056 | if (left <= 0) |
60db5e09 | 2057 | left = period; |
e6878835 | 2058 | record = siar_valid(regs); |
4bca770e | 2059 | event->hw.last_period = event->hw.sample_period; |
4574910e | 2060 | } |
98fb1807 PM |
2061 | if (left < 0x80000000LL) |
2062 | val = 0x80000000LL - left; | |
4574910e | 2063 | } |
4574910e | 2064 | |
a4eaf7f1 PZ |
2065 | write_pmc(event->hw.idx, val); |
2066 | local64_set(&event->hw.prev_count, val); | |
2067 | local64_set(&event->hw.period_left, left); | |
2068 | perf_event_update_userpage(event); | |
2069 | ||
4574910e PM |
2070 | /* |
2071 | * Finally record data if requested. | |
2072 | */ | |
0bbd0d4b | 2073 | if (record) { |
dc1d628a PZ |
2074 | struct perf_sample_data data; |
2075 | ||
fd0d000b | 2076 | perf_sample_data_init(&data, ~0ULL, event->hw.last_period); |
df1a132b | 2077 | |
fc7ce9c7 KL |
2078 | if (event->attr.sample_type & |
2079 | (PERF_SAMPLE_ADDR | PERF_SAMPLE_PHYS_ADDR)) | |
98fb1807 PM |
2080 | perf_get_data_addr(regs, &data.addr); |
2081 | ||
3925f46b AK |
2082 | if (event->attr.sample_type & PERF_SAMPLE_BRANCH_STACK) { |
2083 | struct cpu_hw_events *cpuhw; | |
69111bac | 2084 | cpuhw = this_cpu_ptr(&cpu_hw_events); |
3925f46b AK |
2085 | power_pmu_bhrb_read(cpuhw); |
2086 | data.br_stack = &cpuhw->bhrb_stack; | |
2087 | } | |
2088 | ||
79e96f8f MS |
2089 | if (event->attr.sample_type & PERF_SAMPLE_DATA_SRC && |
2090 | ppmu->get_mem_data_src) | |
2091 | ppmu->get_mem_data_src(&data.data_src, ppmu->flags, regs); | |
2092 | ||
170a315f MS |
2093 | if (event->attr.sample_type & PERF_SAMPLE_WEIGHT && |
2094 | ppmu->get_mem_weight) | |
2095 | ppmu->get_mem_weight(&data.weight); | |
2096 | ||
a8b0ca17 | 2097 | if (perf_event_overflow(event, &data, regs)) |
a4eaf7f1 | 2098 | power_pmu_stop(event, 0); |
0bbd0d4b PM |
2099 | } |
2100 | } | |
2101 | ||
2102 | /* | |
2103 | * Called from generic code to get the misc flags (i.e. processor mode) | |
cdd6c482 | 2104 | * for an event_id. |
0bbd0d4b PM |
2105 | */ |
2106 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
2107 | { | |
98fb1807 | 2108 | u32 flags = perf_get_misc_flags(regs); |
0bbd0d4b | 2109 | |
98fb1807 PM |
2110 | if (flags) |
2111 | return flags; | |
cdd6c482 IM |
2112 | return user_mode(regs) ? PERF_RECORD_MISC_USER : |
2113 | PERF_RECORD_MISC_KERNEL; | |
0bbd0d4b PM |
2114 | } |
2115 | ||
2116 | /* | |
2117 | * Called from generic code to get the instruction pointer | |
cdd6c482 | 2118 | * for an event_id. |
0bbd0d4b PM |
2119 | */ |
2120 | unsigned long perf_instruction_pointer(struct pt_regs *regs) | |
2121 | { | |
33904054 | 2122 | bool use_siar = regs_use_siar(regs); |
0bbd0d4b | 2123 | |
e6878835 | 2124 | if (use_siar && siar_valid(regs)) |
75382aa7 | 2125 | return mfspr(SPRN_SIAR) + perf_ip_adjust(regs); |
e6878835 | 2126 | else if (use_siar) |
2127 | return 0; // no valid instruction pointer | |
75382aa7 | 2128 | else |
1ce447b9 | 2129 | return regs->nip; |
4574910e PM |
2130 | } |
2131 | ||
bc09c219 | 2132 | static bool pmc_overflow_power7(unsigned long val) |
0837e324 | 2133 | { |
0837e324 AB |
2134 | /* |
2135 | * Events on POWER7 can roll back if a speculative event doesn't | |
2136 | * eventually complete. Unfortunately in some rare cases they will | |
2137 | * raise a performance monitor exception. We need to catch this to | |
2138 | * ensure we reset the PMC. In all cases the PMC will be 256 or less | |
2139 | * cycles from overflow. | |
2140 | * | |
2141 | * We only do this if the first pass fails to find any overflowing | |
2142 | * PMCs because a user might set a period of less than 256 and we | |
2143 | * don't want to mistakenly reset them. | |
2144 | */ | |
bc09c219 MN |
2145 | if ((0x80000000 - val) <= 256) |
2146 | return true; | |
2147 | ||
2148 | return false; | |
2149 | } | |
2150 | ||
2151 | static bool pmc_overflow(unsigned long val) | |
2152 | { | |
2153 | if ((int)val < 0) | |
0837e324 AB |
2154 | return true; |
2155 | ||
2156 | return false; | |
2157 | } | |
2158 | ||
4574910e PM |
2159 | /* |
2160 | * Performance monitor interrupt stuff | |
2161 | */ | |
cdd6c482 | 2162 | static void perf_event_interrupt(struct pt_regs *regs) |
4574910e | 2163 | { |
bc09c219 | 2164 | int i, j; |
69111bac | 2165 | struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); |
cdd6c482 | 2166 | struct perf_event *event; |
bc09c219 MN |
2167 | unsigned long val[8]; |
2168 | int found, active; | |
ca8f2d7f PM |
2169 | int nmi; |
2170 | ||
ab7ef2e5 | 2171 | if (cpuhw->n_limited) |
a8f90e90 | 2172 | freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5), |
ab7ef2e5 PM |
2173 | mfspr(SPRN_PMC6)); |
2174 | ||
98fb1807 | 2175 | perf_read_regs(regs); |
0bbd0d4b | 2176 | |
98fb1807 | 2177 | nmi = perf_intr_is_nmi(regs); |
ca8f2d7f PM |
2178 | if (nmi) |
2179 | nmi_enter(); | |
2180 | else | |
2181 | irq_enter(); | |
4574910e | 2182 | |
bc09c219 MN |
2183 | /* Read all the PMCs since we'll need them a bunch of times */ |
2184 | for (i = 0; i < ppmu->n_counter; ++i) | |
2185 | val[i] = read_pmc(i + 1); | |
2186 | ||
2187 | /* Try to find what caused the IRQ */ | |
2188 | found = 0; | |
2189 | for (i = 0; i < ppmu->n_counter; ++i) { | |
2190 | if (!pmc_overflow(val[i])) | |
ab7ef2e5 | 2191 | continue; |
bc09c219 MN |
2192 | if (is_limited_pmc(i + 1)) |
2193 | continue; /* these won't generate IRQs */ | |
2194 | /* | |
2195 | * We've found one that's overflowed. For active | |
2196 | * counters we need to log this. For inactive | |
2197 | * counters, we need to reset it anyway | |
2198 | */ | |
2199 | found = 1; | |
2200 | active = 0; | |
2201 | for (j = 0; j < cpuhw->n_events; ++j) { | |
2202 | event = cpuhw->event[j]; | |
2203 | if (event->hw.idx == (i + 1)) { | |
2204 | active = 1; | |
2205 | record_and_restart(event, val[i], regs); | |
2206 | break; | |
2207 | } | |
4574910e | 2208 | } |
bc09c219 MN |
2209 | if (!active) |
2210 | /* reset non active counters that have overflowed */ | |
2211 | write_pmc(i + 1, 0); | |
4574910e | 2212 | } |
bc09c219 MN |
2213 | if (!found && pvr_version_is(PVR_POWER7)) { |
2214 | /* check active counters for special buggy p7 overflow */ | |
2215 | for (i = 0; i < cpuhw->n_events; ++i) { | |
2216 | event = cpuhw->event[i]; | |
2217 | if (!event->hw.idx || is_limited_pmc(event->hw.idx)) | |
ab7ef2e5 | 2218 | continue; |
bc09c219 MN |
2219 | if (pmc_overflow_power7(val[event->hw.idx - 1])) { |
2220 | /* event has overflowed in a buggy way*/ | |
2221 | found = 1; | |
2222 | record_and_restart(event, | |
2223 | val[event->hw.idx - 1], | |
2224 | regs); | |
2225 | } | |
4574910e PM |
2226 | } |
2227 | } | |
6772faa1 | 2228 | if (!found && !nmi && printk_ratelimit()) |
bc09c219 | 2229 | printk(KERN_WARNING "Can't find PMC that caused IRQ\n"); |
4574910e PM |
2230 | |
2231 | /* | |
2232 | * Reset MMCR0 to its normal value. This will set PMXE and | |
57c0c15b | 2233 | * clear FC (freeze counters) and PMAO (perf mon alert occurred) |
4574910e | 2234 | * and thus allow interrupts to occur again. |
cdd6c482 | 2235 | * XXX might want to use MSR.PM to keep the events frozen until |
4574910e PM |
2236 | * we get back out of this interrupt. |
2237 | */ | |
ab7ef2e5 | 2238 | write_mmcr0(cpuhw, cpuhw->mmcr[0]); |
4574910e | 2239 | |
ca8f2d7f PM |
2240 | if (nmi) |
2241 | nmi_exit(); | |
2242 | else | |
db4fb5ac | 2243 | irq_exit(); |
4574910e PM |
2244 | } |
2245 | ||
7c98bd72 | 2246 | static int power_pmu_prepare_cpu(unsigned int cpu) |
01d0287f | 2247 | { |
cdd6c482 | 2248 | struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu); |
01d0287f | 2249 | |
57ecde42 TG |
2250 | if (ppmu) { |
2251 | memset(cpuhw, 0, sizeof(*cpuhw)); | |
2252 | cpuhw->mmcr[0] = MMCR0_FC; | |
3f6da390 | 2253 | } |
57ecde42 | 2254 | return 0; |
3f6da390 PZ |
2255 | } |
2256 | ||
061d19f2 | 2257 | int register_power_pmu(struct power_pmu *pmu) |
4574910e | 2258 | { |
079b3c56 PM |
2259 | if (ppmu) |
2260 | return -EBUSY; /* something's already registered */ | |
2261 | ||
2262 | ppmu = pmu; | |
2263 | pr_info("%s performance monitor hardware support registered\n", | |
2264 | pmu->name); | |
d095cd46 | 2265 | |
1c53a270 SB |
2266 | power_pmu.attr_groups = ppmu->attr_groups; |
2267 | ||
98fb1807 | 2268 | #ifdef MSR_HV |
d095cd46 PM |
2269 | /* |
2270 | * Use FCHV to ignore kernel events if MSR.HV is set. | |
2271 | */ | |
2272 | if (mfmsr() & MSR_HV) | |
cdd6c482 | 2273 | freeze_events_kernel = MMCR0_FCHV; |
98fb1807 | 2274 | #endif /* CONFIG_PPC64 */ |
d095cd46 | 2275 | |
2e80a82a | 2276 | perf_pmu_register(&power_pmu, "cpu", PERF_TYPE_RAW); |
73c1b41e | 2277 | cpuhp_setup_state(CPUHP_PERF_POWER, "perf/powerpc:prepare", |
57ecde42 | 2278 | power_pmu_prepare_cpu, NULL); |
4574910e PM |
2279 | return 0; |
2280 | } |