[mirror_ubuntu-eoan-kernel.git] / arch / powerpc / platforms / 52xx / media5200.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Support for 'media5200-platform' compatible boards.
 *
 * Copyright (C) 2008 Secret Lab Technologies Ltd.
 *
 * Description:
 * This code implements support for the Freescape Media5200 platform
 * (built around the MPC5200 SoC).
 *
 * Notable characteristic of the Media5200 is the presence of an FPGA
 * that has all external IRQ lines routed through it.  This file implements
 * a cascaded interrupt controller driver which attaches itself to the
 * Virtual IRQ subsystem after the primary mpc5200 interrupt controller
 * is initialized.
 */

#undef DEBUG

#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <asm/time.h>
#include <asm/prom.h>
#include <asm/machdep.h>
#include <asm/mpc52xx.h>

static const struct of_device_id mpc5200_gpio_ids[] __initconst = {
	{ .compatible = "fsl,mpc5200-gpio", },
	{ .compatible = "mpc5200-gpio", },
	{}
};

/* FPGA register set */
#define MEDIA5200_IRQ_ENABLE (0x40c)
#define MEDIA5200_IRQ_STATUS (0x410)
#define MEDIA5200_NUM_IRQS   (6)
#define MEDIA5200_IRQ_SHIFT  (32 - MEDIA5200_NUM_IRQS)

struct media5200_irq {
	void __iomem *regs;
	spinlock_t lock;
	struct irq_domain *irqhost;
};
struct media5200_irq media5200_irq;

static void media5200_irq_unmask(struct irq_data *d)
{
	unsigned long flags;
	u32 val;

	spin_lock_irqsave(&media5200_irq.lock, flags);
	val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
	val |= 1 << (MEDIA5200_IRQ_SHIFT + irqd_to_hwirq(d));
	out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val);
	spin_unlock_irqrestore(&media5200_irq.lock, flags);
}

static void media5200_irq_mask(struct irq_data *d)
{
	unsigned long flags;
	u32 val;

	spin_lock_irqsave(&media5200_irq.lock, flags);
	val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
	val &= ~(1 << (MEDIA5200_IRQ_SHIFT + irqd_to_hwirq(d)));
	out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val);
	spin_unlock_irqrestore(&media5200_irq.lock, flags);
}

static struct irq_chip media5200_irq_chip = {
	.name = "Media5200 FPGA",
	.irq_unmask = media5200_irq_unmask,
	.irq_mask = media5200_irq_mask,
	.irq_mask_ack = media5200_irq_mask,
};

static void media5200_irq_cascade(struct irq_desc *desc)
{
	struct irq_chip *chip = irq_desc_get_chip(desc);
	int sub_virq, val;
	u32 status, enable;

	/* Mask off the cascaded IRQ */
	raw_spin_lock(&desc->lock);
	chip->irq_mask(&desc->irq_data);
	raw_spin_unlock(&desc->lock);

	/* Ask the FPGA for IRQ status.  If 'val' is 0, then no irqs
	 * are pending.  'ffs()' is 1 based */
	status = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
	enable = in_be32(media5200_irq.regs + MEDIA5200_IRQ_STATUS);
	val = ffs((status & enable) >> MEDIA5200_IRQ_SHIFT);
	if (val) {
		sub_virq = irq_linear_revmap(media5200_irq.irqhost, val - 1);
		/* pr_debug("%s: virq=%i s=%.8x e=%.8x hwirq=%i subvirq=%i\n",
		 *          __func__, virq, status, enable, val - 1, sub_virq);
		 */
		generic_handle_irq(sub_virq);
	}

	/* Processing done; can reenable the cascade now */
	raw_spin_lock(&desc->lock);
	chip->irq_ack(&desc->irq_data);
	if (!irqd_irq_disabled(&desc->irq_data))
		chip->irq_unmask(&desc->irq_data);
	raw_spin_unlock(&desc->lock);
}

static int media5200_irq_map(struct irq_domain *h, unsigned int virq,
			     irq_hw_number_t hw)
{
	pr_debug("%s: h=%p, virq=%i, hwirq=%i\n", __func__, h, virq, (int)hw);
	irq_set_chip_data(virq, &media5200_irq);
	irq_set_chip_and_handler(virq, &media5200_irq_chip, handle_level_irq);
	irq_set_status_flags(virq, IRQ_LEVEL);
	return 0;
}

static int media5200_irq_xlate(struct irq_domain *h, struct device_node *ct,
				 const u32 *intspec, unsigned int intsize,
				 irq_hw_number_t *out_hwirq,
				 unsigned int *out_flags)
{
	if (intsize != 2)
		return -1;

	pr_debug("%s: bank=%i, number=%i\n", __func__, intspec[0], intspec[1]);
	*out_hwirq = intspec[1];
	*out_flags = IRQ_TYPE_NONE;
	return 0;
}

static const struct irq_domain_ops media5200_irq_ops = {
	.map = media5200_irq_map,
	.xlate = media5200_irq_xlate,
};

/*
 * Setup Media5200 IRQ mapping
 */
static void __init media5200_init_irq(void)
{
	struct device_node *fpga_np;
	int cascade_virq;

	/* First setup the regular MPC5200 interrupt controller */
	mpc52xx_init_irq();

	/* Now find the FPGA IRQ */
	fpga_np = of_find_compatible_node(NULL, NULL, "fsl,media5200-fpga");
	if (!fpga_np)
		goto out;
	pr_debug("%s: found fpga node: %pOF\n", __func__, fpga_np);

	media5200_irq.regs = of_iomap(fpga_np, 0);
	if (!media5200_irq.regs)
		goto out;
	pr_debug("%s: mapped to %p\n", __func__, media5200_irq.regs);

	cascade_virq = irq_of_parse_and_map(fpga_np, 0);
	if (!cascade_virq)
		goto out;
	pr_debug("%s: cascaded on virq=%i\n", __func__, cascade_virq);

	/* Disable all FPGA IRQs */
	out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, 0);

	spin_lock_init(&media5200_irq.lock);

	media5200_irq.irqhost = irq_domain_add_linear(fpga_np,
			MEDIA5200_NUM_IRQS, &media5200_irq_ops, &media5200_irq);
	if (!media5200_irq.irqhost)
		goto out;
	pr_debug("%s: allocated irqhost\n", __func__);

	irq_set_handler_data(cascade_virq, &media5200_irq);
	irq_set_chained_handler(cascade_virq, media5200_irq_cascade);

	return;

 out:
	pr_err("Could not find Media5200 FPGA; PCI interrupts will not work\n");
}

/*
 * Setup the architecture
 */
static void __init media5200_setup_arch(void)
{

	struct device_node *np;
	struct mpc52xx_gpio __iomem *gpio;
	u32 port_config;

	if (ppc_md.progress)
		ppc_md.progress("media5200_setup_arch()", 0);

	/* Map important registers from the internal memory map */
	mpc52xx_map_common_devices();

	/* Some mpc5200 & mpc5200b related configuration */
	mpc5200_setup_xlb_arbiter();

	mpc52xx_setup_pci();

	np = of_find_matching_node(NULL, mpc5200_gpio_ids);
	gpio = of_iomap(np, 0);
	of_node_put(np);
	if (!gpio) {
		printk(KERN_ERR "%s() failed. expect abnormal behavior\n",
		       __func__);
		return;
	}

	/* Set port config */
	port_config = in_be32(&gpio->port_config);

	port_config &= ~0x03000000;	/* ATA CS is on csb_4/5		*/
	port_config |=  0x01000000;

	out_be32(&gpio->port_config, port_config);

	/* Unmap zone */
	iounmap(gpio);

}

/* list of the supported boards */
static const char * const board[] __initconst = {
	"fsl,media5200",
	NULL
};

/*
 * Called very early, MMU is off, device-tree isn't unflattened
 */
static int __init media5200_probe(void)
{
	return of_device_compatible_match(of_root, board);
}

define_machine(media5200_platform) {
	.name		= "media5200-platform",
	.probe		= media5200_probe,
	.setup_arch	= media5200_setup_arch,
	.init		= mpc52xx_declare_of_platform_devices,
	.init_IRQ	= media5200_init_irq,
	.get_irq	= mpc52xx_get_irq,
	.restart	= mpc52xx_restart,
	.calibrate_decr	= generic_calibrate_decr,
};
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
bfee95bb GL	2	/*
	3	* Support for 'media5200-platform' compatible boards.
	4	*
	5	* Copyright (C) 2008 Secret Lab Technologies Ltd.
	6	*
bfee95bb GL	7	* Description:
	8	* This code implements support for the Freescape Media5200 platform
	9	* (built around the MPC5200 SoC).
	10	*
	11	* Notable characteristic of the Media5200 is the presence of an FPGA
	12	* that has all external IRQ lines routed through it. This file implements
	13	* a cascaded interrupt controller driver which attaches itself to the
	14	* Virtual IRQ subsystem after the primary mpc5200 interrupt controller
	15	* is initialized.
bfee95bb GL	16	*/
	17
	18	#undef DEBUG
	19
	20	#include <linux/irq.h>
	21	#include <linux/interrupt.h>
	22	#include <linux/io.h>
	23	#include <asm/time.h>
	24	#include <asm/prom.h>
	25	#include <asm/machdep.h>
	26	#include <asm/mpc52xx.h>
	27
ce6d73c9	28	static const struct of_device_id mpc5200_gpio_ids[] __initconst = {
bfee95bb GL	29	{ .compatible = "fsl,mpc5200-gpio", },
	30	{ .compatible = "mpc5200-gpio", },
	31	{}
	32	};
	33
	34	/* FPGA register set */
	35	#define MEDIA5200_IRQ_ENABLE (0x40c)
	36	#define MEDIA5200_IRQ_STATUS (0x410)
	37	#define MEDIA5200_NUM_IRQS (6)
	38	#define MEDIA5200_IRQ_SHIFT (32 - MEDIA5200_NUM_IRQS)
	39
	40	struct media5200_irq {
	41	void __iomem *regs;
	42	spinlock_t lock;
bae1d8f1	43	struct irq_domain *irqhost;
bfee95bb GL	44	};
	45	struct media5200_irq media5200_irq;
	46
8a2df7a0	47	static void media5200_irq_unmask(struct irq_data *d)
bfee95bb GL	48	{
	49	unsigned long flags;
	50	u32 val;
	51
	52	spin_lock_irqsave(&media5200_irq.lock, flags);
	53	val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
476eb491	54	val \|= 1 << (MEDIA5200_IRQ_SHIFT + irqd_to_hwirq(d));
bfee95bb GL	55	out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val);
	56	spin_unlock_irqrestore(&media5200_irq.lock, flags);
	57	}
	58
8a2df7a0	59	static void media5200_irq_mask(struct irq_data *d)
bfee95bb GL	60	{
	61	unsigned long flags;
	62	u32 val;
	63
	64	spin_lock_irqsave(&media5200_irq.lock, flags);
	65	val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
476eb491	66	val &= ~(1 << (MEDIA5200_IRQ_SHIFT + irqd_to_hwirq(d)));
bfee95bb GL	67	out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val);
	68	spin_unlock_irqrestore(&media5200_irq.lock, flags);
	69	}
	70
	71	static struct irq_chip media5200_irq_chip = {
b27df672	72	.name = "Media5200 FPGA",
8a2df7a0 LB	73	.irq_unmask = media5200_irq_unmask,
	74	.irq_mask = media5200_irq_mask,
	75	.irq_mask_ack = media5200_irq_mask,
bfee95bb GL	76	};
bfee95bb GL	77
bd0b9ac4	78	static void media5200_irq_cascade(struct irq_desc *desc)
bfee95bb	79	{
ec775d0e	80	struct irq_chip *chip = irq_desc_get_chip(desc);
bfee95bb GL	81	int sub_virq, val;
	82	u32 status, enable;
	83
	84	/* Mask off the cascaded IRQ */
239007b8	85	raw_spin_lock(&desc->lock);
8a2df7a0	86	chip->irq_mask(&desc->irq_data);
239007b8	87	raw_spin_unlock(&desc->lock);
bfee95bb GL	88
	89	/* Ask the FPGA for IRQ status. If 'val' is 0, then no irqs
	90	* are pending. 'ffs()' is 1 based */
	91	status = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
	92	enable = in_be32(media5200_irq.regs + MEDIA5200_IRQ_STATUS);
	93	val = ffs((status & enable) >> MEDIA5200_IRQ_SHIFT);
	94	if (val) {
	95	sub_virq = irq_linear_revmap(media5200_irq.irqhost, val - 1);
	96	/* pr_debug("%s: virq=%i s=%.8x e=%.8x hwirq=%i subvirq=%i\n",
	97	* __func__, virq, status, enable, val - 1, sub_virq);
	98	*/
	99	generic_handle_irq(sub_virq);
	100	}
	101
	102	/* Processing done; can reenable the cascade now */
239007b8	103	raw_spin_lock(&desc->lock);
8a2df7a0	104	chip->irq_ack(&desc->irq_data);
98488db9	105	if (!irqd_irq_disabled(&desc->irq_data))
8a2df7a0	106	chip->irq_unmask(&desc->irq_data);
239007b8	107	raw_spin_unlock(&desc->lock);
bfee95bb GL	108	}
bfee95bb GL	109
bae1d8f1	110	static int media5200_irq_map(struct irq_domain *h, unsigned int virq,
bfee95bb GL	111	irq_hw_number_t hw)
bfee95bb GL	112	{
bfee95bb	113	pr_debug("%s: h=%p, virq=%i, hwirq=%i\n", __func__, h, virq, (int)hw);
ec775d0e TG	114	irq_set_chip_data(virq, &media5200_irq);
ec775d0e TG	115	irq_set_chip_and_handler(virq, &media5200_irq_chip, handle_level_irq);
212d786d	116	irq_set_status_flags(virq, IRQ_LEVEL);
bfee95bb GL	117	return 0;
	118	}
	119
bae1d8f1	120	static int media5200_irq_xlate(struct irq_domain h, struct device_node ct,
40d50cf7	121	const u32 *intspec, unsigned int intsize,
bfee95bb GL	122	irq_hw_number_t *out_hwirq,
	123	unsigned int *out_flags)
	124	{
	125	if (intsize != 2)
	126	return -1;
	127
	128	pr_debug("%s: bank=%i, number=%i\n", __func__, intspec[0], intspec[1]);
	129	*out_hwirq = intspec[1];
	130	*out_flags = IRQ_TYPE_NONE;
	131	return 0;
	132	}
	133
9f70b8eb	134	static const struct irq_domain_ops media5200_irq_ops = {
bfee95bb GL	135	.map = media5200_irq_map,
	136	.xlate = media5200_irq_xlate,
	137	};
	138
	139	/*
	140	* Setup Media5200 IRQ mapping
	141	*/
	142	static void __init media5200_init_irq(void)
	143	{
	144	struct device_node *fpga_np;
	145	int cascade_virq;
	146
	147	/* First setup the regular MPC5200 interrupt controller */
	148	mpc52xx_init_irq();
	149
	150	/* Now find the FPGA IRQ */
	151	fpga_np = of_find_compatible_node(NULL, NULL, "fsl,media5200-fpga");
	152	if (!fpga_np)
	153	goto out;
b7c670d6	154	pr_debug("%s: found fpga node: %pOF\n", __func__, fpga_np);
bfee95bb GL	155
	156	media5200_irq.regs = of_iomap(fpga_np, 0);
	157	if (!media5200_irq.regs)
	158	goto out;
	159	pr_debug("%s: mapped to %p\n", __func__, media5200_irq.regs);
	160
	161	cascade_virq = irq_of_parse_and_map(fpga_np, 0);
	162	if (!cascade_virq)
	163	goto out;
	164	pr_debug("%s: cascaded on virq=%i\n", __func__, cascade_virq);
	165
	166	/* Disable all FPGA IRQs */
	167	out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, 0);
	168
	169	spin_lock_init(&media5200_irq.lock);
	170
a8db8cf0 GL	171	media5200_irq.irqhost = irq_domain_add_linear(fpga_np,
a8db8cf0 GL	172	MEDIA5200_NUM_IRQS, &media5200_irq_ops, &media5200_irq);
bfee95bb GL	173	if (!media5200_irq.irqhost)
	174	goto out;
	175	pr_debug("%s: allocated irqhost\n", __func__);
	176
ec775d0e TG	177	irq_set_handler_data(cascade_virq, &media5200_irq);
ec775d0e TG	178	irq_set_chained_handler(cascade_virq, media5200_irq_cascade);
bfee95bb GL	179
	180	return;
	181
	182	out:
	183	pr_err("Could not find Media5200 FPGA; PCI interrupts will not work\n");
	184	}
	185
	186	/*
	187	* Setup the architecture
	188	*/
	189	static void __init media5200_setup_arch(void)
	190	{
	191
	192	struct device_node *np;
	193	struct mpc52xx_gpio __iomem *gpio;
	194	u32 port_config;
	195
	196	if (ppc_md.progress)
	197	ppc_md.progress("media5200_setup_arch()", 0);
	198
	199	/* Map important registers from the internal memory map */
	200	mpc52xx_map_common_devices();
	201
	202	/* Some mpc5200 & mpc5200b related configuration */
	203	mpc5200_setup_xlb_arbiter();
	204
	205	mpc52xx_setup_pci();
	206
	207	np = of_find_matching_node(NULL, mpc5200_gpio_ids);
	208	gpio = of_iomap(np, 0);
	209	of_node_put(np);
	210	if (!gpio) {
	211	printk(KERN_ERR "%s() failed. expect abnormal behavior\n",
	212	__func__);
	213	return;
	214	}
	215
	216	/* Set port config */
	217	port_config = in_be32(&gpio->port_config);
	218
	219	port_config &= ~0x03000000; /* ATA CS is on csb_4/5 */
	220	port_config \|= 0x01000000;
	221
	222	out_be32(&gpio->port_config, port_config);
	223
	224	/* Unmap zone */
	225	iounmap(gpio);
	226
	227	}
	228
	229	/* list of the supported boards */
9597abe0	230	static const char * const board[] __initconst = {
bfee95bb GL	231	"fsl,media5200",
	232	NULL
	233	};
	234
	235	/*
	236	* Called very early, MMU is off, device-tree isn't unflattened
	237	*/
	238	static int __init media5200_probe(void)
	239	{
56571384	240	return of_device_compatible_match(of_root, board);
bfee95bb GL	241	}
	242
	243	define_machine(media5200_platform) {
	244	.name = "media5200-platform",
	245	.probe = media5200_probe,
	246	.setup_arch = media5200_setup_arch,
	247	.init = mpc52xx_declare_of_platform_devices,
	248	.init_IRQ = media5200_init_irq,
	249	.get_irq = mpc52xx_get_irq,
	250	.restart = mpc52xx_restart,
	251	.calibrate_decr = generic_calibrate_decr,
	252	};