[mirror_ubuntu-eoan-kernel.git] / arch / powerpc / platforms / 52xx / media5200.c

/*
 * Support for 'media5200-platform' compatible boards.
 *
 * Copyright (C) 2008 Secret Lab Technologies Ltd.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 * Description:
 * This code implements support for the Freescape Media5200 platform
 * (built around the MPC5200 SoC).
 *
 * Notable characteristic of the Media5200 is the presence of an FPGA
 * that has all external IRQ lines routed through it.  This file implements
 * a cascaded interrupt controller driver which attaches itself to the
 * Virtual IRQ subsystem after the primary mpc5200 interrupt controller
 * is initialized.
 *
 */

#undef DEBUG

#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <asm/time.h>
#include <asm/prom.h>
#include <asm/machdep.h>
#include <asm/mpc52xx.h>

static const struct of_device_id mpc5200_gpio_ids[] __initconst = {
	{ .compatible = "fsl,mpc5200-gpio", },
	{ .compatible = "mpc5200-gpio", },
	{}
};

/* FPGA register set */
#define MEDIA5200_IRQ_ENABLE (0x40c)
#define MEDIA5200_IRQ_STATUS (0x410)
#define MEDIA5200_NUM_IRQS   (6)
#define MEDIA5200_IRQ_SHIFT  (32 - MEDIA5200_NUM_IRQS)

struct media5200_irq {
	void __iomem *regs;
	spinlock_t lock;
	struct irq_domain *irqhost;
};
struct media5200_irq media5200_irq;

static void media5200_irq_unmask(struct irq_data *d)
{
	unsigned long flags;
	u32 val;

	spin_lock_irqsave(&media5200_irq.lock, flags);
	val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
	val |= 1 << (MEDIA5200_IRQ_SHIFT + irqd_to_hwirq(d));
	out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val);
	spin_unlock_irqrestore(&media5200_irq.lock, flags);
}

static void media5200_irq_mask(struct irq_data *d)
{
	unsigned long flags;
	u32 val;

	spin_lock_irqsave(&media5200_irq.lock, flags);
	val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
	val &= ~(1 << (MEDIA5200_IRQ_SHIFT + irqd_to_hwirq(d)));
	out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val);
	spin_unlock_irqrestore(&media5200_irq.lock, flags);
}

static struct irq_chip media5200_irq_chip = {
	.name = "Media5200 FPGA",
	.irq_unmask = media5200_irq_unmask,
	.irq_mask = media5200_irq_mask,
	.irq_mask_ack = media5200_irq_mask,
};

static void media5200_irq_cascade(struct irq_desc *desc)
{
	struct irq_chip *chip = irq_desc_get_chip(desc);
	int sub_virq, val;
	u32 status, enable;

	/* Mask off the cascaded IRQ */
	raw_spin_lock(&desc->lock);
	chip->irq_mask(&desc->irq_data);
	raw_spin_unlock(&desc->lock);

	/* Ask the FPGA for IRQ status.  If 'val' is 0, then no irqs
	 * are pending.  'ffs()' is 1 based */
	status = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
	enable = in_be32(media5200_irq.regs + MEDIA5200_IRQ_STATUS);
	val = ffs((status & enable) >> MEDIA5200_IRQ_SHIFT);
	if (val) {
		sub_virq = irq_linear_revmap(media5200_irq.irqhost, val - 1);
		/* pr_debug("%s: virq=%i s=%.8x e=%.8x hwirq=%i subvirq=%i\n",
		 *          __func__, virq, status, enable, val - 1, sub_virq);
		 */
		generic_handle_irq(sub_virq);
	}

	/* Processing done; can reenable the cascade now */
	raw_spin_lock(&desc->lock);
	chip->irq_ack(&desc->irq_data);
	if (!irqd_irq_disabled(&desc->irq_data))
		chip->irq_unmask(&desc->irq_data);
	raw_spin_unlock(&desc->lock);
}

static int media5200_irq_map(struct irq_domain *h, unsigned int virq,
			     irq_hw_number_t hw)
{
	pr_debug("%s: h=%p, virq=%i, hwirq=%i\n", __func__, h, virq, (int)hw);
	irq_set_chip_data(virq, &media5200_irq);
	irq_set_chip_and_handler(virq, &media5200_irq_chip, handle_level_irq);
	irq_set_status_flags(virq, IRQ_LEVEL);
	return 0;
}

static int media5200_irq_xlate(struct irq_domain *h, struct device_node *ct,
				 const u32 *intspec, unsigned int intsize,
				 irq_hw_number_t *out_hwirq,
				 unsigned int *out_flags)
{
	if (intsize != 2)
		return -1;

	pr_debug("%s: bank=%i, number=%i\n", __func__, intspec[0], intspec[1]);
	*out_hwirq = intspec[1];
	*out_flags = IRQ_TYPE_NONE;
	return 0;
}

static const struct irq_domain_ops media5200_irq_ops = {
	.map = media5200_irq_map,
	.xlate = media5200_irq_xlate,
};

/*
 * Setup Media5200 IRQ mapping
 */
static void __init media5200_init_irq(void)
{
	struct device_node *fpga_np;
	int cascade_virq;

	/* First setup the regular MPC5200 interrupt controller */
	mpc52xx_init_irq();

	/* Now find the FPGA IRQ */
	fpga_np = of_find_compatible_node(NULL, NULL, "fsl,media5200-fpga");
	if (!fpga_np)
		goto out;
	pr_debug("%s: found fpga node: %s\n", __func__, fpga_np->full_name);

	media5200_irq.regs = of_iomap(fpga_np, 0);
	if (!media5200_irq.regs)
		goto out;
	pr_debug("%s: mapped to %p\n", __func__, media5200_irq.regs);

	cascade_virq = irq_of_parse_and_map(fpga_np, 0);
	if (!cascade_virq)
		goto out;
	pr_debug("%s: cascaded on virq=%i\n", __func__, cascade_virq);

	/* Disable all FPGA IRQs */
	out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, 0);

	spin_lock_init(&media5200_irq.lock);

	media5200_irq.irqhost = irq_domain_add_linear(fpga_np,
			MEDIA5200_NUM_IRQS, &media5200_irq_ops, &media5200_irq);
	if (!media5200_irq.irqhost)
		goto out;
	pr_debug("%s: allocated irqhost\n", __func__);

	irq_set_handler_data(cascade_virq, &media5200_irq);
	irq_set_chained_handler(cascade_virq, media5200_irq_cascade);

	return;

 out:
	pr_err("Could not find Media5200 FPGA; PCI interrupts will not work\n");
}

/*
 * Setup the architecture
 */
static void __init media5200_setup_arch(void)
{

	struct device_node *np;
	struct mpc52xx_gpio __iomem *gpio;
	u32 port_config;

	if (ppc_md.progress)
		ppc_md.progress("media5200_setup_arch()", 0);

	/* Map important registers from the internal memory map */
	mpc52xx_map_common_devices();

	/* Some mpc5200 & mpc5200b related configuration */
	mpc5200_setup_xlb_arbiter();

	mpc52xx_setup_pci();

	np = of_find_matching_node(NULL, mpc5200_gpio_ids);
	gpio = of_iomap(np, 0);
	of_node_put(np);
	if (!gpio) {
		printk(KERN_ERR "%s() failed. expect abnormal behavior\n",
		       __func__);
		return;
	}

	/* Set port config */
	port_config = in_be32(&gpio->port_config);

	port_config &= ~0x03000000;	/* ATA CS is on csb_4/5		*/
	port_config |=  0x01000000;

	out_be32(&gpio->port_config, port_config);

	/* Unmap zone */
	iounmap(gpio);

}

/* list of the supported boards */
static const char * const board[] __initconst = {
	"fsl,media5200",
	NULL
};

/*
 * Called very early, MMU is off, device-tree isn't unflattened
 */
static int __init media5200_probe(void)
{
	return of_device_compatible_match(of_root, board);
}

define_machine(media5200_platform) {
	.name		= "media5200-platform",
	.probe		= media5200_probe,
	.setup_arch	= media5200_setup_arch,
	.init		= mpc52xx_declare_of_platform_devices,
	.init_IRQ	= media5200_init_irq,
	.get_irq	= mpc52xx_get_irq,
	.restart	= mpc52xx_restart,
	.calibrate_decr	= generic_calibrate_decr,
};
Commit	Line	Data
bfee95bb GL	1	/*
	2	* Support for 'media5200-platform' compatible boards.
	3	*
	4	* Copyright (C) 2008 Secret Lab Technologies Ltd.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*
	11	* Description:
	12	* This code implements support for the Freescape Media5200 platform
	13	* (built around the MPC5200 SoC).
	14	*
	15	* Notable characteristic of the Media5200 is the presence of an FPGA
	16	* that has all external IRQ lines routed through it. This file implements
	17	* a cascaded interrupt controller driver which attaches itself to the
	18	* Virtual IRQ subsystem after the primary mpc5200 interrupt controller
	19	* is initialized.
	20	*
	21	*/
	22
	23	#undef DEBUG
	24
	25	#include <linux/irq.h>
	26	#include <linux/interrupt.h>
	27	#include <linux/io.h>
	28	#include <asm/time.h>
	29	#include <asm/prom.h>
	30	#include <asm/machdep.h>
	31	#include <asm/mpc52xx.h>
	32
ce6d73c9	33	static const struct of_device_id mpc5200_gpio_ids[] __initconst = {
bfee95bb GL	34	{ .compatible = "fsl,mpc5200-gpio", },
	35	{ .compatible = "mpc5200-gpio", },
	36	{}
	37	};
	38
	39	/* FPGA register set */
	40	#define MEDIA5200_IRQ_ENABLE (0x40c)
	41	#define MEDIA5200_IRQ_STATUS (0x410)
	42	#define MEDIA5200_NUM_IRQS (6)
	43	#define MEDIA5200_IRQ_SHIFT (32 - MEDIA5200_NUM_IRQS)
	44
	45	struct media5200_irq {
	46	void __iomem *regs;
	47	spinlock_t lock;
bae1d8f1	48	struct irq_domain *irqhost;
bfee95bb GL	49	};
	50	struct media5200_irq media5200_irq;
	51
8a2df7a0	52	static void media5200_irq_unmask(struct irq_data *d)
bfee95bb GL	53	{
	54	unsigned long flags;
	55	u32 val;
	56
	57	spin_lock_irqsave(&media5200_irq.lock, flags);
	58	val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
476eb491	59	val \|= 1 << (MEDIA5200_IRQ_SHIFT + irqd_to_hwirq(d));
bfee95bb GL	60	out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val);
	61	spin_unlock_irqrestore(&media5200_irq.lock, flags);
	62	}
	63
8a2df7a0	64	static void media5200_irq_mask(struct irq_data *d)
bfee95bb GL	65	{
	66	unsigned long flags;
	67	u32 val;
	68
	69	spin_lock_irqsave(&media5200_irq.lock, flags);
	70	val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
476eb491	71	val &= ~(1 << (MEDIA5200_IRQ_SHIFT + irqd_to_hwirq(d)));
bfee95bb GL	72	out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val);
	73	spin_unlock_irqrestore(&media5200_irq.lock, flags);
	74	}
	75
	76	static struct irq_chip media5200_irq_chip = {
b27df672	77	.name = "Media5200 FPGA",
8a2df7a0 LB	78	.irq_unmask = media5200_irq_unmask,
	79	.irq_mask = media5200_irq_mask,
	80	.irq_mask_ack = media5200_irq_mask,
bfee95bb GL	81	};
bfee95bb GL	82
bd0b9ac4	83	static void media5200_irq_cascade(struct irq_desc *desc)
bfee95bb	84	{
ec775d0e	85	struct irq_chip *chip = irq_desc_get_chip(desc);
bfee95bb GL	86	int sub_virq, val;
	87	u32 status, enable;
	88
	89	/* Mask off the cascaded IRQ */
239007b8	90	raw_spin_lock(&desc->lock);
8a2df7a0	91	chip->irq_mask(&desc->irq_data);
239007b8	92	raw_spin_unlock(&desc->lock);
bfee95bb GL	93
	94	/* Ask the FPGA for IRQ status. If 'val' is 0, then no irqs
	95	* are pending. 'ffs()' is 1 based */
	96	status = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
	97	enable = in_be32(media5200_irq.regs + MEDIA5200_IRQ_STATUS);
	98	val = ffs((status & enable) >> MEDIA5200_IRQ_SHIFT);
	99	if (val) {
	100	sub_virq = irq_linear_revmap(media5200_irq.irqhost, val - 1);
	101	/* pr_debug("%s: virq=%i s=%.8x e=%.8x hwirq=%i subvirq=%i\n",
	102	* __func__, virq, status, enable, val - 1, sub_virq);
	103	*/
	104	generic_handle_irq(sub_virq);
	105	}
	106
	107	/* Processing done; can reenable the cascade now */
239007b8	108	raw_spin_lock(&desc->lock);
8a2df7a0	109	chip->irq_ack(&desc->irq_data);
98488db9	110	if (!irqd_irq_disabled(&desc->irq_data))
8a2df7a0	111	chip->irq_unmask(&desc->irq_data);
239007b8	112	raw_spin_unlock(&desc->lock);
bfee95bb GL	113	}
bfee95bb GL	114
bae1d8f1	115	static int media5200_irq_map(struct irq_domain *h, unsigned int virq,
bfee95bb GL	116	irq_hw_number_t hw)
bfee95bb GL	117	{
bfee95bb	118	pr_debug("%s: h=%p, virq=%i, hwirq=%i\n", __func__, h, virq, (int)hw);
ec775d0e TG	119	irq_set_chip_data(virq, &media5200_irq);
ec775d0e TG	120	irq_set_chip_and_handler(virq, &media5200_irq_chip, handle_level_irq);
212d786d	121	irq_set_status_flags(virq, IRQ_LEVEL);
bfee95bb GL	122	return 0;
	123	}
	124
bae1d8f1	125	static int media5200_irq_xlate(struct irq_domain h, struct device_node ct,
40d50cf7	126	const u32 *intspec, unsigned int intsize,
bfee95bb GL	127	irq_hw_number_t *out_hwirq,
	128	unsigned int *out_flags)
	129	{
	130	if (intsize != 2)
	131	return -1;
	132
	133	pr_debug("%s: bank=%i, number=%i\n", __func__, intspec[0], intspec[1]);
	134	*out_hwirq = intspec[1];
	135	*out_flags = IRQ_TYPE_NONE;
	136	return 0;
	137	}
	138
9f70b8eb	139	static const struct irq_domain_ops media5200_irq_ops = {
bfee95bb GL	140	.map = media5200_irq_map,
	141	.xlate = media5200_irq_xlate,
	142	};
	143
	144	/*
	145	* Setup Media5200 IRQ mapping
	146	*/
	147	static void __init media5200_init_irq(void)
	148	{
	149	struct device_node *fpga_np;
	150	int cascade_virq;
	151
	152	/* First setup the regular MPC5200 interrupt controller */
	153	mpc52xx_init_irq();
	154
	155	/* Now find the FPGA IRQ */
	156	fpga_np = of_find_compatible_node(NULL, NULL, "fsl,media5200-fpga");
	157	if (!fpga_np)
	158	goto out;
	159	pr_debug("%s: found fpga node: %s\n", __func__, fpga_np->full_name);
	160
	161	media5200_irq.regs = of_iomap(fpga_np, 0);
	162	if (!media5200_irq.regs)
	163	goto out;
	164	pr_debug("%s: mapped to %p\n", __func__, media5200_irq.regs);
	165
	166	cascade_virq = irq_of_parse_and_map(fpga_np, 0);
	167	if (!cascade_virq)
	168	goto out;
	169	pr_debug("%s: cascaded on virq=%i\n", __func__, cascade_virq);
	170
	171	/* Disable all FPGA IRQs */
	172	out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, 0);
	173
	174	spin_lock_init(&media5200_irq.lock);
	175
a8db8cf0 GL	176	media5200_irq.irqhost = irq_domain_add_linear(fpga_np,
a8db8cf0 GL	177	MEDIA5200_NUM_IRQS, &media5200_irq_ops, &media5200_irq);
bfee95bb GL	178	if (!media5200_irq.irqhost)
	179	goto out;
	180	pr_debug("%s: allocated irqhost\n", __func__);
	181
ec775d0e TG	182	irq_set_handler_data(cascade_virq, &media5200_irq);
ec775d0e TG	183	irq_set_chained_handler(cascade_virq, media5200_irq_cascade);
bfee95bb GL	184
	185	return;
	186
	187	out:
	188	pr_err("Could not find Media5200 FPGA; PCI interrupts will not work\n");
	189	}
	190
	191	/*
	192	* Setup the architecture
	193	*/
	194	static void __init media5200_setup_arch(void)
	195	{
	196
	197	struct device_node *np;
	198	struct mpc52xx_gpio __iomem *gpio;
	199	u32 port_config;
	200
	201	if (ppc_md.progress)
	202	ppc_md.progress("media5200_setup_arch()", 0);
	203
	204	/* Map important registers from the internal memory map */
	205	mpc52xx_map_common_devices();
	206
	207	/* Some mpc5200 & mpc5200b related configuration */
	208	mpc5200_setup_xlb_arbiter();
	209
	210	mpc52xx_setup_pci();
	211
	212	np = of_find_matching_node(NULL, mpc5200_gpio_ids);
	213	gpio = of_iomap(np, 0);
	214	of_node_put(np);
	215	if (!gpio) {
	216	printk(KERN_ERR "%s() failed. expect abnormal behavior\n",
	217	__func__);
	218	return;
	219	}
	220
	221	/* Set port config */
	222	port_config = in_be32(&gpio->port_config);
	223
	224	port_config &= ~0x03000000; /* ATA CS is on csb_4/5 */
	225	port_config \|= 0x01000000;
	226
	227	out_be32(&gpio->port_config, port_config);
	228
	229	/* Unmap zone */
	230	iounmap(gpio);
	231
	232	}
	233
	234	/* list of the supported boards */
9597abe0	235	static const char * const board[] __initconst = {
bfee95bb GL	236	"fsl,media5200",
	237	NULL
	238	};
	239
	240	/*
	241	* Called very early, MMU is off, device-tree isn't unflattened
	242	*/
	243	static int __init media5200_probe(void)
	244	{
56571384	245	return of_device_compatible_match(of_root, board);
bfee95bb GL	246	}
	247
	248	define_machine(media5200_platform) {
	249	.name = "media5200-platform",
	250	.probe = media5200_probe,
	251	.setup_arch = media5200_setup_arch,
	252	.init = mpc52xx_declare_of_platform_devices,
	253	.init_IRQ = media5200_init_irq,
	254	.get_irq = mpc52xx_get_irq,
	255	.restart = mpc52xx_restart,
	256	.calibrate_decr = generic_calibrate_decr,
	257	};