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5496eab2 GL |
1 | /* |
2 | * MPC5200 General Purpose Timer device driver | |
3 | * | |
4 | * Copyright (c) 2009 Secret Lab Technologies Ltd. | |
5 | * Copyright (c) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License as published by the | |
9 | * Free Software Foundation; either version 2 of the License, or (at your | |
10 | * option) any later version. | |
11 | * | |
12 | * This file is a driver for the the General Purpose Timer (gpt) devices | |
13 | * found on the MPC5200 SoC. Each timer has an IO pin which can be used | |
14 | * for GPIO or can be used to raise interrupts. The timer function can | |
15 | * be used independently from the IO pin, or it can be used to control | |
16 | * output signals or measure input signals. | |
17 | * | |
18 | * This driver supports the GPIO and IRQ controller functions of the GPT | |
eda43d16 AD |
19 | * device. Timer functions are not yet supported. |
20 | * | |
21 | * The timer gpt0 can be used as watchdog (wdt). If the wdt mode is used, | |
22 | * this prevents the use of any gpt0 gpt function (i.e. they will fail with | |
23 | * -EBUSY). Thus, the safety wdt function always has precedence over the gpt | |
24 | * function. If the kernel has been compiled with CONFIG_WATCHDOG_NOWAYOUT, | |
25 | * this means that gpt0 is locked in wdt mode until the next reboot - this | |
26 | * may be a requirement in safety applications. | |
5496eab2 GL |
27 | * |
28 | * To use the GPIO function, the following two properties must be added | |
29 | * to the device tree node for the gpt device (typically in the .dts file | |
30 | * for the board): | |
31 | * gpio-controller; | |
32 | * #gpio-cells = < 2 >; | |
33 | * This driver will register the GPIO pin if it finds the gpio-controller | |
34 | * property in the device tree. | |
35 | * | |
36 | * To use the IRQ controller function, the following two properties must | |
37 | * be added to the device tree node for the gpt device: | |
38 | * interrupt-controller; | |
39 | * #interrupt-cells = < 1 >; | |
40 | * The IRQ controller binding only uses one cell to specify the interrupt, | |
41 | * and the IRQ flags are encoded in the cell. A cell is not used to encode | |
42 | * the IRQ number because the GPT only has a single IRQ source. For flags, | |
43 | * a value of '1' means rising edge sensitive and '2' means falling edge. | |
44 | * | |
45 | * The GPIO and the IRQ controller functions can be used at the same time, | |
46 | * but in this use case the IO line will only work as an input. Trying to | |
47 | * use it as a GPIO output will not work. | |
48 | * | |
49 | * When using the GPIO line as an output, it can either be driven as normal | |
50 | * IO, or it can be an Open Collector (OC) output. At the moment it is the | |
51 | * responsibility of either the bootloader or the platform setup code to set | |
52 | * the output mode. This driver does not change the output mode setting. | |
53 | */ | |
54 | ||
4f59ecfa | 55 | #include <linux/device.h> |
5496eab2 GL |
56 | #include <linux/irq.h> |
57 | #include <linux/interrupt.h> | |
58 | #include <linux/io.h> | |
4f59ecfa GL |
59 | #include <linux/list.h> |
60 | #include <linux/mutex.h> | |
5496eab2 GL |
61 | #include <linux/of.h> |
62 | #include <linux/of_platform.h> | |
63 | #include <linux/of_gpio.h> | |
64 | #include <linux/kernel.h> | |
5a0e3ad6 | 65 | #include <linux/slab.h> |
5e2f55c6 | 66 | #include <linux/fs.h> |
eda43d16 AD |
67 | #include <linux/watchdog.h> |
68 | #include <linux/miscdevice.h> | |
69 | #include <linux/uaccess.h> | |
4f59ecfa | 70 | #include <asm/div64.h> |
5496eab2 GL |
71 | #include <asm/mpc52xx.h> |
72 | ||
73 | MODULE_DESCRIPTION("Freescale MPC52xx gpt driver"); | |
eda43d16 | 74 | MODULE_AUTHOR("Sascha Hauer, Grant Likely, Albrecht Dreß"); |
5496eab2 GL |
75 | MODULE_LICENSE("GPL"); |
76 | ||
77 | /** | |
78 | * struct mpc52xx_gpt - Private data structure for MPC52xx GPT driver | |
79 | * @dev: pointer to device structure | |
80 | * @regs: virtual address of GPT registers | |
81 | * @lock: spinlock to coordinate between different functions. | |
a19e3da5 | 82 | * @gc: gpio_chip instance structure; used when GPIO is enabled |
5496eab2 | 83 | * @irqhost: Pointer to irq_host instance; used when IRQ mode is supported |
eda43d16 AD |
84 | * @wdt_mode: only relevant for gpt0: bit 0 (MPC52xx_GPT_CAN_WDT) indicates |
85 | * if the gpt may be used as wdt, bit 1 (MPC52xx_GPT_IS_WDT) indicates | |
86 | * if the timer is actively used as wdt which blocks gpt functions | |
5496eab2 GL |
87 | */ |
88 | struct mpc52xx_gpt_priv { | |
4f59ecfa | 89 | struct list_head list; /* List of all GPT devices */ |
5496eab2 GL |
90 | struct device *dev; |
91 | struct mpc52xx_gpt __iomem *regs; | |
92 | spinlock_t lock; | |
93 | struct irq_host *irqhost; | |
4f59ecfa | 94 | u32 ipb_freq; |
eda43d16 | 95 | u8 wdt_mode; |
5496eab2 GL |
96 | |
97 | #if defined(CONFIG_GPIOLIB) | |
a19e3da5 | 98 | struct gpio_chip gc; |
5496eab2 GL |
99 | #endif |
100 | }; | |
101 | ||
4f59ecfa GL |
102 | LIST_HEAD(mpc52xx_gpt_list); |
103 | DEFINE_MUTEX(mpc52xx_gpt_list_mutex); | |
104 | ||
5496eab2 GL |
105 | #define MPC52xx_GPT_MODE_MS_MASK (0x07) |
106 | #define MPC52xx_GPT_MODE_MS_IC (0x01) | |
107 | #define MPC52xx_GPT_MODE_MS_OC (0x02) | |
108 | #define MPC52xx_GPT_MODE_MS_PWM (0x03) | |
109 | #define MPC52xx_GPT_MODE_MS_GPIO (0x04) | |
110 | ||
111 | #define MPC52xx_GPT_MODE_GPIO_MASK (0x30) | |
112 | #define MPC52xx_GPT_MODE_GPIO_OUT_LOW (0x20) | |
113 | #define MPC52xx_GPT_MODE_GPIO_OUT_HIGH (0x30) | |
114 | ||
4f59ecfa GL |
115 | #define MPC52xx_GPT_MODE_COUNTER_ENABLE (0x1000) |
116 | #define MPC52xx_GPT_MODE_CONTINUOUS (0x0400) | |
117 | #define MPC52xx_GPT_MODE_OPEN_DRAIN (0x0200) | |
5496eab2 | 118 | #define MPC52xx_GPT_MODE_IRQ_EN (0x0100) |
eda43d16 | 119 | #define MPC52xx_GPT_MODE_WDT_EN (0x8000) |
5496eab2 GL |
120 | |
121 | #define MPC52xx_GPT_MODE_ICT_MASK (0x030000) | |
122 | #define MPC52xx_GPT_MODE_ICT_RISING (0x010000) | |
123 | #define MPC52xx_GPT_MODE_ICT_FALLING (0x020000) | |
124 | #define MPC52xx_GPT_MODE_ICT_TOGGLE (0x030000) | |
125 | ||
eda43d16 AD |
126 | #define MPC52xx_GPT_MODE_WDT_PING (0xa5) |
127 | ||
5496eab2 GL |
128 | #define MPC52xx_GPT_STATUS_IRQMASK (0x000f) |
129 | ||
eda43d16 AD |
130 | #define MPC52xx_GPT_CAN_WDT (1 << 0) |
131 | #define MPC52xx_GPT_IS_WDT (1 << 1) | |
132 | ||
133 | ||
5496eab2 GL |
134 | /* --------------------------------------------------------------------- |
135 | * Cascaded interrupt controller hooks | |
136 | */ | |
137 | ||
8a2df7a0 | 138 | static void mpc52xx_gpt_irq_unmask(struct irq_data *d) |
5496eab2 | 139 | { |
8a2df7a0 | 140 | struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d); |
5496eab2 GL |
141 | unsigned long flags; |
142 | ||
143 | spin_lock_irqsave(&gpt->lock, flags); | |
144 | setbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN); | |
145 | spin_unlock_irqrestore(&gpt->lock, flags); | |
146 | } | |
147 | ||
8a2df7a0 | 148 | static void mpc52xx_gpt_irq_mask(struct irq_data *d) |
5496eab2 | 149 | { |
8a2df7a0 | 150 | struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d); |
5496eab2 GL |
151 | unsigned long flags; |
152 | ||
153 | spin_lock_irqsave(&gpt->lock, flags); | |
154 | clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN); | |
155 | spin_unlock_irqrestore(&gpt->lock, flags); | |
156 | } | |
157 | ||
8a2df7a0 | 158 | static void mpc52xx_gpt_irq_ack(struct irq_data *d) |
5496eab2 | 159 | { |
8a2df7a0 | 160 | struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d); |
5496eab2 GL |
161 | |
162 | out_be32(&gpt->regs->status, MPC52xx_GPT_STATUS_IRQMASK); | |
163 | } | |
164 | ||
8a2df7a0 | 165 | static int mpc52xx_gpt_irq_set_type(struct irq_data *d, unsigned int flow_type) |
5496eab2 | 166 | { |
8a2df7a0 | 167 | struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d); |
5496eab2 GL |
168 | unsigned long flags; |
169 | u32 reg; | |
170 | ||
8a2df7a0 | 171 | dev_dbg(gpt->dev, "%s: virq=%i type=%x\n", __func__, d->irq, flow_type); |
5496eab2 GL |
172 | |
173 | spin_lock_irqsave(&gpt->lock, flags); | |
174 | reg = in_be32(&gpt->regs->mode) & ~MPC52xx_GPT_MODE_ICT_MASK; | |
175 | if (flow_type & IRQF_TRIGGER_RISING) | |
176 | reg |= MPC52xx_GPT_MODE_ICT_RISING; | |
177 | if (flow_type & IRQF_TRIGGER_FALLING) | |
178 | reg |= MPC52xx_GPT_MODE_ICT_FALLING; | |
179 | out_be32(&gpt->regs->mode, reg); | |
180 | spin_unlock_irqrestore(&gpt->lock, flags); | |
181 | ||
182 | return 0; | |
183 | } | |
184 | ||
185 | static struct irq_chip mpc52xx_gpt_irq_chip = { | |
b27df672 | 186 | .name = "MPC52xx GPT", |
8a2df7a0 LB |
187 | .irq_unmask = mpc52xx_gpt_irq_unmask, |
188 | .irq_mask = mpc52xx_gpt_irq_mask, | |
189 | .irq_ack = mpc52xx_gpt_irq_ack, | |
190 | .irq_set_type = mpc52xx_gpt_irq_set_type, | |
5496eab2 GL |
191 | }; |
192 | ||
193 | void mpc52xx_gpt_irq_cascade(unsigned int virq, struct irq_desc *desc) | |
194 | { | |
ec775d0e | 195 | struct mpc52xx_gpt_priv *gpt = irq_get_handler_data(virq); |
5496eab2 GL |
196 | int sub_virq; |
197 | u32 status; | |
198 | ||
199 | status = in_be32(&gpt->regs->status) & MPC52xx_GPT_STATUS_IRQMASK; | |
200 | if (status) { | |
201 | sub_virq = irq_linear_revmap(gpt->irqhost, 0); | |
202 | generic_handle_irq(sub_virq); | |
203 | } | |
204 | } | |
205 | ||
206 | static int mpc52xx_gpt_irq_map(struct irq_host *h, unsigned int virq, | |
207 | irq_hw_number_t hw) | |
208 | { | |
209 | struct mpc52xx_gpt_priv *gpt = h->host_data; | |
210 | ||
211 | dev_dbg(gpt->dev, "%s: h=%p, virq=%i\n", __func__, h, virq); | |
ec775d0e TG |
212 | irq_set_chip_data(virq, gpt); |
213 | irq_set_chip_and_handler(virq, &mpc52xx_gpt_irq_chip, handle_edge_irq); | |
5496eab2 GL |
214 | |
215 | return 0; | |
216 | } | |
217 | ||
218 | static int mpc52xx_gpt_irq_xlate(struct irq_host *h, struct device_node *ct, | |
40d50cf7 | 219 | const u32 *intspec, unsigned int intsize, |
5496eab2 GL |
220 | irq_hw_number_t *out_hwirq, |
221 | unsigned int *out_flags) | |
222 | { | |
223 | struct mpc52xx_gpt_priv *gpt = h->host_data; | |
224 | ||
225 | dev_dbg(gpt->dev, "%s: flags=%i\n", __func__, intspec[0]); | |
226 | ||
4f59ecfa | 227 | if ((intsize < 1) || (intspec[0] > 3)) { |
5496eab2 GL |
228 | dev_err(gpt->dev, "bad irq specifier in %s\n", ct->full_name); |
229 | return -EINVAL; | |
230 | } | |
231 | ||
232 | *out_hwirq = 0; /* The GPT only has 1 IRQ line */ | |
233 | *out_flags = intspec[0]; | |
234 | ||
235 | return 0; | |
236 | } | |
237 | ||
238 | static struct irq_host_ops mpc52xx_gpt_irq_ops = { | |
239 | .map = mpc52xx_gpt_irq_map, | |
240 | .xlate = mpc52xx_gpt_irq_xlate, | |
241 | }; | |
242 | ||
243 | static void | |
244 | mpc52xx_gpt_irq_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node) | |
245 | { | |
246 | int cascade_virq; | |
247 | unsigned long flags; | |
4f59ecfa | 248 | u32 mode; |
5496eab2 GL |
249 | |
250 | cascade_virq = irq_of_parse_and_map(node, 0); | |
4f59ecfa GL |
251 | if (!cascade_virq) |
252 | return; | |
5496eab2 GL |
253 | |
254 | gpt->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR, 1, | |
255 | &mpc52xx_gpt_irq_ops, -1); | |
256 | if (!gpt->irqhost) { | |
257 | dev_err(gpt->dev, "irq_alloc_host() failed\n"); | |
258 | return; | |
259 | } | |
260 | ||
261 | gpt->irqhost->host_data = gpt; | |
ec775d0e TG |
262 | irq_set_handler_data(cascade_virq, gpt); |
263 | irq_set_chained_handler(cascade_virq, mpc52xx_gpt_irq_cascade); | |
5496eab2 | 264 | |
4f59ecfa GL |
265 | /* If the GPT is currently disabled, then change it to be in Input |
266 | * Capture mode. If the mode is non-zero, then the pin could be | |
267 | * already in use for something. */ | |
5496eab2 | 268 | spin_lock_irqsave(&gpt->lock, flags); |
4f59ecfa GL |
269 | mode = in_be32(&gpt->regs->mode); |
270 | if ((mode & MPC52xx_GPT_MODE_MS_MASK) == 0) | |
271 | out_be32(&gpt->regs->mode, mode | MPC52xx_GPT_MODE_MS_IC); | |
5496eab2 GL |
272 | spin_unlock_irqrestore(&gpt->lock, flags); |
273 | ||
274 | dev_dbg(gpt->dev, "%s() complete. virq=%i\n", __func__, cascade_virq); | |
275 | } | |
276 | ||
277 | ||
278 | /* --------------------------------------------------------------------- | |
279 | * GPIOLIB hooks | |
280 | */ | |
281 | #if defined(CONFIG_GPIOLIB) | |
282 | static inline struct mpc52xx_gpt_priv *gc_to_mpc52xx_gpt(struct gpio_chip *gc) | |
283 | { | |
a19e3da5 | 284 | return container_of(gc, struct mpc52xx_gpt_priv, gc); |
5496eab2 GL |
285 | } |
286 | ||
287 | static int mpc52xx_gpt_gpio_get(struct gpio_chip *gc, unsigned int gpio) | |
288 | { | |
289 | struct mpc52xx_gpt_priv *gpt = gc_to_mpc52xx_gpt(gc); | |
290 | ||
291 | return (in_be32(&gpt->regs->status) >> 8) & 1; | |
292 | } | |
293 | ||
294 | static void | |
295 | mpc52xx_gpt_gpio_set(struct gpio_chip *gc, unsigned int gpio, int v) | |
296 | { | |
297 | struct mpc52xx_gpt_priv *gpt = gc_to_mpc52xx_gpt(gc); | |
298 | unsigned long flags; | |
299 | u32 r; | |
300 | ||
301 | dev_dbg(gpt->dev, "%s: gpio:%d v:%d\n", __func__, gpio, v); | |
302 | r = v ? MPC52xx_GPT_MODE_GPIO_OUT_HIGH : MPC52xx_GPT_MODE_GPIO_OUT_LOW; | |
303 | ||
304 | spin_lock_irqsave(&gpt->lock, flags); | |
305 | clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK, r); | |
306 | spin_unlock_irqrestore(&gpt->lock, flags); | |
307 | } | |
308 | ||
309 | static int mpc52xx_gpt_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio) | |
310 | { | |
311 | struct mpc52xx_gpt_priv *gpt = gc_to_mpc52xx_gpt(gc); | |
312 | unsigned long flags; | |
313 | ||
314 | dev_dbg(gpt->dev, "%s: gpio:%d\n", __func__, gpio); | |
315 | ||
316 | spin_lock_irqsave(&gpt->lock, flags); | |
317 | clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK); | |
318 | spin_unlock_irqrestore(&gpt->lock, flags); | |
319 | ||
320 | return 0; | |
321 | } | |
322 | ||
323 | static int | |
324 | mpc52xx_gpt_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) | |
325 | { | |
326 | mpc52xx_gpt_gpio_set(gc, gpio, val); | |
327 | return 0; | |
328 | } | |
329 | ||
330 | static void | |
331 | mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node) | |
332 | { | |
333 | int rc; | |
334 | ||
335 | /* Only setup GPIO if the device tree claims the GPT is | |
336 | * a GPIO controller */ | |
337 | if (!of_find_property(node, "gpio-controller", NULL)) | |
338 | return; | |
339 | ||
a19e3da5 AV |
340 | gpt->gc.label = kstrdup(node->full_name, GFP_KERNEL); |
341 | if (!gpt->gc.label) { | |
5496eab2 GL |
342 | dev_err(gpt->dev, "out of memory\n"); |
343 | return; | |
344 | } | |
345 | ||
a19e3da5 AV |
346 | gpt->gc.ngpio = 1; |
347 | gpt->gc.direction_input = mpc52xx_gpt_gpio_dir_in; | |
348 | gpt->gc.direction_output = mpc52xx_gpt_gpio_dir_out; | |
349 | gpt->gc.get = mpc52xx_gpt_gpio_get; | |
350 | gpt->gc.set = mpc52xx_gpt_gpio_set; | |
351 | gpt->gc.base = -1; | |
594fa265 | 352 | gpt->gc.of_node = node; |
5496eab2 GL |
353 | |
354 | /* Setup external pin in GPIO mode */ | |
355 | clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_MS_MASK, | |
356 | MPC52xx_GPT_MODE_MS_GPIO); | |
357 | ||
a19e3da5 | 358 | rc = gpiochip_add(&gpt->gc); |
5496eab2 GL |
359 | if (rc) |
360 | dev_err(gpt->dev, "gpiochip_add() failed; rc=%i\n", rc); | |
361 | ||
362 | dev_dbg(gpt->dev, "%s() complete.\n", __func__); | |
363 | } | |
364 | #else /* defined(CONFIG_GPIOLIB) */ | |
365 | static void | |
366 | mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv *p, struct device_node *np) { } | |
367 | #endif /* defined(CONFIG_GPIOLIB) */ | |
368 | ||
4f59ecfa GL |
369 | /*********************************************************************** |
370 | * Timer API | |
371 | */ | |
372 | ||
373 | /** | |
374 | * mpc52xx_gpt_from_irq - Return the GPT device associated with an IRQ number | |
375 | * @irq: irq of timer. | |
376 | */ | |
377 | struct mpc52xx_gpt_priv *mpc52xx_gpt_from_irq(int irq) | |
378 | { | |
379 | struct mpc52xx_gpt_priv *gpt; | |
380 | struct list_head *pos; | |
381 | ||
382 | /* Iterate over the list of timers looking for a matching device */ | |
383 | mutex_lock(&mpc52xx_gpt_list_mutex); | |
384 | list_for_each(pos, &mpc52xx_gpt_list) { | |
385 | gpt = container_of(pos, struct mpc52xx_gpt_priv, list); | |
386 | if (gpt->irqhost && irq == irq_linear_revmap(gpt->irqhost, 0)) { | |
387 | mutex_unlock(&mpc52xx_gpt_list_mutex); | |
388 | return gpt; | |
389 | } | |
390 | } | |
391 | mutex_unlock(&mpc52xx_gpt_list_mutex); | |
392 | ||
393 | return NULL; | |
394 | } | |
395 | EXPORT_SYMBOL(mpc52xx_gpt_from_irq); | |
396 | ||
eda43d16 AD |
397 | static int mpc52xx_gpt_do_start(struct mpc52xx_gpt_priv *gpt, u64 period, |
398 | int continuous, int as_wdt) | |
4f59ecfa GL |
399 | { |
400 | u32 clear, set; | |
401 | u64 clocks; | |
402 | u32 prescale; | |
403 | unsigned long flags; | |
404 | ||
405 | clear = MPC52xx_GPT_MODE_MS_MASK | MPC52xx_GPT_MODE_CONTINUOUS; | |
406 | set = MPC52xx_GPT_MODE_MS_GPIO | MPC52xx_GPT_MODE_COUNTER_ENABLE; | |
eda43d16 AD |
407 | if (as_wdt) { |
408 | clear |= MPC52xx_GPT_MODE_IRQ_EN; | |
409 | set |= MPC52xx_GPT_MODE_WDT_EN; | |
410 | } else if (continuous) | |
4f59ecfa GL |
411 | set |= MPC52xx_GPT_MODE_CONTINUOUS; |
412 | ||
413 | /* Determine the number of clocks in the requested period. 64 bit | |
414 | * arithmatic is done here to preserve the precision until the value | |
415 | * is scaled back down into the u32 range. Period is in 'ns', bus | |
416 | * frequency is in Hz. */ | |
690b846a | 417 | clocks = period * (u64)gpt->ipb_freq; |
4f59ecfa GL |
418 | do_div(clocks, 1000000000); /* Scale it down to ns range */ |
419 | ||
420 | /* This device cannot handle a clock count greater than 32 bits */ | |
421 | if (clocks > 0xffffffff) | |
422 | return -EINVAL; | |
423 | ||
424 | /* Calculate the prescaler and count values from the clocks value. | |
425 | * 'clocks' is the number of clock ticks in the period. The timer | |
426 | * has 16 bit precision and a 16 bit prescaler. Prescaler is | |
427 | * calculated by integer dividing the clocks by 0x10000 (shifting | |
428 | * down 16 bits) to obtain the smallest possible divisor for clocks | |
429 | * to get a 16 bit count value. | |
430 | * | |
431 | * Note: the prescale register is '1' based, not '0' based. ie. a | |
432 | * value of '1' means divide the clock by one. 0xffff divides the | |
433 | * clock by 0xffff. '0x0000' does not divide by zero, but wraps | |
434 | * around and divides by 0x10000. That is why prescale must be | |
435 | * a u32 variable, not a u16, for this calculation. */ | |
436 | prescale = (clocks >> 16) + 1; | |
437 | do_div(clocks, prescale); | |
438 | if (clocks > 0xffff) { | |
439 | pr_err("calculation error; prescale:%x clocks:%llx\n", | |
440 | prescale, clocks); | |
441 | return -EINVAL; | |
442 | } | |
443 | ||
eda43d16 | 444 | /* Set and enable the timer, reject an attempt to use a wdt as gpt */ |
4f59ecfa | 445 | spin_lock_irqsave(&gpt->lock, flags); |
eda43d16 AD |
446 | if (as_wdt) |
447 | gpt->wdt_mode |= MPC52xx_GPT_IS_WDT; | |
448 | else if ((gpt->wdt_mode & MPC52xx_GPT_IS_WDT) != 0) { | |
449 | spin_unlock_irqrestore(&gpt->lock, flags); | |
450 | return -EBUSY; | |
451 | } | |
4f59ecfa GL |
452 | out_be32(&gpt->regs->count, prescale << 16 | clocks); |
453 | clrsetbits_be32(&gpt->regs->mode, clear, set); | |
454 | spin_unlock_irqrestore(&gpt->lock, flags); | |
455 | ||
456 | return 0; | |
457 | } | |
eda43d16 AD |
458 | |
459 | /** | |
460 | * mpc52xx_gpt_start_timer - Set and enable the GPT timer | |
461 | * @gpt: Pointer to gpt private data structure | |
462 | * @period: period of timer in ns; max. ~130s @ 33MHz IPB clock | |
463 | * @continuous: set to 1 to make timer continuous free running | |
464 | * | |
465 | * An interrupt will be generated every time the timer fires | |
466 | */ | |
467 | int mpc52xx_gpt_start_timer(struct mpc52xx_gpt_priv *gpt, u64 period, | |
468 | int continuous) | |
469 | { | |
470 | return mpc52xx_gpt_do_start(gpt, period, continuous, 0); | |
471 | } | |
4f59ecfa GL |
472 | EXPORT_SYMBOL(mpc52xx_gpt_start_timer); |
473 | ||
eda43d16 AD |
474 | /** |
475 | * mpc52xx_gpt_stop_timer - Stop a gpt | |
476 | * @gpt: Pointer to gpt private data structure | |
477 | * | |
478 | * Returns an error if attempting to stop a wdt | |
479 | */ | |
480 | int mpc52xx_gpt_stop_timer(struct mpc52xx_gpt_priv *gpt) | |
4f59ecfa | 481 | { |
eda43d16 AD |
482 | unsigned long flags; |
483 | ||
484 | /* reject the operation if the timer is used as watchdog (gpt 0 only) */ | |
485 | spin_lock_irqsave(&gpt->lock, flags); | |
486 | if ((gpt->wdt_mode & MPC52xx_GPT_IS_WDT) != 0) { | |
487 | spin_unlock_irqrestore(&gpt->lock, flags); | |
488 | return -EBUSY; | |
489 | } | |
490 | ||
4f59ecfa | 491 | clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_COUNTER_ENABLE); |
eda43d16 AD |
492 | spin_unlock_irqrestore(&gpt->lock, flags); |
493 | return 0; | |
4f59ecfa GL |
494 | } |
495 | EXPORT_SYMBOL(mpc52xx_gpt_stop_timer); | |
496 | ||
eda43d16 AD |
497 | /** |
498 | * mpc52xx_gpt_timer_period - Read the timer period | |
499 | * @gpt: Pointer to gpt private data structure | |
500 | * | |
501 | * Returns the timer period in ns | |
502 | */ | |
503 | u64 mpc52xx_gpt_timer_period(struct mpc52xx_gpt_priv *gpt) | |
504 | { | |
505 | u64 period; | |
506 | u64 prescale; | |
507 | unsigned long flags; | |
508 | ||
509 | spin_lock_irqsave(&gpt->lock, flags); | |
510 | period = in_be32(&gpt->regs->count); | |
511 | spin_unlock_irqrestore(&gpt->lock, flags); | |
512 | ||
513 | prescale = period >> 16; | |
514 | period &= 0xffff; | |
515 | if (prescale == 0) | |
516 | prescale = 0x10000; | |
517 | period = period * prescale * 1000000000ULL; | |
518 | do_div(period, (u64)gpt->ipb_freq); | |
519 | return period; | |
520 | } | |
521 | EXPORT_SYMBOL(mpc52xx_gpt_timer_period); | |
522 | ||
523 | #if defined(CONFIG_MPC5200_WDT) | |
524 | /*********************************************************************** | |
525 | * Watchdog API for gpt0 | |
526 | */ | |
527 | ||
528 | #define WDT_IDENTITY "mpc52xx watchdog on GPT0" | |
529 | ||
530 | /* wdt_is_active stores wether or not the /dev/watchdog device is opened */ | |
531 | static unsigned long wdt_is_active; | |
532 | ||
533 | /* wdt-capable gpt */ | |
534 | static struct mpc52xx_gpt_priv *mpc52xx_gpt_wdt; | |
535 | ||
536 | /* low-level wdt functions */ | |
537 | static inline void mpc52xx_gpt_wdt_ping(struct mpc52xx_gpt_priv *gpt_wdt) | |
538 | { | |
539 | unsigned long flags; | |
540 | ||
541 | spin_lock_irqsave(&gpt_wdt->lock, flags); | |
542 | out_8((u8 *) &gpt_wdt->regs->mode, MPC52xx_GPT_MODE_WDT_PING); | |
543 | spin_unlock_irqrestore(&gpt_wdt->lock, flags); | |
544 | } | |
545 | ||
546 | /* wdt misc device api */ | |
547 | static ssize_t mpc52xx_wdt_write(struct file *file, const char __user *data, | |
548 | size_t len, loff_t *ppos) | |
549 | { | |
550 | struct mpc52xx_gpt_priv *gpt_wdt = file->private_data; | |
551 | mpc52xx_gpt_wdt_ping(gpt_wdt); | |
552 | return 0; | |
553 | } | |
554 | ||
42747d71 | 555 | static const struct watchdog_info mpc5200_wdt_info = { |
eda43d16 AD |
556 | .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, |
557 | .identity = WDT_IDENTITY, | |
558 | }; | |
559 | ||
560 | static long mpc52xx_wdt_ioctl(struct file *file, unsigned int cmd, | |
561 | unsigned long arg) | |
562 | { | |
563 | struct mpc52xx_gpt_priv *gpt_wdt = file->private_data; | |
564 | int __user *data = (int __user *)arg; | |
565 | int timeout; | |
566 | u64 real_timeout; | |
567 | int ret = 0; | |
568 | ||
569 | switch (cmd) { | |
570 | case WDIOC_GETSUPPORT: | |
571 | ret = copy_to_user(data, &mpc5200_wdt_info, | |
572 | sizeof(mpc5200_wdt_info)); | |
573 | if (ret) | |
574 | ret = -EFAULT; | |
575 | break; | |
576 | ||
577 | case WDIOC_GETSTATUS: | |
578 | case WDIOC_GETBOOTSTATUS: | |
579 | ret = put_user(0, data); | |
580 | break; | |
581 | ||
582 | case WDIOC_KEEPALIVE: | |
583 | mpc52xx_gpt_wdt_ping(gpt_wdt); | |
584 | break; | |
585 | ||
586 | case WDIOC_SETTIMEOUT: | |
587 | ret = get_user(timeout, data); | |
588 | if (ret) | |
589 | break; | |
590 | real_timeout = (u64) timeout * 1000000000ULL; | |
591 | ret = mpc52xx_gpt_do_start(gpt_wdt, real_timeout, 0, 1); | |
592 | if (ret) | |
593 | break; | |
594 | /* fall through and return the timeout */ | |
595 | ||
596 | case WDIOC_GETTIMEOUT: | |
597 | /* we need to round here as to avoid e.g. the following | |
598 | * situation: | |
599 | * - timeout requested is 1 second; | |
600 | * - real timeout @33MHz is 999997090ns | |
601 | * - the int divide by 10^9 will return 0. | |
602 | */ | |
603 | real_timeout = | |
604 | mpc52xx_gpt_timer_period(gpt_wdt) + 500000000ULL; | |
605 | do_div(real_timeout, 1000000000ULL); | |
606 | timeout = (int) real_timeout; | |
607 | ret = put_user(timeout, data); | |
608 | break; | |
609 | ||
610 | default: | |
611 | ret = -ENOTTY; | |
612 | } | |
613 | return ret; | |
614 | } | |
615 | ||
616 | static int mpc52xx_wdt_open(struct inode *inode, struct file *file) | |
617 | { | |
618 | int ret; | |
619 | ||
620 | /* sanity check */ | |
621 | if (!mpc52xx_gpt_wdt) | |
622 | return -ENODEV; | |
623 | ||
624 | /* /dev/watchdog can only be opened once */ | |
625 | if (test_and_set_bit(0, &wdt_is_active)) | |
626 | return -EBUSY; | |
627 | ||
628 | /* Set and activate the watchdog with 30 seconds timeout */ | |
629 | ret = mpc52xx_gpt_do_start(mpc52xx_gpt_wdt, 30ULL * 1000000000ULL, | |
630 | 0, 1); | |
631 | if (ret) { | |
632 | clear_bit(0, &wdt_is_active); | |
633 | return ret; | |
634 | } | |
635 | ||
636 | file->private_data = mpc52xx_gpt_wdt; | |
637 | return nonseekable_open(inode, file); | |
638 | } | |
639 | ||
640 | static int mpc52xx_wdt_release(struct inode *inode, struct file *file) | |
641 | { | |
642 | /* note: releasing the wdt in NOWAYOUT-mode does not stop it */ | |
643 | #if !defined(CONFIG_WATCHDOG_NOWAYOUT) | |
644 | struct mpc52xx_gpt_priv *gpt_wdt = file->private_data; | |
645 | unsigned long flags; | |
646 | ||
647 | spin_lock_irqsave(&gpt_wdt->lock, flags); | |
648 | clrbits32(&gpt_wdt->regs->mode, | |
649 | MPC52xx_GPT_MODE_COUNTER_ENABLE | MPC52xx_GPT_MODE_WDT_EN); | |
650 | gpt_wdt->wdt_mode &= ~MPC52xx_GPT_IS_WDT; | |
651 | spin_unlock_irqrestore(&gpt_wdt->lock, flags); | |
652 | #endif | |
653 | clear_bit(0, &wdt_is_active); | |
654 | return 0; | |
655 | } | |
656 | ||
657 | ||
658 | static const struct file_operations mpc52xx_wdt_fops = { | |
659 | .owner = THIS_MODULE, | |
660 | .llseek = no_llseek, | |
661 | .write = mpc52xx_wdt_write, | |
662 | .unlocked_ioctl = mpc52xx_wdt_ioctl, | |
663 | .open = mpc52xx_wdt_open, | |
664 | .release = mpc52xx_wdt_release, | |
665 | }; | |
666 | ||
667 | static struct miscdevice mpc52xx_wdt_miscdev = { | |
668 | .minor = WATCHDOG_MINOR, | |
669 | .name = "watchdog", | |
670 | .fops = &mpc52xx_wdt_fops, | |
671 | }; | |
672 | ||
673 | static int __devinit mpc52xx_gpt_wdt_init(void) | |
674 | { | |
675 | int err; | |
676 | ||
677 | /* try to register the watchdog misc device */ | |
678 | err = misc_register(&mpc52xx_wdt_miscdev); | |
679 | if (err) | |
680 | pr_err("%s: cannot register watchdog device\n", WDT_IDENTITY); | |
681 | else | |
682 | pr_info("%s: watchdog device registered\n", WDT_IDENTITY); | |
683 | return err; | |
684 | } | |
685 | ||
686 | static int mpc52xx_gpt_wdt_setup(struct mpc52xx_gpt_priv *gpt, | |
687 | const u32 *period) | |
688 | { | |
689 | u64 real_timeout; | |
690 | ||
691 | /* remember the gpt for the wdt operation */ | |
692 | mpc52xx_gpt_wdt = gpt; | |
693 | ||
694 | /* configure the wdt if the device tree contained a timeout */ | |
695 | if (!period || *period == 0) | |
696 | return 0; | |
697 | ||
698 | real_timeout = (u64) *period * 1000000000ULL; | |
699 | if (mpc52xx_gpt_do_start(gpt, real_timeout, 0, 1)) | |
700 | dev_warn(gpt->dev, "starting as wdt failed\n"); | |
701 | else | |
702 | dev_info(gpt->dev, "watchdog set to %us timeout\n", *period); | |
703 | return 0; | |
704 | } | |
705 | ||
706 | #else | |
707 | ||
708 | static int __devinit mpc52xx_gpt_wdt_init(void) | |
709 | { | |
710 | return 0; | |
711 | } | |
712 | ||
9205124c GL |
713 | static inline int mpc52xx_gpt_wdt_setup(struct mpc52xx_gpt_priv *gpt, |
714 | const u32 *period) | |
715 | { | |
716 | return 0; | |
717 | } | |
eda43d16 AD |
718 | |
719 | #endif /* CONFIG_MPC5200_WDT */ | |
720 | ||
5496eab2 GL |
721 | /* --------------------------------------------------------------------- |
722 | * of_platform bus binding code | |
723 | */ | |
00006124 | 724 | static int __devinit mpc52xx_gpt_probe(struct platform_device *ofdev) |
5496eab2 GL |
725 | { |
726 | struct mpc52xx_gpt_priv *gpt; | |
727 | ||
728 | gpt = kzalloc(sizeof *gpt, GFP_KERNEL); | |
729 | if (!gpt) | |
730 | return -ENOMEM; | |
731 | ||
732 | spin_lock_init(&gpt->lock); | |
733 | gpt->dev = &ofdev->dev; | |
61c7a080 GL |
734 | gpt->ipb_freq = mpc5xxx_get_bus_frequency(ofdev->dev.of_node); |
735 | gpt->regs = of_iomap(ofdev->dev.of_node, 0); | |
5496eab2 GL |
736 | if (!gpt->regs) { |
737 | kfree(gpt); | |
738 | return -ENOMEM; | |
739 | } | |
740 | ||
741 | dev_set_drvdata(&ofdev->dev, gpt); | |
742 | ||
61c7a080 GL |
743 | mpc52xx_gpt_gpio_setup(gpt, ofdev->dev.of_node); |
744 | mpc52xx_gpt_irq_setup(gpt, ofdev->dev.of_node); | |
5496eab2 | 745 | |
4f59ecfa GL |
746 | mutex_lock(&mpc52xx_gpt_list_mutex); |
747 | list_add(&gpt->list, &mpc52xx_gpt_list); | |
748 | mutex_unlock(&mpc52xx_gpt_list_mutex); | |
749 | ||
eda43d16 | 750 | /* check if this device could be a watchdog */ |
61c7a080 GL |
751 | if (of_get_property(ofdev->dev.of_node, "fsl,has-wdt", NULL) || |
752 | of_get_property(ofdev->dev.of_node, "has-wdt", NULL)) { | |
eda43d16 AD |
753 | const u32 *on_boot_wdt; |
754 | ||
755 | gpt->wdt_mode = MPC52xx_GPT_CAN_WDT; | |
61c7a080 GL |
756 | on_boot_wdt = of_get_property(ofdev->dev.of_node, |
757 | "fsl,wdt-on-boot", NULL); | |
eda43d16 AD |
758 | if (on_boot_wdt) { |
759 | dev_info(gpt->dev, "used as watchdog\n"); | |
760 | gpt->wdt_mode |= MPC52xx_GPT_IS_WDT; | |
761 | } else | |
762 | dev_info(gpt->dev, "can function as watchdog\n"); | |
763 | mpc52xx_gpt_wdt_setup(gpt, on_boot_wdt); | |
764 | } | |
765 | ||
5496eab2 GL |
766 | return 0; |
767 | } | |
768 | ||
a454dc50 | 769 | static int mpc52xx_gpt_remove(struct platform_device *ofdev) |
5496eab2 GL |
770 | { |
771 | return -EBUSY; | |
772 | } | |
773 | ||
774 | static const struct of_device_id mpc52xx_gpt_match[] = { | |
775 | { .compatible = "fsl,mpc5200-gpt", }, | |
776 | ||
777 | /* Depreciated compatible values; don't use for new dts files */ | |
778 | { .compatible = "fsl,mpc5200-gpt-gpio", }, | |
779 | { .compatible = "mpc5200-gpt", }, | |
780 | {} | |
781 | }; | |
782 | ||
00006124 | 783 | static struct platform_driver mpc52xx_gpt_driver = { |
4018294b GL |
784 | .driver = { |
785 | .name = "mpc52xx-gpt", | |
786 | .owner = THIS_MODULE, | |
787 | .of_match_table = mpc52xx_gpt_match, | |
788 | }, | |
5496eab2 GL |
789 | .probe = mpc52xx_gpt_probe, |
790 | .remove = mpc52xx_gpt_remove, | |
791 | }; | |
792 | ||
793 | static int __init mpc52xx_gpt_init(void) | |
794 | { | |
00006124 | 795 | return platform_driver_register(&mpc52xx_gpt_driver); |
5496eab2 GL |
796 | } |
797 | ||
798 | /* Make sure GPIOs and IRQs get set up before anyone tries to use them */ | |
799 | subsys_initcall(mpc52xx_gpt_init); | |
eda43d16 | 800 | device_initcall(mpc52xx_gpt_wdt_init); |