[mirror_ubuntu-artful-kernel.git] / arch / powerpc / platforms / 82xx / ep8248e.c

/*
 * Embedded Planet EP8248E support
 *
 * Copyright 2007 Freescale Semiconductor, Inc.
 * Author: Scott Wood <scottwood@freescale.com>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/fsl_devices.h>
#include <linux/mdio-bitbang.h>
#include <linux/of_mdio.h>
#include <linux/slab.h>
#include <linux/of_platform.h>

#include <asm/io.h>
#include <asm/cpm2.h>
#include <asm/udbg.h>
#include <asm/machdep.h>
#include <asm/time.h>
#include <asm/mpc8260.h>
#include <asm/prom.h>

#include <sysdev/fsl_soc.h>
#include <sysdev/cpm2_pic.h>

#include "pq2.h"

static u8 __iomem *ep8248e_bcsr;
static struct device_node *ep8248e_bcsr_node;

#define BCSR7_SCC2_ENABLE 0x10

#define BCSR8_PHY1_ENABLE 0x80
#define BCSR8_PHY1_POWER  0x40
#define BCSR8_PHY2_ENABLE 0x20
#define BCSR8_PHY2_POWER  0x10
#define BCSR8_MDIO_READ   0x04
#define BCSR8_MDIO_CLOCK  0x02
#define BCSR8_MDIO_DATA   0x01

#define BCSR9_USB_ENABLE  0x80
#define BCSR9_USB_POWER   0x40
#define BCSR9_USB_HOST    0x20
#define BCSR9_USB_FULL_SPEED_TARGET 0x10

static void __init ep8248e_pic_init(void)
{
	struct device_node *np = of_find_compatible_node(NULL, NULL, "fsl,pq2-pic");
	if (!np) {
		printk(KERN_ERR "PIC init: can not find cpm-pic node\n");
		return;
	}

	cpm2_pic_init(np);
	of_node_put(np);
}

static void ep8248e_set_mdc(struct mdiobb_ctrl *ctrl, int level)
{
	if (level)
		setbits8(&ep8248e_bcsr[8], BCSR8_MDIO_CLOCK);
	else
		clrbits8(&ep8248e_bcsr[8], BCSR8_MDIO_CLOCK);

	/* Read back to flush the write. */
	in_8(&ep8248e_bcsr[8]);
}

static void ep8248e_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
{
	if (output)
		clrbits8(&ep8248e_bcsr[8], BCSR8_MDIO_READ);
	else
		setbits8(&ep8248e_bcsr[8], BCSR8_MDIO_READ);

	/* Read back to flush the write. */
	in_8(&ep8248e_bcsr[8]);
}

static void ep8248e_set_mdio_data(struct mdiobb_ctrl *ctrl, int data)
{
	if (data)
		setbits8(&ep8248e_bcsr[8], BCSR8_MDIO_DATA);
	else
		clrbits8(&ep8248e_bcsr[8], BCSR8_MDIO_DATA);

	/* Read back to flush the write. */
	in_8(&ep8248e_bcsr[8]);
}

static int ep8248e_get_mdio_data(struct mdiobb_ctrl *ctrl)
{
	return in_8(&ep8248e_bcsr[8]) & BCSR8_MDIO_DATA;
}

static const struct mdiobb_ops ep8248e_mdio_ops = {
	.set_mdc = ep8248e_set_mdc,
	.set_mdio_dir = ep8248e_set_mdio_dir,
	.set_mdio_data = ep8248e_set_mdio_data,
	.get_mdio_data = ep8248e_get_mdio_data,
	.owner = THIS_MODULE,
};

static struct mdiobb_ctrl ep8248e_mdio_ctrl = {
	.ops = &ep8248e_mdio_ops,
};

static int ep8248e_mdio_probe(struct platform_device *ofdev)
{
	struct mii_bus *bus;
	struct resource res;
	struct device_node *node;
	int ret;

	node = of_get_parent(ofdev->dev.of_node);
	of_node_put(node);
	if (node != ep8248e_bcsr_node)
		return -ENODEV;

	ret = of_address_to_resource(ofdev->dev.of_node, 0, &res);
	if (ret)
		return ret;

	bus = alloc_mdio_bitbang(&ep8248e_mdio_ctrl);
	if (!bus)
		return -ENOMEM;

	bus->name = "ep8248e-mdio-bitbang";
	bus->parent = &ofdev->dev;
	snprintf(bus->id, MII_BUS_ID_SIZE, "%x", res.start);

	ret = of_mdiobus_register(bus, ofdev->dev.of_node);
	if (ret)
		goto err_free_bus;

	return 0;
err_free_bus:
	free_mdio_bitbang(bus);
	return ret;
}

static int ep8248e_mdio_remove(struct platform_device *ofdev)
{
	BUG();
	return 0;
}

static const struct of_device_id ep8248e_mdio_match[] = {
	{
		.compatible = "fsl,ep8248e-mdio-bitbang",
	},
	{},
};

static struct platform_driver ep8248e_mdio_driver = {
	.driver = {
		.name = "ep8248e-mdio-bitbang",
		.of_match_table = ep8248e_mdio_match,
	},
	.probe = ep8248e_mdio_probe,
	.remove = ep8248e_mdio_remove,
};

struct cpm_pin {
	int port, pin, flags;
};

static __initdata struct cpm_pin ep8248e_pins[] = {
	/* SMC1 */
	{2, 4, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
	{2, 5, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},

	/* SCC1 */
	{2, 14, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
	{2, 15, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
	{3, 29, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
	{3, 30, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
	{3, 31, CPM_PIN_INPUT | CPM_PIN_PRIMARY},

	/* FCC1 */
	{0, 14, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
	{0, 15, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
	{0, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
	{0, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
	{0, 18, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
	{0, 19, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
	{0, 20, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
	{0, 21, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
	{0, 26, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
	{0, 27, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
	{0, 28, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
	{0, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
	{0, 30, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
	{0, 31, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
	{2, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
	{2, 22, CPM_PIN_INPUT | CPM_PIN_PRIMARY},

	/* FCC2 */
	{1, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
	{1, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
	{1, 20, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
	{1, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
	{1, 22, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
	{1, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
	{1, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
	{1, 25, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
	{1, 26, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
	{1, 27, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
	{1, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
	{1, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
	{1, 30, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
	{1, 31, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
	{2, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
	{2, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY},

	/* I2C */
	{4, 14, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
	{4, 15, CPM_PIN_INPUT | CPM_PIN_SECONDARY},

	/* USB */
	{2, 10, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
	{2, 11, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
	{2, 20, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
	{2, 24, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
	{3, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
	{3, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
	{3, 25, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
};

static void __init init_ioports(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(ep8248e_pins); i++) {
		const struct cpm_pin *pin = &ep8248e_pins[i];
		cpm2_set_pin(pin->port, pin->pin, pin->flags);
	}

	cpm2_smc_clk_setup(CPM_CLK_SMC1, CPM_BRG7);
	cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_RX);
	cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_TX);
	cpm2_clk_setup(CPM_CLK_SCC3, CPM_CLK8, CPM_CLK_TX); /* USB */
	cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK11, CPM_CLK_RX);
	cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK10, CPM_CLK_TX);
	cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK13, CPM_CLK_RX);
	cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK14, CPM_CLK_TX);
}

static void __init ep8248e_setup_arch(void)
{
	if (ppc_md.progress)
		ppc_md.progress("ep8248e_setup_arch()", 0);

	cpm2_reset();

	/* When this is set, snooping CPM DMA from RAM causes
	 * machine checks.  See erratum SIU18.
	 */
	clrbits32(&cpm2_immr->im_siu_conf.siu_82xx.sc_bcr, MPC82XX_BCR_PLDP);

	ep8248e_bcsr_node =
		of_find_compatible_node(NULL, NULL, "fsl,ep8248e-bcsr");
	if (!ep8248e_bcsr_node) {
		printk(KERN_ERR "No bcsr in device tree\n");
		return;
	}

	ep8248e_bcsr = of_iomap(ep8248e_bcsr_node, 0);
	if (!ep8248e_bcsr) {
		printk(KERN_ERR "Cannot map BCSR registers\n");
		of_node_put(ep8248e_bcsr_node);
		ep8248e_bcsr_node = NULL;
		return;
	}

	setbits8(&ep8248e_bcsr[7], BCSR7_SCC2_ENABLE);
	setbits8(&ep8248e_bcsr[8], BCSR8_PHY1_ENABLE | BCSR8_PHY1_POWER |
	                           BCSR8_PHY2_ENABLE | BCSR8_PHY2_POWER);

	init_ioports();

	if (ppc_md.progress)
		ppc_md.progress("ep8248e_setup_arch(), finish", 0);
}

static const struct of_device_id of_bus_ids[] __initconst = {
	{ .compatible = "simple-bus", },
	{ .compatible = "fsl,ep8248e-bcsr", },
	{},
};

static int __init declare_of_platform_devices(void)
{
	of_platform_bus_probe(NULL, of_bus_ids, NULL);

	if (IS_ENABLED(CONFIG_MDIO_BITBANG))
		platform_driver_register(&ep8248e_mdio_driver);

	return 0;
}
machine_device_initcall(ep8248e, declare_of_platform_devices);

/*
 * Called very early, device-tree isn't unflattened
 */
static int __init ep8248e_probe(void)
{
	return of_machine_is_compatible("fsl,ep8248e");
}

define_machine(ep8248e)
{
	.name = "Embedded Planet EP8248E",
	.probe = ep8248e_probe,
	.setup_arch = ep8248e_setup_arch,
	.init_IRQ = ep8248e_pic_init,
	.get_irq = cpm2_get_irq,
	.calibrate_decr = generic_calibrate_decr,
	.restart = pq2_restart,
	.progress = udbg_progress,
};
Commit	Line	Data
0dde1a1d SW	1	/*
	2	* Embedded Planet EP8248E support
	3	*
	4	* Copyright 2007 Freescale Semiconductor, Inc.
	5	* Author: Scott Wood <scottwood@freescale.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License as published by the
	9	* Free Software Foundation; either version 2 of the License, or (at your
	10	* option) any later version.
	11	*/
	12
	13	#include <linux/init.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/fsl_devices.h>
	16	#include <linux/mdio-bitbang.h>
fd84f0ee	17	#include <linux/of_mdio.h>
5a0e3ad6	18	#include <linux/slab.h>
0dde1a1d SW	19	#include <linux/of_platform.h>
	20
	21	#include <asm/io.h>
	22	#include <asm/cpm2.h>
	23	#include <asm/udbg.h>
	24	#include <asm/machdep.h>
	25	#include <asm/time.h>
	26	#include <asm/mpc8260.h>
	27	#include <asm/prom.h>
	28
	29	#include <sysdev/fsl_soc.h>
	30	#include <sysdev/cpm2_pic.h>
	31
	32	#include "pq2.h"
	33
	34	static u8 __iomem *ep8248e_bcsr;
	35	static struct device_node *ep8248e_bcsr_node;
	36
	37	#define BCSR7_SCC2_ENABLE 0x10
	38
	39	#define BCSR8_PHY1_ENABLE 0x80
	40	#define BCSR8_PHY1_POWER 0x40
	41	#define BCSR8_PHY2_ENABLE 0x20
	42	#define BCSR8_PHY2_POWER 0x10
	43	#define BCSR8_MDIO_READ 0x04
	44	#define BCSR8_MDIO_CLOCK 0x02
	45	#define BCSR8_MDIO_DATA 0x01
	46
	47	#define BCSR9_USB_ENABLE 0x80
	48	#define BCSR9_USB_POWER 0x40
	49	#define BCSR9_USB_HOST 0x20
	50	#define BCSR9_USB_FULL_SPEED_TARGET 0x10
	51
	52	static void __init ep8248e_pic_init(void)
	53	{
	54	struct device_node *np = of_find_compatible_node(NULL, NULL, "fsl,pq2-pic");
	55	if (!np) {
	56	printk(KERN_ERR "PIC init: can not find cpm-pic node\n");
	57	return;
	58	}
	59
	60	cpm2_pic_init(np);
	61	of_node_put(np);
	62	}
	63
	64	static void ep8248e_set_mdc(struct mdiobb_ctrl *ctrl, int level)
	65	{
	66	if (level)
	67	setbits8(&ep8248e_bcsr[8], BCSR8_MDIO_CLOCK);
	68	else
	69	clrbits8(&ep8248e_bcsr[8], BCSR8_MDIO_CLOCK);
	70
	71	/* Read back to flush the write. */
	72	in_8(&ep8248e_bcsr[8]);
	73	}
	74
	75	static void ep8248e_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
	76	{
	77	if (output)
	78	clrbits8(&ep8248e_bcsr[8], BCSR8_MDIO_READ);
	79	else
	80	setbits8(&ep8248e_bcsr[8], BCSR8_MDIO_READ);
	81
	82	/* Read back to flush the write. */
83	in_8(&ep8248e_bcsr[8]);
84	}
85
86	static void ep8248e_set_mdio_data(struct mdiobb_ctrl *ctrl, int data)
87	{
88	if (data)
89	setbits8(&ep8248e_bcsr[8], BCSR8_MDIO_DATA);
90	else
91	clrbits8(&ep8248e_bcsr[8], BCSR8_MDIO_DATA);
92
93	/* Read back to flush the write. */
94	in_8(&ep8248e_bcsr[8]);
95	}
96
97	static int ep8248e_get_mdio_data(struct mdiobb_ctrl *ctrl)
98	{
99	return in_8(&ep8248e_bcsr[8]) & BCSR8_MDIO_DATA;
100	}
101
102	static const struct mdiobb_ops ep8248e_mdio_ops = {
103	.set_mdc = ep8248e_set_mdc,
104	.set_mdio_dir = ep8248e_set_mdio_dir,
105	.set_mdio_data = ep8248e_set_mdio_data,
106	.get_mdio_data = ep8248e_get_mdio_data,
107	.owner = THIS_MODULE,
108	};
109
110	static struct mdiobb_ctrl ep8248e_mdio_ctrl = {
111	.ops = &ep8248e_mdio_ops,
112	};
113
cad5cef6	114	static int ep8248e_mdio_probe(struct platform_device *ofdev)
0dde1a1d SW	115	{
	116	struct mii_bus *bus;
	117	struct resource res;
	118	struct device_node *node;
fd84f0ee	119	int ret;
0dde1a1d	120
61c7a080	121	node = of_get_parent(ofdev->dev.of_node);
0dde1a1d SW	122	of_node_put(node);
	123	if (node != ep8248e_bcsr_node)
	124	return -ENODEV;
	125
61c7a080	126	ret = of_address_to_resource(ofdev->dev.of_node, 0, &res);
0dde1a1d SW	127	if (ret)
	128	return ret;
	129
	130	bus = alloc_mdio_bitbang(&ep8248e_mdio_ctrl);
	131	if (!bus)
	132	return -ENOMEM;
	133
0dde1a1d	134	bus->name = "ep8248e-mdio-bitbang";
18ee49dd	135	bus->parent = &ofdev->dev;
9d9326d3	136	snprintf(bus->id, MII_BUS_ID_SIZE, "%x", res.start);
0dde1a1d	137
61c7a080	138	ret = of_mdiobus_register(bus, ofdev->dev.of_node);
58459a4e	139	if (ret)
e7f4dc35	140	goto err_free_bus;
58459a4e RK	141
58459a4e RK	142	return 0;
58459a4e RK	143	err_free_bus:
	144	free_mdio_bitbang(bus);
	145	return ret;
0dde1a1d SW	146	}
0dde1a1d SW	147
a454dc50	148	static int ep8248e_mdio_remove(struct platform_device *ofdev)
0dde1a1d SW	149	{
	150	BUG();
	151	return 0;
	152	}
	153
	154	static const struct of_device_id ep8248e_mdio_match[] = {
	155	{
	156	.compatible = "fsl,ep8248e-mdio-bitbang",
	157	},
	158	{},
	159	};
	160
00006124	161	static struct platform_driver ep8248e_mdio_driver = {
0dde1a1d SW	162	.driver = {
0dde1a1d SW	163	.name = "ep8248e-mdio-bitbang",
4018294b	164	.of_match_table = ep8248e_mdio_match,
0dde1a1d	165	},
0dde1a1d SW	166	.probe = ep8248e_mdio_probe,
	167	.remove = ep8248e_mdio_remove,
	168	};
	169
	170	struct cpm_pin {
	171	int port, pin, flags;
	172	};
	173
	174	static __initdata struct cpm_pin ep8248e_pins[] = {
	175	/* SMC1 */
	176	{2, 4, CPM_PIN_INPUT \| CPM_PIN_PRIMARY},
	177	{2, 5, CPM_PIN_OUTPUT \| CPM_PIN_PRIMARY},
	178
	179	/* SCC1 */
	180	{2, 14, CPM_PIN_INPUT \| CPM_PIN_PRIMARY},
	181	{2, 15, CPM_PIN_INPUT \| CPM_PIN_PRIMARY},
	182	{3, 29, CPM_PIN_OUTPUT \| CPM_PIN_PRIMARY},
	183	{3, 30, CPM_PIN_OUTPUT \| CPM_PIN_SECONDARY},
	184	{3, 31, CPM_PIN_INPUT \| CPM_PIN_PRIMARY},
	185
	186	/* FCC1 */
	187	{0, 14, CPM_PIN_INPUT \| CPM_PIN_PRIMARY},
	188	{0, 15, CPM_PIN_INPUT \| CPM_PIN_PRIMARY},
	189	{0, 16, CPM_PIN_INPUT \| CPM_PIN_PRIMARY},
	190	{0, 17, CPM_PIN_INPUT \| CPM_PIN_PRIMARY},
	191	{0, 18, CPM_PIN_OUTPUT \| CPM_PIN_PRIMARY},
	192	{0, 19, CPM_PIN_OUTPUT \| CPM_PIN_PRIMARY},
	193	{0, 20, CPM_PIN_OUTPUT \| CPM_PIN_PRIMARY},
	194	{0, 21, CPM_PIN_OUTPUT \| CPM_PIN_PRIMARY},
	195	{0, 26, CPM_PIN_INPUT \| CPM_PIN_SECONDARY},
	196	{0, 27, CPM_PIN_INPUT \| CPM_PIN_SECONDARY},
	197	{0, 28, CPM_PIN_OUTPUT \| CPM_PIN_SECONDARY},
	198	{0, 29, CPM_PIN_OUTPUT \| CPM_PIN_SECONDARY},
	199	{0, 30, CPM_PIN_INPUT \| CPM_PIN_SECONDARY},
	200	{0, 31, CPM_PIN_INPUT \| CPM_PIN_SECONDARY},
	201	{2, 21, CPM_PIN_INPUT \| CPM_PIN_PRIMARY},
	202	{2, 22, CPM_PIN_INPUT \| CPM_PIN_PRIMARY},
	203
	204	/* FCC2 */
	205	{1, 18, CPM_PIN_INPUT \| CPM_PIN_PRIMARY},
	206	{1, 19, CPM_PIN_INPUT \| CPM_PIN_PRIMARY},
	207	{1, 20, CPM_PIN_INPUT \| CPM_PIN_PRIMARY},
	208	{1, 21, CPM_PIN_INPUT \| CPM_PIN_PRIMARY},
	209	{1, 22, CPM_PIN_OUTPUT \| CPM_PIN_PRIMARY},
	210	{1, 23, CPM_PIN_OUTPUT \| CPM_PIN_PRIMARY},
	211	{1, 24, CPM_PIN_OUTPUT \| CPM_PIN_PRIMARY},
	212	{1, 25, CPM_PIN_OUTPUT \| CPM_PIN_PRIMARY},
	213	{1, 26, CPM_PIN_INPUT \| CPM_PIN_PRIMARY},
	214	{1, 27, CPM_PIN_INPUT \| CPM_PIN_PRIMARY},
	215	{1, 28, CPM_PIN_INPUT \| CPM_PIN_PRIMARY},
	216	{1, 29, CPM_PIN_OUTPUT \| CPM_PIN_SECONDARY},
	217	{1, 30, CPM_PIN_INPUT \| CPM_PIN_PRIMARY},
	218	{1, 31, CPM_PIN_OUTPUT \| CPM_PIN_PRIMARY},
	219	{2, 18, CPM_PIN_INPUT \| CPM_PIN_PRIMARY},
	220	{2, 19, CPM_PIN_INPUT \| CPM_PIN_PRIMARY},
	221
	222	/* I2C */
	223	{4, 14, CPM_PIN_INPUT \| CPM_PIN_SECONDARY},
	224	{4, 15, CPM_PIN_INPUT \| CPM_PIN_SECONDARY},
	225
	226	/* USB */
	227	{2, 10, CPM_PIN_INPUT \| CPM_PIN_PRIMARY},
	228	{2, 11, CPM_PIN_INPUT \| CPM_PIN_PRIMARY},
	229	{2, 20, CPM_PIN_OUTPUT \| CPM_PIN_PRIMARY},
230	{2, 24, CPM_PIN_INPUT \| CPM_PIN_PRIMARY},
231	{3, 23, CPM_PIN_OUTPUT \| CPM_PIN_PRIMARY},
232	{3, 24, CPM_PIN_OUTPUT \| CPM_PIN_PRIMARY},
233	{3, 25, CPM_PIN_INPUT \| CPM_PIN_PRIMARY},
234	};
235
236	static void __init init_ioports(void)
237	{
238	int i;
239
240	for (i = 0; i < ARRAY_SIZE(ep8248e_pins); i++) {
241	const struct cpm_pin *pin = &ep8248e_pins[i];
242	cpm2_set_pin(pin->port, pin->pin, pin->flags);
243	}
244
245	cpm2_smc_clk_setup(CPM_CLK_SMC1, CPM_BRG7);
246	cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_RX);
247	cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_TX);
248	cpm2_clk_setup(CPM_CLK_SCC3, CPM_CLK8, CPM_CLK_TX); /* USB */
249	cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK11, CPM_CLK_RX);
250	cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK10, CPM_CLK_TX);
251	cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK13, CPM_CLK_RX);
252	cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK14, CPM_CLK_TX);
253	}
254
255	static void __init ep8248e_setup_arch(void)
256	{
257	if (ppc_md.progress)
258	ppc_md.progress("ep8248e_setup_arch()", 0);
259
260	cpm2_reset();
261
262	/* When this is set, snooping CPM DMA from RAM causes
263	* machine checks. See erratum SIU18.
264	*/
265	clrbits32(&cpm2_immr->im_siu_conf.siu_82xx.sc_bcr, MPC82XX_BCR_PLDP);
266
267	ep8248e_bcsr_node =
268	of_find_compatible_node(NULL, NULL, "fsl,ep8248e-bcsr");
269	if (!ep8248e_bcsr_node) {
270	printk(KERN_ERR "No bcsr in device tree\n");
271	return;
272	}
273
274	ep8248e_bcsr = of_iomap(ep8248e_bcsr_node, 0);
275	if (!ep8248e_bcsr) {
276	printk(KERN_ERR "Cannot map BCSR registers\n");
277	of_node_put(ep8248e_bcsr_node);
278	ep8248e_bcsr_node = NULL;
279	return;
280	}
281
282	setbits8(&ep8248e_bcsr[7], BCSR7_SCC2_ENABLE);
283	setbits8(&ep8248e_bcsr[8], BCSR8_PHY1_ENABLE \| BCSR8_PHY1_POWER \|
284	BCSR8_PHY2_ENABLE \| BCSR8_PHY2_POWER);
285
286	init_ioports();
287
288	if (ppc_md.progress)
289	ppc_md.progress("ep8248e_setup_arch(), finish", 0);
290	}
291
ce6d73c9	292	static const struct of_device_id of_bus_ids[] __initconst = {
0dde1a1d SW	293	{ .compatible = "simple-bus", },
	294	{ .compatible = "fsl,ep8248e-bcsr", },
	295	{},
	296	};
	297
	298	static int __init declare_of_platform_devices(void)
	299	{
	300	of_platform_bus_probe(NULL, of_bus_ids, NULL);
49bf9279 AS	301
	302	if (IS_ENABLED(CONFIG_MDIO_BITBANG))
	303	platform_driver_register(&ep8248e_mdio_driver);
0dde1a1d SW	304
	305	return 0;
	306	}
	307	machine_device_initcall(ep8248e, declare_of_platform_devices);
	308
	309	/*
	310	* Called very early, device-tree isn't unflattened
	311	*/
	312	static int __init ep8248e_probe(void)
	313	{
56571384	314	return of_machine_is_compatible("fsl,ep8248e");
0dde1a1d SW	315	}
	316
	317	define_machine(ep8248e)
	318	{
	319	.name = "Embedded Planet EP8248E",
	320	.probe = ep8248e_probe,
	321	.setup_arch = ep8248e_setup_arch,
	322	.init_IRQ = ep8248e_pic_init,
	323	.get_irq = cpm2_get_irq,
	324	.calibrate_decr = generic_calibrate_decr,
	325	.restart = pq2_restart,
	326	.progress = udbg_progress,
	327	};