]> git.proxmox.com Git - mirror_ubuntu-eoan-kernel.git/blame - arch/powerpc/platforms/82xx/km82xx.c
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152
[mirror_ubuntu-eoan-kernel.git] / arch / powerpc / platforms / 82xx / km82xx.c
CommitLineData
2874c5fd 1// SPDX-License-Identifier: GPL-2.0-or-later
63716633 2/*
c513e7c9
HB
3 * Keymile km82xx support
4 * Copyright 2008-2011 DENX Software Engineering GmbH
63716633
HS
5 * Author: Heiko Schocher <hs@denx.de>
6 *
7 * based on code from:
8 * Copyright 2007 Freescale Semiconductor, Inc.
9 * Author: Scott Wood <scottwood@freescale.com>
63716633
HS
10 */
11
12#include <linux/init.h>
13#include <linux/interrupt.h>
14#include <linux/fsl_devices.h>
15#include <linux/of_platform.h>
16
3c00433b 17#include <linux/io.h>
63716633
HS
18#include <asm/cpm2.h>
19#include <asm/udbg.h>
20#include <asm/machdep.h>
3c00433b 21#include <linux/time.h>
63716633
HS
22#include <asm/mpc8260.h>
23#include <asm/prom.h>
24
25#include <sysdev/fsl_soc.h>
26#include <sysdev/cpm2_pic.h>
27
28#include "pq2.h"
29
c513e7c9 30static void __init km82xx_pic_init(void)
63716633 31{
c513e7c9
HB
32 struct device_node *np = of_find_compatible_node(NULL, NULL,
33 "fsl,pq2-pic");
63716633 34 if (!np) {
3c00433b 35 pr_err("PIC init: can not find cpm-pic node\n");
63716633
HS
36 return;
37 }
38
39 cpm2_pic_init(np);
40 of_node_put(np);
41}
42
43struct cpm_pin {
44 int port, pin, flags;
45};
46
c513e7c9 47static __initdata struct cpm_pin km82xx_pins[] = {
2a05e333
HB
48 /* SMC1 */
49 {2, 4, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
50 {2, 5, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
63716633
HS
51
52 /* SMC2 */
9239c89b
HS
53 {0, 8, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
54 {0, 9, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
63716633 55
c513e7c9
HB
56 /* SCC1 */
57 {2, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
58 {2, 15, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
59 {3, 31, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
60 {3, 30, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
61
63716633 62 /* SCC4 */
9239c89b
HS
63 {2, 25, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
64 {2, 24, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
65 {2, 9, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
66 {2, 8, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
67 {3, 22, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
68 {3, 21, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
69
70 /* FCC1 */
71 {0, 14, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
72 {0, 15, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
73 {0, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
74 {0, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
75 {0, 18, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
76 {0, 19, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
77 {0, 20, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
78 {0, 21, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
79 {0, 26, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
80 {0, 27, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
81 {0, 28, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
82 {0, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
83 {0, 30, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
84 {0, 31, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
85
86 {2, 22, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
87 {2, 23, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
88
89 /* FCC2 */
90 {1, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
91 {1, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
92 {1, 20, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
93 {1, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
94 {1, 22, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
95 {1, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
96 {1, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
97 {1, 25, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
98 {1, 26, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
99 {1, 27, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
100 {1, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
101 {1, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
102 {1, 30, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
103 {1, 31, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
104
105 {2, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
106 {2, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
107
108 /* MDC */
109 {0, 13, CPM_PIN_OUTPUT | CPM_PIN_GPIO},
110
111#if defined(CONFIG_I2C_CPM)
112 /* I2C */
113 {3, 14, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_OPENDRAIN},
114 {3, 15, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_OPENDRAIN},
115#endif
c513e7c9
HB
116
117 /* USB */
118 {0, 10, CPM_PIN_OUTPUT | CPM_PIN_GPIO}, /* FULL_SPEED */
119 {0, 11, CPM_PIN_OUTPUT | CPM_PIN_GPIO}, /*/SLAVE */
120 {2, 10, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* RXN */
121 {2, 11, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* RXP */
122 {2, 20, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, /* /OE */
123 {2, 27, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* RXCLK */
124 {3, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, /* TXP */
125 {3, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, /* TXN */
126 {3, 25, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* RXD */
5d1d67e3
HB
127
128 /* SPI */
129 {3, 16, CPM_PIN_INPUT | CPM_PIN_SECONDARY},/* SPI_MISO PD16 */
130 {3, 17, CPM_PIN_INPUT | CPM_PIN_SECONDARY},/* SPI_MOSI PD17 */
131 {3, 18, CPM_PIN_INPUT | CPM_PIN_SECONDARY},/* SPI_CLK PD18 */
63716633
HS
132};
133
134static void __init init_ioports(void)
135{
136 int i;
137
c513e7c9
HB
138 for (i = 0; i < ARRAY_SIZE(km82xx_pins); i++) {
139 const struct cpm_pin *pin = &km82xx_pins[i];
9239c89b 140 cpm2_set_pin(pin->port, pin->pin, pin->flags);
63716633
HS
141 }
142
143 cpm2_smc_clk_setup(CPM_CLK_SMC2, CPM_BRG8);
2a05e333 144 cpm2_smc_clk_setup(CPM_CLK_SMC1, CPM_BRG7);
c513e7c9
HB
145 cpm2_clk_setup(CPM_CLK_SCC1, CPM_CLK11, CPM_CLK_RX);
146 cpm2_clk_setup(CPM_CLK_SCC1, CPM_CLK11, CPM_CLK_TX);
147 cpm2_clk_setup(CPM_CLK_SCC3, CPM_CLK5, CPM_CLK_RTX);
63716633
HS
148 cpm2_clk_setup(CPM_CLK_SCC4, CPM_CLK7, CPM_CLK_RX);
149 cpm2_clk_setup(CPM_CLK_SCC4, CPM_CLK8, CPM_CLK_TX);
9239c89b
HS
150 cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK10, CPM_CLK_RX);
151 cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK9, CPM_CLK_TX);
152 cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK13, CPM_CLK_RX);
153 cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK14, CPM_CLK_TX);
c513e7c9
HB
154
155 /* Force USB FULL SPEED bit to '1' */
156 setbits32(&cpm2_immr->im_ioport.iop_pdata, 1 << (31 - 10));
157 /* clear USB_SLAVE */
158 clrbits32(&cpm2_immr->im_ioport.iop_pdata, 1 << (31 - 11));
63716633
HS
159}
160
c513e7c9 161static void __init km82xx_setup_arch(void)
63716633
HS
162{
163 if (ppc_md.progress)
c513e7c9 164 ppc_md.progress("km82xx_setup_arch()", 0);
63716633
HS
165
166 cpm2_reset();
167
168 /* When this is set, snooping CPM DMA from RAM causes
169 * machine checks. See erratum SIU18.
170 */
171 clrbits32(&cpm2_immr->im_siu_conf.siu_82xx.sc_bcr, MPC82XX_BCR_PLDP);
172
173 init_ioports();
174
175 if (ppc_md.progress)
c513e7c9 176 ppc_md.progress("km82xx_setup_arch(), finish", 0);
63716633
HS
177}
178
ce6d73c9 179static const struct of_device_id of_bus_ids[] __initconst = {
63716633
HS
180 { .compatible = "simple-bus", },
181 {},
182};
183
184static int __init declare_of_platform_devices(void)
185{
186 of_platform_bus_probe(NULL, of_bus_ids, NULL);
187
188 return 0;
189}
c513e7c9 190machine_device_initcall(km82xx, declare_of_platform_devices);
63716633
HS
191
192/*
193 * Called very early, device-tree isn't unflattened
194 */
c513e7c9 195static int __init km82xx_probe(void)
63716633 196{
56571384 197 return of_machine_is_compatible("keymile,km82xx");
63716633
HS
198}
199
c513e7c9 200define_machine(km82xx)
63716633 201{
c513e7c9
HB
202 .name = "Keymile km82xx",
203 .probe = km82xx_probe,
204 .setup_arch = km82xx_setup_arch,
205 .init_IRQ = km82xx_pic_init,
63716633
HS
206 .get_irq = cpm2_get_irq,
207 .calibrate_decr = generic_calibrate_decr,
208 .restart = pq2_restart,
209 .progress = udbg_progress,
210};